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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -O3 -mtriple=riscv64 -mattr=+v | FileCheck %s3 4; The case below demonstrates cross block CSE of vector instructions with5; undefined passthru operands.6define void @foo(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y, ptr %p1, ptr %p2, i1 zeroext %cond) {7; CHECK-LABEL: foo:8; CHECK: # %bb.0:9; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma10; CHECK-NEXT: vadd.vv v8, v8, v911; CHECK-NEXT: vs1r.v v8, (a0)12; CHECK-NEXT: bnez a2, .LBB0_213; CHECK-NEXT: # %bb.1: # %falsebb14; CHECK-NEXT: vs1r.v v8, (a1)15; CHECK-NEXT: .LBB0_2: # %mergebb16; CHECK-NEXT: ret17 %a = add <vscale x 2 x i32> %x, %y18 store <vscale x 2 x i32> %a, ptr %p119 br i1 %cond, label %mergebb, label %falsebb20 21falsebb:22 %b = add <vscale x 2 x i32> %x, %y23 store <vscale x 2 x i32> %b, ptr %p224 br label %mergebb25 26mergebb:27 ret void28}29