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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV646; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB8; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+m -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB10 11define <vscale x 1 x i8> @vp_ctpop_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {12; CHECK-LABEL: vp_ctpop_nxv1i8:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma15; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t16; CHECK-NEXT: li a0, 8517; CHECK-NEXT: vand.vx v9, v9, a0, v0.t18; CHECK-NEXT: li a0, 5119; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t20; CHECK-NEXT: vand.vx v9, v8, a0, v0.t21; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t22; CHECK-NEXT: vand.vx v8, v8, a0, v0.t23; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t24; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t25; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t26; CHECK-NEXT: vand.vi v8, v8, 15, v0.t27; CHECK-NEXT: ret28;29; CHECK-ZVBB-LABEL: vp_ctpop_nxv1i8:30; CHECK-ZVBB: # %bb.0:31; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma32; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t33; CHECK-ZVBB-NEXT: ret34 %v = call <vscale x 1 x i8> @llvm.vp.ctpop.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl)35 ret <vscale x 1 x i8> %v36}37 38define <vscale x 1 x i8> @vp_ctpop_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {39; CHECK-LABEL: vp_ctpop_nxv1i8_unmasked:40; CHECK: # %bb.0:41; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma42; CHECK-NEXT: vsrl.vi v9, v8, 143; CHECK-NEXT: li a0, 8544; CHECK-NEXT: vand.vx v9, v9, a045; CHECK-NEXT: li a0, 5146; CHECK-NEXT: vsub.vv v8, v8, v947; CHECK-NEXT: vand.vx v9, v8, a048; CHECK-NEXT: vsrl.vi v8, v8, 249; CHECK-NEXT: vand.vx v8, v8, a050; CHECK-NEXT: vadd.vv v8, v9, v851; CHECK-NEXT: vsrl.vi v9, v8, 452; CHECK-NEXT: vadd.vv v8, v8, v953; CHECK-NEXT: vand.vi v8, v8, 1554; CHECK-NEXT: ret55;56; CHECK-ZVBB-LABEL: vp_ctpop_nxv1i8_unmasked:57; CHECK-ZVBB: # %bb.0:58; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma59; CHECK-ZVBB-NEXT: vcpop.v v8, v860; CHECK-ZVBB-NEXT: ret61 %v = call <vscale x 1 x i8> @llvm.vp.ctpop.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)62 ret <vscale x 1 x i8> %v63}64 65define <vscale x 2 x i8> @vp_ctpop_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {66; CHECK-LABEL: vp_ctpop_nxv2i8:67; CHECK: # %bb.0:68; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma69; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t70; CHECK-NEXT: li a0, 8571; CHECK-NEXT: vand.vx v9, v9, a0, v0.t72; CHECK-NEXT: li a0, 5173; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t74; CHECK-NEXT: vand.vx v9, v8, a0, v0.t75; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t76; CHECK-NEXT: vand.vx v8, v8, a0, v0.t77; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t78; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t79; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t80; CHECK-NEXT: vand.vi v8, v8, 15, v0.t81; CHECK-NEXT: ret82;83; CHECK-ZVBB-LABEL: vp_ctpop_nxv2i8:84; CHECK-ZVBB: # %bb.0:85; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma86; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t87; CHECK-ZVBB-NEXT: ret88 %v = call <vscale x 2 x i8> @llvm.vp.ctpop.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl)89 ret <vscale x 2 x i8> %v90}91 92define <vscale x 2 x i8> @vp_ctpop_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {93; CHECK-LABEL: vp_ctpop_nxv2i8_unmasked:94; CHECK: # %bb.0:95; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma96; CHECK-NEXT: vsrl.vi v9, v8, 197; CHECK-NEXT: li a0, 8598; CHECK-NEXT: vand.vx v9, v9, a099; CHECK-NEXT: li a0, 51100; CHECK-NEXT: vsub.vv v8, v8, v9101; CHECK-NEXT: vand.vx v9, v8, a0102; CHECK-NEXT: vsrl.vi v8, v8, 2103; CHECK-NEXT: vand.vx v8, v8, a0104; CHECK-NEXT: vadd.vv v8, v9, v8105; CHECK-NEXT: vsrl.vi v9, v8, 4106; CHECK-NEXT: vadd.vv v8, v8, v9107; CHECK-NEXT: vand.vi v8, v8, 15108; CHECK-NEXT: ret109;110; CHECK-ZVBB-LABEL: vp_ctpop_nxv2i8_unmasked:111; CHECK-ZVBB: # %bb.0:112; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma113; CHECK-ZVBB-NEXT: vcpop.v v8, v8114; CHECK-ZVBB-NEXT: ret115 %v = call <vscale x 2 x i8> @llvm.vp.ctpop.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)116 ret <vscale x 2 x i8> %v117}118 119define <vscale x 4 x i8> @vp_ctpop_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {120; CHECK-LABEL: vp_ctpop_nxv4i8:121; CHECK: # %bb.0:122; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma123; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t124; CHECK-NEXT: li a0, 85125; CHECK-NEXT: vand.vx v9, v9, a0, v0.t126; CHECK-NEXT: li a0, 51127; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t128; CHECK-NEXT: vand.vx v9, v8, a0, v0.t129; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t130; CHECK-NEXT: vand.vx v8, v8, a0, v0.t131; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t132; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t133; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t134; CHECK-NEXT: vand.vi v8, v8, 15, v0.t135; CHECK-NEXT: ret136;137; CHECK-ZVBB-LABEL: vp_ctpop_nxv4i8:138; CHECK-ZVBB: # %bb.0:139; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma140; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t141; CHECK-ZVBB-NEXT: ret142 %v = call <vscale x 4 x i8> @llvm.vp.ctpop.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 %evl)143 ret <vscale x 4 x i8> %v144}145 146define <vscale x 4 x i8> @vp_ctpop_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {147; CHECK-LABEL: vp_ctpop_nxv4i8_unmasked:148; CHECK: # %bb.0:149; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma150; CHECK-NEXT: vsrl.vi v9, v8, 1151; CHECK-NEXT: li a0, 85152; CHECK-NEXT: vand.vx v9, v9, a0153; CHECK-NEXT: li a0, 51154; CHECK-NEXT: vsub.vv v8, v8, v9155; CHECK-NEXT: vand.vx v9, v8, a0156; CHECK-NEXT: vsrl.vi v8, v8, 2157; CHECK-NEXT: vand.vx v8, v8, a0158; CHECK-NEXT: vadd.vv v8, v9, v8159; CHECK-NEXT: vsrl.vi v9, v8, 4160; CHECK-NEXT: vadd.vv v8, v8, v9161; CHECK-NEXT: vand.vi v8, v8, 15162; CHECK-NEXT: ret163;164; CHECK-ZVBB-LABEL: vp_ctpop_nxv4i8_unmasked:165; CHECK-ZVBB: # %bb.0:166; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma167; CHECK-ZVBB-NEXT: vcpop.v v8, v8168; CHECK-ZVBB-NEXT: ret169 %v = call <vscale x 4 x i8> @llvm.vp.ctpop.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)170 ret <vscale x 4 x i8> %v171}172 173define <vscale x 8 x i8> @vp_ctpop_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {174; CHECK-LABEL: vp_ctpop_nxv8i8:175; CHECK: # %bb.0:176; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma177; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t178; CHECK-NEXT: li a0, 85179; CHECK-NEXT: vand.vx v9, v9, a0, v0.t180; CHECK-NEXT: li a0, 51181; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t182; CHECK-NEXT: vand.vx v9, v8, a0, v0.t183; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t184; CHECK-NEXT: vand.vx v8, v8, a0, v0.t185; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t186; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t187; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t188; CHECK-NEXT: vand.vi v8, v8, 15, v0.t189; CHECK-NEXT: ret190;191; CHECK-ZVBB-LABEL: vp_ctpop_nxv8i8:192; CHECK-ZVBB: # %bb.0:193; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma194; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t195; CHECK-ZVBB-NEXT: ret196 %v = call <vscale x 8 x i8> @llvm.vp.ctpop.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 %evl)197 ret <vscale x 8 x i8> %v198}199 200define <vscale x 8 x i8> @vp_ctpop_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {201; CHECK-LABEL: vp_ctpop_nxv8i8_unmasked:202; CHECK: # %bb.0:203; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma204; CHECK-NEXT: vsrl.vi v9, v8, 1205; CHECK-NEXT: li a0, 85206; CHECK-NEXT: vand.vx v9, v9, a0207; CHECK-NEXT: li a0, 51208; CHECK-NEXT: vsub.vv v8, v8, v9209; CHECK-NEXT: vand.vx v9, v8, a0210; CHECK-NEXT: vsrl.vi v8, v8, 2211; CHECK-NEXT: vand.vx v8, v8, a0212; CHECK-NEXT: vadd.vv v8, v9, v8213; CHECK-NEXT: vsrl.vi v9, v8, 4214; CHECK-NEXT: vadd.vv v8, v8, v9215; CHECK-NEXT: vand.vi v8, v8, 15216; CHECK-NEXT: ret217;218; CHECK-ZVBB-LABEL: vp_ctpop_nxv8i8_unmasked:219; CHECK-ZVBB: # %bb.0:220; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma221; CHECK-ZVBB-NEXT: vcpop.v v8, v8222; CHECK-ZVBB-NEXT: ret223 %v = call <vscale x 8 x i8> @llvm.vp.ctpop.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)224 ret <vscale x 8 x i8> %v225}226 227define <vscale x 16 x i8> @vp_ctpop_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {228; CHECK-LABEL: vp_ctpop_nxv16i8:229; CHECK: # %bb.0:230; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma231; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t232; CHECK-NEXT: li a0, 85233; CHECK-NEXT: vand.vx v10, v10, a0, v0.t234; CHECK-NEXT: li a0, 51235; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t236; CHECK-NEXT: vand.vx v10, v8, a0, v0.t237; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t238; CHECK-NEXT: vand.vx v8, v8, a0, v0.t239; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t240; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t241; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t242; CHECK-NEXT: vand.vi v8, v8, 15, v0.t243; CHECK-NEXT: ret244;245; CHECK-ZVBB-LABEL: vp_ctpop_nxv16i8:246; CHECK-ZVBB: # %bb.0:247; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma248; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t249; CHECK-ZVBB-NEXT: ret250 %v = call <vscale x 16 x i8> @llvm.vp.ctpop.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 %evl)251 ret <vscale x 16 x i8> %v252}253 254define <vscale x 16 x i8> @vp_ctpop_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {255; CHECK-LABEL: vp_ctpop_nxv16i8_unmasked:256; CHECK: # %bb.0:257; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma258; CHECK-NEXT: vsrl.vi v10, v8, 1259; CHECK-NEXT: li a0, 85260; CHECK-NEXT: vand.vx v10, v10, a0261; CHECK-NEXT: li a0, 51262; CHECK-NEXT: vsub.vv v8, v8, v10263; CHECK-NEXT: vand.vx v10, v8, a0264; CHECK-NEXT: vsrl.vi v8, v8, 2265; CHECK-NEXT: vand.vx v8, v8, a0266; CHECK-NEXT: vadd.vv v8, v10, v8267; CHECK-NEXT: vsrl.vi v10, v8, 4268; CHECK-NEXT: vadd.vv v8, v8, v10269; CHECK-NEXT: vand.vi v8, v8, 15270; CHECK-NEXT: ret271;272; CHECK-ZVBB-LABEL: vp_ctpop_nxv16i8_unmasked:273; CHECK-ZVBB: # %bb.0:274; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma275; CHECK-ZVBB-NEXT: vcpop.v v8, v8276; CHECK-ZVBB-NEXT: ret277 %v = call <vscale x 16 x i8> @llvm.vp.ctpop.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)278 ret <vscale x 16 x i8> %v279}280 281define <vscale x 32 x i8> @vp_ctpop_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {282; CHECK-LABEL: vp_ctpop_nxv32i8:283; CHECK: # %bb.0:284; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma285; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t286; CHECK-NEXT: li a0, 85287; CHECK-NEXT: vand.vx v12, v12, a0, v0.t288; CHECK-NEXT: li a0, 51289; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t290; CHECK-NEXT: vand.vx v12, v8, a0, v0.t291; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t292; CHECK-NEXT: vand.vx v8, v8, a0, v0.t293; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t294; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t295; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t296; CHECK-NEXT: vand.vi v8, v8, 15, v0.t297; CHECK-NEXT: ret298;299; CHECK-ZVBB-LABEL: vp_ctpop_nxv32i8:300; CHECK-ZVBB: # %bb.0:301; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma302; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t303; CHECK-ZVBB-NEXT: ret304 %v = call <vscale x 32 x i8> @llvm.vp.ctpop.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 %evl)305 ret <vscale x 32 x i8> %v306}307 308define <vscale x 32 x i8> @vp_ctpop_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {309; CHECK-LABEL: vp_ctpop_nxv32i8_unmasked:310; CHECK: # %bb.0:311; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma312; CHECK-NEXT: vsrl.vi v12, v8, 1313; CHECK-NEXT: li a0, 85314; CHECK-NEXT: vand.vx v12, v12, a0315; CHECK-NEXT: li a0, 51316; CHECK-NEXT: vsub.vv v8, v8, v12317; CHECK-NEXT: vand.vx v12, v8, a0318; CHECK-NEXT: vsrl.vi v8, v8, 2319; CHECK-NEXT: vand.vx v8, v8, a0320; CHECK-NEXT: vadd.vv v8, v12, v8321; CHECK-NEXT: vsrl.vi v12, v8, 4322; CHECK-NEXT: vadd.vv v8, v8, v12323; CHECK-NEXT: vand.vi v8, v8, 15324; CHECK-NEXT: ret325;326; CHECK-ZVBB-LABEL: vp_ctpop_nxv32i8_unmasked:327; CHECK-ZVBB: # %bb.0:328; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma329; CHECK-ZVBB-NEXT: vcpop.v v8, v8330; CHECK-ZVBB-NEXT: ret331 %v = call <vscale x 32 x i8> @llvm.vp.ctpop.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)332 ret <vscale x 32 x i8> %v333}334 335define <vscale x 64 x i8> @vp_ctpop_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {336; CHECK-LABEL: vp_ctpop_nxv64i8:337; CHECK: # %bb.0:338; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma339; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t340; CHECK-NEXT: li a0, 85341; CHECK-NEXT: vand.vx v16, v16, a0, v0.t342; CHECK-NEXT: li a0, 51343; CHECK-NEXT: vsub.vv v8, v8, v16, v0.t344; CHECK-NEXT: vand.vx v16, v8, a0, v0.t345; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t346; CHECK-NEXT: vand.vx v8, v8, a0, v0.t347; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t348; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t349; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t350; CHECK-NEXT: vand.vi v8, v8, 15, v0.t351; CHECK-NEXT: ret352;353; CHECK-ZVBB-LABEL: vp_ctpop_nxv64i8:354; CHECK-ZVBB: # %bb.0:355; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma356; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t357; CHECK-ZVBB-NEXT: ret358 %v = call <vscale x 64 x i8> @llvm.vp.ctpop.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 %evl)359 ret <vscale x 64 x i8> %v360}361 362define <vscale x 64 x i8> @vp_ctpop_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {363; CHECK-LABEL: vp_ctpop_nxv64i8_unmasked:364; CHECK: # %bb.0:365; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma366; CHECK-NEXT: vsrl.vi v16, v8, 1367; CHECK-NEXT: li a0, 85368; CHECK-NEXT: vand.vx v16, v16, a0369; CHECK-NEXT: li a0, 51370; CHECK-NEXT: vsub.vv v8, v8, v16371; CHECK-NEXT: vand.vx v16, v8, a0372; CHECK-NEXT: vsrl.vi v8, v8, 2373; CHECK-NEXT: vand.vx v8, v8, a0374; CHECK-NEXT: vadd.vv v8, v16, v8375; CHECK-NEXT: vsrl.vi v16, v8, 4376; CHECK-NEXT: vadd.vv v8, v8, v16377; CHECK-NEXT: vand.vi v8, v8, 15378; CHECK-NEXT: ret379;380; CHECK-ZVBB-LABEL: vp_ctpop_nxv64i8_unmasked:381; CHECK-ZVBB: # %bb.0:382; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma383; CHECK-ZVBB-NEXT: vcpop.v v8, v8384; CHECK-ZVBB-NEXT: ret385 %v = call <vscale x 64 x i8> @llvm.vp.ctpop.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> splat (i1 true), i32 %evl)386 ret <vscale x 64 x i8> %v387}388 389define <vscale x 1 x i16> @vp_ctpop_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {390; CHECK-LABEL: vp_ctpop_nxv1i16:391; CHECK: # %bb.0:392; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma393; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t394; CHECK-NEXT: lui a0, 5395; CHECK-NEXT: addi a0, a0, 1365396; CHECK-NEXT: vand.vx v9, v9, a0, v0.t397; CHECK-NEXT: lui a0, 3398; CHECK-NEXT: addi a0, a0, 819399; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t400; CHECK-NEXT: vand.vx v9, v8, a0, v0.t401; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t402; CHECK-NEXT: vand.vx v8, v8, a0, v0.t403; CHECK-NEXT: lui a0, 1404; CHECK-NEXT: addi a0, a0, -241405; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t406; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t407; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t408; CHECK-NEXT: vand.vx v8, v8, a0, v0.t409; CHECK-NEXT: li a0, 257410; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t411; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t412; CHECK-NEXT: ret413;414; CHECK-ZVBB-LABEL: vp_ctpop_nxv1i16:415; CHECK-ZVBB: # %bb.0:416; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma417; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t418; CHECK-ZVBB-NEXT: ret419 %v = call <vscale x 1 x i16> @llvm.vp.ctpop.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 %evl)420 ret <vscale x 1 x i16> %v421}422 423define <vscale x 1 x i16> @vp_ctpop_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {424; CHECK-LABEL: vp_ctpop_nxv1i16_unmasked:425; CHECK: # %bb.0:426; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma427; CHECK-NEXT: vsrl.vi v9, v8, 1428; CHECK-NEXT: lui a0, 5429; CHECK-NEXT: addi a0, a0, 1365430; CHECK-NEXT: vand.vx v9, v9, a0431; CHECK-NEXT: lui a0, 3432; CHECK-NEXT: addi a0, a0, 819433; CHECK-NEXT: vsub.vv v8, v8, v9434; CHECK-NEXT: vand.vx v9, v8, a0435; CHECK-NEXT: vsrl.vi v8, v8, 2436; CHECK-NEXT: vand.vx v8, v8, a0437; CHECK-NEXT: lui a0, 1438; CHECK-NEXT: addi a0, a0, -241439; CHECK-NEXT: vadd.vv v8, v9, v8440; CHECK-NEXT: vsrl.vi v9, v8, 4441; CHECK-NEXT: vadd.vv v8, v8, v9442; CHECK-NEXT: vand.vx v8, v8, a0443; CHECK-NEXT: li a0, 257444; CHECK-NEXT: vmul.vx v8, v8, a0445; CHECK-NEXT: vsrl.vi v8, v8, 8446; CHECK-NEXT: ret447;448; CHECK-ZVBB-LABEL: vp_ctpop_nxv1i16_unmasked:449; CHECK-ZVBB: # %bb.0:450; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma451; CHECK-ZVBB-NEXT: vcpop.v v8, v8452; CHECK-ZVBB-NEXT: ret453 %v = call <vscale x 1 x i16> @llvm.vp.ctpop.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)454 ret <vscale x 1 x i16> %v455}456 457define <vscale x 2 x i16> @vp_ctpop_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {458; CHECK-LABEL: vp_ctpop_nxv2i16:459; CHECK: # %bb.0:460; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma461; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t462; CHECK-NEXT: lui a0, 5463; CHECK-NEXT: addi a0, a0, 1365464; CHECK-NEXT: vand.vx v9, v9, a0, v0.t465; CHECK-NEXT: lui a0, 3466; CHECK-NEXT: addi a0, a0, 819467; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t468; CHECK-NEXT: vand.vx v9, v8, a0, v0.t469; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t470; CHECK-NEXT: vand.vx v8, v8, a0, v0.t471; CHECK-NEXT: lui a0, 1472; CHECK-NEXT: addi a0, a0, -241473; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t474; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t475; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t476; CHECK-NEXT: vand.vx v8, v8, a0, v0.t477; CHECK-NEXT: li a0, 257478; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t479; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t480; CHECK-NEXT: ret481;482; CHECK-ZVBB-LABEL: vp_ctpop_nxv2i16:483; CHECK-ZVBB: # %bb.0:484; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma485; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t486; CHECK-ZVBB-NEXT: ret487 %v = call <vscale x 2 x i16> @llvm.vp.ctpop.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl)488 ret <vscale x 2 x i16> %v489}490 491define <vscale x 2 x i16> @vp_ctpop_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {492; CHECK-LABEL: vp_ctpop_nxv2i16_unmasked:493; CHECK: # %bb.0:494; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma495; CHECK-NEXT: vsrl.vi v9, v8, 1496; CHECK-NEXT: lui a0, 5497; CHECK-NEXT: addi a0, a0, 1365498; CHECK-NEXT: vand.vx v9, v9, a0499; CHECK-NEXT: lui a0, 3500; CHECK-NEXT: addi a0, a0, 819501; CHECK-NEXT: vsub.vv v8, v8, v9502; CHECK-NEXT: vand.vx v9, v8, a0503; CHECK-NEXT: vsrl.vi v8, v8, 2504; CHECK-NEXT: vand.vx v8, v8, a0505; CHECK-NEXT: lui a0, 1506; CHECK-NEXT: addi a0, a0, -241507; CHECK-NEXT: vadd.vv v8, v9, v8508; CHECK-NEXT: vsrl.vi v9, v8, 4509; CHECK-NEXT: vadd.vv v8, v8, v9510; CHECK-NEXT: vand.vx v8, v8, a0511; CHECK-NEXT: li a0, 257512; CHECK-NEXT: vmul.vx v8, v8, a0513; CHECK-NEXT: vsrl.vi v8, v8, 8514; CHECK-NEXT: ret515;516; CHECK-ZVBB-LABEL: vp_ctpop_nxv2i16_unmasked:517; CHECK-ZVBB: # %bb.0:518; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma519; CHECK-ZVBB-NEXT: vcpop.v v8, v8520; CHECK-ZVBB-NEXT: ret521 %v = call <vscale x 2 x i16> @llvm.vp.ctpop.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)522 ret <vscale x 2 x i16> %v523}524 525define <vscale x 4 x i16> @vp_ctpop_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {526; CHECK-LABEL: vp_ctpop_nxv4i16:527; CHECK: # %bb.0:528; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma529; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t530; CHECK-NEXT: lui a0, 5531; CHECK-NEXT: addi a0, a0, 1365532; CHECK-NEXT: vand.vx v9, v9, a0, v0.t533; CHECK-NEXT: lui a0, 3534; CHECK-NEXT: addi a0, a0, 819535; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t536; CHECK-NEXT: vand.vx v9, v8, a0, v0.t537; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t538; CHECK-NEXT: vand.vx v8, v8, a0, v0.t539; CHECK-NEXT: lui a0, 1540; CHECK-NEXT: addi a0, a0, -241541; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t542; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t543; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t544; CHECK-NEXT: vand.vx v8, v8, a0, v0.t545; CHECK-NEXT: li a0, 257546; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t547; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t548; CHECK-NEXT: ret549;550; CHECK-ZVBB-LABEL: vp_ctpop_nxv4i16:551; CHECK-ZVBB: # %bb.0:552; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma553; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t554; CHECK-ZVBB-NEXT: ret555 %v = call <vscale x 4 x i16> @llvm.vp.ctpop.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl)556 ret <vscale x 4 x i16> %v557}558 559define <vscale x 4 x i16> @vp_ctpop_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {560; CHECK-LABEL: vp_ctpop_nxv4i16_unmasked:561; CHECK: # %bb.0:562; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma563; CHECK-NEXT: vsrl.vi v9, v8, 1564; CHECK-NEXT: lui a0, 5565; CHECK-NEXT: addi a0, a0, 1365566; CHECK-NEXT: vand.vx v9, v9, a0567; CHECK-NEXT: lui a0, 3568; CHECK-NEXT: addi a0, a0, 819569; CHECK-NEXT: vsub.vv v8, v8, v9570; CHECK-NEXT: vand.vx v9, v8, a0571; CHECK-NEXT: vsrl.vi v8, v8, 2572; CHECK-NEXT: vand.vx v8, v8, a0573; CHECK-NEXT: lui a0, 1574; CHECK-NEXT: addi a0, a0, -241575; CHECK-NEXT: vadd.vv v8, v9, v8576; CHECK-NEXT: vsrl.vi v9, v8, 4577; CHECK-NEXT: vadd.vv v8, v8, v9578; CHECK-NEXT: vand.vx v8, v8, a0579; CHECK-NEXT: li a0, 257580; CHECK-NEXT: vmul.vx v8, v8, a0581; CHECK-NEXT: vsrl.vi v8, v8, 8582; CHECK-NEXT: ret583;584; CHECK-ZVBB-LABEL: vp_ctpop_nxv4i16_unmasked:585; CHECK-ZVBB: # %bb.0:586; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma587; CHECK-ZVBB-NEXT: vcpop.v v8, v8588; CHECK-ZVBB-NEXT: ret589 %v = call <vscale x 4 x i16> @llvm.vp.ctpop.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)590 ret <vscale x 4 x i16> %v591}592 593define <vscale x 8 x i16> @vp_ctpop_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {594; CHECK-LABEL: vp_ctpop_nxv8i16:595; CHECK: # %bb.0:596; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma597; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t598; CHECK-NEXT: lui a0, 5599; CHECK-NEXT: addi a0, a0, 1365600; CHECK-NEXT: vand.vx v10, v10, a0, v0.t601; CHECK-NEXT: lui a0, 3602; CHECK-NEXT: addi a0, a0, 819603; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t604; CHECK-NEXT: vand.vx v10, v8, a0, v0.t605; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t606; CHECK-NEXT: vand.vx v8, v8, a0, v0.t607; CHECK-NEXT: lui a0, 1608; CHECK-NEXT: addi a0, a0, -241609; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t610; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t611; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t612; CHECK-NEXT: vand.vx v8, v8, a0, v0.t613; CHECK-NEXT: li a0, 257614; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t615; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t616; CHECK-NEXT: ret617;618; CHECK-ZVBB-LABEL: vp_ctpop_nxv8i16:619; CHECK-ZVBB: # %bb.0:620; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma621; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t622; CHECK-ZVBB-NEXT: ret623 %v = call <vscale x 8 x i16> @llvm.vp.ctpop.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 %evl)624 ret <vscale x 8 x i16> %v625}626 627define <vscale x 8 x i16> @vp_ctpop_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {628; CHECK-LABEL: vp_ctpop_nxv8i16_unmasked:629; CHECK: # %bb.0:630; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma631; CHECK-NEXT: vsrl.vi v10, v8, 1632; CHECK-NEXT: lui a0, 5633; CHECK-NEXT: addi a0, a0, 1365634; CHECK-NEXT: vand.vx v10, v10, a0635; CHECK-NEXT: lui a0, 3636; CHECK-NEXT: addi a0, a0, 819637; CHECK-NEXT: vsub.vv v8, v8, v10638; CHECK-NEXT: vand.vx v10, v8, a0639; CHECK-NEXT: vsrl.vi v8, v8, 2640; CHECK-NEXT: vand.vx v8, v8, a0641; CHECK-NEXT: lui a0, 1642; CHECK-NEXT: addi a0, a0, -241643; CHECK-NEXT: vadd.vv v8, v10, v8644; CHECK-NEXT: vsrl.vi v10, v8, 4645; CHECK-NEXT: vadd.vv v8, v8, v10646; CHECK-NEXT: vand.vx v8, v8, a0647; CHECK-NEXT: li a0, 257648; CHECK-NEXT: vmul.vx v8, v8, a0649; CHECK-NEXT: vsrl.vi v8, v8, 8650; CHECK-NEXT: ret651;652; CHECK-ZVBB-LABEL: vp_ctpop_nxv8i16_unmasked:653; CHECK-ZVBB: # %bb.0:654; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma655; CHECK-ZVBB-NEXT: vcpop.v v8, v8656; CHECK-ZVBB-NEXT: ret657 %v = call <vscale x 8 x i16> @llvm.vp.ctpop.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)658 ret <vscale x 8 x i16> %v659}660 661define <vscale x 16 x i16> @vp_ctpop_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {662; CHECK-LABEL: vp_ctpop_nxv16i16:663; CHECK: # %bb.0:664; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma665; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t666; CHECK-NEXT: lui a0, 5667; CHECK-NEXT: addi a0, a0, 1365668; CHECK-NEXT: vand.vx v12, v12, a0, v0.t669; CHECK-NEXT: lui a0, 3670; CHECK-NEXT: addi a0, a0, 819671; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t672; CHECK-NEXT: vand.vx v12, v8, a0, v0.t673; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t674; CHECK-NEXT: vand.vx v8, v8, a0, v0.t675; CHECK-NEXT: lui a0, 1676; CHECK-NEXT: addi a0, a0, -241677; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t678; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t679; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t680; CHECK-NEXT: vand.vx v8, v8, a0, v0.t681; CHECK-NEXT: li a0, 257682; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t683; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t684; CHECK-NEXT: ret685;686; CHECK-ZVBB-LABEL: vp_ctpop_nxv16i16:687; CHECK-ZVBB: # %bb.0:688; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma689; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t690; CHECK-ZVBB-NEXT: ret691 %v = call <vscale x 16 x i16> @llvm.vp.ctpop.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 %evl)692 ret <vscale x 16 x i16> %v693}694 695define <vscale x 16 x i16> @vp_ctpop_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {696; CHECK-LABEL: vp_ctpop_nxv16i16_unmasked:697; CHECK: # %bb.0:698; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma699; CHECK-NEXT: vsrl.vi v12, v8, 1700; CHECK-NEXT: lui a0, 5701; CHECK-NEXT: addi a0, a0, 1365702; CHECK-NEXT: vand.vx v12, v12, a0703; CHECK-NEXT: lui a0, 3704; CHECK-NEXT: addi a0, a0, 819705; CHECK-NEXT: vsub.vv v8, v8, v12706; CHECK-NEXT: vand.vx v12, v8, a0707; CHECK-NEXT: vsrl.vi v8, v8, 2708; CHECK-NEXT: vand.vx v8, v8, a0709; CHECK-NEXT: lui a0, 1710; CHECK-NEXT: addi a0, a0, -241711; CHECK-NEXT: vadd.vv v8, v12, v8712; CHECK-NEXT: vsrl.vi v12, v8, 4713; CHECK-NEXT: vadd.vv v8, v8, v12714; CHECK-NEXT: vand.vx v8, v8, a0715; CHECK-NEXT: li a0, 257716; CHECK-NEXT: vmul.vx v8, v8, a0717; CHECK-NEXT: vsrl.vi v8, v8, 8718; CHECK-NEXT: ret719;720; CHECK-ZVBB-LABEL: vp_ctpop_nxv16i16_unmasked:721; CHECK-ZVBB: # %bb.0:722; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma723; CHECK-ZVBB-NEXT: vcpop.v v8, v8724; CHECK-ZVBB-NEXT: ret725 %v = call <vscale x 16 x i16> @llvm.vp.ctpop.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)726 ret <vscale x 16 x i16> %v727}728 729define <vscale x 32 x i16> @vp_ctpop_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {730; CHECK-LABEL: vp_ctpop_nxv32i16:731; CHECK: # %bb.0:732; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma733; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t734; CHECK-NEXT: lui a0, 5735; CHECK-NEXT: addi a0, a0, 1365736; CHECK-NEXT: vand.vx v16, v16, a0, v0.t737; CHECK-NEXT: lui a0, 3738; CHECK-NEXT: addi a0, a0, 819739; CHECK-NEXT: vsub.vv v16, v8, v16, v0.t740; CHECK-NEXT: vand.vx v8, v16, a0, v0.t741; CHECK-NEXT: vsrl.vi v16, v16, 2, v0.t742; CHECK-NEXT: vand.vx v16, v16, a0, v0.t743; CHECK-NEXT: lui a0, 1744; CHECK-NEXT: addi a0, a0, -241745; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t746; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t747; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t748; CHECK-NEXT: vand.vx v8, v8, a0, v0.t749; CHECK-NEXT: li a0, 257750; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t751; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t752; CHECK-NEXT: ret753;754; CHECK-ZVBB-LABEL: vp_ctpop_nxv32i16:755; CHECK-ZVBB: # %bb.0:756; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma757; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t758; CHECK-ZVBB-NEXT: ret759 %v = call <vscale x 32 x i16> @llvm.vp.ctpop.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 %evl)760 ret <vscale x 32 x i16> %v761}762 763define <vscale x 32 x i16> @vp_ctpop_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {764; CHECK-LABEL: vp_ctpop_nxv32i16_unmasked:765; CHECK: # %bb.0:766; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma767; CHECK-NEXT: vsrl.vi v16, v8, 1768; CHECK-NEXT: lui a0, 5769; CHECK-NEXT: addi a0, a0, 1365770; CHECK-NEXT: vand.vx v16, v16, a0771; CHECK-NEXT: lui a0, 3772; CHECK-NEXT: addi a0, a0, 819773; CHECK-NEXT: vsub.vv v8, v8, v16774; CHECK-NEXT: vand.vx v16, v8, a0775; CHECK-NEXT: vsrl.vi v8, v8, 2776; CHECK-NEXT: vand.vx v8, v8, a0777; CHECK-NEXT: lui a0, 1778; CHECK-NEXT: addi a0, a0, -241779; CHECK-NEXT: vadd.vv v8, v16, v8780; CHECK-NEXT: vsrl.vi v16, v8, 4781; CHECK-NEXT: vadd.vv v8, v8, v16782; CHECK-NEXT: vand.vx v8, v8, a0783; CHECK-NEXT: li a0, 257784; CHECK-NEXT: vmul.vx v8, v8, a0785; CHECK-NEXT: vsrl.vi v8, v8, 8786; CHECK-NEXT: ret787;788; CHECK-ZVBB-LABEL: vp_ctpop_nxv32i16_unmasked:789; CHECK-ZVBB: # %bb.0:790; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma791; CHECK-ZVBB-NEXT: vcpop.v v8, v8792; CHECK-ZVBB-NEXT: ret793 %v = call <vscale x 32 x i16> @llvm.vp.ctpop.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)794 ret <vscale x 32 x i16> %v795}796 797define <vscale x 1 x i32> @vp_ctpop_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {798; CHECK-LABEL: vp_ctpop_nxv1i32:799; CHECK: # %bb.0:800; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma801; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t802; CHECK-NEXT: lui a0, 349525803; CHECK-NEXT: addi a0, a0, 1365804; CHECK-NEXT: vand.vx v9, v9, a0, v0.t805; CHECK-NEXT: lui a0, 209715806; CHECK-NEXT: addi a0, a0, 819807; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t808; CHECK-NEXT: vand.vx v9, v8, a0, v0.t809; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t810; CHECK-NEXT: vand.vx v8, v8, a0, v0.t811; CHECK-NEXT: lui a0, 61681812; CHECK-NEXT: addi a0, a0, -241813; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t814; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t815; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t816; CHECK-NEXT: vand.vx v8, v8, a0, v0.t817; CHECK-NEXT: lui a0, 4112818; CHECK-NEXT: addi a0, a0, 257819; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t820; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t821; CHECK-NEXT: ret822;823; CHECK-ZVBB-LABEL: vp_ctpop_nxv1i32:824; CHECK-ZVBB: # %bb.0:825; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma826; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t827; CHECK-ZVBB-NEXT: ret828 %v = call <vscale x 1 x i32> @llvm.vp.ctpop.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 %evl)829 ret <vscale x 1 x i32> %v830}831 832define <vscale x 1 x i32> @vp_ctpop_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {833; CHECK-LABEL: vp_ctpop_nxv1i32_unmasked:834; CHECK: # %bb.0:835; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma836; CHECK-NEXT: vsrl.vi v9, v8, 1837; CHECK-NEXT: lui a0, 349525838; CHECK-NEXT: addi a0, a0, 1365839; CHECK-NEXT: vand.vx v9, v9, a0840; CHECK-NEXT: lui a0, 209715841; CHECK-NEXT: addi a0, a0, 819842; CHECK-NEXT: vsub.vv v8, v8, v9843; CHECK-NEXT: vand.vx v9, v8, a0844; CHECK-NEXT: vsrl.vi v8, v8, 2845; CHECK-NEXT: vand.vx v8, v8, a0846; CHECK-NEXT: lui a0, 61681847; CHECK-NEXT: addi a0, a0, -241848; CHECK-NEXT: vadd.vv v8, v9, v8849; CHECK-NEXT: vsrl.vi v9, v8, 4850; CHECK-NEXT: vadd.vv v8, v8, v9851; CHECK-NEXT: vand.vx v8, v8, a0852; CHECK-NEXT: lui a0, 4112853; CHECK-NEXT: addi a0, a0, 257854; CHECK-NEXT: vmul.vx v8, v8, a0855; CHECK-NEXT: vsrl.vi v8, v8, 24856; CHECK-NEXT: ret857;858; CHECK-ZVBB-LABEL: vp_ctpop_nxv1i32_unmasked:859; CHECK-ZVBB: # %bb.0:860; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma861; CHECK-ZVBB-NEXT: vcpop.v v8, v8862; CHECK-ZVBB-NEXT: ret863 %v = call <vscale x 1 x i32> @llvm.vp.ctpop.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)864 ret <vscale x 1 x i32> %v865}866 867define <vscale x 2 x i32> @vp_ctpop_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {868; CHECK-LABEL: vp_ctpop_nxv2i32:869; CHECK: # %bb.0:870; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma871; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t872; CHECK-NEXT: lui a0, 349525873; CHECK-NEXT: addi a0, a0, 1365874; CHECK-NEXT: vand.vx v9, v9, a0, v0.t875; CHECK-NEXT: lui a0, 209715876; CHECK-NEXT: addi a0, a0, 819877; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t878; CHECK-NEXT: vand.vx v9, v8, a0, v0.t879; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t880; CHECK-NEXT: vand.vx v8, v8, a0, v0.t881; CHECK-NEXT: lui a0, 61681882; CHECK-NEXT: addi a0, a0, -241883; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t884; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t885; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t886; CHECK-NEXT: vand.vx v8, v8, a0, v0.t887; CHECK-NEXT: lui a0, 4112888; CHECK-NEXT: addi a0, a0, 257889; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t890; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t891; CHECK-NEXT: ret892;893; CHECK-ZVBB-LABEL: vp_ctpop_nxv2i32:894; CHECK-ZVBB: # %bb.0:895; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma896; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t897; CHECK-ZVBB-NEXT: ret898 %v = call <vscale x 2 x i32> @llvm.vp.ctpop.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl)899 ret <vscale x 2 x i32> %v900}901 902define <vscale x 2 x i32> @vp_ctpop_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {903; CHECK-LABEL: vp_ctpop_nxv2i32_unmasked:904; CHECK: # %bb.0:905; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma906; CHECK-NEXT: vsrl.vi v9, v8, 1907; CHECK-NEXT: lui a0, 349525908; CHECK-NEXT: addi a0, a0, 1365909; CHECK-NEXT: vand.vx v9, v9, a0910; CHECK-NEXT: lui a0, 209715911; CHECK-NEXT: addi a0, a0, 819912; CHECK-NEXT: vsub.vv v8, v8, v9913; CHECK-NEXT: vand.vx v9, v8, a0914; CHECK-NEXT: vsrl.vi v8, v8, 2915; CHECK-NEXT: vand.vx v8, v8, a0916; CHECK-NEXT: lui a0, 61681917; CHECK-NEXT: addi a0, a0, -241918; CHECK-NEXT: vadd.vv v8, v9, v8919; CHECK-NEXT: vsrl.vi v9, v8, 4920; CHECK-NEXT: vadd.vv v8, v8, v9921; CHECK-NEXT: vand.vx v8, v8, a0922; CHECK-NEXT: lui a0, 4112923; CHECK-NEXT: addi a0, a0, 257924; CHECK-NEXT: vmul.vx v8, v8, a0925; CHECK-NEXT: vsrl.vi v8, v8, 24926; CHECK-NEXT: ret927;928; CHECK-ZVBB-LABEL: vp_ctpop_nxv2i32_unmasked:929; CHECK-ZVBB: # %bb.0:930; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma931; CHECK-ZVBB-NEXT: vcpop.v v8, v8932; CHECK-ZVBB-NEXT: ret933 %v = call <vscale x 2 x i32> @llvm.vp.ctpop.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)934 ret <vscale x 2 x i32> %v935}936 937define <vscale x 4 x i32> @vp_ctpop_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {938; CHECK-LABEL: vp_ctpop_nxv4i32:939; CHECK: # %bb.0:940; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma941; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t942; CHECK-NEXT: lui a0, 349525943; CHECK-NEXT: addi a0, a0, 1365944; CHECK-NEXT: vand.vx v10, v10, a0, v0.t945; CHECK-NEXT: lui a0, 209715946; CHECK-NEXT: addi a0, a0, 819947; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t948; CHECK-NEXT: vand.vx v10, v8, a0, v0.t949; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t950; CHECK-NEXT: vand.vx v8, v8, a0, v0.t951; CHECK-NEXT: lui a0, 61681952; CHECK-NEXT: addi a0, a0, -241953; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t954; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t955; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t956; CHECK-NEXT: vand.vx v8, v8, a0, v0.t957; CHECK-NEXT: lui a0, 4112958; CHECK-NEXT: addi a0, a0, 257959; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t960; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t961; CHECK-NEXT: ret962;963; CHECK-ZVBB-LABEL: vp_ctpop_nxv4i32:964; CHECK-ZVBB: # %bb.0:965; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma966; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t967; CHECK-ZVBB-NEXT: ret968 %v = call <vscale x 4 x i32> @llvm.vp.ctpop.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl)969 ret <vscale x 4 x i32> %v970}971 972define <vscale x 4 x i32> @vp_ctpop_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {973; CHECK-LABEL: vp_ctpop_nxv4i32_unmasked:974; CHECK: # %bb.0:975; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma976; CHECK-NEXT: vsrl.vi v10, v8, 1977; CHECK-NEXT: lui a0, 349525978; CHECK-NEXT: addi a0, a0, 1365979; CHECK-NEXT: vand.vx v10, v10, a0980; CHECK-NEXT: lui a0, 209715981; CHECK-NEXT: addi a0, a0, 819982; CHECK-NEXT: vsub.vv v8, v8, v10983; CHECK-NEXT: vand.vx v10, v8, a0984; CHECK-NEXT: vsrl.vi v8, v8, 2985; CHECK-NEXT: vand.vx v8, v8, a0986; CHECK-NEXT: lui a0, 61681987; CHECK-NEXT: addi a0, a0, -241988; CHECK-NEXT: vadd.vv v8, v10, v8989; CHECK-NEXT: vsrl.vi v10, v8, 4990; CHECK-NEXT: vadd.vv v8, v8, v10991; CHECK-NEXT: vand.vx v8, v8, a0992; CHECK-NEXT: lui a0, 4112993; CHECK-NEXT: addi a0, a0, 257994; CHECK-NEXT: vmul.vx v8, v8, a0995; CHECK-NEXT: vsrl.vi v8, v8, 24996; CHECK-NEXT: ret997;998; CHECK-ZVBB-LABEL: vp_ctpop_nxv4i32_unmasked:999; CHECK-ZVBB: # %bb.0:1000; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma1001; CHECK-ZVBB-NEXT: vcpop.v v8, v81002; CHECK-ZVBB-NEXT: ret1003 %v = call <vscale x 4 x i32> @llvm.vp.ctpop.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)1004 ret <vscale x 4 x i32> %v1005}1006 1007define <vscale x 8 x i32> @vp_ctpop_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1008; CHECK-LABEL: vp_ctpop_nxv8i32:1009; CHECK: # %bb.0:1010; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1011; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t1012; CHECK-NEXT: lui a0, 3495251013; CHECK-NEXT: addi a0, a0, 13651014; CHECK-NEXT: vand.vx v12, v12, a0, v0.t1015; CHECK-NEXT: lui a0, 2097151016; CHECK-NEXT: addi a0, a0, 8191017; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t1018; CHECK-NEXT: vand.vx v12, v8, a0, v0.t1019; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t1020; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1021; CHECK-NEXT: lui a0, 616811022; CHECK-NEXT: addi a0, a0, -2411023; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t1024; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t1025; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t1026; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1027; CHECK-NEXT: lui a0, 41121028; CHECK-NEXT: addi a0, a0, 2571029; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t1030; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t1031; CHECK-NEXT: ret1032;1033; CHECK-ZVBB-LABEL: vp_ctpop_nxv8i32:1034; CHECK-ZVBB: # %bb.0:1035; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma1036; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t1037; CHECK-ZVBB-NEXT: ret1038 %v = call <vscale x 8 x i32> @llvm.vp.ctpop.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 %evl)1039 ret <vscale x 8 x i32> %v1040}1041 1042define <vscale x 8 x i32> @vp_ctpop_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {1043; CHECK-LABEL: vp_ctpop_nxv8i32_unmasked:1044; CHECK: # %bb.0:1045; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1046; CHECK-NEXT: vsrl.vi v12, v8, 11047; CHECK-NEXT: lui a0, 3495251048; CHECK-NEXT: addi a0, a0, 13651049; CHECK-NEXT: vand.vx v12, v12, a01050; CHECK-NEXT: lui a0, 2097151051; CHECK-NEXT: addi a0, a0, 8191052; CHECK-NEXT: vsub.vv v8, v8, v121053; CHECK-NEXT: vand.vx v12, v8, a01054; CHECK-NEXT: vsrl.vi v8, v8, 21055; CHECK-NEXT: vand.vx v8, v8, a01056; CHECK-NEXT: lui a0, 616811057; CHECK-NEXT: addi a0, a0, -2411058; CHECK-NEXT: vadd.vv v8, v12, v81059; CHECK-NEXT: vsrl.vi v12, v8, 41060; CHECK-NEXT: vadd.vv v8, v8, v121061; CHECK-NEXT: vand.vx v8, v8, a01062; CHECK-NEXT: lui a0, 41121063; CHECK-NEXT: addi a0, a0, 2571064; CHECK-NEXT: vmul.vx v8, v8, a01065; CHECK-NEXT: vsrl.vi v8, v8, 241066; CHECK-NEXT: ret1067;1068; CHECK-ZVBB-LABEL: vp_ctpop_nxv8i32_unmasked:1069; CHECK-ZVBB: # %bb.0:1070; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma1071; CHECK-ZVBB-NEXT: vcpop.v v8, v81072; CHECK-ZVBB-NEXT: ret1073 %v = call <vscale x 8 x i32> @llvm.vp.ctpop.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)1074 ret <vscale x 8 x i32> %v1075}1076 1077define <vscale x 16 x i32> @vp_ctpop_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1078; CHECK-LABEL: vp_ctpop_nxv16i32:1079; CHECK: # %bb.0:1080; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1081; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t1082; CHECK-NEXT: lui a0, 3495251083; CHECK-NEXT: addi a0, a0, 13651084; CHECK-NEXT: vand.vx v16, v16, a0, v0.t1085; CHECK-NEXT: lui a0, 2097151086; CHECK-NEXT: addi a0, a0, 8191087; CHECK-NEXT: vsub.vv v16, v8, v16, v0.t1088; CHECK-NEXT: vand.vx v8, v16, a0, v0.t1089; CHECK-NEXT: vsrl.vi v16, v16, 2, v0.t1090; CHECK-NEXT: vand.vx v16, v16, a0, v0.t1091; CHECK-NEXT: lui a0, 616811092; CHECK-NEXT: addi a0, a0, -2411093; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t1094; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t1095; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t1096; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1097; CHECK-NEXT: lui a0, 41121098; CHECK-NEXT: addi a0, a0, 2571099; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t1100; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t1101; CHECK-NEXT: ret1102;1103; CHECK-ZVBB-LABEL: vp_ctpop_nxv16i32:1104; CHECK-ZVBB: # %bb.0:1105; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma1106; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t1107; CHECK-ZVBB-NEXT: ret1108 %v = call <vscale x 16 x i32> @llvm.vp.ctpop.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 %evl)1109 ret <vscale x 16 x i32> %v1110}1111 1112define <vscale x 16 x i32> @vp_ctpop_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {1113; CHECK-LABEL: vp_ctpop_nxv16i32_unmasked:1114; CHECK: # %bb.0:1115; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1116; CHECK-NEXT: vsrl.vi v16, v8, 11117; CHECK-NEXT: lui a0, 3495251118; CHECK-NEXT: addi a0, a0, 13651119; CHECK-NEXT: vand.vx v16, v16, a01120; CHECK-NEXT: lui a0, 2097151121; CHECK-NEXT: addi a0, a0, 8191122; CHECK-NEXT: vsub.vv v8, v8, v161123; CHECK-NEXT: vand.vx v16, v8, a01124; CHECK-NEXT: vsrl.vi v8, v8, 21125; CHECK-NEXT: vand.vx v8, v8, a01126; CHECK-NEXT: lui a0, 616811127; CHECK-NEXT: addi a0, a0, -2411128; CHECK-NEXT: vadd.vv v8, v16, v81129; CHECK-NEXT: vsrl.vi v16, v8, 41130; CHECK-NEXT: vadd.vv v8, v8, v161131; CHECK-NEXT: vand.vx v8, v8, a01132; CHECK-NEXT: lui a0, 41121133; CHECK-NEXT: addi a0, a0, 2571134; CHECK-NEXT: vmul.vx v8, v8, a01135; CHECK-NEXT: vsrl.vi v8, v8, 241136; CHECK-NEXT: ret1137;1138; CHECK-ZVBB-LABEL: vp_ctpop_nxv16i32_unmasked:1139; CHECK-ZVBB: # %bb.0:1140; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma1141; CHECK-ZVBB-NEXT: vcpop.v v8, v81142; CHECK-ZVBB-NEXT: ret1143 %v = call <vscale x 16 x i32> @llvm.vp.ctpop.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)1144 ret <vscale x 16 x i32> %v1145}1146 1147define <vscale x 1 x i64> @vp_ctpop_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1148; RV32-LABEL: vp_ctpop_nxv1i64:1149; RV32: # %bb.0:1150; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1151; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t1152; RV32-NEXT: lui a1, 3495251153; RV32-NEXT: addi a1, a1, 13651154; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1155; RV32-NEXT: vmv.v.x v10, a11156; RV32-NEXT: lui a1, 2097151157; RV32-NEXT: addi a1, a1, 8191158; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1159; RV32-NEXT: vand.vv v9, v9, v10, v0.t1160; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1161; RV32-NEXT: vmv.v.x v10, a11162; RV32-NEXT: lui a1, 616811163; RV32-NEXT: addi a1, a1, -2411164; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1165; RV32-NEXT: vsub.vv v8, v8, v9, v0.t1166; RV32-NEXT: vand.vv v9, v8, v10, v0.t1167; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t1168; RV32-NEXT: vand.vv v8, v8, v10, v0.t1169; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1170; RV32-NEXT: vmv.v.x v10, a11171; RV32-NEXT: lui a1, 41121172; RV32-NEXT: addi a1, a1, 2571173; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1174; RV32-NEXT: vadd.vv v8, v9, v8, v0.t1175; RV32-NEXT: vsrl.vi v9, v8, 4, v0.t1176; RV32-NEXT: vadd.vv v8, v8, v9, v0.t1177; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1178; RV32-NEXT: vmv.v.x v9, a11179; RV32-NEXT: li a1, 561180; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1181; RV32-NEXT: vand.vv v8, v8, v10, v0.t1182; RV32-NEXT: vmul.vv v8, v8, v9, v0.t1183; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1184; RV32-NEXT: ret1185;1186; RV64-LABEL: vp_ctpop_nxv1i64:1187; RV64: # %bb.0:1188; RV64-NEXT: lui a1, 3495251189; RV64-NEXT: lui a2, 2097151190; RV64-NEXT: lui a3, 616811191; RV64-NEXT: lui a4, 41121192; RV64-NEXT: addi a1, a1, 13651193; RV64-NEXT: addi a2, a2, 8191194; RV64-NEXT: addi a3, a3, -2411195; RV64-NEXT: addi a4, a4, 2571196; RV64-NEXT: slli a5, a1, 321197; RV64-NEXT: add a1, a1, a51198; RV64-NEXT: slli a5, a2, 321199; RV64-NEXT: add a2, a2, a51200; RV64-NEXT: slli a5, a3, 321201; RV64-NEXT: add a3, a3, a51202; RV64-NEXT: slli a5, a4, 321203; RV64-NEXT: add a4, a4, a51204; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma1205; RV64-NEXT: vsrl.vi v9, v8, 1, v0.t1206; RV64-NEXT: vand.vx v9, v9, a1, v0.t1207; RV64-NEXT: vsub.vv v8, v8, v9, v0.t1208; RV64-NEXT: vand.vx v9, v8, a2, v0.t1209; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1210; RV64-NEXT: vand.vx v8, v8, a2, v0.t1211; RV64-NEXT: vadd.vv v8, v9, v8, v0.t1212; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t1213; RV64-NEXT: vadd.vv v8, v8, v9, v0.t1214; RV64-NEXT: vand.vx v8, v8, a3, v0.t1215; RV64-NEXT: li a0, 561216; RV64-NEXT: vmul.vx v8, v8, a4, v0.t1217; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1218; RV64-NEXT: ret1219;1220; CHECK-ZVBB-LABEL: vp_ctpop_nxv1i64:1221; CHECK-ZVBB: # %bb.0:1222; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma1223; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t1224; CHECK-ZVBB-NEXT: ret1225 %v = call <vscale x 1 x i64> @llvm.vp.ctpop.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl)1226 ret <vscale x 1 x i64> %v1227}1228 1229define <vscale x 1 x i64> @vp_ctpop_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {1230; RV32-LABEL: vp_ctpop_nxv1i64_unmasked:1231; RV32: # %bb.0:1232; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1233; RV32-NEXT: vsrl.vi v9, v8, 11234; RV32-NEXT: lui a1, 3495251235; RV32-NEXT: addi a1, a1, 13651236; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1237; RV32-NEXT: vmv.v.x v10, a11238; RV32-NEXT: lui a1, 2097151239; RV32-NEXT: addi a1, a1, 8191240; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1241; RV32-NEXT: vand.vv v9, v9, v101242; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1243; RV32-NEXT: vmv.v.x v10, a11244; RV32-NEXT: lui a1, 616811245; RV32-NEXT: addi a1, a1, -2411246; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1247; RV32-NEXT: vsub.vv v8, v8, v91248; RV32-NEXT: vand.vv v9, v8, v101249; RV32-NEXT: vsrl.vi v8, v8, 21250; RV32-NEXT: vand.vv v8, v8, v101251; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1252; RV32-NEXT: vmv.v.x v10, a11253; RV32-NEXT: lui a1, 41121254; RV32-NEXT: addi a1, a1, 2571255; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1256; RV32-NEXT: vadd.vv v8, v9, v81257; RV32-NEXT: vsrl.vi v9, v8, 41258; RV32-NEXT: vadd.vv v8, v8, v91259; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1260; RV32-NEXT: vmv.v.x v9, a11261; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1262; RV32-NEXT: vand.vv v8, v8, v101263; RV32-NEXT: vmul.vv v8, v8, v91264; RV32-NEXT: li a0, 561265; RV32-NEXT: vsrl.vx v8, v8, a01266; RV32-NEXT: ret1267;1268; RV64-LABEL: vp_ctpop_nxv1i64_unmasked:1269; RV64: # %bb.0:1270; RV64-NEXT: lui a1, 3495251271; RV64-NEXT: lui a2, 2097151272; RV64-NEXT: lui a3, 616811273; RV64-NEXT: lui a4, 41121274; RV64-NEXT: addi a1, a1, 13651275; RV64-NEXT: addi a2, a2, 8191276; RV64-NEXT: addi a3, a3, -2411277; RV64-NEXT: addi a4, a4, 2571278; RV64-NEXT: slli a5, a1, 321279; RV64-NEXT: add a1, a1, a51280; RV64-NEXT: slli a5, a2, 321281; RV64-NEXT: add a2, a2, a51282; RV64-NEXT: slli a5, a3, 321283; RV64-NEXT: add a3, a3, a51284; RV64-NEXT: slli a5, a4, 321285; RV64-NEXT: add a4, a4, a51286; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma1287; RV64-NEXT: vsrl.vi v9, v8, 11288; RV64-NEXT: vand.vx v9, v9, a11289; RV64-NEXT: vsub.vv v8, v8, v91290; RV64-NEXT: vand.vx v9, v8, a21291; RV64-NEXT: vsrl.vi v8, v8, 21292; RV64-NEXT: vand.vx v8, v8, a21293; RV64-NEXT: vadd.vv v8, v9, v81294; RV64-NEXT: vsrl.vi v9, v8, 41295; RV64-NEXT: vadd.vv v8, v8, v91296; RV64-NEXT: vand.vx v8, v8, a31297; RV64-NEXT: vmul.vx v8, v8, a41298; RV64-NEXT: li a0, 561299; RV64-NEXT: vsrl.vx v8, v8, a01300; RV64-NEXT: ret1301;1302; CHECK-ZVBB-LABEL: vp_ctpop_nxv1i64_unmasked:1303; CHECK-ZVBB: # %bb.0:1304; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma1305; CHECK-ZVBB-NEXT: vcpop.v v8, v81306; CHECK-ZVBB-NEXT: ret1307 %v = call <vscale x 1 x i64> @llvm.vp.ctpop.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)1308 ret <vscale x 1 x i64> %v1309}1310 1311define <vscale x 2 x i64> @vp_ctpop_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1312; RV32-LABEL: vp_ctpop_nxv2i64:1313; RV32: # %bb.0:1314; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1315; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t1316; RV32-NEXT: lui a1, 3495251317; RV32-NEXT: addi a1, a1, 13651318; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1319; RV32-NEXT: vmv.v.x v12, a11320; RV32-NEXT: lui a1, 2097151321; RV32-NEXT: addi a1, a1, 8191322; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1323; RV32-NEXT: vand.vv v10, v10, v12, v0.t1324; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1325; RV32-NEXT: vmv.v.x v12, a11326; RV32-NEXT: lui a1, 616811327; RV32-NEXT: addi a1, a1, -2411328; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1329; RV32-NEXT: vsub.vv v8, v8, v10, v0.t1330; RV32-NEXT: vand.vv v10, v8, v12, v0.t1331; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t1332; RV32-NEXT: vand.vv v8, v8, v12, v0.t1333; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1334; RV32-NEXT: vmv.v.x v12, a11335; RV32-NEXT: lui a1, 41121336; RV32-NEXT: addi a1, a1, 2571337; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1338; RV32-NEXT: vadd.vv v8, v10, v8, v0.t1339; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t1340; RV32-NEXT: vadd.vv v8, v8, v10, v0.t1341; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1342; RV32-NEXT: vmv.v.x v10, a11343; RV32-NEXT: li a1, 561344; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1345; RV32-NEXT: vand.vv v8, v8, v12, v0.t1346; RV32-NEXT: vmul.vv v8, v8, v10, v0.t1347; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1348; RV32-NEXT: ret1349;1350; RV64-LABEL: vp_ctpop_nxv2i64:1351; RV64: # %bb.0:1352; RV64-NEXT: lui a1, 3495251353; RV64-NEXT: lui a2, 2097151354; RV64-NEXT: lui a3, 616811355; RV64-NEXT: lui a4, 41121356; RV64-NEXT: addi a1, a1, 13651357; RV64-NEXT: addi a2, a2, 8191358; RV64-NEXT: addi a3, a3, -2411359; RV64-NEXT: addi a4, a4, 2571360; RV64-NEXT: slli a5, a1, 321361; RV64-NEXT: add a1, a1, a51362; RV64-NEXT: slli a5, a2, 321363; RV64-NEXT: add a2, a2, a51364; RV64-NEXT: slli a5, a3, 321365; RV64-NEXT: add a3, a3, a51366; RV64-NEXT: slli a5, a4, 321367; RV64-NEXT: add a4, a4, a51368; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma1369; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t1370; RV64-NEXT: vand.vx v10, v10, a1, v0.t1371; RV64-NEXT: vsub.vv v8, v8, v10, v0.t1372; RV64-NEXT: vand.vx v10, v8, a2, v0.t1373; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1374; RV64-NEXT: vand.vx v8, v8, a2, v0.t1375; RV64-NEXT: vadd.vv v8, v10, v8, v0.t1376; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t1377; RV64-NEXT: vadd.vv v8, v8, v10, v0.t1378; RV64-NEXT: vand.vx v8, v8, a3, v0.t1379; RV64-NEXT: li a0, 561380; RV64-NEXT: vmul.vx v8, v8, a4, v0.t1381; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1382; RV64-NEXT: ret1383;1384; CHECK-ZVBB-LABEL: vp_ctpop_nxv2i64:1385; CHECK-ZVBB: # %bb.0:1386; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma1387; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t1388; CHECK-ZVBB-NEXT: ret1389 %v = call <vscale x 2 x i64> @llvm.vp.ctpop.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl)1390 ret <vscale x 2 x i64> %v1391}1392 1393define <vscale x 2 x i64> @vp_ctpop_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {1394; RV32-LABEL: vp_ctpop_nxv2i64_unmasked:1395; RV32: # %bb.0:1396; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1397; RV32-NEXT: vsrl.vi v10, v8, 11398; RV32-NEXT: lui a1, 3495251399; RV32-NEXT: addi a1, a1, 13651400; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1401; RV32-NEXT: vmv.v.x v12, a11402; RV32-NEXT: lui a1, 2097151403; RV32-NEXT: addi a1, a1, 8191404; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1405; RV32-NEXT: vand.vv v10, v10, v121406; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1407; RV32-NEXT: vmv.v.x v12, a11408; RV32-NEXT: lui a1, 616811409; RV32-NEXT: addi a1, a1, -2411410; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1411; RV32-NEXT: vsub.vv v8, v8, v101412; RV32-NEXT: vand.vv v10, v8, v121413; RV32-NEXT: vsrl.vi v8, v8, 21414; RV32-NEXT: vand.vv v8, v8, v121415; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1416; RV32-NEXT: vmv.v.x v12, a11417; RV32-NEXT: lui a1, 41121418; RV32-NEXT: addi a1, a1, 2571419; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1420; RV32-NEXT: vadd.vv v8, v10, v81421; RV32-NEXT: vsrl.vi v10, v8, 41422; RV32-NEXT: vadd.vv v8, v8, v101423; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1424; RV32-NEXT: vmv.v.x v10, a11425; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1426; RV32-NEXT: vand.vv v8, v8, v121427; RV32-NEXT: vmul.vv v8, v8, v101428; RV32-NEXT: li a0, 561429; RV32-NEXT: vsrl.vx v8, v8, a01430; RV32-NEXT: ret1431;1432; RV64-LABEL: vp_ctpop_nxv2i64_unmasked:1433; RV64: # %bb.0:1434; RV64-NEXT: lui a1, 3495251435; RV64-NEXT: lui a2, 2097151436; RV64-NEXT: lui a3, 616811437; RV64-NEXT: lui a4, 41121438; RV64-NEXT: addi a1, a1, 13651439; RV64-NEXT: addi a2, a2, 8191440; RV64-NEXT: addi a3, a3, -2411441; RV64-NEXT: addi a4, a4, 2571442; RV64-NEXT: slli a5, a1, 321443; RV64-NEXT: add a1, a1, a51444; RV64-NEXT: slli a5, a2, 321445; RV64-NEXT: add a2, a2, a51446; RV64-NEXT: slli a5, a3, 321447; RV64-NEXT: add a3, a3, a51448; RV64-NEXT: slli a5, a4, 321449; RV64-NEXT: add a4, a4, a51450; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma1451; RV64-NEXT: vsrl.vi v10, v8, 11452; RV64-NEXT: vand.vx v10, v10, a11453; RV64-NEXT: vsub.vv v8, v8, v101454; RV64-NEXT: vand.vx v10, v8, a21455; RV64-NEXT: vsrl.vi v8, v8, 21456; RV64-NEXT: vand.vx v8, v8, a21457; RV64-NEXT: vadd.vv v8, v10, v81458; RV64-NEXT: vsrl.vi v10, v8, 41459; RV64-NEXT: vadd.vv v8, v8, v101460; RV64-NEXT: vand.vx v8, v8, a31461; RV64-NEXT: vmul.vx v8, v8, a41462; RV64-NEXT: li a0, 561463; RV64-NEXT: vsrl.vx v8, v8, a01464; RV64-NEXT: ret1465;1466; CHECK-ZVBB-LABEL: vp_ctpop_nxv2i64_unmasked:1467; CHECK-ZVBB: # %bb.0:1468; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma1469; CHECK-ZVBB-NEXT: vcpop.v v8, v81470; CHECK-ZVBB-NEXT: ret1471 %v = call <vscale x 2 x i64> @llvm.vp.ctpop.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)1472 ret <vscale x 2 x i64> %v1473}1474 1475define <vscale x 4 x i64> @vp_ctpop_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1476; RV32-LABEL: vp_ctpop_nxv4i64:1477; RV32: # %bb.0:1478; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1479; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t1480; RV32-NEXT: lui a1, 3495251481; RV32-NEXT: addi a1, a1, 13651482; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1483; RV32-NEXT: vmv.v.x v16, a11484; RV32-NEXT: lui a1, 2097151485; RV32-NEXT: addi a1, a1, 8191486; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1487; RV32-NEXT: vand.vv v16, v12, v16, v0.t1488; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1489; RV32-NEXT: vmv.v.x v12, a11490; RV32-NEXT: lui a1, 616811491; RV32-NEXT: addi a1, a1, -2411492; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1493; RV32-NEXT: vsub.vv v8, v8, v16, v0.t1494; RV32-NEXT: vand.vv v16, v8, v12, v0.t1495; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t1496; RV32-NEXT: vand.vv v8, v8, v12, v0.t1497; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1498; RV32-NEXT: vmv.v.x v12, a11499; RV32-NEXT: lui a1, 41121500; RV32-NEXT: addi a1, a1, 2571501; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1502; RV32-NEXT: vadd.vv v8, v16, v8, v0.t1503; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t1504; RV32-NEXT: vadd.vv v8, v8, v16, v0.t1505; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1506; RV32-NEXT: vmv.v.x v16, a11507; RV32-NEXT: li a1, 561508; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1509; RV32-NEXT: vand.vv v8, v8, v12, v0.t1510; RV32-NEXT: vmul.vv v8, v8, v16, v0.t1511; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1512; RV32-NEXT: ret1513;1514; RV64-LABEL: vp_ctpop_nxv4i64:1515; RV64: # %bb.0:1516; RV64-NEXT: lui a1, 3495251517; RV64-NEXT: lui a2, 2097151518; RV64-NEXT: lui a3, 616811519; RV64-NEXT: lui a4, 41121520; RV64-NEXT: addi a1, a1, 13651521; RV64-NEXT: addi a2, a2, 8191522; RV64-NEXT: addi a3, a3, -2411523; RV64-NEXT: addi a4, a4, 2571524; RV64-NEXT: slli a5, a1, 321525; RV64-NEXT: add a1, a1, a51526; RV64-NEXT: slli a5, a2, 321527; RV64-NEXT: add a2, a2, a51528; RV64-NEXT: slli a5, a3, 321529; RV64-NEXT: add a3, a3, a51530; RV64-NEXT: slli a5, a4, 321531; RV64-NEXT: add a4, a4, a51532; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma1533; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t1534; RV64-NEXT: vand.vx v12, v12, a1, v0.t1535; RV64-NEXT: vsub.vv v8, v8, v12, v0.t1536; RV64-NEXT: vand.vx v12, v8, a2, v0.t1537; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1538; RV64-NEXT: vand.vx v8, v8, a2, v0.t1539; RV64-NEXT: vadd.vv v8, v12, v8, v0.t1540; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t1541; RV64-NEXT: vadd.vv v8, v8, v12, v0.t1542; RV64-NEXT: vand.vx v8, v8, a3, v0.t1543; RV64-NEXT: li a0, 561544; RV64-NEXT: vmul.vx v8, v8, a4, v0.t1545; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1546; RV64-NEXT: ret1547;1548; CHECK-ZVBB-LABEL: vp_ctpop_nxv4i64:1549; CHECK-ZVBB: # %bb.0:1550; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma1551; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t1552; CHECK-ZVBB-NEXT: ret1553 %v = call <vscale x 4 x i64> @llvm.vp.ctpop.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl)1554 ret <vscale x 4 x i64> %v1555}1556 1557define <vscale x 4 x i64> @vp_ctpop_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {1558; RV32-LABEL: vp_ctpop_nxv4i64_unmasked:1559; RV32: # %bb.0:1560; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1561; RV32-NEXT: vsrl.vi v12, v8, 11562; RV32-NEXT: lui a1, 3495251563; RV32-NEXT: addi a1, a1, 13651564; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1565; RV32-NEXT: vmv.v.x v16, a11566; RV32-NEXT: lui a1, 2097151567; RV32-NEXT: addi a1, a1, 8191568; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1569; RV32-NEXT: vand.vv v12, v12, v161570; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1571; RV32-NEXT: vmv.v.x v16, a11572; RV32-NEXT: lui a1, 616811573; RV32-NEXT: addi a1, a1, -2411574; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1575; RV32-NEXT: vsub.vv v8, v8, v121576; RV32-NEXT: vand.vv v12, v8, v161577; RV32-NEXT: vsrl.vi v8, v8, 21578; RV32-NEXT: vand.vv v8, v8, v161579; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1580; RV32-NEXT: vmv.v.x v16, a11581; RV32-NEXT: lui a1, 41121582; RV32-NEXT: addi a1, a1, 2571583; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1584; RV32-NEXT: vadd.vv v8, v12, v81585; RV32-NEXT: vsrl.vi v12, v8, 41586; RV32-NEXT: vadd.vv v8, v8, v121587; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1588; RV32-NEXT: vmv.v.x v12, a11589; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1590; RV32-NEXT: vand.vv v8, v8, v161591; RV32-NEXT: vmul.vv v8, v8, v121592; RV32-NEXT: li a0, 561593; RV32-NEXT: vsrl.vx v8, v8, a01594; RV32-NEXT: ret1595;1596; RV64-LABEL: vp_ctpop_nxv4i64_unmasked:1597; RV64: # %bb.0:1598; RV64-NEXT: lui a1, 3495251599; RV64-NEXT: lui a2, 2097151600; RV64-NEXT: lui a3, 616811601; RV64-NEXT: lui a4, 41121602; RV64-NEXT: addi a1, a1, 13651603; RV64-NEXT: addi a2, a2, 8191604; RV64-NEXT: addi a3, a3, -2411605; RV64-NEXT: addi a4, a4, 2571606; RV64-NEXT: slli a5, a1, 321607; RV64-NEXT: add a1, a1, a51608; RV64-NEXT: slli a5, a2, 321609; RV64-NEXT: add a2, a2, a51610; RV64-NEXT: slli a5, a3, 321611; RV64-NEXT: add a3, a3, a51612; RV64-NEXT: slli a5, a4, 321613; RV64-NEXT: add a4, a4, a51614; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma1615; RV64-NEXT: vsrl.vi v12, v8, 11616; RV64-NEXT: vand.vx v12, v12, a11617; RV64-NEXT: vsub.vv v8, v8, v121618; RV64-NEXT: vand.vx v12, v8, a21619; RV64-NEXT: vsrl.vi v8, v8, 21620; RV64-NEXT: vand.vx v8, v8, a21621; RV64-NEXT: vadd.vv v8, v12, v81622; RV64-NEXT: vsrl.vi v12, v8, 41623; RV64-NEXT: vadd.vv v8, v8, v121624; RV64-NEXT: vand.vx v8, v8, a31625; RV64-NEXT: vmul.vx v8, v8, a41626; RV64-NEXT: li a0, 561627; RV64-NEXT: vsrl.vx v8, v8, a01628; RV64-NEXT: ret1629;1630; CHECK-ZVBB-LABEL: vp_ctpop_nxv4i64_unmasked:1631; CHECK-ZVBB: # %bb.0:1632; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma1633; CHECK-ZVBB-NEXT: vcpop.v v8, v81634; CHECK-ZVBB-NEXT: ret1635 %v = call <vscale x 4 x i64> @llvm.vp.ctpop.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)1636 ret <vscale x 4 x i64> %v1637}1638 1639define <vscale x 7 x i64> @vp_ctpop_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {1640; RV32-LABEL: vp_ctpop_nxv7i64:1641; RV32: # %bb.0:1642; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1643; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t1644; RV32-NEXT: lui a1, 3495251645; RV32-NEXT: addi a1, a1, 13651646; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1647; RV32-NEXT: vmv.v.x v24, a11648; RV32-NEXT: lui a1, 2097151649; RV32-NEXT: addi a1, a1, 8191650; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1651; RV32-NEXT: vand.vv v24, v16, v24, v0.t1652; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1653; RV32-NEXT: vmv.v.x v16, a11654; RV32-NEXT: lui a1, 616811655; RV32-NEXT: addi a1, a1, -2411656; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1657; RV32-NEXT: vsub.vv v8, v8, v24, v0.t1658; RV32-NEXT: vand.vv v24, v8, v16, v0.t1659; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t1660; RV32-NEXT: vand.vv v16, v8, v16, v0.t1661; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1662; RV32-NEXT: vmv.v.x v8, a11663; RV32-NEXT: lui a1, 41121664; RV32-NEXT: addi a1, a1, 2571665; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1666; RV32-NEXT: vadd.vv v16, v24, v16, v0.t1667; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t1668; RV32-NEXT: vadd.vv v16, v16, v24, v0.t1669; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1670; RV32-NEXT: vmv.v.x v24, a11671; RV32-NEXT: li a1, 561672; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1673; RV32-NEXT: vand.vv v8, v16, v8, v0.t1674; RV32-NEXT: vmul.vv v8, v8, v24, v0.t1675; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1676; RV32-NEXT: ret1677;1678; RV64-LABEL: vp_ctpop_nxv7i64:1679; RV64: # %bb.0:1680; RV64-NEXT: lui a1, 3495251681; RV64-NEXT: lui a2, 2097151682; RV64-NEXT: lui a3, 616811683; RV64-NEXT: lui a4, 41121684; RV64-NEXT: addi a1, a1, 13651685; RV64-NEXT: addi a2, a2, 8191686; RV64-NEXT: addi a3, a3, -2411687; RV64-NEXT: addi a4, a4, 2571688; RV64-NEXT: slli a5, a1, 321689; RV64-NEXT: add a1, a1, a51690; RV64-NEXT: slli a5, a2, 321691; RV64-NEXT: add a2, a2, a51692; RV64-NEXT: slli a5, a3, 321693; RV64-NEXT: add a3, a3, a51694; RV64-NEXT: slli a5, a4, 321695; RV64-NEXT: add a4, a4, a51696; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1697; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t1698; RV64-NEXT: vand.vx v16, v16, a1, v0.t1699; RV64-NEXT: vsub.vv v8, v8, v16, v0.t1700; RV64-NEXT: vand.vx v16, v8, a2, v0.t1701; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1702; RV64-NEXT: vand.vx v8, v8, a2, v0.t1703; RV64-NEXT: vadd.vv v8, v16, v8, v0.t1704; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t1705; RV64-NEXT: vadd.vv v8, v8, v16, v0.t1706; RV64-NEXT: vand.vx v8, v8, a3, v0.t1707; RV64-NEXT: li a0, 561708; RV64-NEXT: vmul.vx v8, v8, a4, v0.t1709; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1710; RV64-NEXT: ret1711;1712; CHECK-ZVBB-LABEL: vp_ctpop_nxv7i64:1713; CHECK-ZVBB: # %bb.0:1714; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma1715; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t1716; CHECK-ZVBB-NEXT: ret1717 %v = call <vscale x 7 x i64> @llvm.vp.ctpop.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 %evl)1718 ret <vscale x 7 x i64> %v1719}1720 1721define <vscale x 7 x i64> @vp_ctpop_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {1722; RV32-LABEL: vp_ctpop_nxv7i64_unmasked:1723; RV32: # %bb.0:1724; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1725; RV32-NEXT: vsrl.vi v16, v8, 11726; RV32-NEXT: lui a1, 3495251727; RV32-NEXT: addi a1, a1, 13651728; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1729; RV32-NEXT: vmv.v.x v24, a11730; RV32-NEXT: lui a1, 2097151731; RV32-NEXT: addi a1, a1, 8191732; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1733; RV32-NEXT: vand.vv v24, v16, v241734; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1735; RV32-NEXT: vmv.v.x v16, a11736; RV32-NEXT: lui a1, 616811737; RV32-NEXT: addi a1, a1, -2411738; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1739; RV32-NEXT: vsub.vv v8, v8, v241740; RV32-NEXT: vand.vv v24, v8, v161741; RV32-NEXT: vsrl.vi v8, v8, 21742; RV32-NEXT: vand.vv v8, v8, v161743; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1744; RV32-NEXT: vmv.v.x v16, a11745; RV32-NEXT: lui a1, 41121746; RV32-NEXT: addi a1, a1, 2571747; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1748; RV32-NEXT: vadd.vv v8, v24, v81749; RV32-NEXT: vsrl.vi v24, v8, 41750; RV32-NEXT: vadd.vv v8, v8, v241751; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1752; RV32-NEXT: vmv.v.x v24, a11753; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1754; RV32-NEXT: vand.vv v8, v8, v161755; RV32-NEXT: vmul.vv v8, v8, v241756; RV32-NEXT: li a0, 561757; RV32-NEXT: vsrl.vx v8, v8, a01758; RV32-NEXT: ret1759;1760; RV64-LABEL: vp_ctpop_nxv7i64_unmasked:1761; RV64: # %bb.0:1762; RV64-NEXT: lui a1, 3495251763; RV64-NEXT: lui a2, 2097151764; RV64-NEXT: lui a3, 616811765; RV64-NEXT: lui a4, 41121766; RV64-NEXT: addi a1, a1, 13651767; RV64-NEXT: addi a2, a2, 8191768; RV64-NEXT: addi a3, a3, -2411769; RV64-NEXT: addi a4, a4, 2571770; RV64-NEXT: slli a5, a1, 321771; RV64-NEXT: add a1, a1, a51772; RV64-NEXT: slli a5, a2, 321773; RV64-NEXT: add a2, a2, a51774; RV64-NEXT: slli a5, a3, 321775; RV64-NEXT: add a3, a3, a51776; RV64-NEXT: slli a5, a4, 321777; RV64-NEXT: add a4, a4, a51778; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1779; RV64-NEXT: vsrl.vi v16, v8, 11780; RV64-NEXT: vand.vx v16, v16, a11781; RV64-NEXT: vsub.vv v8, v8, v161782; RV64-NEXT: vand.vx v16, v8, a21783; RV64-NEXT: vsrl.vi v8, v8, 21784; RV64-NEXT: vand.vx v8, v8, a21785; RV64-NEXT: vadd.vv v8, v16, v81786; RV64-NEXT: vsrl.vi v16, v8, 41787; RV64-NEXT: vadd.vv v8, v8, v161788; RV64-NEXT: vand.vx v8, v8, a31789; RV64-NEXT: vmul.vx v8, v8, a41790; RV64-NEXT: li a0, 561791; RV64-NEXT: vsrl.vx v8, v8, a01792; RV64-NEXT: ret1793;1794; CHECK-ZVBB-LABEL: vp_ctpop_nxv7i64_unmasked:1795; CHECK-ZVBB: # %bb.0:1796; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma1797; CHECK-ZVBB-NEXT: vcpop.v v8, v81798; CHECK-ZVBB-NEXT: ret1799 %v = call <vscale x 7 x i64> @llvm.vp.ctpop.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> splat (i1 true), i32 %evl)1800 ret <vscale x 7 x i64> %v1801}1802 1803define <vscale x 8 x i64> @vp_ctpop_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1804; RV32-LABEL: vp_ctpop_nxv8i64:1805; RV32: # %bb.0:1806; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1807; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t1808; RV32-NEXT: lui a1, 3495251809; RV32-NEXT: addi a1, a1, 13651810; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1811; RV32-NEXT: vmv.v.x v24, a11812; RV32-NEXT: lui a1, 2097151813; RV32-NEXT: addi a1, a1, 8191814; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1815; RV32-NEXT: vand.vv v24, v16, v24, v0.t1816; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1817; RV32-NEXT: vmv.v.x v16, a11818; RV32-NEXT: lui a1, 616811819; RV32-NEXT: addi a1, a1, -2411820; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1821; RV32-NEXT: vsub.vv v8, v8, v24, v0.t1822; RV32-NEXT: vand.vv v24, v8, v16, v0.t1823; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t1824; RV32-NEXT: vand.vv v16, v8, v16, v0.t1825; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1826; RV32-NEXT: vmv.v.x v8, a11827; RV32-NEXT: lui a1, 41121828; RV32-NEXT: addi a1, a1, 2571829; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1830; RV32-NEXT: vadd.vv v16, v24, v16, v0.t1831; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t1832; RV32-NEXT: vadd.vv v16, v16, v24, v0.t1833; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1834; RV32-NEXT: vmv.v.x v24, a11835; RV32-NEXT: li a1, 561836; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1837; RV32-NEXT: vand.vv v8, v16, v8, v0.t1838; RV32-NEXT: vmul.vv v8, v8, v24, v0.t1839; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1840; RV32-NEXT: ret1841;1842; RV64-LABEL: vp_ctpop_nxv8i64:1843; RV64: # %bb.0:1844; RV64-NEXT: lui a1, 3495251845; RV64-NEXT: lui a2, 2097151846; RV64-NEXT: lui a3, 616811847; RV64-NEXT: lui a4, 41121848; RV64-NEXT: addi a1, a1, 13651849; RV64-NEXT: addi a2, a2, 8191850; RV64-NEXT: addi a3, a3, -2411851; RV64-NEXT: addi a4, a4, 2571852; RV64-NEXT: slli a5, a1, 321853; RV64-NEXT: add a1, a1, a51854; RV64-NEXT: slli a5, a2, 321855; RV64-NEXT: add a2, a2, a51856; RV64-NEXT: slli a5, a3, 321857; RV64-NEXT: add a3, a3, a51858; RV64-NEXT: slli a5, a4, 321859; RV64-NEXT: add a4, a4, a51860; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1861; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t1862; RV64-NEXT: vand.vx v16, v16, a1, v0.t1863; RV64-NEXT: vsub.vv v8, v8, v16, v0.t1864; RV64-NEXT: vand.vx v16, v8, a2, v0.t1865; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1866; RV64-NEXT: vand.vx v8, v8, a2, v0.t1867; RV64-NEXT: vadd.vv v8, v16, v8, v0.t1868; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t1869; RV64-NEXT: vadd.vv v8, v8, v16, v0.t1870; RV64-NEXT: vand.vx v8, v8, a3, v0.t1871; RV64-NEXT: li a0, 561872; RV64-NEXT: vmul.vx v8, v8, a4, v0.t1873; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1874; RV64-NEXT: ret1875;1876; CHECK-ZVBB-LABEL: vp_ctpop_nxv8i64:1877; CHECK-ZVBB: # %bb.0:1878; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma1879; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t1880; CHECK-ZVBB-NEXT: ret1881 %v = call <vscale x 8 x i64> @llvm.vp.ctpop.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl)1882 ret <vscale x 8 x i64> %v1883}1884 1885define <vscale x 8 x i64> @vp_ctpop_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {1886; RV32-LABEL: vp_ctpop_nxv8i64_unmasked:1887; RV32: # %bb.0:1888; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1889; RV32-NEXT: vsrl.vi v16, v8, 11890; RV32-NEXT: lui a1, 3495251891; RV32-NEXT: addi a1, a1, 13651892; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1893; RV32-NEXT: vmv.v.x v24, a11894; RV32-NEXT: lui a1, 2097151895; RV32-NEXT: addi a1, a1, 8191896; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1897; RV32-NEXT: vand.vv v24, v16, v241898; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1899; RV32-NEXT: vmv.v.x v16, a11900; RV32-NEXT: lui a1, 616811901; RV32-NEXT: addi a1, a1, -2411902; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1903; RV32-NEXT: vsub.vv v8, v8, v241904; RV32-NEXT: vand.vv v24, v8, v161905; RV32-NEXT: vsrl.vi v8, v8, 21906; RV32-NEXT: vand.vv v8, v8, v161907; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1908; RV32-NEXT: vmv.v.x v16, a11909; RV32-NEXT: lui a1, 41121910; RV32-NEXT: addi a1, a1, 2571911; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1912; RV32-NEXT: vadd.vv v8, v24, v81913; RV32-NEXT: vsrl.vi v24, v8, 41914; RV32-NEXT: vadd.vv v8, v8, v241915; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1916; RV32-NEXT: vmv.v.x v24, a11917; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1918; RV32-NEXT: vand.vv v8, v8, v161919; RV32-NEXT: vmul.vv v8, v8, v241920; RV32-NEXT: li a0, 561921; RV32-NEXT: vsrl.vx v8, v8, a01922; RV32-NEXT: ret1923;1924; RV64-LABEL: vp_ctpop_nxv8i64_unmasked:1925; RV64: # %bb.0:1926; RV64-NEXT: lui a1, 3495251927; RV64-NEXT: lui a2, 2097151928; RV64-NEXT: lui a3, 616811929; RV64-NEXT: lui a4, 41121930; RV64-NEXT: addi a1, a1, 13651931; RV64-NEXT: addi a2, a2, 8191932; RV64-NEXT: addi a3, a3, -2411933; RV64-NEXT: addi a4, a4, 2571934; RV64-NEXT: slli a5, a1, 321935; RV64-NEXT: add a1, a1, a51936; RV64-NEXT: slli a5, a2, 321937; RV64-NEXT: add a2, a2, a51938; RV64-NEXT: slli a5, a3, 321939; RV64-NEXT: add a3, a3, a51940; RV64-NEXT: slli a5, a4, 321941; RV64-NEXT: add a4, a4, a51942; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1943; RV64-NEXT: vsrl.vi v16, v8, 11944; RV64-NEXT: vand.vx v16, v16, a11945; RV64-NEXT: vsub.vv v8, v8, v161946; RV64-NEXT: vand.vx v16, v8, a21947; RV64-NEXT: vsrl.vi v8, v8, 21948; RV64-NEXT: vand.vx v8, v8, a21949; RV64-NEXT: vadd.vv v8, v16, v81950; RV64-NEXT: vsrl.vi v16, v8, 41951; RV64-NEXT: vadd.vv v8, v8, v161952; RV64-NEXT: vand.vx v8, v8, a31953; RV64-NEXT: vmul.vx v8, v8, a41954; RV64-NEXT: li a0, 561955; RV64-NEXT: vsrl.vx v8, v8, a01956; RV64-NEXT: ret1957;1958; CHECK-ZVBB-LABEL: vp_ctpop_nxv8i64_unmasked:1959; CHECK-ZVBB: # %bb.0:1960; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma1961; CHECK-ZVBB-NEXT: vcpop.v v8, v81962; CHECK-ZVBB-NEXT: ret1963 %v = call <vscale x 8 x i64> @llvm.vp.ctpop.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)1964 ret <vscale x 8 x i64> %v1965}1966 1967define <vscale x 16 x i64> @vp_ctpop_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1968; RV32-LABEL: vp_ctpop_nxv16i64:1969; RV32: # %bb.0:1970; RV32-NEXT: addi sp, sp, -161971; RV32-NEXT: .cfi_def_cfa_offset 161972; RV32-NEXT: csrr a1, vlenb1973; RV32-NEXT: li a2, 481974; RV32-NEXT: mul a1, a1, a21975; RV32-NEXT: sub sp, sp, a11976; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb1977; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, ma1978; RV32-NEXT: vmv1r.v v7, v01979; RV32-NEXT: csrr a1, vlenb1980; RV32-NEXT: li a2, 401981; RV32-NEXT: mul a1, a1, a21982; RV32-NEXT: add a1, sp, a11983; RV32-NEXT: addi a1, a1, 161984; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1985; RV32-NEXT: csrr a1, vlenb1986; RV32-NEXT: lui a2, 3495251987; RV32-NEXT: srli a3, a1, 31988; RV32-NEXT: vslidedown.vx v0, v0, a31989; RV32-NEXT: sub a3, a0, a11990; RV32-NEXT: addi a2, a2, 13651991; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma1992; RV32-NEXT: vmv.v.x v24, a21993; RV32-NEXT: sltu a2, a0, a31994; RV32-NEXT: addi a2, a2, -11995; RV32-NEXT: and a2, a2, a31996; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1997; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t1998; RV32-NEXT: csrr a3, vlenb1999; RV32-NEXT: slli a3, a3, 52000; RV32-NEXT: add a3, sp, a32001; RV32-NEXT: addi a3, a3, 162002; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill2003; RV32-NEXT: vand.vv v8, v8, v24, v0.t2004; RV32-NEXT: vsub.vv v8, v16, v8, v0.t2005; RV32-NEXT: lui a3, 2097152006; RV32-NEXT: addi a3, a3, 8192007; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2008; RV32-NEXT: vmv.v.x v24, a32009; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2010; RV32-NEXT: vand.vv v16, v8, v24, v0.t2011; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t2012; RV32-NEXT: csrr a3, vlenb2013; RV32-NEXT: li a4, 242014; RV32-NEXT: mul a3, a3, a42015; RV32-NEXT: add a3, sp, a32016; RV32-NEXT: addi a3, a3, 162017; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill2018; RV32-NEXT: vand.vv v8, v8, v24, v0.t2019; RV32-NEXT: vadd.vv v8, v16, v8, v0.t2020; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t2021; RV32-NEXT: vadd.vv v8, v8, v16, v0.t2022; RV32-NEXT: lui a3, 616812023; RV32-NEXT: addi a3, a3, -2412024; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2025; RV32-NEXT: vmv.v.x v16, a32026; RV32-NEXT: csrr a3, vlenb2027; RV32-NEXT: slli a3, a3, 42028; RV32-NEXT: add a3, sp, a32029; RV32-NEXT: addi a3, a3, 162030; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill2031; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2032; RV32-NEXT: vand.vv v16, v8, v16, v0.t2033; RV32-NEXT: lui a3, 41122034; RV32-NEXT: addi a3, a3, 2572035; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2036; RV32-NEXT: vmv.v.x v8, a32037; RV32-NEXT: csrr a3, vlenb2038; RV32-NEXT: slli a3, a3, 32039; RV32-NEXT: add a3, sp, a32040; RV32-NEXT: addi a3, a3, 162041; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill2042; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2043; RV32-NEXT: vmul.vv v16, v16, v8, v0.t2044; RV32-NEXT: li a2, 562045; RV32-NEXT: vsrl.vx v8, v16, a2, v0.t2046; RV32-NEXT: addi a3, sp, 162047; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill2048; RV32-NEXT: bltu a0, a1, .LBB46_22049; RV32-NEXT: # %bb.1:2050; RV32-NEXT: mv a0, a12051; RV32-NEXT: .LBB46_2:2052; RV32-NEXT: vmv1r.v v0, v72053; RV32-NEXT: li a3, 402054; RV32-NEXT: mul a1, a1, a32055; RV32-NEXT: add a1, sp, a12056; RV32-NEXT: addi a1, a1, 162057; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload2058; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2059; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t2060; RV32-NEXT: csrr a0, vlenb2061; RV32-NEXT: slli a0, a0, 52062; RV32-NEXT: add a0, sp, a02063; RV32-NEXT: addi a0, a0, 162064; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload2065; RV32-NEXT: vand.vv v16, v16, v24, v0.t2066; RV32-NEXT: vsub.vv v16, v8, v16, v0.t2067; RV32-NEXT: csrr a0, vlenb2068; RV32-NEXT: li a1, 242069; RV32-NEXT: mul a0, a0, a12070; RV32-NEXT: add a0, sp, a02071; RV32-NEXT: addi a0, a0, 162072; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload2073; RV32-NEXT: vand.vv v8, v16, v24, v0.t2074; RV32-NEXT: vsrl.vi v16, v16, 2, v0.t2075; RV32-NEXT: vand.vv v16, v16, v24, v0.t2076; RV32-NEXT: vadd.vv v8, v8, v16, v0.t2077; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t2078; RV32-NEXT: vadd.vv v8, v8, v16, v0.t2079; RV32-NEXT: csrr a0, vlenb2080; RV32-NEXT: slli a0, a0, 42081; RV32-NEXT: add a0, sp, a02082; RV32-NEXT: addi a0, a0, 162083; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2084; RV32-NEXT: vand.vv v8, v8, v16, v0.t2085; RV32-NEXT: csrr a0, vlenb2086; RV32-NEXT: slli a0, a0, 32087; RV32-NEXT: add a0, sp, a02088; RV32-NEXT: addi a0, a0, 162089; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2090; RV32-NEXT: vmul.vv v8, v8, v16, v0.t2091; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t2092; RV32-NEXT: addi a0, sp, 162093; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2094; RV32-NEXT: csrr a0, vlenb2095; RV32-NEXT: li a1, 482096; RV32-NEXT: mul a0, a0, a12097; RV32-NEXT: add sp, sp, a02098; RV32-NEXT: .cfi_def_cfa sp, 162099; RV32-NEXT: addi sp, sp, 162100; RV32-NEXT: .cfi_def_cfa_offset 02101; RV32-NEXT: ret2102;2103; RV64-LABEL: vp_ctpop_nxv16i64:2104; RV64: # %bb.0:2105; RV64-NEXT: csrr a1, vlenb2106; RV64-NEXT: srli a2, a1, 32107; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma2108; RV64-NEXT: vslidedown.vx v7, v0, a22109; RV64-NEXT: mv a2, a02110; RV64-NEXT: bltu a0, a1, .LBB46_22111; RV64-NEXT: # %bb.1:2112; RV64-NEXT: mv a2, a12113; RV64-NEXT: .LBB46_2:2114; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma2115; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t2116; RV64-NEXT: lui a2, 3495252117; RV64-NEXT: lui a3, 2097152118; RV64-NEXT: lui a4, 616812119; RV64-NEXT: lui a5, 41122120; RV64-NEXT: addi a2, a2, 13652121; RV64-NEXT: addi a3, a3, 8192122; RV64-NEXT: addi a4, a4, -2412123; RV64-NEXT: addi a5, a5, 2572124; RV64-NEXT: slli a6, a2, 322125; RV64-NEXT: add a2, a2, a62126; RV64-NEXT: slli a6, a3, 322127; RV64-NEXT: add a3, a3, a62128; RV64-NEXT: slli a6, a4, 322129; RV64-NEXT: add a4, a4, a62130; RV64-NEXT: slli a6, a5, 322131; RV64-NEXT: add a5, a5, a62132; RV64-NEXT: li a6, 562133; RV64-NEXT: sub a1, a0, a12134; RV64-NEXT: sltu a0, a0, a12135; RV64-NEXT: addi a0, a0, -12136; RV64-NEXT: and a0, a0, a12137; RV64-NEXT: vand.vx v24, v24, a2, v0.t2138; RV64-NEXT: vsub.vv v8, v8, v24, v0.t2139; RV64-NEXT: vand.vx v24, v8, a3, v0.t2140; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t2141; RV64-NEXT: vand.vx v8, v8, a3, v0.t2142; RV64-NEXT: vadd.vv v8, v24, v8, v0.t2143; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t2144; RV64-NEXT: vadd.vv v8, v8, v24, v0.t2145; RV64-NEXT: vand.vx v8, v8, a4, v0.t2146; RV64-NEXT: vmul.vx v8, v8, a5, v0.t2147; RV64-NEXT: vsrl.vx v8, v8, a6, v0.t2148; RV64-NEXT: vmv1r.v v0, v72149; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2150; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t2151; RV64-NEXT: vand.vx v24, v24, a2, v0.t2152; RV64-NEXT: vsub.vv v16, v16, v24, v0.t2153; RV64-NEXT: vand.vx v24, v16, a3, v0.t2154; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t2155; RV64-NEXT: vand.vx v16, v16, a3, v0.t2156; RV64-NEXT: vadd.vv v16, v24, v16, v0.t2157; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t2158; RV64-NEXT: vadd.vv v16, v16, v24, v0.t2159; RV64-NEXT: vand.vx v16, v16, a4, v0.t2160; RV64-NEXT: vmul.vx v16, v16, a5, v0.t2161; RV64-NEXT: vsrl.vx v16, v16, a6, v0.t2162; RV64-NEXT: ret2163;2164; CHECK-ZVBB-LABEL: vp_ctpop_nxv16i64:2165; CHECK-ZVBB: # %bb.0:2166; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma2167; CHECK-ZVBB-NEXT: vmv1r.v v24, v02168; CHECK-ZVBB-NEXT: csrr a1, vlenb2169; CHECK-ZVBB-NEXT: srli a2, a1, 32170; CHECK-ZVBB-NEXT: sub a3, a0, a12171; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a22172; CHECK-ZVBB-NEXT: sltu a2, a0, a32173; CHECK-ZVBB-NEXT: addi a2, a2, -12174; CHECK-ZVBB-NEXT: and a2, a2, a32175; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma2176; CHECK-ZVBB-NEXT: vcpop.v v16, v16, v0.t2177; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_22178; CHECK-ZVBB-NEXT: # %bb.1:2179; CHECK-ZVBB-NEXT: mv a0, a12180; CHECK-ZVBB-NEXT: .LBB46_2:2181; CHECK-ZVBB-NEXT: vmv1r.v v0, v242182; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma2183; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t2184; CHECK-ZVBB-NEXT: ret2185 %v = call <vscale x 16 x i64> @llvm.vp.ctpop.nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 %evl)2186 ret <vscale x 16 x i64> %v2187}2188 2189define <vscale x 16 x i64> @vp_ctpop_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {2190; RV32-LABEL: vp_ctpop_nxv16i64_unmasked:2191; RV32: # %bb.0:2192; RV32-NEXT: addi sp, sp, -162193; RV32-NEXT: .cfi_def_cfa_offset 162194; RV32-NEXT: csrr a1, vlenb2195; RV32-NEXT: slli a1, a1, 52196; RV32-NEXT: sub sp, sp, a12197; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb2198; RV32-NEXT: csrr a1, vlenb2199; RV32-NEXT: lui a2, 3495252200; RV32-NEXT: lui a3, 2097152201; RV32-NEXT: sub a4, a0, a12202; RV32-NEXT: addi a2, a2, 13652203; RV32-NEXT: addi a3, a3, 8192204; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma2205; RV32-NEXT: vmv.v.x v0, a22206; RV32-NEXT: sltu a2, a0, a42207; RV32-NEXT: addi a2, a2, -12208; RV32-NEXT: and a2, a2, a42209; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2210; RV32-NEXT: vsrl.vi v24, v16, 12211; RV32-NEXT: csrr a4, vlenb2212; RV32-NEXT: li a5, 242213; RV32-NEXT: mul a4, a4, a52214; RV32-NEXT: add a4, sp, a42215; RV32-NEXT: addi a4, a4, 162216; RV32-NEXT: vs8r.v v0, (a4) # vscale x 64-byte Folded Spill2217; RV32-NEXT: vand.vv v24, v24, v02218; RV32-NEXT: vsub.vv v24, v16, v242219; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2220; RV32-NEXT: vmv.v.x v0, a32221; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2222; RV32-NEXT: vand.vv v16, v24, v02223; RV32-NEXT: vsrl.vi v24, v24, 22224; RV32-NEXT: csrr a3, vlenb2225; RV32-NEXT: slli a3, a3, 42226; RV32-NEXT: add a3, sp, a32227; RV32-NEXT: addi a3, a3, 162228; RV32-NEXT: vs8r.v v0, (a3) # vscale x 64-byte Folded Spill2229; RV32-NEXT: vand.vv v24, v24, v02230; RV32-NEXT: vadd.vv v24, v16, v242231; RV32-NEXT: vsrl.vi v16, v24, 42232; RV32-NEXT: vadd.vv v16, v24, v162233; RV32-NEXT: lui a3, 616812234; RV32-NEXT: lui a4, 41122235; RV32-NEXT: addi a3, a3, -2412236; RV32-NEXT: addi a4, a4, 2572237; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma2238; RV32-NEXT: vmv.v.x v24, a32239; RV32-NEXT: csrr a3, vlenb2240; RV32-NEXT: slli a3, a3, 32241; RV32-NEXT: add a3, sp, a32242; RV32-NEXT: addi a3, a3, 162243; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill2244; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2245; RV32-NEXT: vand.vv v16, v16, v242246; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma2247; RV32-NEXT: vmv.v.x v24, a42248; RV32-NEXT: addi a3, sp, 162249; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill2250; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2251; RV32-NEXT: vmul.vv v16, v16, v242252; RV32-NEXT: li a2, 562253; RV32-NEXT: vsrl.vx v16, v16, a22254; RV32-NEXT: bltu a0, a1, .LBB47_22255; RV32-NEXT: # %bb.1:2256; RV32-NEXT: mv a0, a12257; RV32-NEXT: .LBB47_2:2258; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2259; RV32-NEXT: vsrl.vi v24, v8, 12260; RV32-NEXT: csrr a0, vlenb2261; RV32-NEXT: li a1, 242262; RV32-NEXT: mul a0, a0, a12263; RV32-NEXT: add a0, sp, a02264; RV32-NEXT: addi a0, a0, 162265; RV32-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload2266; RV32-NEXT: vand.vv v24, v24, v02267; RV32-NEXT: vsub.vv v24, v8, v242268; RV32-NEXT: csrr a0, vlenb2269; RV32-NEXT: slli a0, a0, 42270; RV32-NEXT: add a0, sp, a02271; RV32-NEXT: addi a0, a0, 162272; RV32-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload2273; RV32-NEXT: vand.vv v8, v24, v02274; RV32-NEXT: vsrl.vi v24, v24, 22275; RV32-NEXT: vand.vv v24, v24, v02276; RV32-NEXT: vadd.vv v8, v8, v242277; RV32-NEXT: vsrl.vi v24, v8, 42278; RV32-NEXT: vadd.vv v8, v8, v242279; RV32-NEXT: csrr a0, vlenb2280; RV32-NEXT: slli a0, a0, 32281; RV32-NEXT: add a0, sp, a02282; RV32-NEXT: addi a0, a0, 162283; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload2284; RV32-NEXT: vand.vv v8, v8, v242285; RV32-NEXT: addi a0, sp, 162286; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload2287; RV32-NEXT: vmul.vv v8, v8, v242288; RV32-NEXT: vsrl.vx v8, v8, a22289; RV32-NEXT: csrr a0, vlenb2290; RV32-NEXT: slli a0, a0, 52291; RV32-NEXT: add sp, sp, a02292; RV32-NEXT: .cfi_def_cfa sp, 162293; RV32-NEXT: addi sp, sp, 162294; RV32-NEXT: .cfi_def_cfa_offset 02295; RV32-NEXT: ret2296;2297; RV64-LABEL: vp_ctpop_nxv16i64_unmasked:2298; RV64: # %bb.0:2299; RV64-NEXT: csrr a2, vlenb2300; RV64-NEXT: mv a1, a02301; RV64-NEXT: bltu a0, a2, .LBB47_22302; RV64-NEXT: # %bb.1:2303; RV64-NEXT: mv a1, a22304; RV64-NEXT: .LBB47_2:2305; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2306; RV64-NEXT: vsrl.vi v24, v8, 12307; RV64-NEXT: lui a3, 3495252308; RV64-NEXT: lui a4, 2097152309; RV64-NEXT: lui a5, 616812310; RV64-NEXT: lui a6, 41122311; RV64-NEXT: addi a3, a3, 13652312; RV64-NEXT: addi a4, a4, 8192313; RV64-NEXT: addi a5, a5, -2412314; RV64-NEXT: addi a6, a6, 2572315; RV64-NEXT: slli a7, a3, 322316; RV64-NEXT: add a3, a3, a72317; RV64-NEXT: slli a7, a4, 322318; RV64-NEXT: add a4, a4, a72319; RV64-NEXT: slli a7, a5, 322320; RV64-NEXT: add a5, a5, a72321; RV64-NEXT: slli a7, a6, 322322; RV64-NEXT: add a6, a6, a72323; RV64-NEXT: li a7, 562324; RV64-NEXT: sub a2, a0, a22325; RV64-NEXT: sltu a0, a0, a22326; RV64-NEXT: addi a0, a0, -12327; RV64-NEXT: and a0, a0, a22328; RV64-NEXT: vand.vx v24, v24, a32329; RV64-NEXT: vsub.vv v8, v8, v242330; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2331; RV64-NEXT: vsrl.vi v24, v16, 12332; RV64-NEXT: vand.vx v24, v24, a32333; RV64-NEXT: vsub.vv v16, v16, v242334; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2335; RV64-NEXT: vand.vx v24, v8, a42336; RV64-NEXT: vsrl.vi v8, v8, 22337; RV64-NEXT: vand.vx v8, v8, a42338; RV64-NEXT: vadd.vv v8, v24, v82339; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2340; RV64-NEXT: vand.vx v24, v16, a42341; RV64-NEXT: vsrl.vi v16, v16, 22342; RV64-NEXT: vand.vx v16, v16, a42343; RV64-NEXT: vadd.vv v16, v24, v162344; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2345; RV64-NEXT: vsrl.vi v24, v8, 42346; RV64-NEXT: vadd.vv v8, v8, v242347; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2348; RV64-NEXT: vsrl.vi v24, v16, 42349; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2350; RV64-NEXT: vand.vx v8, v8, a52351; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2352; RV64-NEXT: vadd.vv v16, v16, v242353; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2354; RV64-NEXT: vmul.vx v8, v8, a62355; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2356; RV64-NEXT: vand.vx v16, v16, a52357; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2358; RV64-NEXT: vsrl.vx v8, v8, a72359; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2360; RV64-NEXT: vmul.vx v16, v16, a62361; RV64-NEXT: vsrl.vx v16, v16, a72362; RV64-NEXT: ret2363;2364; CHECK-ZVBB-LABEL: vp_ctpop_nxv16i64_unmasked:2365; CHECK-ZVBB: # %bb.0:2366; CHECK-ZVBB-NEXT: csrr a1, vlenb2367; CHECK-ZVBB-NEXT: sub a2, a0, a12368; CHECK-ZVBB-NEXT: sltu a3, a0, a22369; CHECK-ZVBB-NEXT: addi a3, a3, -12370; CHECK-ZVBB-NEXT: and a2, a3, a22371; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma2372; CHECK-ZVBB-NEXT: vcpop.v v16, v162373; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB47_22374; CHECK-ZVBB-NEXT: # %bb.1:2375; CHECK-ZVBB-NEXT: mv a0, a12376; CHECK-ZVBB-NEXT: .LBB47_2:2377; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma2378; CHECK-ZVBB-NEXT: vcpop.v v8, v82379; CHECK-ZVBB-NEXT: ret2380 %v = call <vscale x 16 x i64> @llvm.vp.ctpop.nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)2381 ret <vscale x 16 x i64> %v2382}2383 2384; Test promotion.2385 2386define <vscale x 1 x i9> @vp_ctpop_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {2387; CHECK-LABEL: vp_ctpop_nxv1i9:2388; CHECK: # %bb.0:2389; CHECK-NEXT: li a1, 5112390; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma2391; CHECK-NEXT: vand.vx v8, v8, a1, v0.t2392; CHECK-NEXT: lui a0, 52393; CHECK-NEXT: addi a0, a0, 13652394; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2395; CHECK-NEXT: vand.vx v9, v9, a0, v0.t2396; CHECK-NEXT: lui a0, 32397; CHECK-NEXT: addi a0, a0, 8192398; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t2399; CHECK-NEXT: vand.vx v9, v8, a0, v0.t2400; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2401; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2402; CHECK-NEXT: lui a0, 12403; CHECK-NEXT: addi a0, a0, -2412404; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t2405; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2406; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t2407; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2408; CHECK-NEXT: li a0, 2572409; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t2410; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t2411; CHECK-NEXT: ret2412;2413; CHECK-ZVBB-LABEL: vp_ctpop_nxv1i9:2414; CHECK-ZVBB: # %bb.0:2415; CHECK-ZVBB-NEXT: li a1, 5112416; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma2417; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1, v0.t2418; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t2419; CHECK-ZVBB-NEXT: ret2420 %v = call <vscale x 1 x i9> @llvm.vp.ctpop.nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 %evl)2421 ret <vscale x 1 x i9> %v2422}2423