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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV646; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB8; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+m -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB10 11define <vscale x 1 x i8> @vp_cttz_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {12; CHECK-LABEL: vp_cttz_nxv1i8:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma15; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t16; CHECK-NEXT: li a0, 8517; CHECK-NEXT: vnot.v v8, v8, v0.t18; CHECK-NEXT: vand.vv v8, v8, v9, v0.t19; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t20; CHECK-NEXT: vand.vx v9, v9, a0, v0.t21; CHECK-NEXT: li a0, 5122; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t23; CHECK-NEXT: vand.vx v9, v8, a0, v0.t24; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t25; CHECK-NEXT: vand.vx v8, v8, a0, v0.t26; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t27; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t28; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t29; CHECK-NEXT: vand.vi v8, v8, 15, v0.t30; CHECK-NEXT: ret31;32; CHECK-ZVBB-LABEL: vp_cttz_nxv1i8:33; CHECK-ZVBB: # %bb.0:34; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma35; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t36; CHECK-ZVBB-NEXT: ret37 %v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)38 ret <vscale x 1 x i8> %v39}40 41define <vscale x 1 x i8> @vp_cttz_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {42; CHECK-LABEL: vp_cttz_nxv1i8_unmasked:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma45; CHECK-NEXT: vadd.vi v9, v8, -146; CHECK-NEXT: vnot.v v8, v847; CHECK-NEXT: li a0, 8548; CHECK-NEXT: vand.vv v8, v8, v949; CHECK-NEXT: vsrl.vi v9, v8, 150; CHECK-NEXT: vand.vx v9, v9, a051; CHECK-NEXT: li a0, 5152; CHECK-NEXT: vsub.vv v8, v8, v953; CHECK-NEXT: vand.vx v9, v8, a054; CHECK-NEXT: vsrl.vi v8, v8, 255; CHECK-NEXT: vand.vx v8, v8, a056; CHECK-NEXT: vadd.vv v8, v9, v857; CHECK-NEXT: vsrl.vi v9, v8, 458; CHECK-NEXT: vadd.vv v8, v8, v959; CHECK-NEXT: vand.vi v8, v8, 1560; CHECK-NEXT: ret61;62; CHECK-ZVBB-LABEL: vp_cttz_nxv1i8_unmasked:63; CHECK-ZVBB: # %bb.0:64; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma65; CHECK-ZVBB-NEXT: vctz.v v8, v866; CHECK-ZVBB-NEXT: ret67 %v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)68 ret <vscale x 1 x i8> %v69}70 71define <vscale x 2 x i8> @vp_cttz_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {72; CHECK-LABEL: vp_cttz_nxv2i8:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma75; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t76; CHECK-NEXT: li a0, 8577; CHECK-NEXT: vnot.v v8, v8, v0.t78; CHECK-NEXT: vand.vv v8, v8, v9, v0.t79; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t80; CHECK-NEXT: vand.vx v9, v9, a0, v0.t81; CHECK-NEXT: li a0, 5182; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t83; CHECK-NEXT: vand.vx v9, v8, a0, v0.t84; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t85; CHECK-NEXT: vand.vx v8, v8, a0, v0.t86; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t87; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t88; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t89; CHECK-NEXT: vand.vi v8, v8, 15, v0.t90; CHECK-NEXT: ret91;92; CHECK-ZVBB-LABEL: vp_cttz_nxv2i8:93; CHECK-ZVBB: # %bb.0:94; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma95; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t96; CHECK-ZVBB-NEXT: ret97 %v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)98 ret <vscale x 2 x i8> %v99}100 101define <vscale x 2 x i8> @vp_cttz_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {102; CHECK-LABEL: vp_cttz_nxv2i8_unmasked:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma105; CHECK-NEXT: vadd.vi v9, v8, -1106; CHECK-NEXT: vnot.v v8, v8107; CHECK-NEXT: li a0, 85108; CHECK-NEXT: vand.vv v8, v8, v9109; CHECK-NEXT: vsrl.vi v9, v8, 1110; CHECK-NEXT: vand.vx v9, v9, a0111; CHECK-NEXT: li a0, 51112; CHECK-NEXT: vsub.vv v8, v8, v9113; CHECK-NEXT: vand.vx v9, v8, a0114; CHECK-NEXT: vsrl.vi v8, v8, 2115; CHECK-NEXT: vand.vx v8, v8, a0116; CHECK-NEXT: vadd.vv v8, v9, v8117; CHECK-NEXT: vsrl.vi v9, v8, 4118; CHECK-NEXT: vadd.vv v8, v8, v9119; CHECK-NEXT: vand.vi v8, v8, 15120; CHECK-NEXT: ret121;122; CHECK-ZVBB-LABEL: vp_cttz_nxv2i8_unmasked:123; CHECK-ZVBB: # %bb.0:124; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma125; CHECK-ZVBB-NEXT: vctz.v v8, v8126; CHECK-ZVBB-NEXT: ret127 %v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)128 ret <vscale x 2 x i8> %v129}130 131define <vscale x 4 x i8> @vp_cttz_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {132; CHECK-LABEL: vp_cttz_nxv4i8:133; CHECK: # %bb.0:134; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma135; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t136; CHECK-NEXT: li a0, 85137; CHECK-NEXT: vnot.v v8, v8, v0.t138; CHECK-NEXT: vand.vv v8, v8, v9, v0.t139; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t140; CHECK-NEXT: vand.vx v9, v9, a0, v0.t141; CHECK-NEXT: li a0, 51142; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t143; CHECK-NEXT: vand.vx v9, v8, a0, v0.t144; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t145; CHECK-NEXT: vand.vx v8, v8, a0, v0.t146; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t147; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t148; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t149; CHECK-NEXT: vand.vi v8, v8, 15, v0.t150; CHECK-NEXT: ret151;152; CHECK-ZVBB-LABEL: vp_cttz_nxv4i8:153; CHECK-ZVBB: # %bb.0:154; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma155; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t156; CHECK-ZVBB-NEXT: ret157 %v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)158 ret <vscale x 4 x i8> %v159}160 161define <vscale x 4 x i8> @vp_cttz_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {162; CHECK-LABEL: vp_cttz_nxv4i8_unmasked:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma165; CHECK-NEXT: vadd.vi v9, v8, -1166; CHECK-NEXT: vnot.v v8, v8167; CHECK-NEXT: li a0, 85168; CHECK-NEXT: vand.vv v8, v8, v9169; CHECK-NEXT: vsrl.vi v9, v8, 1170; CHECK-NEXT: vand.vx v9, v9, a0171; CHECK-NEXT: li a0, 51172; CHECK-NEXT: vsub.vv v8, v8, v9173; CHECK-NEXT: vand.vx v9, v8, a0174; CHECK-NEXT: vsrl.vi v8, v8, 2175; CHECK-NEXT: vand.vx v8, v8, a0176; CHECK-NEXT: vadd.vv v8, v9, v8177; CHECK-NEXT: vsrl.vi v9, v8, 4178; CHECK-NEXT: vadd.vv v8, v8, v9179; CHECK-NEXT: vand.vi v8, v8, 15180; CHECK-NEXT: ret181;182; CHECK-ZVBB-LABEL: vp_cttz_nxv4i8_unmasked:183; CHECK-ZVBB: # %bb.0:184; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma185; CHECK-ZVBB-NEXT: vctz.v v8, v8186; CHECK-ZVBB-NEXT: ret187 %v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)188 ret <vscale x 4 x i8> %v189}190 191define <vscale x 8 x i8> @vp_cttz_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {192; CHECK-LABEL: vp_cttz_nxv8i8:193; CHECK: # %bb.0:194; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma195; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t196; CHECK-NEXT: li a0, 85197; CHECK-NEXT: vnot.v v8, v8, v0.t198; CHECK-NEXT: vand.vv v8, v8, v9, v0.t199; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t200; CHECK-NEXT: vand.vx v9, v9, a0, v0.t201; CHECK-NEXT: li a0, 51202; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t203; CHECK-NEXT: vand.vx v9, v8, a0, v0.t204; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t205; CHECK-NEXT: vand.vx v8, v8, a0, v0.t206; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t207; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t208; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t209; CHECK-NEXT: vand.vi v8, v8, 15, v0.t210; CHECK-NEXT: ret211;212; CHECK-ZVBB-LABEL: vp_cttz_nxv8i8:213; CHECK-ZVBB: # %bb.0:214; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma215; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t216; CHECK-ZVBB-NEXT: ret217 %v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)218 ret <vscale x 8 x i8> %v219}220 221define <vscale x 8 x i8> @vp_cttz_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {222; CHECK-LABEL: vp_cttz_nxv8i8_unmasked:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma225; CHECK-NEXT: vadd.vi v9, v8, -1226; CHECK-NEXT: vnot.v v8, v8227; CHECK-NEXT: li a0, 85228; CHECK-NEXT: vand.vv v8, v8, v9229; CHECK-NEXT: vsrl.vi v9, v8, 1230; CHECK-NEXT: vand.vx v9, v9, a0231; CHECK-NEXT: li a0, 51232; CHECK-NEXT: vsub.vv v8, v8, v9233; CHECK-NEXT: vand.vx v9, v8, a0234; CHECK-NEXT: vsrl.vi v8, v8, 2235; CHECK-NEXT: vand.vx v8, v8, a0236; CHECK-NEXT: vadd.vv v8, v9, v8237; CHECK-NEXT: vsrl.vi v9, v8, 4238; CHECK-NEXT: vadd.vv v8, v8, v9239; CHECK-NEXT: vand.vi v8, v8, 15240; CHECK-NEXT: ret241;242; CHECK-ZVBB-LABEL: vp_cttz_nxv8i8_unmasked:243; CHECK-ZVBB: # %bb.0:244; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma245; CHECK-ZVBB-NEXT: vctz.v v8, v8246; CHECK-ZVBB-NEXT: ret247 %v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)248 ret <vscale x 8 x i8> %v249}250 251define <vscale x 16 x i8> @vp_cttz_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {252; CHECK-LABEL: vp_cttz_nxv16i8:253; CHECK: # %bb.0:254; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma255; CHECK-NEXT: vadd.vi v10, v8, -1, v0.t256; CHECK-NEXT: li a0, 85257; CHECK-NEXT: vnot.v v8, v8, v0.t258; CHECK-NEXT: vand.vv v8, v8, v10, v0.t259; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t260; CHECK-NEXT: vand.vx v10, v10, a0, v0.t261; CHECK-NEXT: li a0, 51262; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t263; CHECK-NEXT: vand.vx v10, v8, a0, v0.t264; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t265; CHECK-NEXT: vand.vx v8, v8, a0, v0.t266; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t267; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t268; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t269; CHECK-NEXT: vand.vi v8, v8, 15, v0.t270; CHECK-NEXT: ret271;272; CHECK-ZVBB-LABEL: vp_cttz_nxv16i8:273; CHECK-ZVBB: # %bb.0:274; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma275; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t276; CHECK-ZVBB-NEXT: ret277 %v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)278 ret <vscale x 16 x i8> %v279}280 281define <vscale x 16 x i8> @vp_cttz_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {282; CHECK-LABEL: vp_cttz_nxv16i8_unmasked:283; CHECK: # %bb.0:284; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma285; CHECK-NEXT: vadd.vi v10, v8, -1286; CHECK-NEXT: vnot.v v8, v8287; CHECK-NEXT: li a0, 85288; CHECK-NEXT: vand.vv v8, v8, v10289; CHECK-NEXT: vsrl.vi v10, v8, 1290; CHECK-NEXT: vand.vx v10, v10, a0291; CHECK-NEXT: li a0, 51292; CHECK-NEXT: vsub.vv v8, v8, v10293; CHECK-NEXT: vand.vx v10, v8, a0294; CHECK-NEXT: vsrl.vi v8, v8, 2295; CHECK-NEXT: vand.vx v8, v8, a0296; CHECK-NEXT: vadd.vv v8, v10, v8297; CHECK-NEXT: vsrl.vi v10, v8, 4298; CHECK-NEXT: vadd.vv v8, v8, v10299; CHECK-NEXT: vand.vi v8, v8, 15300; CHECK-NEXT: ret301;302; CHECK-ZVBB-LABEL: vp_cttz_nxv16i8_unmasked:303; CHECK-ZVBB: # %bb.0:304; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma305; CHECK-ZVBB-NEXT: vctz.v v8, v8306; CHECK-ZVBB-NEXT: ret307 %v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)308 ret <vscale x 16 x i8> %v309}310 311define <vscale x 32 x i8> @vp_cttz_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {312; CHECK-LABEL: vp_cttz_nxv32i8:313; CHECK: # %bb.0:314; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma315; CHECK-NEXT: vadd.vi v12, v8, -1, v0.t316; CHECK-NEXT: li a0, 85317; CHECK-NEXT: vnot.v v8, v8, v0.t318; CHECK-NEXT: vand.vv v8, v8, v12, v0.t319; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t320; CHECK-NEXT: vand.vx v12, v12, a0, v0.t321; CHECK-NEXT: li a0, 51322; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t323; CHECK-NEXT: vand.vx v12, v8, a0, v0.t324; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t325; CHECK-NEXT: vand.vx v8, v8, a0, v0.t326; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t327; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t328; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t329; CHECK-NEXT: vand.vi v8, v8, 15, v0.t330; CHECK-NEXT: ret331;332; CHECK-ZVBB-LABEL: vp_cttz_nxv32i8:333; CHECK-ZVBB: # %bb.0:334; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma335; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t336; CHECK-ZVBB-NEXT: ret337 %v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)338 ret <vscale x 32 x i8> %v339}340 341define <vscale x 32 x i8> @vp_cttz_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {342; CHECK-LABEL: vp_cttz_nxv32i8_unmasked:343; CHECK: # %bb.0:344; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma345; CHECK-NEXT: vadd.vi v12, v8, -1346; CHECK-NEXT: vnot.v v8, v8347; CHECK-NEXT: li a0, 85348; CHECK-NEXT: vand.vv v8, v8, v12349; CHECK-NEXT: vsrl.vi v12, v8, 1350; CHECK-NEXT: vand.vx v12, v12, a0351; CHECK-NEXT: li a0, 51352; CHECK-NEXT: vsub.vv v8, v8, v12353; CHECK-NEXT: vand.vx v12, v8, a0354; CHECK-NEXT: vsrl.vi v8, v8, 2355; CHECK-NEXT: vand.vx v8, v8, a0356; CHECK-NEXT: vadd.vv v8, v12, v8357; CHECK-NEXT: vsrl.vi v12, v8, 4358; CHECK-NEXT: vadd.vv v8, v8, v12359; CHECK-NEXT: vand.vi v8, v8, 15360; CHECK-NEXT: ret361;362; CHECK-ZVBB-LABEL: vp_cttz_nxv32i8_unmasked:363; CHECK-ZVBB: # %bb.0:364; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma365; CHECK-ZVBB-NEXT: vctz.v v8, v8366; CHECK-ZVBB-NEXT: ret367 %v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> splat (i1 true), i32 %evl)368 ret <vscale x 32 x i8> %v369}370 371define <vscale x 64 x i8> @vp_cttz_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {372; CHECK-LABEL: vp_cttz_nxv64i8:373; CHECK: # %bb.0:374; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma375; CHECK-NEXT: vadd.vi v16, v8, -1, v0.t376; CHECK-NEXT: li a0, 85377; CHECK-NEXT: vnot.v v8, v8, v0.t378; CHECK-NEXT: vand.vv v8, v8, v16, v0.t379; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t380; CHECK-NEXT: vand.vx v16, v16, a0, v0.t381; CHECK-NEXT: li a0, 51382; CHECK-NEXT: vsub.vv v8, v8, v16, v0.t383; CHECK-NEXT: vand.vx v16, v8, a0, v0.t384; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t385; CHECK-NEXT: vand.vx v8, v8, a0, v0.t386; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t387; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t388; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t389; CHECK-NEXT: vand.vi v8, v8, 15, v0.t390; CHECK-NEXT: ret391;392; CHECK-ZVBB-LABEL: vp_cttz_nxv64i8:393; CHECK-ZVBB: # %bb.0:394; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma395; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t396; CHECK-ZVBB-NEXT: ret397 %v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> %m, i32 %evl)398 ret <vscale x 64 x i8> %v399}400 401define <vscale x 64 x i8> @vp_cttz_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {402; CHECK-LABEL: vp_cttz_nxv64i8_unmasked:403; CHECK: # %bb.0:404; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma405; CHECK-NEXT: vadd.vi v16, v8, -1406; CHECK-NEXT: vnot.v v8, v8407; CHECK-NEXT: li a0, 85408; CHECK-NEXT: vand.vv v8, v8, v16409; CHECK-NEXT: vsrl.vi v16, v8, 1410; CHECK-NEXT: vand.vx v16, v16, a0411; CHECK-NEXT: li a0, 51412; CHECK-NEXT: vsub.vv v8, v8, v16413; CHECK-NEXT: vand.vx v16, v8, a0414; CHECK-NEXT: vsrl.vi v8, v8, 2415; CHECK-NEXT: vand.vx v8, v8, a0416; CHECK-NEXT: vadd.vv v8, v16, v8417; CHECK-NEXT: vsrl.vi v16, v8, 4418; CHECK-NEXT: vadd.vv v8, v8, v16419; CHECK-NEXT: vand.vi v8, v8, 15420; CHECK-NEXT: ret421;422; CHECK-ZVBB-LABEL: vp_cttz_nxv64i8_unmasked:423; CHECK-ZVBB: # %bb.0:424; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma425; CHECK-ZVBB-NEXT: vctz.v v8, v8426; CHECK-ZVBB-NEXT: ret427 %v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> splat (i1 true), i32 %evl)428 ret <vscale x 64 x i8> %v429}430 431define <vscale x 1 x i16> @vp_cttz_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {432; CHECK-LABEL: vp_cttz_nxv1i16:433; CHECK: # %bb.0:434; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma435; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t436; CHECK-NEXT: lui a0, 5437; CHECK-NEXT: vnot.v v8, v8, v0.t438; CHECK-NEXT: addi a0, a0, 1365439; CHECK-NEXT: vand.vv v8, v8, v9, v0.t440; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t441; CHECK-NEXT: vand.vx v9, v9, a0, v0.t442; CHECK-NEXT: lui a0, 3443; CHECK-NEXT: addi a0, a0, 819444; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t445; CHECK-NEXT: vand.vx v9, v8, a0, v0.t446; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t447; CHECK-NEXT: vand.vx v8, v8, a0, v0.t448; CHECK-NEXT: lui a0, 1449; CHECK-NEXT: addi a0, a0, -241450; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t451; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t452; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t453; CHECK-NEXT: vand.vx v8, v8, a0, v0.t454; CHECK-NEXT: li a0, 257455; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t456; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t457; CHECK-NEXT: ret458;459; CHECK-ZVBB-LABEL: vp_cttz_nxv1i16:460; CHECK-ZVBB: # %bb.0:461; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma462; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t463; CHECK-ZVBB-NEXT: ret464 %v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)465 ret <vscale x 1 x i16> %v466}467 468define <vscale x 1 x i16> @vp_cttz_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {469; CHECK-LABEL: vp_cttz_nxv1i16_unmasked:470; CHECK: # %bb.0:471; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma472; CHECK-NEXT: vadd.vi v9, v8, -1473; CHECK-NEXT: vnot.v v8, v8474; CHECK-NEXT: lui a0, 5475; CHECK-NEXT: vand.vv v8, v8, v9476; CHECK-NEXT: addi a0, a0, 1365477; CHECK-NEXT: vsrl.vi v9, v8, 1478; CHECK-NEXT: vand.vx v9, v9, a0479; CHECK-NEXT: lui a0, 3480; CHECK-NEXT: addi a0, a0, 819481; CHECK-NEXT: vsub.vv v8, v8, v9482; CHECK-NEXT: vand.vx v9, v8, a0483; CHECK-NEXT: vsrl.vi v8, v8, 2484; CHECK-NEXT: vand.vx v8, v8, a0485; CHECK-NEXT: lui a0, 1486; CHECK-NEXT: addi a0, a0, -241487; CHECK-NEXT: vadd.vv v8, v9, v8488; CHECK-NEXT: vsrl.vi v9, v8, 4489; CHECK-NEXT: vadd.vv v8, v8, v9490; CHECK-NEXT: vand.vx v8, v8, a0491; CHECK-NEXT: li a0, 257492; CHECK-NEXT: vmul.vx v8, v8, a0493; CHECK-NEXT: vsrl.vi v8, v8, 8494; CHECK-NEXT: ret495;496; CHECK-ZVBB-LABEL: vp_cttz_nxv1i16_unmasked:497; CHECK-ZVBB: # %bb.0:498; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma499; CHECK-ZVBB-NEXT: vctz.v v8, v8500; CHECK-ZVBB-NEXT: ret501 %v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)502 ret <vscale x 1 x i16> %v503}504 505define <vscale x 2 x i16> @vp_cttz_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {506; CHECK-LABEL: vp_cttz_nxv2i16:507; CHECK: # %bb.0:508; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma509; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t510; CHECK-NEXT: lui a0, 5511; CHECK-NEXT: vnot.v v8, v8, v0.t512; CHECK-NEXT: addi a0, a0, 1365513; CHECK-NEXT: vand.vv v8, v8, v9, v0.t514; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t515; CHECK-NEXT: vand.vx v9, v9, a0, v0.t516; CHECK-NEXT: lui a0, 3517; CHECK-NEXT: addi a0, a0, 819518; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t519; CHECK-NEXT: vand.vx v9, v8, a0, v0.t520; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t521; CHECK-NEXT: vand.vx v8, v8, a0, v0.t522; CHECK-NEXT: lui a0, 1523; CHECK-NEXT: addi a0, a0, -241524; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t525; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t526; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t527; CHECK-NEXT: vand.vx v8, v8, a0, v0.t528; CHECK-NEXT: li a0, 257529; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t530; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t531; CHECK-NEXT: ret532;533; CHECK-ZVBB-LABEL: vp_cttz_nxv2i16:534; CHECK-ZVBB: # %bb.0:535; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma536; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t537; CHECK-ZVBB-NEXT: ret538 %v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)539 ret <vscale x 2 x i16> %v540}541 542define <vscale x 2 x i16> @vp_cttz_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {543; CHECK-LABEL: vp_cttz_nxv2i16_unmasked:544; CHECK: # %bb.0:545; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma546; CHECK-NEXT: vadd.vi v9, v8, -1547; CHECK-NEXT: vnot.v v8, v8548; CHECK-NEXT: lui a0, 5549; CHECK-NEXT: vand.vv v8, v8, v9550; CHECK-NEXT: addi a0, a0, 1365551; CHECK-NEXT: vsrl.vi v9, v8, 1552; CHECK-NEXT: vand.vx v9, v9, a0553; CHECK-NEXT: lui a0, 3554; CHECK-NEXT: addi a0, a0, 819555; CHECK-NEXT: vsub.vv v8, v8, v9556; CHECK-NEXT: vand.vx v9, v8, a0557; CHECK-NEXT: vsrl.vi v8, v8, 2558; CHECK-NEXT: vand.vx v8, v8, a0559; CHECK-NEXT: lui a0, 1560; CHECK-NEXT: addi a0, a0, -241561; CHECK-NEXT: vadd.vv v8, v9, v8562; CHECK-NEXT: vsrl.vi v9, v8, 4563; CHECK-NEXT: vadd.vv v8, v8, v9564; CHECK-NEXT: vand.vx v8, v8, a0565; CHECK-NEXT: li a0, 257566; CHECK-NEXT: vmul.vx v8, v8, a0567; CHECK-NEXT: vsrl.vi v8, v8, 8568; CHECK-NEXT: ret569;570; CHECK-ZVBB-LABEL: vp_cttz_nxv2i16_unmasked:571; CHECK-ZVBB: # %bb.0:572; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma573; CHECK-ZVBB-NEXT: vctz.v v8, v8574; CHECK-ZVBB-NEXT: ret575 %v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)576 ret <vscale x 2 x i16> %v577}578 579define <vscale x 4 x i16> @vp_cttz_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {580; CHECK-LABEL: vp_cttz_nxv4i16:581; CHECK: # %bb.0:582; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma583; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t584; CHECK-NEXT: lui a0, 5585; CHECK-NEXT: vnot.v v8, v8, v0.t586; CHECK-NEXT: addi a0, a0, 1365587; CHECK-NEXT: vand.vv v8, v8, v9, v0.t588; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t589; CHECK-NEXT: vand.vx v9, v9, a0, v0.t590; CHECK-NEXT: lui a0, 3591; CHECK-NEXT: addi a0, a0, 819592; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t593; CHECK-NEXT: vand.vx v9, v8, a0, v0.t594; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t595; CHECK-NEXT: vand.vx v8, v8, a0, v0.t596; CHECK-NEXT: lui a0, 1597; CHECK-NEXT: addi a0, a0, -241598; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t599; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t600; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t601; CHECK-NEXT: vand.vx v8, v8, a0, v0.t602; CHECK-NEXT: li a0, 257603; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t604; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t605; CHECK-NEXT: ret606;607; CHECK-ZVBB-LABEL: vp_cttz_nxv4i16:608; CHECK-ZVBB: # %bb.0:609; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma610; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t611; CHECK-ZVBB-NEXT: ret612 %v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)613 ret <vscale x 4 x i16> %v614}615 616define <vscale x 4 x i16> @vp_cttz_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {617; CHECK-LABEL: vp_cttz_nxv4i16_unmasked:618; CHECK: # %bb.0:619; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma620; CHECK-NEXT: vadd.vi v9, v8, -1621; CHECK-NEXT: vnot.v v8, v8622; CHECK-NEXT: lui a0, 5623; CHECK-NEXT: vand.vv v8, v8, v9624; CHECK-NEXT: addi a0, a0, 1365625; CHECK-NEXT: vsrl.vi v9, v8, 1626; CHECK-NEXT: vand.vx v9, v9, a0627; CHECK-NEXT: lui a0, 3628; CHECK-NEXT: addi a0, a0, 819629; CHECK-NEXT: vsub.vv v8, v8, v9630; CHECK-NEXT: vand.vx v9, v8, a0631; CHECK-NEXT: vsrl.vi v8, v8, 2632; CHECK-NEXT: vand.vx v8, v8, a0633; CHECK-NEXT: lui a0, 1634; CHECK-NEXT: addi a0, a0, -241635; CHECK-NEXT: vadd.vv v8, v9, v8636; CHECK-NEXT: vsrl.vi v9, v8, 4637; CHECK-NEXT: vadd.vv v8, v8, v9638; CHECK-NEXT: vand.vx v8, v8, a0639; CHECK-NEXT: li a0, 257640; CHECK-NEXT: vmul.vx v8, v8, a0641; CHECK-NEXT: vsrl.vi v8, v8, 8642; CHECK-NEXT: ret643;644; CHECK-ZVBB-LABEL: vp_cttz_nxv4i16_unmasked:645; CHECK-ZVBB: # %bb.0:646; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma647; CHECK-ZVBB-NEXT: vctz.v v8, v8648; CHECK-ZVBB-NEXT: ret649 %v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)650 ret <vscale x 4 x i16> %v651}652 653define <vscale x 8 x i16> @vp_cttz_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {654; CHECK-LABEL: vp_cttz_nxv8i16:655; CHECK: # %bb.0:656; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma657; CHECK-NEXT: vadd.vi v10, v8, -1, v0.t658; CHECK-NEXT: lui a0, 5659; CHECK-NEXT: vnot.v v8, v8, v0.t660; CHECK-NEXT: addi a0, a0, 1365661; CHECK-NEXT: vand.vv v8, v8, v10, v0.t662; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t663; CHECK-NEXT: vand.vx v10, v10, a0, v0.t664; CHECK-NEXT: lui a0, 3665; CHECK-NEXT: addi a0, a0, 819666; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t667; CHECK-NEXT: vand.vx v10, v8, a0, v0.t668; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t669; CHECK-NEXT: vand.vx v8, v8, a0, v0.t670; CHECK-NEXT: lui a0, 1671; CHECK-NEXT: addi a0, a0, -241672; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t673; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t674; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t675; CHECK-NEXT: vand.vx v8, v8, a0, v0.t676; CHECK-NEXT: li a0, 257677; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t678; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t679; CHECK-NEXT: ret680;681; CHECK-ZVBB-LABEL: vp_cttz_nxv8i16:682; CHECK-ZVBB: # %bb.0:683; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma684; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t685; CHECK-ZVBB-NEXT: ret686 %v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)687 ret <vscale x 8 x i16> %v688}689 690define <vscale x 8 x i16> @vp_cttz_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {691; CHECK-LABEL: vp_cttz_nxv8i16_unmasked:692; CHECK: # %bb.0:693; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma694; CHECK-NEXT: vadd.vi v10, v8, -1695; CHECK-NEXT: vnot.v v8, v8696; CHECK-NEXT: lui a0, 5697; CHECK-NEXT: vand.vv v8, v8, v10698; CHECK-NEXT: addi a0, a0, 1365699; CHECK-NEXT: vsrl.vi v10, v8, 1700; CHECK-NEXT: vand.vx v10, v10, a0701; CHECK-NEXT: lui a0, 3702; CHECK-NEXT: addi a0, a0, 819703; CHECK-NEXT: vsub.vv v8, v8, v10704; CHECK-NEXT: vand.vx v10, v8, a0705; CHECK-NEXT: vsrl.vi v8, v8, 2706; CHECK-NEXT: vand.vx v8, v8, a0707; CHECK-NEXT: lui a0, 1708; CHECK-NEXT: addi a0, a0, -241709; CHECK-NEXT: vadd.vv v8, v10, v8710; CHECK-NEXT: vsrl.vi v10, v8, 4711; CHECK-NEXT: vadd.vv v8, v8, v10712; CHECK-NEXT: vand.vx v8, v8, a0713; CHECK-NEXT: li a0, 257714; CHECK-NEXT: vmul.vx v8, v8, a0715; CHECK-NEXT: vsrl.vi v8, v8, 8716; CHECK-NEXT: ret717;718; CHECK-ZVBB-LABEL: vp_cttz_nxv8i16_unmasked:719; CHECK-ZVBB: # %bb.0:720; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma721; CHECK-ZVBB-NEXT: vctz.v v8, v8722; CHECK-ZVBB-NEXT: ret723 %v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)724 ret <vscale x 8 x i16> %v725}726 727define <vscale x 16 x i16> @vp_cttz_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {728; CHECK-LABEL: vp_cttz_nxv16i16:729; CHECK: # %bb.0:730; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma731; CHECK-NEXT: vadd.vi v12, v8, -1, v0.t732; CHECK-NEXT: lui a0, 5733; CHECK-NEXT: vnot.v v8, v8, v0.t734; CHECK-NEXT: addi a0, a0, 1365735; CHECK-NEXT: vand.vv v8, v8, v12, v0.t736; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t737; CHECK-NEXT: vand.vx v12, v12, a0, v0.t738; CHECK-NEXT: lui a0, 3739; CHECK-NEXT: addi a0, a0, 819740; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t741; CHECK-NEXT: vand.vx v12, v8, a0, v0.t742; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t743; CHECK-NEXT: vand.vx v8, v8, a0, v0.t744; CHECK-NEXT: lui a0, 1745; CHECK-NEXT: addi a0, a0, -241746; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t747; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t748; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t749; CHECK-NEXT: vand.vx v8, v8, a0, v0.t750; CHECK-NEXT: li a0, 257751; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t752; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t753; CHECK-NEXT: ret754;755; CHECK-ZVBB-LABEL: vp_cttz_nxv16i16:756; CHECK-ZVBB: # %bb.0:757; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma758; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t759; CHECK-ZVBB-NEXT: ret760 %v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)761 ret <vscale x 16 x i16> %v762}763 764define <vscale x 16 x i16> @vp_cttz_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {765; CHECK-LABEL: vp_cttz_nxv16i16_unmasked:766; CHECK: # %bb.0:767; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma768; CHECK-NEXT: vadd.vi v12, v8, -1769; CHECK-NEXT: vnot.v v8, v8770; CHECK-NEXT: lui a0, 5771; CHECK-NEXT: vand.vv v8, v8, v12772; CHECK-NEXT: addi a0, a0, 1365773; CHECK-NEXT: vsrl.vi v12, v8, 1774; CHECK-NEXT: vand.vx v12, v12, a0775; CHECK-NEXT: lui a0, 3776; CHECK-NEXT: addi a0, a0, 819777; CHECK-NEXT: vsub.vv v8, v8, v12778; CHECK-NEXT: vand.vx v12, v8, a0779; CHECK-NEXT: vsrl.vi v8, v8, 2780; CHECK-NEXT: vand.vx v8, v8, a0781; CHECK-NEXT: lui a0, 1782; CHECK-NEXT: addi a0, a0, -241783; CHECK-NEXT: vadd.vv v8, v12, v8784; CHECK-NEXT: vsrl.vi v12, v8, 4785; CHECK-NEXT: vadd.vv v8, v8, v12786; CHECK-NEXT: vand.vx v8, v8, a0787; CHECK-NEXT: li a0, 257788; CHECK-NEXT: vmul.vx v8, v8, a0789; CHECK-NEXT: vsrl.vi v8, v8, 8790; CHECK-NEXT: ret791;792; CHECK-ZVBB-LABEL: vp_cttz_nxv16i16_unmasked:793; CHECK-ZVBB: # %bb.0:794; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma795; CHECK-ZVBB-NEXT: vctz.v v8, v8796; CHECK-ZVBB-NEXT: ret797 %v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)798 ret <vscale x 16 x i16> %v799}800 801define <vscale x 32 x i16> @vp_cttz_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {802; CHECK-LABEL: vp_cttz_nxv32i16:803; CHECK: # %bb.0:804; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma805; CHECK-NEXT: vadd.vi v16, v8, -1, v0.t806; CHECK-NEXT: lui a0, 5807; CHECK-NEXT: vnot.v v8, v8, v0.t808; CHECK-NEXT: addi a0, a0, 1365809; CHECK-NEXT: vand.vv v8, v8, v16, v0.t810; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t811; CHECK-NEXT: vand.vx v16, v16, a0, v0.t812; CHECK-NEXT: lui a0, 3813; CHECK-NEXT: addi a0, a0, 819814; CHECK-NEXT: vsub.vv v16, v8, v16, v0.t815; CHECK-NEXT: vand.vx v8, v16, a0, v0.t816; CHECK-NEXT: vsrl.vi v16, v16, 2, v0.t817; CHECK-NEXT: vand.vx v16, v16, a0, v0.t818; CHECK-NEXT: lui a0, 1819; CHECK-NEXT: addi a0, a0, -241820; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t821; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t822; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t823; CHECK-NEXT: vand.vx v8, v8, a0, v0.t824; CHECK-NEXT: li a0, 257825; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t826; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t827; CHECK-NEXT: ret828;829; CHECK-ZVBB-LABEL: vp_cttz_nxv32i16:830; CHECK-ZVBB: # %bb.0:831; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma832; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t833; CHECK-ZVBB-NEXT: ret834 %v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)835 ret <vscale x 32 x i16> %v836}837 838define <vscale x 32 x i16> @vp_cttz_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {839; CHECK-LABEL: vp_cttz_nxv32i16_unmasked:840; CHECK: # %bb.0:841; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma842; CHECK-NEXT: vadd.vi v16, v8, -1843; CHECK-NEXT: vnot.v v8, v8844; CHECK-NEXT: lui a0, 5845; CHECK-NEXT: vand.vv v8, v8, v16846; CHECK-NEXT: addi a0, a0, 1365847; CHECK-NEXT: vsrl.vi v16, v8, 1848; CHECK-NEXT: vand.vx v16, v16, a0849; CHECK-NEXT: lui a0, 3850; CHECK-NEXT: addi a0, a0, 819851; CHECK-NEXT: vsub.vv v8, v8, v16852; CHECK-NEXT: vand.vx v16, v8, a0853; CHECK-NEXT: vsrl.vi v8, v8, 2854; CHECK-NEXT: vand.vx v8, v8, a0855; CHECK-NEXT: lui a0, 1856; CHECK-NEXT: addi a0, a0, -241857; CHECK-NEXT: vadd.vv v8, v16, v8858; CHECK-NEXT: vsrl.vi v16, v8, 4859; CHECK-NEXT: vadd.vv v8, v8, v16860; CHECK-NEXT: vand.vx v8, v8, a0861; CHECK-NEXT: li a0, 257862; CHECK-NEXT: vmul.vx v8, v8, a0863; CHECK-NEXT: vsrl.vi v8, v8, 8864; CHECK-NEXT: ret865;866; CHECK-ZVBB-LABEL: vp_cttz_nxv32i16_unmasked:867; CHECK-ZVBB: # %bb.0:868; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma869; CHECK-ZVBB-NEXT: vctz.v v8, v8870; CHECK-ZVBB-NEXT: ret871 %v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> splat (i1 true), i32 %evl)872 ret <vscale x 32 x i16> %v873}874 875define <vscale x 1 x i32> @vp_cttz_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {876; CHECK-LABEL: vp_cttz_nxv1i32:877; CHECK: # %bb.0:878; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma879; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t880; CHECK-NEXT: lui a0, 349525881; CHECK-NEXT: vnot.v v8, v8, v0.t882; CHECK-NEXT: addi a0, a0, 1365883; CHECK-NEXT: vand.vv v8, v8, v9, v0.t884; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t885; CHECK-NEXT: vand.vx v9, v9, a0, v0.t886; CHECK-NEXT: lui a0, 209715887; CHECK-NEXT: addi a0, a0, 819888; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t889; CHECK-NEXT: vand.vx v9, v8, a0, v0.t890; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t891; CHECK-NEXT: vand.vx v8, v8, a0, v0.t892; CHECK-NEXT: lui a0, 61681893; CHECK-NEXT: addi a0, a0, -241894; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t895; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t896; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t897; CHECK-NEXT: vand.vx v8, v8, a0, v0.t898; CHECK-NEXT: lui a0, 4112899; CHECK-NEXT: addi a0, a0, 257900; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t901; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t902; CHECK-NEXT: ret903;904; CHECK-ZVBB-LABEL: vp_cttz_nxv1i32:905; CHECK-ZVBB: # %bb.0:906; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma907; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t908; CHECK-ZVBB-NEXT: ret909 %v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)910 ret <vscale x 1 x i32> %v911}912 913define <vscale x 1 x i32> @vp_cttz_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {914; CHECK-LABEL: vp_cttz_nxv1i32_unmasked:915; CHECK: # %bb.0:916; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma917; CHECK-NEXT: vadd.vi v9, v8, -1918; CHECK-NEXT: vnot.v v8, v8919; CHECK-NEXT: lui a0, 349525920; CHECK-NEXT: vand.vv v8, v8, v9921; CHECK-NEXT: addi a0, a0, 1365922; CHECK-NEXT: vsrl.vi v9, v8, 1923; CHECK-NEXT: vand.vx v9, v9, a0924; CHECK-NEXT: lui a0, 209715925; CHECK-NEXT: addi a0, a0, 819926; CHECK-NEXT: vsub.vv v8, v8, v9927; CHECK-NEXT: vand.vx v9, v8, a0928; CHECK-NEXT: vsrl.vi v8, v8, 2929; CHECK-NEXT: vand.vx v8, v8, a0930; CHECK-NEXT: lui a0, 61681931; CHECK-NEXT: addi a0, a0, -241932; CHECK-NEXT: vadd.vv v8, v9, v8933; CHECK-NEXT: vsrl.vi v9, v8, 4934; CHECK-NEXT: vadd.vv v8, v8, v9935; CHECK-NEXT: vand.vx v8, v8, a0936; CHECK-NEXT: lui a0, 4112937; CHECK-NEXT: addi a0, a0, 257938; CHECK-NEXT: vmul.vx v8, v8, a0939; CHECK-NEXT: vsrl.vi v8, v8, 24940; CHECK-NEXT: ret941;942; CHECK-ZVBB-LABEL: vp_cttz_nxv1i32_unmasked:943; CHECK-ZVBB: # %bb.0:944; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma945; CHECK-ZVBB-NEXT: vctz.v v8, v8946; CHECK-ZVBB-NEXT: ret947 %v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)948 ret <vscale x 1 x i32> %v949}950 951define <vscale x 2 x i32> @vp_cttz_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {952; CHECK-LABEL: vp_cttz_nxv2i32:953; CHECK: # %bb.0:954; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma955; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t956; CHECK-NEXT: lui a0, 349525957; CHECK-NEXT: vnot.v v8, v8, v0.t958; CHECK-NEXT: addi a0, a0, 1365959; CHECK-NEXT: vand.vv v8, v8, v9, v0.t960; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t961; CHECK-NEXT: vand.vx v9, v9, a0, v0.t962; CHECK-NEXT: lui a0, 209715963; CHECK-NEXT: addi a0, a0, 819964; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t965; CHECK-NEXT: vand.vx v9, v8, a0, v0.t966; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t967; CHECK-NEXT: vand.vx v8, v8, a0, v0.t968; CHECK-NEXT: lui a0, 61681969; CHECK-NEXT: addi a0, a0, -241970; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t971; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t972; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t973; CHECK-NEXT: vand.vx v8, v8, a0, v0.t974; CHECK-NEXT: lui a0, 4112975; CHECK-NEXT: addi a0, a0, 257976; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t977; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t978; CHECK-NEXT: ret979;980; CHECK-ZVBB-LABEL: vp_cttz_nxv2i32:981; CHECK-ZVBB: # %bb.0:982; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma983; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t984; CHECK-ZVBB-NEXT: ret985 %v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)986 ret <vscale x 2 x i32> %v987}988 989define <vscale x 2 x i32> @vp_cttz_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {990; CHECK-LABEL: vp_cttz_nxv2i32_unmasked:991; CHECK: # %bb.0:992; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma993; CHECK-NEXT: vadd.vi v9, v8, -1994; CHECK-NEXT: vnot.v v8, v8995; CHECK-NEXT: lui a0, 349525996; CHECK-NEXT: vand.vv v8, v8, v9997; CHECK-NEXT: addi a0, a0, 1365998; CHECK-NEXT: vsrl.vi v9, v8, 1999; CHECK-NEXT: vand.vx v9, v9, a01000; CHECK-NEXT: lui a0, 2097151001; CHECK-NEXT: addi a0, a0, 8191002; CHECK-NEXT: vsub.vv v8, v8, v91003; CHECK-NEXT: vand.vx v9, v8, a01004; CHECK-NEXT: vsrl.vi v8, v8, 21005; CHECK-NEXT: vand.vx v8, v8, a01006; CHECK-NEXT: lui a0, 616811007; CHECK-NEXT: addi a0, a0, -2411008; CHECK-NEXT: vadd.vv v8, v9, v81009; CHECK-NEXT: vsrl.vi v9, v8, 41010; CHECK-NEXT: vadd.vv v8, v8, v91011; CHECK-NEXT: vand.vx v8, v8, a01012; CHECK-NEXT: lui a0, 41121013; CHECK-NEXT: addi a0, a0, 2571014; CHECK-NEXT: vmul.vx v8, v8, a01015; CHECK-NEXT: vsrl.vi v8, v8, 241016; CHECK-NEXT: ret1017;1018; CHECK-ZVBB-LABEL: vp_cttz_nxv2i32_unmasked:1019; CHECK-ZVBB: # %bb.0:1020; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma1021; CHECK-ZVBB-NEXT: vctz.v v8, v81022; CHECK-ZVBB-NEXT: ret1023 %v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)1024 ret <vscale x 2 x i32> %v1025}1026 1027define <vscale x 4 x i32> @vp_cttz_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1028; CHECK-LABEL: vp_cttz_nxv4i32:1029; CHECK: # %bb.0:1030; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1031; CHECK-NEXT: vadd.vi v10, v8, -1, v0.t1032; CHECK-NEXT: lui a0, 3495251033; CHECK-NEXT: vnot.v v8, v8, v0.t1034; CHECK-NEXT: addi a0, a0, 13651035; CHECK-NEXT: vand.vv v8, v8, v10, v0.t1036; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t1037; CHECK-NEXT: vand.vx v10, v10, a0, v0.t1038; CHECK-NEXT: lui a0, 2097151039; CHECK-NEXT: addi a0, a0, 8191040; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t1041; CHECK-NEXT: vand.vx v10, v8, a0, v0.t1042; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t1043; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1044; CHECK-NEXT: lui a0, 616811045; CHECK-NEXT: addi a0, a0, -2411046; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t1047; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t1048; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t1049; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1050; CHECK-NEXT: lui a0, 41121051; CHECK-NEXT: addi a0, a0, 2571052; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t1053; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t1054; CHECK-NEXT: ret1055;1056; CHECK-ZVBB-LABEL: vp_cttz_nxv4i32:1057; CHECK-ZVBB: # %bb.0:1058; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma1059; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t1060; CHECK-ZVBB-NEXT: ret1061 %v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)1062 ret <vscale x 4 x i32> %v1063}1064 1065define <vscale x 4 x i32> @vp_cttz_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {1066; CHECK-LABEL: vp_cttz_nxv4i32_unmasked:1067; CHECK: # %bb.0:1068; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1069; CHECK-NEXT: vadd.vi v10, v8, -11070; CHECK-NEXT: vnot.v v8, v81071; CHECK-NEXT: lui a0, 3495251072; CHECK-NEXT: vand.vv v8, v8, v101073; CHECK-NEXT: addi a0, a0, 13651074; CHECK-NEXT: vsrl.vi v10, v8, 11075; CHECK-NEXT: vand.vx v10, v10, a01076; CHECK-NEXT: lui a0, 2097151077; CHECK-NEXT: addi a0, a0, 8191078; CHECK-NEXT: vsub.vv v8, v8, v101079; CHECK-NEXT: vand.vx v10, v8, a01080; CHECK-NEXT: vsrl.vi v8, v8, 21081; CHECK-NEXT: vand.vx v8, v8, a01082; CHECK-NEXT: lui a0, 616811083; CHECK-NEXT: addi a0, a0, -2411084; CHECK-NEXT: vadd.vv v8, v10, v81085; CHECK-NEXT: vsrl.vi v10, v8, 41086; CHECK-NEXT: vadd.vv v8, v8, v101087; CHECK-NEXT: vand.vx v8, v8, a01088; CHECK-NEXT: lui a0, 41121089; CHECK-NEXT: addi a0, a0, 2571090; CHECK-NEXT: vmul.vx v8, v8, a01091; CHECK-NEXT: vsrl.vi v8, v8, 241092; CHECK-NEXT: ret1093;1094; CHECK-ZVBB-LABEL: vp_cttz_nxv4i32_unmasked:1095; CHECK-ZVBB: # %bb.0:1096; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma1097; CHECK-ZVBB-NEXT: vctz.v v8, v81098; CHECK-ZVBB-NEXT: ret1099 %v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)1100 ret <vscale x 4 x i32> %v1101}1102 1103define <vscale x 8 x i32> @vp_cttz_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1104; CHECK-LABEL: vp_cttz_nxv8i32:1105; CHECK: # %bb.0:1106; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1107; CHECK-NEXT: vadd.vi v12, v8, -1, v0.t1108; CHECK-NEXT: lui a0, 3495251109; CHECK-NEXT: vnot.v v8, v8, v0.t1110; CHECK-NEXT: addi a0, a0, 13651111; CHECK-NEXT: vand.vv v8, v8, v12, v0.t1112; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t1113; CHECK-NEXT: vand.vx v12, v12, a0, v0.t1114; CHECK-NEXT: lui a0, 2097151115; CHECK-NEXT: addi a0, a0, 8191116; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t1117; CHECK-NEXT: vand.vx v12, v8, a0, v0.t1118; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t1119; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1120; CHECK-NEXT: lui a0, 616811121; CHECK-NEXT: addi a0, a0, -2411122; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t1123; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t1124; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t1125; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1126; CHECK-NEXT: lui a0, 41121127; CHECK-NEXT: addi a0, a0, 2571128; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t1129; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t1130; CHECK-NEXT: ret1131;1132; CHECK-ZVBB-LABEL: vp_cttz_nxv8i32:1133; CHECK-ZVBB: # %bb.0:1134; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma1135; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t1136; CHECK-ZVBB-NEXT: ret1137 %v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)1138 ret <vscale x 8 x i32> %v1139}1140 1141define <vscale x 8 x i32> @vp_cttz_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {1142; CHECK-LABEL: vp_cttz_nxv8i32_unmasked:1143; CHECK: # %bb.0:1144; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1145; CHECK-NEXT: vadd.vi v12, v8, -11146; CHECK-NEXT: vnot.v v8, v81147; CHECK-NEXT: lui a0, 3495251148; CHECK-NEXT: vand.vv v8, v8, v121149; CHECK-NEXT: addi a0, a0, 13651150; CHECK-NEXT: vsrl.vi v12, v8, 11151; CHECK-NEXT: vand.vx v12, v12, a01152; CHECK-NEXT: lui a0, 2097151153; CHECK-NEXT: addi a0, a0, 8191154; CHECK-NEXT: vsub.vv v8, v8, v121155; CHECK-NEXT: vand.vx v12, v8, a01156; CHECK-NEXT: vsrl.vi v8, v8, 21157; CHECK-NEXT: vand.vx v8, v8, a01158; CHECK-NEXT: lui a0, 616811159; CHECK-NEXT: addi a0, a0, -2411160; CHECK-NEXT: vadd.vv v8, v12, v81161; CHECK-NEXT: vsrl.vi v12, v8, 41162; CHECK-NEXT: vadd.vv v8, v8, v121163; CHECK-NEXT: vand.vx v8, v8, a01164; CHECK-NEXT: lui a0, 41121165; CHECK-NEXT: addi a0, a0, 2571166; CHECK-NEXT: vmul.vx v8, v8, a01167; CHECK-NEXT: vsrl.vi v8, v8, 241168; CHECK-NEXT: ret1169;1170; CHECK-ZVBB-LABEL: vp_cttz_nxv8i32_unmasked:1171; CHECK-ZVBB: # %bb.0:1172; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma1173; CHECK-ZVBB-NEXT: vctz.v v8, v81174; CHECK-ZVBB-NEXT: ret1175 %v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)1176 ret <vscale x 8 x i32> %v1177}1178 1179define <vscale x 16 x i32> @vp_cttz_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1180; CHECK-LABEL: vp_cttz_nxv16i32:1181; CHECK: # %bb.0:1182; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1183; CHECK-NEXT: vadd.vi v16, v8, -1, v0.t1184; CHECK-NEXT: lui a0, 3495251185; CHECK-NEXT: vnot.v v8, v8, v0.t1186; CHECK-NEXT: addi a0, a0, 13651187; CHECK-NEXT: vand.vv v8, v8, v16, v0.t1188; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t1189; CHECK-NEXT: vand.vx v16, v16, a0, v0.t1190; CHECK-NEXT: lui a0, 2097151191; CHECK-NEXT: addi a0, a0, 8191192; CHECK-NEXT: vsub.vv v16, v8, v16, v0.t1193; CHECK-NEXT: vand.vx v8, v16, a0, v0.t1194; CHECK-NEXT: vsrl.vi v16, v16, 2, v0.t1195; CHECK-NEXT: vand.vx v16, v16, a0, v0.t1196; CHECK-NEXT: lui a0, 616811197; CHECK-NEXT: addi a0, a0, -2411198; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t1199; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t1200; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t1201; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1202; CHECK-NEXT: lui a0, 41121203; CHECK-NEXT: addi a0, a0, 2571204; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t1205; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t1206; CHECK-NEXT: ret1207;1208; CHECK-ZVBB-LABEL: vp_cttz_nxv16i32:1209; CHECK-ZVBB: # %bb.0:1210; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma1211; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t1212; CHECK-ZVBB-NEXT: ret1213 %v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)1214 ret <vscale x 16 x i32> %v1215}1216 1217define <vscale x 16 x i32> @vp_cttz_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {1218; CHECK-LABEL: vp_cttz_nxv16i32_unmasked:1219; CHECK: # %bb.0:1220; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1221; CHECK-NEXT: vadd.vi v16, v8, -11222; CHECK-NEXT: vnot.v v8, v81223; CHECK-NEXT: lui a0, 3495251224; CHECK-NEXT: vand.vv v8, v8, v161225; CHECK-NEXT: addi a0, a0, 13651226; CHECK-NEXT: vsrl.vi v16, v8, 11227; CHECK-NEXT: vand.vx v16, v16, a01228; CHECK-NEXT: lui a0, 2097151229; CHECK-NEXT: addi a0, a0, 8191230; CHECK-NEXT: vsub.vv v8, v8, v161231; CHECK-NEXT: vand.vx v16, v8, a01232; CHECK-NEXT: vsrl.vi v8, v8, 21233; CHECK-NEXT: vand.vx v8, v8, a01234; CHECK-NEXT: lui a0, 616811235; CHECK-NEXT: addi a0, a0, -2411236; CHECK-NEXT: vadd.vv v8, v16, v81237; CHECK-NEXT: vsrl.vi v16, v8, 41238; CHECK-NEXT: vadd.vv v8, v8, v161239; CHECK-NEXT: vand.vx v8, v8, a01240; CHECK-NEXT: lui a0, 41121241; CHECK-NEXT: addi a0, a0, 2571242; CHECK-NEXT: vmul.vx v8, v8, a01243; CHECK-NEXT: vsrl.vi v8, v8, 241244; CHECK-NEXT: ret1245;1246; CHECK-ZVBB-LABEL: vp_cttz_nxv16i32_unmasked:1247; CHECK-ZVBB: # %bb.0:1248; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma1249; CHECK-ZVBB-NEXT: vctz.v v8, v81250; CHECK-ZVBB-NEXT: ret1251 %v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)1252 ret <vscale x 16 x i32> %v1253}1254 1255define <vscale x 1 x i64> @vp_cttz_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1256; RV32-LABEL: vp_cttz_nxv1i64:1257; RV32: # %bb.0:1258; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1259; RV32-NEXT: vadd.vi v9, v8, -1, v0.t1260; RV32-NEXT: lui a1, 3495251261; RV32-NEXT: addi a1, a1, 13651262; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1263; RV32-NEXT: vmv.v.x v10, a11264; RV32-NEXT: lui a1, 2097151265; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1266; RV32-NEXT: vnot.v v8, v8, v0.t1267; RV32-NEXT: addi a1, a1, 8191268; RV32-NEXT: vand.vv v8, v8, v9, v0.t1269; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t1270; RV32-NEXT: vand.vv v9, v9, v10, v0.t1271; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1272; RV32-NEXT: vmv.v.x v10, a11273; RV32-NEXT: lui a1, 616811274; RV32-NEXT: addi a1, a1, -2411275; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1276; RV32-NEXT: vsub.vv v8, v8, v9, v0.t1277; RV32-NEXT: vand.vv v9, v8, v10, v0.t1278; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t1279; RV32-NEXT: vand.vv v8, v8, v10, v0.t1280; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1281; RV32-NEXT: vmv.v.x v10, a11282; RV32-NEXT: lui a1, 41121283; RV32-NEXT: addi a1, a1, 2571284; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1285; RV32-NEXT: vadd.vv v8, v9, v8, v0.t1286; RV32-NEXT: vsrl.vi v9, v8, 4, v0.t1287; RV32-NEXT: vadd.vv v8, v8, v9, v0.t1288; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1289; RV32-NEXT: vmv.v.x v9, a11290; RV32-NEXT: li a1, 561291; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1292; RV32-NEXT: vand.vv v8, v8, v10, v0.t1293; RV32-NEXT: vmul.vv v8, v8, v9, v0.t1294; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1295; RV32-NEXT: ret1296;1297; RV64-LABEL: vp_cttz_nxv1i64:1298; RV64: # %bb.0:1299; RV64-NEXT: lui a1, 3495251300; RV64-NEXT: lui a2, 2097151301; RV64-NEXT: lui a3, 616811302; RV64-NEXT: lui a4, 41121303; RV64-NEXT: addi a1, a1, 13651304; RV64-NEXT: addi a2, a2, 8191305; RV64-NEXT: addi a3, a3, -2411306; RV64-NEXT: addi a4, a4, 2571307; RV64-NEXT: slli a5, a1, 321308; RV64-NEXT: add a1, a1, a51309; RV64-NEXT: slli a5, a2, 321310; RV64-NEXT: add a2, a2, a51311; RV64-NEXT: slli a5, a3, 321312; RV64-NEXT: add a3, a3, a51313; RV64-NEXT: slli a5, a4, 321314; RV64-NEXT: add a4, a4, a51315; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma1316; RV64-NEXT: vadd.vi v9, v8, -1, v0.t1317; RV64-NEXT: vnot.v v8, v8, v0.t1318; RV64-NEXT: vand.vv v8, v8, v9, v0.t1319; RV64-NEXT: vsrl.vi v9, v8, 1, v0.t1320; RV64-NEXT: vand.vx v9, v9, a1, v0.t1321; RV64-NEXT: vsub.vv v8, v8, v9, v0.t1322; RV64-NEXT: vand.vx v9, v8, a2, v0.t1323; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1324; RV64-NEXT: vand.vx v8, v8, a2, v0.t1325; RV64-NEXT: vadd.vv v8, v9, v8, v0.t1326; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t1327; RV64-NEXT: vadd.vv v8, v8, v9, v0.t1328; RV64-NEXT: vand.vx v8, v8, a3, v0.t1329; RV64-NEXT: li a0, 561330; RV64-NEXT: vmul.vx v8, v8, a4, v0.t1331; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1332; RV64-NEXT: ret1333;1334; CHECK-ZVBB-LABEL: vp_cttz_nxv1i64:1335; CHECK-ZVBB: # %bb.0:1336; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma1337; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t1338; CHECK-ZVBB-NEXT: ret1339 %v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)1340 ret <vscale x 1 x i64> %v1341}1342 1343define <vscale x 1 x i64> @vp_cttz_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {1344; RV32-LABEL: vp_cttz_nxv1i64_unmasked:1345; RV32: # %bb.0:1346; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1347; RV32-NEXT: vadd.vi v9, v8, -11348; RV32-NEXT: vnot.v v8, v81349; RV32-NEXT: lui a1, 3495251350; RV32-NEXT: addi a1, a1, 13651351; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1352; RV32-NEXT: vmv.v.x v10, a11353; RV32-NEXT: lui a1, 2097151354; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1355; RV32-NEXT: vand.vv v8, v8, v91356; RV32-NEXT: addi a1, a1, 8191357; RV32-NEXT: vsrl.vi v9, v8, 11358; RV32-NEXT: vand.vv v9, v9, v101359; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1360; RV32-NEXT: vmv.v.x v10, a11361; RV32-NEXT: lui a1, 616811362; RV32-NEXT: addi a1, a1, -2411363; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1364; RV32-NEXT: vsub.vv v8, v8, v91365; RV32-NEXT: vand.vv v9, v8, v101366; RV32-NEXT: vsrl.vi v8, v8, 21367; RV32-NEXT: vand.vv v8, v8, v101368; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1369; RV32-NEXT: vmv.v.x v10, a11370; RV32-NEXT: lui a1, 41121371; RV32-NEXT: addi a1, a1, 2571372; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1373; RV32-NEXT: vadd.vv v8, v9, v81374; RV32-NEXT: vsrl.vi v9, v8, 41375; RV32-NEXT: vadd.vv v8, v8, v91376; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1377; RV32-NEXT: vmv.v.x v9, a11378; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1379; RV32-NEXT: vand.vv v8, v8, v101380; RV32-NEXT: vmul.vv v8, v8, v91381; RV32-NEXT: li a0, 561382; RV32-NEXT: vsrl.vx v8, v8, a01383; RV32-NEXT: ret1384;1385; RV64-LABEL: vp_cttz_nxv1i64_unmasked:1386; RV64: # %bb.0:1387; RV64-NEXT: lui a1, 3495251388; RV64-NEXT: lui a2, 2097151389; RV64-NEXT: lui a3, 616811390; RV64-NEXT: lui a4, 41121391; RV64-NEXT: addi a1, a1, 13651392; RV64-NEXT: addi a2, a2, 8191393; RV64-NEXT: addi a3, a3, -2411394; RV64-NEXT: addi a4, a4, 2571395; RV64-NEXT: slli a5, a1, 321396; RV64-NEXT: add a1, a1, a51397; RV64-NEXT: slli a5, a2, 321398; RV64-NEXT: add a2, a2, a51399; RV64-NEXT: slli a5, a3, 321400; RV64-NEXT: add a3, a3, a51401; RV64-NEXT: slli a5, a4, 321402; RV64-NEXT: add a4, a4, a51403; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma1404; RV64-NEXT: vadd.vi v9, v8, -11405; RV64-NEXT: vnot.v v8, v81406; RV64-NEXT: vand.vv v8, v8, v91407; RV64-NEXT: vsrl.vi v9, v8, 11408; RV64-NEXT: vand.vx v9, v9, a11409; RV64-NEXT: vsub.vv v8, v8, v91410; RV64-NEXT: vand.vx v9, v8, a21411; RV64-NEXT: vsrl.vi v8, v8, 21412; RV64-NEXT: vand.vx v8, v8, a21413; RV64-NEXT: vadd.vv v8, v9, v81414; RV64-NEXT: vsrl.vi v9, v8, 41415; RV64-NEXT: vadd.vv v8, v8, v91416; RV64-NEXT: vand.vx v8, v8, a31417; RV64-NEXT: vmul.vx v8, v8, a41418; RV64-NEXT: li a0, 561419; RV64-NEXT: vsrl.vx v8, v8, a01420; RV64-NEXT: ret1421;1422; CHECK-ZVBB-LABEL: vp_cttz_nxv1i64_unmasked:1423; CHECK-ZVBB: # %bb.0:1424; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma1425; CHECK-ZVBB-NEXT: vctz.v v8, v81426; CHECK-ZVBB-NEXT: ret1427 %v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)1428 ret <vscale x 1 x i64> %v1429}1430 1431define <vscale x 2 x i64> @vp_cttz_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1432; RV32-LABEL: vp_cttz_nxv2i64:1433; RV32: # %bb.0:1434; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1435; RV32-NEXT: vadd.vi v10, v8, -1, v0.t1436; RV32-NEXT: lui a1, 3495251437; RV32-NEXT: addi a1, a1, 13651438; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1439; RV32-NEXT: vmv.v.x v12, a11440; RV32-NEXT: lui a1, 2097151441; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1442; RV32-NEXT: vnot.v v8, v8, v0.t1443; RV32-NEXT: addi a1, a1, 8191444; RV32-NEXT: vand.vv v8, v8, v10, v0.t1445; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t1446; RV32-NEXT: vand.vv v10, v10, v12, v0.t1447; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1448; RV32-NEXT: vmv.v.x v12, a11449; RV32-NEXT: lui a1, 616811450; RV32-NEXT: addi a1, a1, -2411451; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1452; RV32-NEXT: vsub.vv v8, v8, v10, v0.t1453; RV32-NEXT: vand.vv v10, v8, v12, v0.t1454; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t1455; RV32-NEXT: vand.vv v8, v8, v12, v0.t1456; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1457; RV32-NEXT: vmv.v.x v12, a11458; RV32-NEXT: lui a1, 41121459; RV32-NEXT: addi a1, a1, 2571460; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1461; RV32-NEXT: vadd.vv v8, v10, v8, v0.t1462; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t1463; RV32-NEXT: vadd.vv v8, v8, v10, v0.t1464; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1465; RV32-NEXT: vmv.v.x v10, a11466; RV32-NEXT: li a1, 561467; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1468; RV32-NEXT: vand.vv v8, v8, v12, v0.t1469; RV32-NEXT: vmul.vv v8, v8, v10, v0.t1470; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1471; RV32-NEXT: ret1472;1473; RV64-LABEL: vp_cttz_nxv2i64:1474; RV64: # %bb.0:1475; RV64-NEXT: lui a1, 3495251476; RV64-NEXT: lui a2, 2097151477; RV64-NEXT: lui a3, 616811478; RV64-NEXT: lui a4, 41121479; RV64-NEXT: addi a1, a1, 13651480; RV64-NEXT: addi a2, a2, 8191481; RV64-NEXT: addi a3, a3, -2411482; RV64-NEXT: addi a4, a4, 2571483; RV64-NEXT: slli a5, a1, 321484; RV64-NEXT: add a1, a1, a51485; RV64-NEXT: slli a5, a2, 321486; RV64-NEXT: add a2, a2, a51487; RV64-NEXT: slli a5, a3, 321488; RV64-NEXT: add a3, a3, a51489; RV64-NEXT: slli a5, a4, 321490; RV64-NEXT: add a4, a4, a51491; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma1492; RV64-NEXT: vadd.vi v10, v8, -1, v0.t1493; RV64-NEXT: vnot.v v8, v8, v0.t1494; RV64-NEXT: vand.vv v8, v8, v10, v0.t1495; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t1496; RV64-NEXT: vand.vx v10, v10, a1, v0.t1497; RV64-NEXT: vsub.vv v8, v8, v10, v0.t1498; RV64-NEXT: vand.vx v10, v8, a2, v0.t1499; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1500; RV64-NEXT: vand.vx v8, v8, a2, v0.t1501; RV64-NEXT: vadd.vv v8, v10, v8, v0.t1502; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t1503; RV64-NEXT: vadd.vv v8, v8, v10, v0.t1504; RV64-NEXT: vand.vx v8, v8, a3, v0.t1505; RV64-NEXT: li a0, 561506; RV64-NEXT: vmul.vx v8, v8, a4, v0.t1507; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1508; RV64-NEXT: ret1509;1510; CHECK-ZVBB-LABEL: vp_cttz_nxv2i64:1511; CHECK-ZVBB: # %bb.0:1512; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma1513; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t1514; CHECK-ZVBB-NEXT: ret1515 %v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)1516 ret <vscale x 2 x i64> %v1517}1518 1519define <vscale x 2 x i64> @vp_cttz_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {1520; RV32-LABEL: vp_cttz_nxv2i64_unmasked:1521; RV32: # %bb.0:1522; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1523; RV32-NEXT: vadd.vi v10, v8, -11524; RV32-NEXT: vnot.v v8, v81525; RV32-NEXT: lui a1, 3495251526; RV32-NEXT: addi a1, a1, 13651527; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1528; RV32-NEXT: vmv.v.x v12, a11529; RV32-NEXT: lui a1, 2097151530; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1531; RV32-NEXT: vand.vv v8, v8, v101532; RV32-NEXT: addi a1, a1, 8191533; RV32-NEXT: vsrl.vi v10, v8, 11534; RV32-NEXT: vand.vv v10, v10, v121535; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1536; RV32-NEXT: vmv.v.x v12, a11537; RV32-NEXT: lui a1, 616811538; RV32-NEXT: addi a1, a1, -2411539; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1540; RV32-NEXT: vsub.vv v8, v8, v101541; RV32-NEXT: vand.vv v10, v8, v121542; RV32-NEXT: vsrl.vi v8, v8, 21543; RV32-NEXT: vand.vv v8, v8, v121544; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1545; RV32-NEXT: vmv.v.x v12, a11546; RV32-NEXT: lui a1, 41121547; RV32-NEXT: addi a1, a1, 2571548; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1549; RV32-NEXT: vadd.vv v8, v10, v81550; RV32-NEXT: vsrl.vi v10, v8, 41551; RV32-NEXT: vadd.vv v8, v8, v101552; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1553; RV32-NEXT: vmv.v.x v10, a11554; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1555; RV32-NEXT: vand.vv v8, v8, v121556; RV32-NEXT: vmul.vv v8, v8, v101557; RV32-NEXT: li a0, 561558; RV32-NEXT: vsrl.vx v8, v8, a01559; RV32-NEXT: ret1560;1561; RV64-LABEL: vp_cttz_nxv2i64_unmasked:1562; RV64: # %bb.0:1563; RV64-NEXT: lui a1, 3495251564; RV64-NEXT: lui a2, 2097151565; RV64-NEXT: lui a3, 616811566; RV64-NEXT: lui a4, 41121567; RV64-NEXT: addi a1, a1, 13651568; RV64-NEXT: addi a2, a2, 8191569; RV64-NEXT: addi a3, a3, -2411570; RV64-NEXT: addi a4, a4, 2571571; RV64-NEXT: slli a5, a1, 321572; RV64-NEXT: add a1, a1, a51573; RV64-NEXT: slli a5, a2, 321574; RV64-NEXT: add a2, a2, a51575; RV64-NEXT: slli a5, a3, 321576; RV64-NEXT: add a3, a3, a51577; RV64-NEXT: slli a5, a4, 321578; RV64-NEXT: add a4, a4, a51579; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma1580; RV64-NEXT: vadd.vi v10, v8, -11581; RV64-NEXT: vnot.v v8, v81582; RV64-NEXT: vand.vv v8, v8, v101583; RV64-NEXT: vsrl.vi v10, v8, 11584; RV64-NEXT: vand.vx v10, v10, a11585; RV64-NEXT: vsub.vv v8, v8, v101586; RV64-NEXT: vand.vx v10, v8, a21587; RV64-NEXT: vsrl.vi v8, v8, 21588; RV64-NEXT: vand.vx v8, v8, a21589; RV64-NEXT: vadd.vv v8, v10, v81590; RV64-NEXT: vsrl.vi v10, v8, 41591; RV64-NEXT: vadd.vv v8, v8, v101592; RV64-NEXT: vand.vx v8, v8, a31593; RV64-NEXT: vmul.vx v8, v8, a41594; RV64-NEXT: li a0, 561595; RV64-NEXT: vsrl.vx v8, v8, a01596; RV64-NEXT: ret1597;1598; CHECK-ZVBB-LABEL: vp_cttz_nxv2i64_unmasked:1599; CHECK-ZVBB: # %bb.0:1600; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma1601; CHECK-ZVBB-NEXT: vctz.v v8, v81602; CHECK-ZVBB-NEXT: ret1603 %v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)1604 ret <vscale x 2 x i64> %v1605}1606 1607define <vscale x 4 x i64> @vp_cttz_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1608; RV32-LABEL: vp_cttz_nxv4i64:1609; RV32: # %bb.0:1610; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1611; RV32-NEXT: vadd.vi v12, v8, -1, v0.t1612; RV32-NEXT: lui a1, 3495251613; RV32-NEXT: addi a1, a1, 13651614; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1615; RV32-NEXT: vmv.v.x v16, a11616; RV32-NEXT: lui a1, 2097151617; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1618; RV32-NEXT: vnot.v v8, v8, v0.t1619; RV32-NEXT: addi a1, a1, 8191620; RV32-NEXT: vand.vv v12, v8, v12, v0.t1621; RV32-NEXT: vsrl.vi v8, v12, 1, v0.t1622; RV32-NEXT: vand.vv v16, v8, v16, v0.t1623; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1624; RV32-NEXT: vmv.v.x v8, a11625; RV32-NEXT: lui a1, 616811626; RV32-NEXT: addi a1, a1, -2411627; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1628; RV32-NEXT: vsub.vv v12, v12, v16, v0.t1629; RV32-NEXT: vand.vv v16, v12, v8, v0.t1630; RV32-NEXT: vsrl.vi v12, v12, 2, v0.t1631; RV32-NEXT: vand.vv v8, v12, v8, v0.t1632; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1633; RV32-NEXT: vmv.v.x v12, a11634; RV32-NEXT: lui a1, 41121635; RV32-NEXT: addi a1, a1, 2571636; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1637; RV32-NEXT: vadd.vv v8, v16, v8, v0.t1638; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t1639; RV32-NEXT: vadd.vv v8, v8, v16, v0.t1640; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1641; RV32-NEXT: vmv.v.x v16, a11642; RV32-NEXT: li a1, 561643; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1644; RV32-NEXT: vand.vv v8, v8, v12, v0.t1645; RV32-NEXT: vmul.vv v8, v8, v16, v0.t1646; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1647; RV32-NEXT: ret1648;1649; RV64-LABEL: vp_cttz_nxv4i64:1650; RV64: # %bb.0:1651; RV64-NEXT: lui a1, 3495251652; RV64-NEXT: lui a2, 2097151653; RV64-NEXT: lui a3, 616811654; RV64-NEXT: lui a4, 41121655; RV64-NEXT: addi a1, a1, 13651656; RV64-NEXT: addi a2, a2, 8191657; RV64-NEXT: addi a3, a3, -2411658; RV64-NEXT: addi a4, a4, 2571659; RV64-NEXT: slli a5, a1, 321660; RV64-NEXT: add a1, a1, a51661; RV64-NEXT: slli a5, a2, 321662; RV64-NEXT: add a2, a2, a51663; RV64-NEXT: slli a5, a3, 321664; RV64-NEXT: add a3, a3, a51665; RV64-NEXT: slli a5, a4, 321666; RV64-NEXT: add a4, a4, a51667; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma1668; RV64-NEXT: vadd.vi v12, v8, -1, v0.t1669; RV64-NEXT: vnot.v v8, v8, v0.t1670; RV64-NEXT: vand.vv v8, v8, v12, v0.t1671; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t1672; RV64-NEXT: vand.vx v12, v12, a1, v0.t1673; RV64-NEXT: vsub.vv v8, v8, v12, v0.t1674; RV64-NEXT: vand.vx v12, v8, a2, v0.t1675; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1676; RV64-NEXT: vand.vx v8, v8, a2, v0.t1677; RV64-NEXT: vadd.vv v8, v12, v8, v0.t1678; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t1679; RV64-NEXT: vadd.vv v8, v8, v12, v0.t1680; RV64-NEXT: vand.vx v8, v8, a3, v0.t1681; RV64-NEXT: li a0, 561682; RV64-NEXT: vmul.vx v8, v8, a4, v0.t1683; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1684; RV64-NEXT: ret1685;1686; CHECK-ZVBB-LABEL: vp_cttz_nxv4i64:1687; CHECK-ZVBB: # %bb.0:1688; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma1689; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t1690; CHECK-ZVBB-NEXT: ret1691 %v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)1692 ret <vscale x 4 x i64> %v1693}1694 1695define <vscale x 4 x i64> @vp_cttz_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {1696; RV32-LABEL: vp_cttz_nxv4i64_unmasked:1697; RV32: # %bb.0:1698; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1699; RV32-NEXT: vadd.vi v12, v8, -11700; RV32-NEXT: vnot.v v8, v81701; RV32-NEXT: lui a1, 3495251702; RV32-NEXT: addi a1, a1, 13651703; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1704; RV32-NEXT: vmv.v.x v16, a11705; RV32-NEXT: lui a1, 2097151706; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1707; RV32-NEXT: vand.vv v8, v8, v121708; RV32-NEXT: addi a1, a1, 8191709; RV32-NEXT: vsrl.vi v12, v8, 11710; RV32-NEXT: vand.vv v12, v12, v161711; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1712; RV32-NEXT: vmv.v.x v16, a11713; RV32-NEXT: lui a1, 616811714; RV32-NEXT: addi a1, a1, -2411715; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1716; RV32-NEXT: vsub.vv v8, v8, v121717; RV32-NEXT: vand.vv v12, v8, v161718; RV32-NEXT: vsrl.vi v8, v8, 21719; RV32-NEXT: vand.vv v8, v8, v161720; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1721; RV32-NEXT: vmv.v.x v16, a11722; RV32-NEXT: lui a1, 41121723; RV32-NEXT: addi a1, a1, 2571724; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1725; RV32-NEXT: vadd.vv v8, v12, v81726; RV32-NEXT: vsrl.vi v12, v8, 41727; RV32-NEXT: vadd.vv v8, v8, v121728; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1729; RV32-NEXT: vmv.v.x v12, a11730; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1731; RV32-NEXT: vand.vv v8, v8, v161732; RV32-NEXT: vmul.vv v8, v8, v121733; RV32-NEXT: li a0, 561734; RV32-NEXT: vsrl.vx v8, v8, a01735; RV32-NEXT: ret1736;1737; RV64-LABEL: vp_cttz_nxv4i64_unmasked:1738; RV64: # %bb.0:1739; RV64-NEXT: lui a1, 3495251740; RV64-NEXT: lui a2, 2097151741; RV64-NEXT: lui a3, 616811742; RV64-NEXT: lui a4, 41121743; RV64-NEXT: addi a1, a1, 13651744; RV64-NEXT: addi a2, a2, 8191745; RV64-NEXT: addi a3, a3, -2411746; RV64-NEXT: addi a4, a4, 2571747; RV64-NEXT: slli a5, a1, 321748; RV64-NEXT: add a1, a1, a51749; RV64-NEXT: slli a5, a2, 321750; RV64-NEXT: add a2, a2, a51751; RV64-NEXT: slli a5, a3, 321752; RV64-NEXT: add a3, a3, a51753; RV64-NEXT: slli a5, a4, 321754; RV64-NEXT: add a4, a4, a51755; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma1756; RV64-NEXT: vadd.vi v12, v8, -11757; RV64-NEXT: vnot.v v8, v81758; RV64-NEXT: vand.vv v8, v8, v121759; RV64-NEXT: vsrl.vi v12, v8, 11760; RV64-NEXT: vand.vx v12, v12, a11761; RV64-NEXT: vsub.vv v8, v8, v121762; RV64-NEXT: vand.vx v12, v8, a21763; RV64-NEXT: vsrl.vi v8, v8, 21764; RV64-NEXT: vand.vx v8, v8, a21765; RV64-NEXT: vadd.vv v8, v12, v81766; RV64-NEXT: vsrl.vi v12, v8, 41767; RV64-NEXT: vadd.vv v8, v8, v121768; RV64-NEXT: vand.vx v8, v8, a31769; RV64-NEXT: vmul.vx v8, v8, a41770; RV64-NEXT: li a0, 561771; RV64-NEXT: vsrl.vx v8, v8, a01772; RV64-NEXT: ret1773;1774; CHECK-ZVBB-LABEL: vp_cttz_nxv4i64_unmasked:1775; CHECK-ZVBB: # %bb.0:1776; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma1777; CHECK-ZVBB-NEXT: vctz.v v8, v81778; CHECK-ZVBB-NEXT: ret1779 %v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)1780 ret <vscale x 4 x i64> %v1781}1782 1783define <vscale x 7 x i64> @vp_cttz_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {1784; RV32-LABEL: vp_cttz_nxv7i64:1785; RV32: # %bb.0:1786; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1787; RV32-NEXT: vadd.vi v16, v8, -1, v0.t1788; RV32-NEXT: lui a1, 3495251789; RV32-NEXT: addi a1, a1, 13651790; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1791; RV32-NEXT: vmv.v.x v24, a11792; RV32-NEXT: lui a1, 2097151793; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1794; RV32-NEXT: vnot.v v8, v8, v0.t1795; RV32-NEXT: addi a1, a1, 8191796; RV32-NEXT: vand.vv v16, v8, v16, v0.t1797; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t1798; RV32-NEXT: vand.vv v24, v8, v24, v0.t1799; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1800; RV32-NEXT: vmv.v.x v8, a11801; RV32-NEXT: lui a1, 616811802; RV32-NEXT: addi a1, a1, -2411803; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1804; RV32-NEXT: vsub.vv v24, v16, v24, v0.t1805; RV32-NEXT: vand.vv v16, v24, v8, v0.t1806; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t1807; RV32-NEXT: vand.vv v24, v24, v8, v0.t1808; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1809; RV32-NEXT: vmv.v.x v8, a11810; RV32-NEXT: lui a1, 41121811; RV32-NEXT: addi a1, a1, 2571812; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1813; RV32-NEXT: vadd.vv v16, v16, v24, v0.t1814; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t1815; RV32-NEXT: vadd.vv v16, v16, v24, v0.t1816; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1817; RV32-NEXT: vmv.v.x v24, a11818; RV32-NEXT: li a1, 561819; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1820; RV32-NEXT: vand.vv v8, v16, v8, v0.t1821; RV32-NEXT: vmul.vv v8, v8, v24, v0.t1822; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1823; RV32-NEXT: ret1824;1825; RV64-LABEL: vp_cttz_nxv7i64:1826; RV64: # %bb.0:1827; RV64-NEXT: lui a1, 3495251828; RV64-NEXT: lui a2, 2097151829; RV64-NEXT: lui a3, 616811830; RV64-NEXT: lui a4, 41121831; RV64-NEXT: addi a1, a1, 13651832; RV64-NEXT: addi a2, a2, 8191833; RV64-NEXT: addi a3, a3, -2411834; RV64-NEXT: addi a4, a4, 2571835; RV64-NEXT: slli a5, a1, 321836; RV64-NEXT: add a1, a1, a51837; RV64-NEXT: slli a5, a2, 321838; RV64-NEXT: add a2, a2, a51839; RV64-NEXT: slli a5, a3, 321840; RV64-NEXT: add a3, a3, a51841; RV64-NEXT: slli a5, a4, 321842; RV64-NEXT: add a4, a4, a51843; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1844; RV64-NEXT: vadd.vi v16, v8, -1, v0.t1845; RV64-NEXT: vnot.v v8, v8, v0.t1846; RV64-NEXT: vand.vv v8, v8, v16, v0.t1847; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t1848; RV64-NEXT: vand.vx v16, v16, a1, v0.t1849; RV64-NEXT: vsub.vv v8, v8, v16, v0.t1850; RV64-NEXT: vand.vx v16, v8, a2, v0.t1851; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1852; RV64-NEXT: vand.vx v8, v8, a2, v0.t1853; RV64-NEXT: vadd.vv v8, v16, v8, v0.t1854; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t1855; RV64-NEXT: vadd.vv v8, v8, v16, v0.t1856; RV64-NEXT: vand.vx v8, v8, a3, v0.t1857; RV64-NEXT: li a0, 561858; RV64-NEXT: vmul.vx v8, v8, a4, v0.t1859; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1860; RV64-NEXT: ret1861;1862; CHECK-ZVBB-LABEL: vp_cttz_nxv7i64:1863; CHECK-ZVBB: # %bb.0:1864; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma1865; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t1866; CHECK-ZVBB-NEXT: ret1867 %v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> %m, i32 %evl)1868 ret <vscale x 7 x i64> %v1869}1870 1871define <vscale x 7 x i64> @vp_cttz_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {1872; RV32-LABEL: vp_cttz_nxv7i64_unmasked:1873; RV32: # %bb.0:1874; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1875; RV32-NEXT: vadd.vi v16, v8, -11876; RV32-NEXT: vnot.v v8, v81877; RV32-NEXT: lui a1, 3495251878; RV32-NEXT: addi a1, a1, 13651879; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1880; RV32-NEXT: vmv.v.x v24, a11881; RV32-NEXT: lui a1, 2097151882; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1883; RV32-NEXT: vand.vv v8, v8, v161884; RV32-NEXT: addi a1, a1, 8191885; RV32-NEXT: vsrl.vi v16, v8, 11886; RV32-NEXT: vand.vv v24, v16, v241887; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1888; RV32-NEXT: vmv.v.x v16, a11889; RV32-NEXT: lui a1, 616811890; RV32-NEXT: addi a1, a1, -2411891; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1892; RV32-NEXT: vsub.vv v8, v8, v241893; RV32-NEXT: vand.vv v24, v8, v161894; RV32-NEXT: vsrl.vi v8, v8, 21895; RV32-NEXT: vand.vv v8, v8, v161896; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1897; RV32-NEXT: vmv.v.x v16, a11898; RV32-NEXT: lui a1, 41121899; RV32-NEXT: addi a1, a1, 2571900; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1901; RV32-NEXT: vadd.vv v8, v24, v81902; RV32-NEXT: vsrl.vi v24, v8, 41903; RV32-NEXT: vadd.vv v8, v8, v241904; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1905; RV32-NEXT: vmv.v.x v24, a11906; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1907; RV32-NEXT: vand.vv v8, v8, v161908; RV32-NEXT: vmul.vv v8, v8, v241909; RV32-NEXT: li a0, 561910; RV32-NEXT: vsrl.vx v8, v8, a01911; RV32-NEXT: ret1912;1913; RV64-LABEL: vp_cttz_nxv7i64_unmasked:1914; RV64: # %bb.0:1915; RV64-NEXT: lui a1, 3495251916; RV64-NEXT: lui a2, 2097151917; RV64-NEXT: lui a3, 616811918; RV64-NEXT: lui a4, 41121919; RV64-NEXT: addi a1, a1, 13651920; RV64-NEXT: addi a2, a2, 8191921; RV64-NEXT: addi a3, a3, -2411922; RV64-NEXT: addi a4, a4, 2571923; RV64-NEXT: slli a5, a1, 321924; RV64-NEXT: add a1, a1, a51925; RV64-NEXT: slli a5, a2, 321926; RV64-NEXT: add a2, a2, a51927; RV64-NEXT: slli a5, a3, 321928; RV64-NEXT: add a3, a3, a51929; RV64-NEXT: slli a5, a4, 321930; RV64-NEXT: add a4, a4, a51931; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1932; RV64-NEXT: vadd.vi v16, v8, -11933; RV64-NEXT: vnot.v v8, v81934; RV64-NEXT: vand.vv v8, v8, v161935; RV64-NEXT: vsrl.vi v16, v8, 11936; RV64-NEXT: vand.vx v16, v16, a11937; RV64-NEXT: vsub.vv v8, v8, v161938; RV64-NEXT: vand.vx v16, v8, a21939; RV64-NEXT: vsrl.vi v8, v8, 21940; RV64-NEXT: vand.vx v8, v8, a21941; RV64-NEXT: vadd.vv v8, v16, v81942; RV64-NEXT: vsrl.vi v16, v8, 41943; RV64-NEXT: vadd.vv v8, v8, v161944; RV64-NEXT: vand.vx v8, v8, a31945; RV64-NEXT: vmul.vx v8, v8, a41946; RV64-NEXT: li a0, 561947; RV64-NEXT: vsrl.vx v8, v8, a01948; RV64-NEXT: ret1949;1950; CHECK-ZVBB-LABEL: vp_cttz_nxv7i64_unmasked:1951; CHECK-ZVBB: # %bb.0:1952; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma1953; CHECK-ZVBB-NEXT: vctz.v v8, v81954; CHECK-ZVBB-NEXT: ret1955 %v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> splat (i1 true), i32 %evl)1956 ret <vscale x 7 x i64> %v1957}1958 1959define <vscale x 8 x i64> @vp_cttz_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1960; RV32-LABEL: vp_cttz_nxv8i64:1961; RV32: # %bb.0:1962; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1963; RV32-NEXT: vadd.vi v16, v8, -1, v0.t1964; RV32-NEXT: lui a1, 3495251965; RV32-NEXT: addi a1, a1, 13651966; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1967; RV32-NEXT: vmv.v.x v24, a11968; RV32-NEXT: lui a1, 2097151969; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1970; RV32-NEXT: vnot.v v8, v8, v0.t1971; RV32-NEXT: addi a1, a1, 8191972; RV32-NEXT: vand.vv v16, v8, v16, v0.t1973; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t1974; RV32-NEXT: vand.vv v24, v8, v24, v0.t1975; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1976; RV32-NEXT: vmv.v.x v8, a11977; RV32-NEXT: lui a1, 616811978; RV32-NEXT: addi a1, a1, -2411979; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1980; RV32-NEXT: vsub.vv v24, v16, v24, v0.t1981; RV32-NEXT: vand.vv v16, v24, v8, v0.t1982; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t1983; RV32-NEXT: vand.vv v24, v24, v8, v0.t1984; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1985; RV32-NEXT: vmv.v.x v8, a11986; RV32-NEXT: lui a1, 41121987; RV32-NEXT: addi a1, a1, 2571988; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1989; RV32-NEXT: vadd.vv v16, v16, v24, v0.t1990; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t1991; RV32-NEXT: vadd.vv v16, v16, v24, v0.t1992; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1993; RV32-NEXT: vmv.v.x v24, a11994; RV32-NEXT: li a1, 561995; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1996; RV32-NEXT: vand.vv v8, v16, v8, v0.t1997; RV32-NEXT: vmul.vv v8, v8, v24, v0.t1998; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1999; RV32-NEXT: ret2000;2001; RV64-LABEL: vp_cttz_nxv8i64:2002; RV64: # %bb.0:2003; RV64-NEXT: lui a1, 3495252004; RV64-NEXT: lui a2, 2097152005; RV64-NEXT: lui a3, 616812006; RV64-NEXT: lui a4, 41122007; RV64-NEXT: addi a1, a1, 13652008; RV64-NEXT: addi a2, a2, 8192009; RV64-NEXT: addi a3, a3, -2412010; RV64-NEXT: addi a4, a4, 2572011; RV64-NEXT: slli a5, a1, 322012; RV64-NEXT: add a1, a1, a52013; RV64-NEXT: slli a5, a2, 322014; RV64-NEXT: add a2, a2, a52015; RV64-NEXT: slli a5, a3, 322016; RV64-NEXT: add a3, a3, a52017; RV64-NEXT: slli a5, a4, 322018; RV64-NEXT: add a4, a4, a52019; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2020; RV64-NEXT: vadd.vi v16, v8, -1, v0.t2021; RV64-NEXT: vnot.v v8, v8, v0.t2022; RV64-NEXT: vand.vv v8, v8, v16, v0.t2023; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t2024; RV64-NEXT: vand.vx v16, v16, a1, v0.t2025; RV64-NEXT: vsub.vv v8, v8, v16, v0.t2026; RV64-NEXT: vand.vx v16, v8, a2, v0.t2027; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t2028; RV64-NEXT: vand.vx v8, v8, a2, v0.t2029; RV64-NEXT: vadd.vv v8, v16, v8, v0.t2030; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t2031; RV64-NEXT: vadd.vv v8, v8, v16, v0.t2032; RV64-NEXT: vand.vx v8, v8, a3, v0.t2033; RV64-NEXT: li a0, 562034; RV64-NEXT: vmul.vx v8, v8, a4, v0.t2035; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t2036; RV64-NEXT: ret2037;2038; CHECK-ZVBB-LABEL: vp_cttz_nxv8i64:2039; CHECK-ZVBB: # %bb.0:2040; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma2041; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t2042; CHECK-ZVBB-NEXT: ret2043 %v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)2044 ret <vscale x 8 x i64> %v2045}2046 2047define <vscale x 8 x i64> @vp_cttz_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {2048; RV32-LABEL: vp_cttz_nxv8i64_unmasked:2049; RV32: # %bb.0:2050; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2051; RV32-NEXT: vadd.vi v16, v8, -12052; RV32-NEXT: vnot.v v8, v82053; RV32-NEXT: lui a1, 3495252054; RV32-NEXT: addi a1, a1, 13652055; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma2056; RV32-NEXT: vmv.v.x v24, a12057; RV32-NEXT: lui a1, 2097152058; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2059; RV32-NEXT: vand.vv v8, v8, v162060; RV32-NEXT: addi a1, a1, 8192061; RV32-NEXT: vsrl.vi v16, v8, 12062; RV32-NEXT: vand.vv v24, v16, v242063; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma2064; RV32-NEXT: vmv.v.x v16, a12065; RV32-NEXT: lui a1, 616812066; RV32-NEXT: addi a1, a1, -2412067; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2068; RV32-NEXT: vsub.vv v8, v8, v242069; RV32-NEXT: vand.vv v24, v8, v162070; RV32-NEXT: vsrl.vi v8, v8, 22071; RV32-NEXT: vand.vv v8, v8, v162072; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma2073; RV32-NEXT: vmv.v.x v16, a12074; RV32-NEXT: lui a1, 41122075; RV32-NEXT: addi a1, a1, 2572076; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2077; RV32-NEXT: vadd.vv v8, v24, v82078; RV32-NEXT: vsrl.vi v24, v8, 42079; RV32-NEXT: vadd.vv v8, v8, v242080; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma2081; RV32-NEXT: vmv.v.x v24, a12082; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2083; RV32-NEXT: vand.vv v8, v8, v162084; RV32-NEXT: vmul.vv v8, v8, v242085; RV32-NEXT: li a0, 562086; RV32-NEXT: vsrl.vx v8, v8, a02087; RV32-NEXT: ret2088;2089; RV64-LABEL: vp_cttz_nxv8i64_unmasked:2090; RV64: # %bb.0:2091; RV64-NEXT: lui a1, 3495252092; RV64-NEXT: lui a2, 2097152093; RV64-NEXT: lui a3, 616812094; RV64-NEXT: lui a4, 41122095; RV64-NEXT: addi a1, a1, 13652096; RV64-NEXT: addi a2, a2, 8192097; RV64-NEXT: addi a3, a3, -2412098; RV64-NEXT: addi a4, a4, 2572099; RV64-NEXT: slli a5, a1, 322100; RV64-NEXT: add a1, a1, a52101; RV64-NEXT: slli a5, a2, 322102; RV64-NEXT: add a2, a2, a52103; RV64-NEXT: slli a5, a3, 322104; RV64-NEXT: add a3, a3, a52105; RV64-NEXT: slli a5, a4, 322106; RV64-NEXT: add a4, a4, a52107; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2108; RV64-NEXT: vadd.vi v16, v8, -12109; RV64-NEXT: vnot.v v8, v82110; RV64-NEXT: vand.vv v8, v8, v162111; RV64-NEXT: vsrl.vi v16, v8, 12112; RV64-NEXT: vand.vx v16, v16, a12113; RV64-NEXT: vsub.vv v8, v8, v162114; RV64-NEXT: vand.vx v16, v8, a22115; RV64-NEXT: vsrl.vi v8, v8, 22116; RV64-NEXT: vand.vx v8, v8, a22117; RV64-NEXT: vadd.vv v8, v16, v82118; RV64-NEXT: vsrl.vi v16, v8, 42119; RV64-NEXT: vadd.vv v8, v8, v162120; RV64-NEXT: vand.vx v8, v8, a32121; RV64-NEXT: vmul.vx v8, v8, a42122; RV64-NEXT: li a0, 562123; RV64-NEXT: vsrl.vx v8, v8, a02124; RV64-NEXT: ret2125;2126; CHECK-ZVBB-LABEL: vp_cttz_nxv8i64_unmasked:2127; CHECK-ZVBB: # %bb.0:2128; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma2129; CHECK-ZVBB-NEXT: vctz.v v8, v82130; CHECK-ZVBB-NEXT: ret2131 %v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)2132 ret <vscale x 8 x i64> %v2133}2134 2135define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {2136; RV32-LABEL: vp_cttz_nxv16i64:2137; RV32: # %bb.0:2138; RV32-NEXT: addi sp, sp, -162139; RV32-NEXT: .cfi_def_cfa_offset 162140; RV32-NEXT: csrr a1, vlenb2141; RV32-NEXT: li a2, 482142; RV32-NEXT: mul a1, a1, a22143; RV32-NEXT: sub sp, sp, a12144; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb2145; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, ma2146; RV32-NEXT: vmv1r.v v7, v02147; RV32-NEXT: csrr a1, vlenb2148; RV32-NEXT: li a2, 402149; RV32-NEXT: mul a1, a1, a22150; RV32-NEXT: add a1, sp, a12151; RV32-NEXT: addi a1, a1, 162152; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill2153; RV32-NEXT: csrr a1, vlenb2154; RV32-NEXT: srli a2, a1, 32155; RV32-NEXT: sub a3, a0, a12156; RV32-NEXT: vslidedown.vx v0, v0, a22157; RV32-NEXT: sltu a2, a0, a32158; RV32-NEXT: addi a2, a2, -12159; RV32-NEXT: and a2, a2, a32160; RV32-NEXT: lui a3, 3495252161; RV32-NEXT: addi a3, a3, 13652162; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2163; RV32-NEXT: vadd.vi v8, v16, -1, v0.t2164; RV32-NEXT: vnot.v v16, v16, v0.t2165; RV32-NEXT: vand.vv v8, v16, v8, v0.t2166; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2167; RV32-NEXT: vmv.v.x v24, a32168; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2169; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t2170; RV32-NEXT: csrr a3, vlenb2171; RV32-NEXT: slli a3, a3, 52172; RV32-NEXT: add a3, sp, a32173; RV32-NEXT: addi a3, a3, 162174; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill2175; RV32-NEXT: vand.vv v16, v16, v24, v0.t2176; RV32-NEXT: vsub.vv v8, v8, v16, v0.t2177; RV32-NEXT: lui a3, 2097152178; RV32-NEXT: addi a3, a3, 8192179; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2180; RV32-NEXT: vmv.v.x v24, a32181; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2182; RV32-NEXT: vand.vv v16, v8, v24, v0.t2183; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t2184; RV32-NEXT: csrr a3, vlenb2185; RV32-NEXT: li a4, 242186; RV32-NEXT: mul a3, a3, a42187; RV32-NEXT: add a3, sp, a32188; RV32-NEXT: addi a3, a3, 162189; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill2190; RV32-NEXT: vand.vv v8, v8, v24, v0.t2191; RV32-NEXT: vadd.vv v8, v16, v8, v0.t2192; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t2193; RV32-NEXT: vadd.vv v8, v8, v16, v0.t2194; RV32-NEXT: lui a3, 616812195; RV32-NEXT: addi a3, a3, -2412196; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2197; RV32-NEXT: vmv.v.x v16, a32198; RV32-NEXT: csrr a3, vlenb2199; RV32-NEXT: slli a3, a3, 42200; RV32-NEXT: add a3, sp, a32201; RV32-NEXT: addi a3, a3, 162202; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill2203; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2204; RV32-NEXT: vand.vv v16, v8, v16, v0.t2205; RV32-NEXT: lui a3, 41122206; RV32-NEXT: addi a3, a3, 2572207; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2208; RV32-NEXT: vmv.v.x v8, a32209; RV32-NEXT: csrr a3, vlenb2210; RV32-NEXT: slli a3, a3, 32211; RV32-NEXT: add a3, sp, a32212; RV32-NEXT: addi a3, a3, 162213; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill2214; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2215; RV32-NEXT: vmul.vv v16, v16, v8, v0.t2216; RV32-NEXT: li a2, 562217; RV32-NEXT: vsrl.vx v8, v16, a2, v0.t2218; RV32-NEXT: addi a3, sp, 162219; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill2220; RV32-NEXT: bltu a0, a1, .LBB46_22221; RV32-NEXT: # %bb.1:2222; RV32-NEXT: mv a0, a12223; RV32-NEXT: .LBB46_2:2224; RV32-NEXT: vmv1r.v v0, v72225; RV32-NEXT: li a3, 402226; RV32-NEXT: mul a1, a1, a32227; RV32-NEXT: add a1, sp, a12228; RV32-NEXT: addi a1, a1, 162229; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload2230; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2231; RV32-NEXT: vadd.vi v16, v8, -1, v0.t2232; RV32-NEXT: vnot.v v8, v8, v0.t2233; RV32-NEXT: vand.vv v8, v8, v16, v0.t2234; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t2235; RV32-NEXT: csrr a0, vlenb2236; RV32-NEXT: slli a0, a0, 52237; RV32-NEXT: add a0, sp, a02238; RV32-NEXT: addi a0, a0, 162239; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload2240; RV32-NEXT: vand.vv v16, v16, v24, v0.t2241; RV32-NEXT: vsub.vv v8, v8, v16, v0.t2242; RV32-NEXT: csrr a0, vlenb2243; RV32-NEXT: li a1, 242244; RV32-NEXT: mul a0, a0, a12245; RV32-NEXT: add a0, sp, a02246; RV32-NEXT: addi a0, a0, 162247; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload2248; RV32-NEXT: vand.vv v16, v8, v24, v0.t2249; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t2250; RV32-NEXT: vand.vv v8, v8, v24, v0.t2251; RV32-NEXT: vadd.vv v8, v16, v8, v0.t2252; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t2253; RV32-NEXT: vadd.vv v8, v8, v16, v0.t2254; RV32-NEXT: csrr a0, vlenb2255; RV32-NEXT: slli a0, a0, 42256; RV32-NEXT: add a0, sp, a02257; RV32-NEXT: addi a0, a0, 162258; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2259; RV32-NEXT: vand.vv v8, v8, v16, v0.t2260; RV32-NEXT: csrr a0, vlenb2261; RV32-NEXT: slli a0, a0, 32262; RV32-NEXT: add a0, sp, a02263; RV32-NEXT: addi a0, a0, 162264; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2265; RV32-NEXT: vmul.vv v8, v8, v16, v0.t2266; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t2267; RV32-NEXT: addi a0, sp, 162268; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2269; RV32-NEXT: csrr a0, vlenb2270; RV32-NEXT: li a1, 482271; RV32-NEXT: mul a0, a0, a12272; RV32-NEXT: add sp, sp, a02273; RV32-NEXT: .cfi_def_cfa sp, 162274; RV32-NEXT: addi sp, sp, 162275; RV32-NEXT: .cfi_def_cfa_offset 02276; RV32-NEXT: ret2277;2278; RV64-LABEL: vp_cttz_nxv16i64:2279; RV64: # %bb.0:2280; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma2281; RV64-NEXT: vmv1r.v v7, v02282; RV64-NEXT: csrr a1, vlenb2283; RV64-NEXT: lui a2, 3495252284; RV64-NEXT: lui a3, 2097152285; RV64-NEXT: lui a4, 616812286; RV64-NEXT: lui a5, 41122287; RV64-NEXT: srli a6, a1, 32288; RV64-NEXT: sub a7, a0, a12289; RV64-NEXT: addi a2, a2, 13652290; RV64-NEXT: addi a3, a3, 8192291; RV64-NEXT: addi a4, a4, -2412292; RV64-NEXT: addi t0, a5, 2572293; RV64-NEXT: vslidedown.vx v0, v0, a62294; RV64-NEXT: slli a6, a2, 322295; RV64-NEXT: add a6, a2, a62296; RV64-NEXT: slli a5, a3, 322297; RV64-NEXT: add a5, a3, a52298; RV64-NEXT: slli a2, a4, 322299; RV64-NEXT: add a2, a4, a22300; RV64-NEXT: slli a3, t0, 322301; RV64-NEXT: add a3, t0, a32302; RV64-NEXT: sltu a4, a0, a72303; RV64-NEXT: addi a4, a4, -12304; RV64-NEXT: and a7, a4, a72305; RV64-NEXT: li a4, 562306; RV64-NEXT: vsetvli zero, a7, e64, m8, ta, ma2307; RV64-NEXT: vadd.vi v24, v16, -1, v0.t2308; RV64-NEXT: vnot.v v16, v16, v0.t2309; RV64-NEXT: vand.vv v16, v16, v24, v0.t2310; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t2311; RV64-NEXT: vand.vx v24, v24, a6, v0.t2312; RV64-NEXT: vsub.vv v16, v16, v24, v0.t2313; RV64-NEXT: vand.vx v24, v16, a5, v0.t2314; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t2315; RV64-NEXT: vand.vx v16, v16, a5, v0.t2316; RV64-NEXT: vadd.vv v16, v24, v16, v0.t2317; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t2318; RV64-NEXT: vadd.vv v16, v16, v24, v0.t2319; RV64-NEXT: vand.vx v16, v16, a2, v0.t2320; RV64-NEXT: vmul.vx v16, v16, a3, v0.t2321; RV64-NEXT: vsrl.vx v16, v16, a4, v0.t2322; RV64-NEXT: bltu a0, a1, .LBB46_22323; RV64-NEXT: # %bb.1:2324; RV64-NEXT: mv a0, a12325; RV64-NEXT: .LBB46_2:2326; RV64-NEXT: vmv1r.v v0, v72327; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2328; RV64-NEXT: vadd.vi v24, v8, -1, v0.t2329; RV64-NEXT: vnot.v v8, v8, v0.t2330; RV64-NEXT: vand.vv v8, v8, v24, v0.t2331; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t2332; RV64-NEXT: vand.vx v24, v24, a6, v0.t2333; RV64-NEXT: vsub.vv v8, v8, v24, v0.t2334; RV64-NEXT: vand.vx v24, v8, a5, v0.t2335; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t2336; RV64-NEXT: vand.vx v8, v8, a5, v0.t2337; RV64-NEXT: vadd.vv v8, v24, v8, v0.t2338; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t2339; RV64-NEXT: vadd.vv v8, v8, v24, v0.t2340; RV64-NEXT: vand.vx v8, v8, a2, v0.t2341; RV64-NEXT: vmul.vx v8, v8, a3, v0.t2342; RV64-NEXT: vsrl.vx v8, v8, a4, v0.t2343; RV64-NEXT: ret2344;2345; CHECK-ZVBB-LABEL: vp_cttz_nxv16i64:2346; CHECK-ZVBB: # %bb.0:2347; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma2348; CHECK-ZVBB-NEXT: vmv1r.v v24, v02349; CHECK-ZVBB-NEXT: csrr a1, vlenb2350; CHECK-ZVBB-NEXT: srli a2, a1, 32351; CHECK-ZVBB-NEXT: sub a3, a0, a12352; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a22353; CHECK-ZVBB-NEXT: sltu a2, a0, a32354; CHECK-ZVBB-NEXT: addi a2, a2, -12355; CHECK-ZVBB-NEXT: and a2, a2, a32356; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma2357; CHECK-ZVBB-NEXT: vctz.v v16, v16, v0.t2358; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_22359; CHECK-ZVBB-NEXT: # %bb.1:2360; CHECK-ZVBB-NEXT: mv a0, a12361; CHECK-ZVBB-NEXT: .LBB46_2:2362; CHECK-ZVBB-NEXT: vmv1r.v v0, v242363; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma2364; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t2365; CHECK-ZVBB-NEXT: ret2366 %v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)2367 ret <vscale x 16 x i64> %v2368}2369 2370define <vscale x 16 x i64> @vp_cttz_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {2371; RV32-LABEL: vp_cttz_nxv16i64_unmasked:2372; RV32: # %bb.0:2373; RV32-NEXT: addi sp, sp, -162374; RV32-NEXT: .cfi_def_cfa_offset 162375; RV32-NEXT: csrr a1, vlenb2376; RV32-NEXT: slli a1, a1, 52377; RV32-NEXT: sub sp, sp, a12378; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb2379; RV32-NEXT: csrr a1, vlenb2380; RV32-NEXT: lui a2, 3495252381; RV32-NEXT: lui a3, 2097152382; RV32-NEXT: sub a4, a0, a12383; RV32-NEXT: addi a2, a2, 13652384; RV32-NEXT: addi a3, a3, 8192385; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma2386; RV32-NEXT: vmv.v.x v0, a22387; RV32-NEXT: sltu a2, a0, a42388; RV32-NEXT: addi a2, a2, -12389; RV32-NEXT: and a2, a2, a42390; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2391; RV32-NEXT: vadd.vi v24, v16, -12392; RV32-NEXT: vnot.v v16, v162393; RV32-NEXT: vand.vv v24, v16, v242394; RV32-NEXT: vsrl.vi v16, v24, 12395; RV32-NEXT: csrr a4, vlenb2396; RV32-NEXT: li a5, 242397; RV32-NEXT: mul a4, a4, a52398; RV32-NEXT: add a4, sp, a42399; RV32-NEXT: addi a4, a4, 162400; RV32-NEXT: vs8r.v v0, (a4) # vscale x 64-byte Folded Spill2401; RV32-NEXT: vand.vv v16, v16, v02402; RV32-NEXT: vsub.vv v24, v24, v162403; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2404; RV32-NEXT: vmv.v.x v0, a32405; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2406; RV32-NEXT: vand.vv v16, v24, v02407; RV32-NEXT: vsrl.vi v24, v24, 22408; RV32-NEXT: csrr a3, vlenb2409; RV32-NEXT: slli a3, a3, 42410; RV32-NEXT: add a3, sp, a32411; RV32-NEXT: addi a3, a3, 162412; RV32-NEXT: vs8r.v v0, (a3) # vscale x 64-byte Folded Spill2413; RV32-NEXT: vand.vv v24, v24, v02414; RV32-NEXT: vadd.vv v24, v16, v242415; RV32-NEXT: vsrl.vi v16, v24, 42416; RV32-NEXT: vadd.vv v16, v24, v162417; RV32-NEXT: lui a3, 616812418; RV32-NEXT: lui a4, 41122419; RV32-NEXT: addi a3, a3, -2412420; RV32-NEXT: addi a4, a4, 2572421; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma2422; RV32-NEXT: vmv.v.x v24, a32423; RV32-NEXT: csrr a3, vlenb2424; RV32-NEXT: slli a3, a3, 32425; RV32-NEXT: add a3, sp, a32426; RV32-NEXT: addi a3, a3, 162427; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill2428; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2429; RV32-NEXT: vand.vv v16, v16, v242430; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma2431; RV32-NEXT: vmv.v.x v24, a42432; RV32-NEXT: addi a3, sp, 162433; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill2434; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2435; RV32-NEXT: vmul.vv v16, v16, v242436; RV32-NEXT: li a2, 562437; RV32-NEXT: vsrl.vx v16, v16, a22438; RV32-NEXT: bltu a0, a1, .LBB47_22439; RV32-NEXT: # %bb.1:2440; RV32-NEXT: mv a0, a12441; RV32-NEXT: .LBB47_2:2442; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2443; RV32-NEXT: vadd.vi v24, v8, -12444; RV32-NEXT: vnot.v v8, v82445; RV32-NEXT: vand.vv v8, v8, v242446; RV32-NEXT: vsrl.vi v24, v8, 12447; RV32-NEXT: csrr a0, vlenb2448; RV32-NEXT: li a1, 242449; RV32-NEXT: mul a0, a0, a12450; RV32-NEXT: add a0, sp, a02451; RV32-NEXT: addi a0, a0, 162452; RV32-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload2453; RV32-NEXT: vand.vv v24, v24, v02454; RV32-NEXT: vsub.vv v8, v8, v242455; RV32-NEXT: csrr a0, vlenb2456; RV32-NEXT: slli a0, a0, 42457; RV32-NEXT: add a0, sp, a02458; RV32-NEXT: addi a0, a0, 162459; RV32-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload2460; RV32-NEXT: vand.vv v24, v8, v02461; RV32-NEXT: vsrl.vi v8, v8, 22462; RV32-NEXT: vand.vv v8, v8, v02463; RV32-NEXT: vadd.vv v8, v24, v82464; RV32-NEXT: vsrl.vi v24, v8, 42465; RV32-NEXT: vadd.vv v8, v8, v242466; RV32-NEXT: csrr a0, vlenb2467; RV32-NEXT: slli a0, a0, 32468; RV32-NEXT: add a0, sp, a02469; RV32-NEXT: addi a0, a0, 162470; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload2471; RV32-NEXT: vand.vv v8, v8, v242472; RV32-NEXT: addi a0, sp, 162473; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload2474; RV32-NEXT: vmul.vv v8, v8, v242475; RV32-NEXT: vsrl.vx v8, v8, a22476; RV32-NEXT: csrr a0, vlenb2477; RV32-NEXT: slli a0, a0, 52478; RV32-NEXT: add sp, sp, a02479; RV32-NEXT: .cfi_def_cfa sp, 162480; RV32-NEXT: addi sp, sp, 162481; RV32-NEXT: .cfi_def_cfa_offset 02482; RV32-NEXT: ret2483;2484; RV64-LABEL: vp_cttz_nxv16i64_unmasked:2485; RV64: # %bb.0:2486; RV64-NEXT: csrr a1, vlenb2487; RV64-NEXT: lui a2, 3495252488; RV64-NEXT: lui a3, 2097152489; RV64-NEXT: lui a4, 616812490; RV64-NEXT: lui a5, 41122491; RV64-NEXT: sub a6, a0, a12492; RV64-NEXT: addi a2, a2, 13652493; RV64-NEXT: addi a3, a3, 8192494; RV64-NEXT: addi a7, a4, -2412495; RV64-NEXT: addi t0, a5, 2572496; RV64-NEXT: slli a5, a2, 322497; RV64-NEXT: add a5, a2, a52498; RV64-NEXT: slli a4, a3, 322499; RV64-NEXT: add a4, a3, a42500; RV64-NEXT: slli a2, a7, 322501; RV64-NEXT: add a2, a7, a22502; RV64-NEXT: slli a3, t0, 322503; RV64-NEXT: add a3, t0, a32504; RV64-NEXT: sltu a7, a0, a62505; RV64-NEXT: addi a7, a7, -12506; RV64-NEXT: and a6, a7, a62507; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma2508; RV64-NEXT: vadd.vi v24, v16, -12509; RV64-NEXT: vnot.v v16, v162510; RV64-NEXT: vand.vv v16, v16, v242511; RV64-NEXT: vsrl.vi v24, v16, 12512; RV64-NEXT: vand.vx v24, v24, a52513; RV64-NEXT: vsub.vv v16, v16, v242514; RV64-NEXT: vand.vx v24, v16, a42515; RV64-NEXT: vsrl.vi v16, v16, 22516; RV64-NEXT: vand.vx v16, v16, a42517; RV64-NEXT: vadd.vv v16, v24, v162518; RV64-NEXT: vsrl.vi v24, v16, 42519; RV64-NEXT: vadd.vv v16, v16, v242520; RV64-NEXT: vand.vx v16, v16, a22521; RV64-NEXT: vmul.vx v16, v16, a32522; RV64-NEXT: li a6, 562523; RV64-NEXT: vsrl.vx v16, v16, a62524; RV64-NEXT: bltu a0, a1, .LBB47_22525; RV64-NEXT: # %bb.1:2526; RV64-NEXT: mv a0, a12527; RV64-NEXT: .LBB47_2:2528; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2529; RV64-NEXT: vadd.vi v24, v8, -12530; RV64-NEXT: vnot.v v8, v82531; RV64-NEXT: vand.vv v8, v8, v242532; RV64-NEXT: vsrl.vi v24, v8, 12533; RV64-NEXT: vand.vx v24, v24, a52534; RV64-NEXT: vsub.vv v8, v8, v242535; RV64-NEXT: vand.vx v24, v8, a42536; RV64-NEXT: vsrl.vi v8, v8, 22537; RV64-NEXT: vand.vx v8, v8, a42538; RV64-NEXT: vadd.vv v8, v24, v82539; RV64-NEXT: vsrl.vi v24, v8, 42540; RV64-NEXT: vadd.vv v8, v8, v242541; RV64-NEXT: vand.vx v8, v8, a22542; RV64-NEXT: vmul.vx v8, v8, a32543; RV64-NEXT: vsrl.vx v8, v8, a62544; RV64-NEXT: ret2545;2546; CHECK-ZVBB-LABEL: vp_cttz_nxv16i64_unmasked:2547; CHECK-ZVBB: # %bb.0:2548; CHECK-ZVBB-NEXT: csrr a1, vlenb2549; CHECK-ZVBB-NEXT: sub a2, a0, a12550; CHECK-ZVBB-NEXT: sltu a3, a0, a22551; CHECK-ZVBB-NEXT: addi a3, a3, -12552; CHECK-ZVBB-NEXT: and a2, a3, a22553; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma2554; CHECK-ZVBB-NEXT: vctz.v v16, v162555; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB47_22556; CHECK-ZVBB-NEXT: # %bb.1:2557; CHECK-ZVBB-NEXT: mv a0, a12558; CHECK-ZVBB-NEXT: .LBB47_2:2559; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma2560; CHECK-ZVBB-NEXT: vctz.v v8, v82561; CHECK-ZVBB-NEXT: ret2562 %v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)2563 ret <vscale x 16 x i64> %v2564}2565 2566define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {2567; CHECK-LABEL: vp_cttz_zero_undef_nxv1i8:2568; CHECK: # %bb.0:2569; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma2570; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t2571; CHECK-NEXT: li a0, 1272572; CHECK-NEXT: vand.vv v8, v8, v9, v0.t2573; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma2574; CHECK-NEXT: vzext.vf2 v9, v8, v0.t2575; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t2576; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma2577; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t2578; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma2579; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t2580; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma2581; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t2582; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t2583; CHECK-NEXT: ret2584;2585; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i8:2586; CHECK-ZVBB: # %bb.0:2587; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma2588; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t2589; CHECK-ZVBB-NEXT: ret2590 %v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)2591 ret <vscale x 1 x i8> %v2592}2593 2594define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {2595; CHECK-LABEL: vp_cttz_zero_undef_nxv1i8_unmasked:2596; CHECK: # %bb.0:2597; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma2598; CHECK-NEXT: vrsub.vi v9, v8, 02599; CHECK-NEXT: vand.vv v8, v8, v92600; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma2601; CHECK-NEXT: vzext.vf2 v9, v82602; CHECK-NEXT: vfwcvt.f.xu.v v8, v92603; CHECK-NEXT: vnsrl.wi v8, v8, 232604; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma2605; CHECK-NEXT: vnsrl.wi v8, v8, 02606; CHECK-NEXT: li a0, 1272607; CHECK-NEXT: vsub.vx v8, v8, a02608; CHECK-NEXT: ret2609;2610; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i8_unmasked:2611; CHECK-ZVBB: # %bb.0:2612; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma2613; CHECK-ZVBB-NEXT: vctz.v v8, v82614; CHECK-ZVBB-NEXT: ret2615 %v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true, <vscale x 1 x i1> splat (i1 true), i32 %evl)2616 ret <vscale x 1 x i8> %v2617}2618 2619define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {2620; CHECK-LABEL: vp_cttz_zero_undef_nxv2i8:2621; CHECK: # %bb.0:2622; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma2623; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t2624; CHECK-NEXT: li a0, 1272625; CHECK-NEXT: vand.vv v8, v8, v9, v0.t2626; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma2627; CHECK-NEXT: vzext.vf2 v9, v8, v0.t2628; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t2629; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma2630; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t2631; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma2632; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t2633; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma2634; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t2635; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t2636; CHECK-NEXT: ret2637;2638; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i8:2639; CHECK-ZVBB: # %bb.0:2640; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma2641; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t2642; CHECK-ZVBB-NEXT: ret2643 %v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)2644 ret <vscale x 2 x i8> %v2645}2646 2647define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {2648; CHECK-LABEL: vp_cttz_zero_undef_nxv2i8_unmasked:2649; CHECK: # %bb.0:2650; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma2651; CHECK-NEXT: vrsub.vi v9, v8, 02652; CHECK-NEXT: vand.vv v8, v8, v92653; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma2654; CHECK-NEXT: vzext.vf2 v9, v82655; CHECK-NEXT: vfwcvt.f.xu.v v8, v92656; CHECK-NEXT: vnsrl.wi v8, v8, 232657; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma2658; CHECK-NEXT: vnsrl.wi v8, v8, 02659; CHECK-NEXT: li a0, 1272660; CHECK-NEXT: vsub.vx v8, v8, a02661; CHECK-NEXT: ret2662;2663; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i8_unmasked:2664; CHECK-ZVBB: # %bb.0:2665; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma2666; CHECK-ZVBB-NEXT: vctz.v v8, v82667; CHECK-ZVBB-NEXT: ret2668 %v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true, <vscale x 2 x i1> splat (i1 true), i32 %evl)2669 ret <vscale x 2 x i8> %v2670}2671 2672define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {2673; CHECK-LABEL: vp_cttz_zero_undef_nxv4i8:2674; CHECK: # %bb.0:2675; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma2676; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t2677; CHECK-NEXT: li a0, 1272678; CHECK-NEXT: vand.vv v8, v8, v9, v0.t2679; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma2680; CHECK-NEXT: vzext.vf2 v10, v8, v0.t2681; CHECK-NEXT: vfwcvt.f.xu.v v8, v10, v0.t2682; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma2683; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t2684; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma2685; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t2686; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma2687; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t2688; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t2689; CHECK-NEXT: ret2690;2691; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i8:2692; CHECK-ZVBB: # %bb.0:2693; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma2694; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t2695; CHECK-ZVBB-NEXT: ret2696 %v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)2697 ret <vscale x 4 x i8> %v2698}2699 2700define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {2701; CHECK-LABEL: vp_cttz_zero_undef_nxv4i8_unmasked:2702; CHECK: # %bb.0:2703; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma2704; CHECK-NEXT: vrsub.vi v9, v8, 02705; CHECK-NEXT: vand.vv v8, v8, v92706; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma2707; CHECK-NEXT: vzext.vf2 v10, v82708; CHECK-NEXT: vfwcvt.f.xu.v v8, v102709; CHECK-NEXT: vnsrl.wi v10, v8, 232710; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma2711; CHECK-NEXT: vnsrl.wi v8, v10, 02712; CHECK-NEXT: li a0, 1272713; CHECK-NEXT: vsub.vx v8, v8, a02714; CHECK-NEXT: ret2715;2716; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i8_unmasked:2717; CHECK-ZVBB: # %bb.0:2718; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma2719; CHECK-ZVBB-NEXT: vctz.v v8, v82720; CHECK-ZVBB-NEXT: ret2721 %v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true, <vscale x 4 x i1> splat (i1 true), i32 %evl)2722 ret <vscale x 4 x i8> %v2723}2724 2725define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {2726; CHECK-LABEL: vp_cttz_zero_undef_nxv8i8:2727; CHECK: # %bb.0:2728; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma2729; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t2730; CHECK-NEXT: li a0, 1272731; CHECK-NEXT: vand.vv v8, v8, v9, v0.t2732; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma2733; CHECK-NEXT: vzext.vf2 v12, v8, v0.t2734; CHECK-NEXT: vfwcvt.f.xu.v v8, v12, v0.t2735; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma2736; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t2737; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma2738; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t2739; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma2740; CHECK-NEXT: vnsrl.wi v8, v12, 0, v0.t2741; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t2742; CHECK-NEXT: ret2743;2744; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i8:2745; CHECK-ZVBB: # %bb.0:2746; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma2747; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t2748; CHECK-ZVBB-NEXT: ret2749 %v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)2750 ret <vscale x 8 x i8> %v2751}2752 2753define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {2754; CHECK-LABEL: vp_cttz_zero_undef_nxv8i8_unmasked:2755; CHECK: # %bb.0:2756; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma2757; CHECK-NEXT: vrsub.vi v9, v8, 02758; CHECK-NEXT: vand.vv v8, v8, v92759; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma2760; CHECK-NEXT: vzext.vf2 v12, v82761; CHECK-NEXT: vfwcvt.f.xu.v v8, v122762; CHECK-NEXT: vnsrl.wi v12, v8, 232763; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma2764; CHECK-NEXT: vnsrl.wi v8, v12, 02765; CHECK-NEXT: li a0, 1272766; CHECK-NEXT: vsub.vx v8, v8, a02767; CHECK-NEXT: ret2768;2769; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i8_unmasked:2770; CHECK-ZVBB: # %bb.0:2771; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma2772; CHECK-ZVBB-NEXT: vctz.v v8, v82773; CHECK-ZVBB-NEXT: ret2774 %v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true, <vscale x 8 x i1> splat (i1 true), i32 %evl)2775 ret <vscale x 8 x i8> %v2776}2777 2778define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {2779; CHECK-LABEL: vp_cttz_zero_undef_nxv16i8:2780; CHECK: # %bb.0:2781; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma2782; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t2783; CHECK-NEXT: li a0, 1272784; CHECK-NEXT: vand.vv v8, v8, v10, v0.t2785; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma2786; CHECK-NEXT: vzext.vf2 v16, v8, v0.t2787; CHECK-NEXT: vfwcvt.f.xu.v v8, v16, v0.t2788; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma2789; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t2790; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma2791; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t2792; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma2793; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t2794; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t2795; CHECK-NEXT: ret2796;2797; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i8:2798; CHECK-ZVBB: # %bb.0:2799; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma2800; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t2801; CHECK-ZVBB-NEXT: ret2802 %v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)2803 ret <vscale x 16 x i8> %v2804}2805 2806define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {2807; CHECK-LABEL: vp_cttz_zero_undef_nxv16i8_unmasked:2808; CHECK: # %bb.0:2809; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma2810; CHECK-NEXT: vrsub.vi v10, v8, 02811; CHECK-NEXT: vand.vv v8, v8, v102812; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma2813; CHECK-NEXT: vzext.vf2 v16, v82814; CHECK-NEXT: vfwcvt.f.xu.v v8, v162815; CHECK-NEXT: vnsrl.wi v16, v8, 232816; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma2817; CHECK-NEXT: vnsrl.wi v8, v16, 02818; CHECK-NEXT: li a0, 1272819; CHECK-NEXT: vsub.vx v8, v8, a02820; CHECK-NEXT: ret2821;2822; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i8_unmasked:2823; CHECK-ZVBB: # %bb.0:2824; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma2825; CHECK-ZVBB-NEXT: vctz.v v8, v82826; CHECK-ZVBB-NEXT: ret2827 %v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true, <vscale x 16 x i1> splat (i1 true), i32 %evl)2828 ret <vscale x 16 x i8> %v2829}2830 2831define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {2832; CHECK-LABEL: vp_cttz_zero_undef_nxv32i8:2833; CHECK: # %bb.0:2834; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma2835; CHECK-NEXT: vadd.vi v12, v8, -1, v0.t2836; CHECK-NEXT: li a0, 852837; CHECK-NEXT: vnot.v v8, v8, v0.t2838; CHECK-NEXT: vand.vv v8, v8, v12, v0.t2839; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t2840; CHECK-NEXT: vand.vx v12, v12, a0, v0.t2841; CHECK-NEXT: li a0, 512842; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t2843; CHECK-NEXT: vand.vx v12, v8, a0, v0.t2844; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2845; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2846; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t2847; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t2848; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t2849; CHECK-NEXT: vand.vi v8, v8, 15, v0.t2850; CHECK-NEXT: ret2851;2852; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv32i8:2853; CHECK-ZVBB: # %bb.0:2854; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma2855; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t2856; CHECK-ZVBB-NEXT: ret2857 %v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)2858 ret <vscale x 32 x i8> %v2859}2860 2861define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {2862; CHECK-LABEL: vp_cttz_zero_undef_nxv32i8_unmasked:2863; CHECK: # %bb.0:2864; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma2865; CHECK-NEXT: vadd.vi v12, v8, -12866; CHECK-NEXT: vnot.v v8, v82867; CHECK-NEXT: li a0, 852868; CHECK-NEXT: vand.vv v8, v8, v122869; CHECK-NEXT: vsrl.vi v12, v8, 12870; CHECK-NEXT: vand.vx v12, v12, a02871; CHECK-NEXT: li a0, 512872; CHECK-NEXT: vsub.vv v8, v8, v122873; CHECK-NEXT: vand.vx v12, v8, a02874; CHECK-NEXT: vsrl.vi v8, v8, 22875; CHECK-NEXT: vand.vx v8, v8, a02876; CHECK-NEXT: vadd.vv v8, v12, v82877; CHECK-NEXT: vsrl.vi v12, v8, 42878; CHECK-NEXT: vadd.vv v8, v8, v122879; CHECK-NEXT: vand.vi v8, v8, 152880; CHECK-NEXT: ret2881;2882; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv32i8_unmasked:2883; CHECK-ZVBB: # %bb.0:2884; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma2885; CHECK-ZVBB-NEXT: vctz.v v8, v82886; CHECK-ZVBB-NEXT: ret2887 %v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 true, <vscale x 32 x i1> splat (i1 true), i32 %evl)2888 ret <vscale x 32 x i8> %v2889}2890 2891define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {2892; CHECK-LABEL: vp_cttz_zero_undef_nxv64i8:2893; CHECK: # %bb.0:2894; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma2895; CHECK-NEXT: vadd.vi v16, v8, -1, v0.t2896; CHECK-NEXT: li a0, 852897; CHECK-NEXT: vnot.v v8, v8, v0.t2898; CHECK-NEXT: vand.vv v8, v8, v16, v0.t2899; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t2900; CHECK-NEXT: vand.vx v16, v16, a0, v0.t2901; CHECK-NEXT: li a0, 512902; CHECK-NEXT: vsub.vv v8, v8, v16, v0.t2903; CHECK-NEXT: vand.vx v16, v8, a0, v0.t2904; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2905; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2906; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t2907; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t2908; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t2909; CHECK-NEXT: vand.vi v8, v8, 15, v0.t2910; CHECK-NEXT: ret2911;2912; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv64i8:2913; CHECK-ZVBB: # %bb.0:2914; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma2915; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t2916; CHECK-ZVBB-NEXT: ret2917 %v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 true, <vscale x 64 x i1> %m, i32 %evl)2918 ret <vscale x 64 x i8> %v2919}2920 2921define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {2922; CHECK-LABEL: vp_cttz_zero_undef_nxv64i8_unmasked:2923; CHECK: # %bb.0:2924; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma2925; CHECK-NEXT: vadd.vi v16, v8, -12926; CHECK-NEXT: vnot.v v8, v82927; CHECK-NEXT: li a0, 852928; CHECK-NEXT: vand.vv v8, v8, v162929; CHECK-NEXT: vsrl.vi v16, v8, 12930; CHECK-NEXT: vand.vx v16, v16, a02931; CHECK-NEXT: li a0, 512932; CHECK-NEXT: vsub.vv v8, v8, v162933; CHECK-NEXT: vand.vx v16, v8, a02934; CHECK-NEXT: vsrl.vi v8, v8, 22935; CHECK-NEXT: vand.vx v8, v8, a02936; CHECK-NEXT: vadd.vv v8, v16, v82937; CHECK-NEXT: vsrl.vi v16, v8, 42938; CHECK-NEXT: vadd.vv v8, v8, v162939; CHECK-NEXT: vand.vi v8, v8, 152940; CHECK-NEXT: ret2941;2942; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv64i8_unmasked:2943; CHECK-ZVBB: # %bb.0:2944; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma2945; CHECK-ZVBB-NEXT: vctz.v v8, v82946; CHECK-ZVBB-NEXT: ret2947 %v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 true, <vscale x 64 x i1> splat (i1 true), i32 %evl)2948 ret <vscale x 64 x i8> %v2949}2950 2951define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {2952; CHECK-LABEL: vp_cttz_zero_undef_nxv1i16:2953; CHECK: # %bb.0:2954; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma2955; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t2956; CHECK-NEXT: li a0, 1272957; CHECK-NEXT: vand.vv v8, v8, v9, v0.t2958; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t2959; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma2960; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t2961; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma2962; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t2963; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t2964; CHECK-NEXT: ret2965;2966; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i16:2967; CHECK-ZVBB: # %bb.0:2968; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma2969; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t2970; CHECK-ZVBB-NEXT: ret2971 %v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)2972 ret <vscale x 1 x i16> %v2973}2974 2975define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {2976; CHECK-LABEL: vp_cttz_zero_undef_nxv1i16_unmasked:2977; CHECK: # %bb.0:2978; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma2979; CHECK-NEXT: vrsub.vi v9, v8, 02980; CHECK-NEXT: vand.vv v8, v8, v92981; CHECK-NEXT: vfwcvt.f.xu.v v9, v82982; CHECK-NEXT: vnsrl.wi v8, v9, 232983; CHECK-NEXT: li a0, 1272984; CHECK-NEXT: vsub.vx v8, v8, a02985; CHECK-NEXT: ret2986;2987; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i16_unmasked:2988; CHECK-ZVBB: # %bb.0:2989; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma2990; CHECK-ZVBB-NEXT: vctz.v v8, v82991; CHECK-ZVBB-NEXT: ret2992 %v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true, <vscale x 1 x i1> splat (i1 true), i32 %evl)2993 ret <vscale x 1 x i16> %v2994}2995 2996define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {2997; CHECK-LABEL: vp_cttz_zero_undef_nxv2i16:2998; CHECK: # %bb.0:2999; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma3000; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t3001; CHECK-NEXT: li a0, 1273002; CHECK-NEXT: vand.vv v8, v8, v9, v0.t3003; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t3004; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma3005; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t3006; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma3007; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t3008; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t3009; CHECK-NEXT: ret3010;3011; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i16:3012; CHECK-ZVBB: # %bb.0:3013; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma3014; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3015; CHECK-ZVBB-NEXT: ret3016 %v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)3017 ret <vscale x 2 x i16> %v3018}3019 3020define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {3021; CHECK-LABEL: vp_cttz_zero_undef_nxv2i16_unmasked:3022; CHECK: # %bb.0:3023; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma3024; CHECK-NEXT: vrsub.vi v9, v8, 03025; CHECK-NEXT: vand.vv v8, v8, v93026; CHECK-NEXT: vfwcvt.f.xu.v v9, v83027; CHECK-NEXT: vnsrl.wi v8, v9, 233028; CHECK-NEXT: li a0, 1273029; CHECK-NEXT: vsub.vx v8, v8, a03030; CHECK-NEXT: ret3031;3032; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i16_unmasked:3033; CHECK-ZVBB: # %bb.0:3034; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma3035; CHECK-ZVBB-NEXT: vctz.v v8, v83036; CHECK-ZVBB-NEXT: ret3037 %v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true, <vscale x 2 x i1> splat (i1 true), i32 %evl)3038 ret <vscale x 2 x i16> %v3039}3040 3041define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {3042; CHECK-LABEL: vp_cttz_zero_undef_nxv4i16:3043; CHECK: # %bb.0:3044; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma3045; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t3046; CHECK-NEXT: li a0, 1273047; CHECK-NEXT: vand.vv v10, v8, v9, v0.t3048; CHECK-NEXT: vfwcvt.f.xu.v v8, v10, v0.t3049; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma3050; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t3051; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma3052; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t3053; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t3054; CHECK-NEXT: ret3055;3056; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i16:3057; CHECK-ZVBB: # %bb.0:3058; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma3059; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3060; CHECK-ZVBB-NEXT: ret3061 %v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)3062 ret <vscale x 4 x i16> %v3063}3064 3065define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {3066; CHECK-LABEL: vp_cttz_zero_undef_nxv4i16_unmasked:3067; CHECK: # %bb.0:3068; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma3069; CHECK-NEXT: vrsub.vi v9, v8, 03070; CHECK-NEXT: vand.vv v10, v8, v93071; CHECK-NEXT: vfwcvt.f.xu.v v8, v103072; CHECK-NEXT: vnsrl.wi v10, v8, 233073; CHECK-NEXT: li a0, 1273074; CHECK-NEXT: vsub.vx v8, v10, a03075; CHECK-NEXT: ret3076;3077; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i16_unmasked:3078; CHECK-ZVBB: # %bb.0:3079; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma3080; CHECK-ZVBB-NEXT: vctz.v v8, v83081; CHECK-ZVBB-NEXT: ret3082 %v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true, <vscale x 4 x i1> splat (i1 true), i32 %evl)3083 ret <vscale x 4 x i16> %v3084}3085 3086define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {3087; CHECK-LABEL: vp_cttz_zero_undef_nxv8i16:3088; CHECK: # %bb.0:3089; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma3090; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t3091; CHECK-NEXT: li a0, 1273092; CHECK-NEXT: vand.vv v12, v8, v10, v0.t3093; CHECK-NEXT: vfwcvt.f.xu.v v8, v12, v0.t3094; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma3095; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t3096; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma3097; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t3098; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t3099; CHECK-NEXT: ret3100;3101; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i16:3102; CHECK-ZVBB: # %bb.0:3103; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma3104; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3105; CHECK-ZVBB-NEXT: ret3106 %v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)3107 ret <vscale x 8 x i16> %v3108}3109 3110define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {3111; CHECK-LABEL: vp_cttz_zero_undef_nxv8i16_unmasked:3112; CHECK: # %bb.0:3113; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma3114; CHECK-NEXT: vrsub.vi v10, v8, 03115; CHECK-NEXT: vand.vv v12, v8, v103116; CHECK-NEXT: vfwcvt.f.xu.v v8, v123117; CHECK-NEXT: vnsrl.wi v12, v8, 233118; CHECK-NEXT: li a0, 1273119; CHECK-NEXT: vsub.vx v8, v12, a03120; CHECK-NEXT: ret3121;3122; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i16_unmasked:3123; CHECK-ZVBB: # %bb.0:3124; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma3125; CHECK-ZVBB-NEXT: vctz.v v8, v83126; CHECK-ZVBB-NEXT: ret3127 %v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true, <vscale x 8 x i1> splat (i1 true), i32 %evl)3128 ret <vscale x 8 x i16> %v3129}3130 3131define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {3132; CHECK-LABEL: vp_cttz_zero_undef_nxv16i16:3133; CHECK: # %bb.0:3134; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma3135; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t3136; CHECK-NEXT: li a0, 1273137; CHECK-NEXT: vand.vv v16, v8, v12, v0.t3138; CHECK-NEXT: vfwcvt.f.xu.v v8, v16, v0.t3139; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma3140; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t3141; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma3142; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t3143; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t3144; CHECK-NEXT: ret3145;3146; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i16:3147; CHECK-ZVBB: # %bb.0:3148; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma3149; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3150; CHECK-ZVBB-NEXT: ret3151 %v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)3152 ret <vscale x 16 x i16> %v3153}3154 3155define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {3156; CHECK-LABEL: vp_cttz_zero_undef_nxv16i16_unmasked:3157; CHECK: # %bb.0:3158; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma3159; CHECK-NEXT: vrsub.vi v12, v8, 03160; CHECK-NEXT: vand.vv v16, v8, v123161; CHECK-NEXT: vfwcvt.f.xu.v v8, v163162; CHECK-NEXT: vnsrl.wi v16, v8, 233163; CHECK-NEXT: li a0, 1273164; CHECK-NEXT: vsub.vx v8, v16, a03165; CHECK-NEXT: ret3166;3167; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i16_unmasked:3168; CHECK-ZVBB: # %bb.0:3169; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma3170; CHECK-ZVBB-NEXT: vctz.v v8, v83171; CHECK-ZVBB-NEXT: ret3172 %v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true, <vscale x 16 x i1> splat (i1 true), i32 %evl)3173 ret <vscale x 16 x i16> %v3174}3175 3176define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {3177; CHECK-LABEL: vp_cttz_zero_undef_nxv32i16:3178; CHECK: # %bb.0:3179; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma3180; CHECK-NEXT: vadd.vi v16, v8, -1, v0.t3181; CHECK-NEXT: lui a0, 53182; CHECK-NEXT: vnot.v v8, v8, v0.t3183; CHECK-NEXT: addi a0, a0, 13653184; CHECK-NEXT: vand.vv v8, v8, v16, v0.t3185; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t3186; CHECK-NEXT: vand.vx v16, v16, a0, v0.t3187; CHECK-NEXT: lui a0, 33188; CHECK-NEXT: addi a0, a0, 8193189; CHECK-NEXT: vsub.vv v16, v8, v16, v0.t3190; CHECK-NEXT: vand.vx v8, v16, a0, v0.t3191; CHECK-NEXT: vsrl.vi v16, v16, 2, v0.t3192; CHECK-NEXT: vand.vx v16, v16, a0, v0.t3193; CHECK-NEXT: lui a0, 13194; CHECK-NEXT: addi a0, a0, -2413195; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t3196; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t3197; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t3198; CHECK-NEXT: vand.vx v8, v8, a0, v0.t3199; CHECK-NEXT: li a0, 2573200; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t3201; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t3202; CHECK-NEXT: ret3203;3204; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv32i16:3205; CHECK-ZVBB: # %bb.0:3206; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma3207; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3208; CHECK-ZVBB-NEXT: ret3209 %v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)3210 ret <vscale x 32 x i16> %v3211}3212 3213define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {3214; CHECK-LABEL: vp_cttz_zero_undef_nxv32i16_unmasked:3215; CHECK: # %bb.0:3216; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma3217; CHECK-NEXT: vadd.vi v16, v8, -13218; CHECK-NEXT: vnot.v v8, v83219; CHECK-NEXT: lui a0, 53220; CHECK-NEXT: vand.vv v8, v8, v163221; CHECK-NEXT: addi a0, a0, 13653222; CHECK-NEXT: vsrl.vi v16, v8, 13223; CHECK-NEXT: vand.vx v16, v16, a03224; CHECK-NEXT: lui a0, 33225; CHECK-NEXT: addi a0, a0, 8193226; CHECK-NEXT: vsub.vv v8, v8, v163227; CHECK-NEXT: vand.vx v16, v8, a03228; CHECK-NEXT: vsrl.vi v8, v8, 23229; CHECK-NEXT: vand.vx v8, v8, a03230; CHECK-NEXT: lui a0, 13231; CHECK-NEXT: addi a0, a0, -2413232; CHECK-NEXT: vadd.vv v8, v16, v83233; CHECK-NEXT: vsrl.vi v16, v8, 43234; CHECK-NEXT: vadd.vv v8, v8, v163235; CHECK-NEXT: vand.vx v8, v8, a03236; CHECK-NEXT: li a0, 2573237; CHECK-NEXT: vmul.vx v8, v8, a03238; CHECK-NEXT: vsrl.vi v8, v8, 83239; CHECK-NEXT: ret3240;3241; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv32i16_unmasked:3242; CHECK-ZVBB: # %bb.0:3243; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma3244; CHECK-ZVBB-NEXT: vctz.v v8, v83245; CHECK-ZVBB-NEXT: ret3246 %v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 true, <vscale x 32 x i1> splat (i1 true), i32 %evl)3247 ret <vscale x 32 x i16> %v3248}3249 3250define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {3251; CHECK-LABEL: vp_cttz_zero_undef_nxv1i32:3252; CHECK: # %bb.0:3253; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma3254; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t3255; CHECK-NEXT: li a0, 523256; CHECK-NEXT: vand.vv v8, v8, v9, v0.t3257; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t3258; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma3259; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t3260; CHECK-NEXT: li a0, 10233261; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma3262; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t3263; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t3264; CHECK-NEXT: ret3265;3266; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i32:3267; CHECK-ZVBB: # %bb.0:3268; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma3269; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3270; CHECK-ZVBB-NEXT: ret3271 %v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)3272 ret <vscale x 1 x i32> %v3273}3274 3275define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {3276; CHECK-LABEL: vp_cttz_zero_undef_nxv1i32_unmasked:3277; CHECK: # %bb.0:3278; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma3279; CHECK-NEXT: vrsub.vi v9, v8, 03280; CHECK-NEXT: li a0, 523281; CHECK-NEXT: vand.vv v8, v8, v93282; CHECK-NEXT: vfwcvt.f.xu.v v9, v83283; CHECK-NEXT: vnsrl.wx v8, v9, a03284; CHECK-NEXT: li a0, 10233285; CHECK-NEXT: vsub.vx v8, v8, a03286; CHECK-NEXT: ret3287;3288; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i32_unmasked:3289; CHECK-ZVBB: # %bb.0:3290; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma3291; CHECK-ZVBB-NEXT: vctz.v v8, v83292; CHECK-ZVBB-NEXT: ret3293 %v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true, <vscale x 1 x i1> splat (i1 true), i32 %evl)3294 ret <vscale x 1 x i32> %v3295}3296 3297define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {3298; CHECK-LABEL: vp_cttz_zero_undef_nxv2i32:3299; CHECK: # %bb.0:3300; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma3301; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t3302; CHECK-NEXT: li a0, 523303; CHECK-NEXT: vand.vv v10, v8, v9, v0.t3304; CHECK-NEXT: vfwcvt.f.xu.v v8, v10, v0.t3305; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma3306; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t3307; CHECK-NEXT: li a0, 10233308; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma3309; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t3310; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t3311; CHECK-NEXT: ret3312;3313; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i32:3314; CHECK-ZVBB: # %bb.0:3315; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma3316; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3317; CHECK-ZVBB-NEXT: ret3318 %v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)3319 ret <vscale x 2 x i32> %v3320}3321 3322define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {3323; CHECK-LABEL: vp_cttz_zero_undef_nxv2i32_unmasked:3324; CHECK: # %bb.0:3325; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma3326; CHECK-NEXT: vrsub.vi v9, v8, 03327; CHECK-NEXT: li a0, 523328; CHECK-NEXT: vand.vv v10, v8, v93329; CHECK-NEXT: vfwcvt.f.xu.v v8, v103330; CHECK-NEXT: vnsrl.wx v10, v8, a03331; CHECK-NEXT: li a0, 10233332; CHECK-NEXT: vsub.vx v8, v10, a03333; CHECK-NEXT: ret3334;3335; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i32_unmasked:3336; CHECK-ZVBB: # %bb.0:3337; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma3338; CHECK-ZVBB-NEXT: vctz.v v8, v83339; CHECK-ZVBB-NEXT: ret3340 %v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true, <vscale x 2 x i1> splat (i1 true), i32 %evl)3341 ret <vscale x 2 x i32> %v3342}3343 3344define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {3345; CHECK-LABEL: vp_cttz_zero_undef_nxv4i32:3346; CHECK: # %bb.0:3347; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma3348; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t3349; CHECK-NEXT: li a0, 523350; CHECK-NEXT: vand.vv v12, v8, v10, v0.t3351; CHECK-NEXT: vfwcvt.f.xu.v v8, v12, v0.t3352; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma3353; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t3354; CHECK-NEXT: li a0, 10233355; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma3356; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t3357; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t3358; CHECK-NEXT: ret3359;3360; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i32:3361; CHECK-ZVBB: # %bb.0:3362; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma3363; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3364; CHECK-ZVBB-NEXT: ret3365 %v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)3366 ret <vscale x 4 x i32> %v3367}3368 3369define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {3370; CHECK-LABEL: vp_cttz_zero_undef_nxv4i32_unmasked:3371; CHECK: # %bb.0:3372; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma3373; CHECK-NEXT: vrsub.vi v10, v8, 03374; CHECK-NEXT: li a0, 523375; CHECK-NEXT: vand.vv v12, v8, v103376; CHECK-NEXT: vfwcvt.f.xu.v v8, v123377; CHECK-NEXT: vnsrl.wx v12, v8, a03378; CHECK-NEXT: li a0, 10233379; CHECK-NEXT: vsub.vx v8, v12, a03380; CHECK-NEXT: ret3381;3382; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i32_unmasked:3383; CHECK-ZVBB: # %bb.0:3384; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma3385; CHECK-ZVBB-NEXT: vctz.v v8, v83386; CHECK-ZVBB-NEXT: ret3387 %v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true, <vscale x 4 x i1> splat (i1 true), i32 %evl)3388 ret <vscale x 4 x i32> %v3389}3390 3391define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {3392; CHECK-LABEL: vp_cttz_zero_undef_nxv8i32:3393; CHECK: # %bb.0:3394; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma3395; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t3396; CHECK-NEXT: li a0, 523397; CHECK-NEXT: vand.vv v16, v8, v12, v0.t3398; CHECK-NEXT: vfwcvt.f.xu.v v8, v16, v0.t3399; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma3400; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t3401; CHECK-NEXT: li a0, 10233402; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma3403; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t3404; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t3405; CHECK-NEXT: ret3406;3407; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i32:3408; CHECK-ZVBB: # %bb.0:3409; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma3410; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3411; CHECK-ZVBB-NEXT: ret3412 %v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)3413 ret <vscale x 8 x i32> %v3414}3415 3416define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {3417; CHECK-LABEL: vp_cttz_zero_undef_nxv8i32_unmasked:3418; CHECK: # %bb.0:3419; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma3420; CHECK-NEXT: vrsub.vi v12, v8, 03421; CHECK-NEXT: li a0, 523422; CHECK-NEXT: vand.vv v16, v8, v123423; CHECK-NEXT: vfwcvt.f.xu.v v8, v163424; CHECK-NEXT: vnsrl.wx v16, v8, a03425; CHECK-NEXT: li a0, 10233426; CHECK-NEXT: vsub.vx v8, v16, a03427; CHECK-NEXT: ret3428;3429; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i32_unmasked:3430; CHECK-ZVBB: # %bb.0:3431; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma3432; CHECK-ZVBB-NEXT: vctz.v v8, v83433; CHECK-ZVBB-NEXT: ret3434 %v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true, <vscale x 8 x i1> splat (i1 true), i32 %evl)3435 ret <vscale x 8 x i32> %v3436}3437 3438define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {3439; CHECK-LABEL: vp_cttz_zero_undef_nxv16i32:3440; CHECK: # %bb.0:3441; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma3442; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t3443; CHECK-NEXT: fsrmi a0, 13444; CHECK-NEXT: li a1, 1273445; CHECK-NEXT: vand.vv v8, v8, v16, v0.t3446; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t3447; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t3448; CHECK-NEXT: vsub.vx v8, v8, a1, v0.t3449; CHECK-NEXT: fsrm a03450; CHECK-NEXT: ret3451;3452; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i32:3453; CHECK-ZVBB: # %bb.0:3454; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma3455; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3456; CHECK-ZVBB-NEXT: ret3457 %v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)3458 ret <vscale x 16 x i32> %v3459}3460 3461define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {3462; CHECK-LABEL: vp_cttz_zero_undef_nxv16i32_unmasked:3463; CHECK: # %bb.0:3464; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma3465; CHECK-NEXT: vrsub.vi v16, v8, 03466; CHECK-NEXT: fsrmi a0, 13467; CHECK-NEXT: vand.vv v8, v8, v163468; CHECK-NEXT: vfcvt.f.xu.v v8, v83469; CHECK-NEXT: vsrl.vi v8, v8, 233470; CHECK-NEXT: li a1, 1273471; CHECK-NEXT: vsub.vx v8, v8, a13472; CHECK-NEXT: fsrm a03473; CHECK-NEXT: ret3474;3475; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i32_unmasked:3476; CHECK-ZVBB: # %bb.0:3477; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma3478; CHECK-ZVBB-NEXT: vctz.v v8, v83479; CHECK-ZVBB-NEXT: ret3480 %v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 true, <vscale x 16 x i1> splat (i1 true), i32 %evl)3481 ret <vscale x 16 x i32> %v3482}3483 3484define <vscale x 1 x i64> @vp_cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {3485; CHECK-LABEL: vp_cttz_zero_undef_nxv1i64:3486; CHECK: # %bb.0:3487; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma3488; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t3489; CHECK-NEXT: fsrmi a0, 13490; CHECK-NEXT: li a1, 523491; CHECK-NEXT: vand.vv v8, v8, v9, v0.t3492; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t3493; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t3494; CHECK-NEXT: li a1, 10233495; CHECK-NEXT: vsub.vx v8, v8, a1, v0.t3496; CHECK-NEXT: fsrm a03497; CHECK-NEXT: ret3498;3499; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i64:3500; CHECK-ZVBB: # %bb.0:3501; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma3502; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3503; CHECK-ZVBB-NEXT: ret3504 %v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)3505 ret <vscale x 1 x i64> %v3506}3507 3508define <vscale x 1 x i64> @vp_cttz_zero_undef_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {3509; CHECK-LABEL: vp_cttz_zero_undef_nxv1i64_unmasked:3510; CHECK: # %bb.0:3511; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma3512; CHECK-NEXT: vrsub.vi v9, v8, 03513; CHECK-NEXT: fsrmi a0, 13514; CHECK-NEXT: li a1, 523515; CHECK-NEXT: vand.vv v8, v8, v93516; CHECK-NEXT: vfcvt.f.xu.v v8, v83517; CHECK-NEXT: vsrl.vx v8, v8, a13518; CHECK-NEXT: li a1, 10233519; CHECK-NEXT: vsub.vx v8, v8, a13520; CHECK-NEXT: fsrm a03521; CHECK-NEXT: ret3522;3523; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i64_unmasked:3524; CHECK-ZVBB: # %bb.0:3525; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma3526; CHECK-ZVBB-NEXT: vctz.v v8, v83527; CHECK-ZVBB-NEXT: ret3528 %v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 true, <vscale x 1 x i1> splat (i1 true), i32 %evl)3529 ret <vscale x 1 x i64> %v3530}3531 3532define <vscale x 2 x i64> @vp_cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {3533; CHECK-LABEL: vp_cttz_zero_undef_nxv2i64:3534; CHECK: # %bb.0:3535; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma3536; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t3537; CHECK-NEXT: fsrmi a0, 13538; CHECK-NEXT: li a1, 523539; CHECK-NEXT: vand.vv v8, v8, v10, v0.t3540; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t3541; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t3542; CHECK-NEXT: li a1, 10233543; CHECK-NEXT: vsub.vx v8, v8, a1, v0.t3544; CHECK-NEXT: fsrm a03545; CHECK-NEXT: ret3546;3547; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i64:3548; CHECK-ZVBB: # %bb.0:3549; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma3550; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3551; CHECK-ZVBB-NEXT: ret3552 %v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)3553 ret <vscale x 2 x i64> %v3554}3555 3556define <vscale x 2 x i64> @vp_cttz_zero_undef_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {3557; CHECK-LABEL: vp_cttz_zero_undef_nxv2i64_unmasked:3558; CHECK: # %bb.0:3559; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma3560; CHECK-NEXT: vrsub.vi v10, v8, 03561; CHECK-NEXT: fsrmi a0, 13562; CHECK-NEXT: li a1, 523563; CHECK-NEXT: vand.vv v8, v8, v103564; CHECK-NEXT: vfcvt.f.xu.v v8, v83565; CHECK-NEXT: vsrl.vx v8, v8, a13566; CHECK-NEXT: li a1, 10233567; CHECK-NEXT: vsub.vx v8, v8, a13568; CHECK-NEXT: fsrm a03569; CHECK-NEXT: ret3570;3571; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i64_unmasked:3572; CHECK-ZVBB: # %bb.0:3573; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma3574; CHECK-ZVBB-NEXT: vctz.v v8, v83575; CHECK-ZVBB-NEXT: ret3576 %v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 true, <vscale x 2 x i1> splat (i1 true), i32 %evl)3577 ret <vscale x 2 x i64> %v3578}3579 3580define <vscale x 4 x i64> @vp_cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {3581; CHECK-LABEL: vp_cttz_zero_undef_nxv4i64:3582; CHECK: # %bb.0:3583; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma3584; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t3585; CHECK-NEXT: fsrmi a0, 13586; CHECK-NEXT: li a1, 523587; CHECK-NEXT: vand.vv v8, v8, v12, v0.t3588; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t3589; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t3590; CHECK-NEXT: li a1, 10233591; CHECK-NEXT: vsub.vx v8, v8, a1, v0.t3592; CHECK-NEXT: fsrm a03593; CHECK-NEXT: ret3594;3595; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i64:3596; CHECK-ZVBB: # %bb.0:3597; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma3598; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3599; CHECK-ZVBB-NEXT: ret3600 %v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)3601 ret <vscale x 4 x i64> %v3602}3603 3604define <vscale x 4 x i64> @vp_cttz_zero_undef_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {3605; CHECK-LABEL: vp_cttz_zero_undef_nxv4i64_unmasked:3606; CHECK: # %bb.0:3607; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma3608; CHECK-NEXT: vrsub.vi v12, v8, 03609; CHECK-NEXT: fsrmi a0, 13610; CHECK-NEXT: li a1, 523611; CHECK-NEXT: vand.vv v8, v8, v123612; CHECK-NEXT: vfcvt.f.xu.v v8, v83613; CHECK-NEXT: vsrl.vx v8, v8, a13614; CHECK-NEXT: li a1, 10233615; CHECK-NEXT: vsub.vx v8, v8, a13616; CHECK-NEXT: fsrm a03617; CHECK-NEXT: ret3618;3619; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i64_unmasked:3620; CHECK-ZVBB: # %bb.0:3621; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma3622; CHECK-ZVBB-NEXT: vctz.v v8, v83623; CHECK-ZVBB-NEXT: ret3624 %v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 true, <vscale x 4 x i1> splat (i1 true), i32 %evl)3625 ret <vscale x 4 x i64> %v3626}3627 3628define <vscale x 7 x i64> @vp_cttz_zero_undef_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {3629; CHECK-LABEL: vp_cttz_zero_undef_nxv7i64:3630; CHECK: # %bb.0:3631; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma3632; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t3633; CHECK-NEXT: fsrmi a0, 13634; CHECK-NEXT: li a1, 523635; CHECK-NEXT: vand.vv v8, v8, v16, v0.t3636; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t3637; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t3638; CHECK-NEXT: li a1, 10233639; CHECK-NEXT: vsub.vx v8, v8, a1, v0.t3640; CHECK-NEXT: fsrm a03641; CHECK-NEXT: ret3642;3643; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv7i64:3644; CHECK-ZVBB: # %bb.0:3645; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma3646; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3647; CHECK-ZVBB-NEXT: ret3648 %v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, i1 true, <vscale x 7 x i1> %m, i32 %evl)3649 ret <vscale x 7 x i64> %v3650}3651 3652define <vscale x 7 x i64> @vp_cttz_zero_undef_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {3653; CHECK-LABEL: vp_cttz_zero_undef_nxv7i64_unmasked:3654; CHECK: # %bb.0:3655; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma3656; CHECK-NEXT: vrsub.vi v16, v8, 03657; CHECK-NEXT: fsrmi a0, 13658; CHECK-NEXT: li a1, 523659; CHECK-NEXT: vand.vv v8, v8, v163660; CHECK-NEXT: vfcvt.f.xu.v v8, v83661; CHECK-NEXT: vsrl.vx v8, v8, a13662; CHECK-NEXT: li a1, 10233663; CHECK-NEXT: vsub.vx v8, v8, a13664; CHECK-NEXT: fsrm a03665; CHECK-NEXT: ret3666;3667; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv7i64_unmasked:3668; CHECK-ZVBB: # %bb.0:3669; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma3670; CHECK-ZVBB-NEXT: vctz.v v8, v83671; CHECK-ZVBB-NEXT: ret3672 %v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, i1 true, <vscale x 7 x i1> splat (i1 true), i32 %evl)3673 ret <vscale x 7 x i64> %v3674}3675 3676define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {3677; CHECK-LABEL: vp_cttz_zero_undef_nxv8i64:3678; CHECK: # %bb.0:3679; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma3680; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t3681; CHECK-NEXT: fsrmi a0, 13682; CHECK-NEXT: li a1, 523683; CHECK-NEXT: vand.vv v8, v8, v16, v0.t3684; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t3685; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t3686; CHECK-NEXT: li a1, 10233687; CHECK-NEXT: vsub.vx v8, v8, a1, v0.t3688; CHECK-NEXT: fsrm a03689; CHECK-NEXT: ret3690;3691; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i64:3692; CHECK-ZVBB: # %bb.0:3693; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma3694; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3695; CHECK-ZVBB-NEXT: ret3696 %v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)3697 ret <vscale x 8 x i64> %v3698}3699 3700define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {3701; CHECK-LABEL: vp_cttz_zero_undef_nxv8i64_unmasked:3702; CHECK: # %bb.0:3703; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma3704; CHECK-NEXT: vrsub.vi v16, v8, 03705; CHECK-NEXT: fsrmi a0, 13706; CHECK-NEXT: li a1, 523707; CHECK-NEXT: vand.vv v8, v8, v163708; CHECK-NEXT: vfcvt.f.xu.v v8, v83709; CHECK-NEXT: vsrl.vx v8, v8, a13710; CHECK-NEXT: li a1, 10233711; CHECK-NEXT: vsub.vx v8, v8, a13712; CHECK-NEXT: fsrm a03713; CHECK-NEXT: ret3714;3715; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i64_unmasked:3716; CHECK-ZVBB: # %bb.0:3717; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma3718; CHECK-ZVBB-NEXT: vctz.v v8, v83719; CHECK-ZVBB-NEXT: ret3720 %v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 true, <vscale x 8 x i1> splat (i1 true), i32 %evl)3721 ret <vscale x 8 x i64> %v3722}3723 3724define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {3725; CHECK-LABEL: vp_cttz_zero_undef_nxv16i64:3726; CHECK: # %bb.0:3727; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma3728; CHECK-NEXT: vmv1r.v v7, v03729; CHECK-NEXT: csrr a1, vlenb3730; CHECK-NEXT: fsrmi a3, 13731; CHECK-NEXT: srli a2, a1, 33732; CHECK-NEXT: sub a4, a0, a13733; CHECK-NEXT: vslidedown.vx v0, v0, a23734; CHECK-NEXT: sltu a2, a0, a43735; CHECK-NEXT: addi a2, a2, -13736; CHECK-NEXT: and a4, a2, a43737; CHECK-NEXT: li a2, 523738; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma3739; CHECK-NEXT: vrsub.vi v24, v16, 0, v0.t3740; CHECK-NEXT: vand.vv v16, v16, v24, v0.t3741; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t3742; CHECK-NEXT: fsrm a33743; CHECK-NEXT: vsrl.vx v16, v16, a2, v0.t3744; CHECK-NEXT: li a3, 10233745; CHECK-NEXT: vsub.vx v16, v16, a3, v0.t3746; CHECK-NEXT: bltu a0, a1, .LBB94_23747; CHECK-NEXT: # %bb.1:3748; CHECK-NEXT: mv a0, a13749; CHECK-NEXT: .LBB94_2:3750; CHECK-NEXT: vmv1r.v v0, v73751; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma3752; CHECK-NEXT: vrsub.vi v24, v8, 0, v0.t3753; CHECK-NEXT: fsrmi a0, 13754; CHECK-NEXT: vand.vv v8, v8, v24, v0.t3755; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t3756; CHECK-NEXT: vsrl.vx v8, v8, a2, v0.t3757; CHECK-NEXT: vsub.vx v8, v8, a3, v0.t3758; CHECK-NEXT: fsrm a03759; CHECK-NEXT: ret3760;3761; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i64:3762; CHECK-ZVBB: # %bb.0:3763; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma3764; CHECK-ZVBB-NEXT: vmv1r.v v24, v03765; CHECK-ZVBB-NEXT: csrr a1, vlenb3766; CHECK-ZVBB-NEXT: srli a2, a1, 33767; CHECK-ZVBB-NEXT: sub a3, a0, a13768; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a23769; CHECK-ZVBB-NEXT: sltu a2, a0, a33770; CHECK-ZVBB-NEXT: addi a2, a2, -13771; CHECK-ZVBB-NEXT: and a2, a2, a33772; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma3773; CHECK-ZVBB-NEXT: vctz.v v16, v16, v0.t3774; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB94_23775; CHECK-ZVBB-NEXT: # %bb.1:3776; CHECK-ZVBB-NEXT: mv a0, a13777; CHECK-ZVBB-NEXT: .LBB94_2:3778; CHECK-ZVBB-NEXT: vmv1r.v v0, v243779; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma3780; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3781; CHECK-ZVBB-NEXT: ret3782 %v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)3783 ret <vscale x 16 x i64> %v3784}3785 3786define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {3787; CHECK-LABEL: vp_cttz_zero_undef_nxv16i64_unmasked:3788; CHECK: # %bb.0:3789; CHECK-NEXT: csrr a1, vlenb3790; CHECK-NEXT: fsrmi a3, 13791; CHECK-NEXT: sub a2, a0, a13792; CHECK-NEXT: sltu a4, a0, a23793; CHECK-NEXT: addi a4, a4, -13794; CHECK-NEXT: and a4, a4, a23795; CHECK-NEXT: li a2, 523796; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma3797; CHECK-NEXT: vrsub.vi v24, v16, 03798; CHECK-NEXT: vand.vv v16, v16, v243799; CHECK-NEXT: vfcvt.f.xu.v v16, v163800; CHECK-NEXT: fsrm a33801; CHECK-NEXT: vsrl.vx v16, v16, a23802; CHECK-NEXT: li a3, 10233803; CHECK-NEXT: vsub.vx v16, v16, a33804; CHECK-NEXT: bltu a0, a1, .LBB95_23805; CHECK-NEXT: # %bb.1:3806; CHECK-NEXT: mv a0, a13807; CHECK-NEXT: .LBB95_2:3808; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma3809; CHECK-NEXT: vrsub.vi v24, v8, 03810; CHECK-NEXT: vand.vv v8, v8, v243811; CHECK-NEXT: fsrmi a0, 13812; CHECK-NEXT: vfcvt.f.xu.v v8, v83813; CHECK-NEXT: vsrl.vx v8, v8, a23814; CHECK-NEXT: vsub.vx v8, v8, a33815; CHECK-NEXT: fsrm a03816; CHECK-NEXT: ret3817;3818; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i64_unmasked:3819; CHECK-ZVBB: # %bb.0:3820; CHECK-ZVBB-NEXT: csrr a1, vlenb3821; CHECK-ZVBB-NEXT: sub a2, a0, a13822; CHECK-ZVBB-NEXT: sltu a3, a0, a23823; CHECK-ZVBB-NEXT: addi a3, a3, -13824; CHECK-ZVBB-NEXT: and a2, a3, a23825; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma3826; CHECK-ZVBB-NEXT: vctz.v v16, v163827; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB95_23828; CHECK-ZVBB-NEXT: # %bb.1:3829; CHECK-ZVBB-NEXT: mv a0, a13830; CHECK-ZVBB-NEXT: .LBB95_2:3831; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma3832; CHECK-ZVBB-NEXT: vctz.v v8, v83833; CHECK-ZVBB-NEXT: ret3834 %v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, i1 true, <vscale x 16 x i1> splat (i1 true), i32 %evl)3835 ret <vscale x 16 x i64> %v3836}3837 3838; Test promotion.3839define <vscale x 1 x i9> @vp_cttz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {3840; CHECK-LABEL: vp_cttz_nxv1i9:3841; CHECK: # %bb.0:3842; CHECK-NEXT: li a1, 5123843; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma3844; CHECK-NEXT: vor.vx v8, v8, a1, v0.t3845; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t3846; CHECK-NEXT: vand.vv v8, v8, v9, v0.t3847; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t3848; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma3849; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t3850; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma3851; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t3852; CHECK-NEXT: li a0, 1273853; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t3854; CHECK-NEXT: ret3855;3856; CHECK-ZVBB-LABEL: vp_cttz_nxv1i9:3857; CHECK-ZVBB: # %bb.0:3858; CHECK-ZVBB-NEXT: li a1, 5123859; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma3860; CHECK-ZVBB-NEXT: vor.vx v8, v8, a1, v0.t3861; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3862; CHECK-ZVBB-NEXT: ret3863 %v = call <vscale x 1 x i9> @llvm.vp.cttz.nxv1i9(<vscale x 1 x i9> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)3864 ret <vscale x 1 x i9> %v3865}3866define <vscale x 1 x i9> @vp_zero_undef_cttz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {3867; CHECK-LABEL: vp_zero_undef_cttz_nxv1i9:3868; CHECK: # %bb.0:3869; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma3870; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t3871; CHECK-NEXT: li a0, 1273872; CHECK-NEXT: vand.vv v8, v8, v9, v0.t3873; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t3874; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma3875; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t3876; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma3877; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t3878; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t3879; CHECK-NEXT: ret3880;3881; CHECK-ZVBB-LABEL: vp_zero_undef_cttz_nxv1i9:3882; CHECK-ZVBB: # %bb.0:3883; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma3884; CHECK-ZVBB-NEXT: vctz.v v8, v8, v0.t3885; CHECK-ZVBB-NEXT: ret3886 %v = call <vscale x 1 x i9> @llvm.vp.cttz.nxv1i9(<vscale x 1 x i9> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)3887 ret <vscale x 1 x i9> %v3888}3889