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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | \3; RUN: FileCheck %s -check-prefix=RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | \5; RUN: FileCheck %s -check-prefix=RV646 7; ================================================================================8; trunc <vscale x 1 x double>9; ================================================================================10 11define <vscale x 1 x i8> @trunc_nxv1f64_to_si8(<vscale x 1 x double> %x) {12; RV32-LABEL: trunc_nxv1f64_to_si8:13; RV32: # %bb.0:14; RV32-NEXT: lui a0, %hi(.LCPI0_0)15; RV32-NEXT: fld fa5, %lo(.LCPI0_0)(a0)16; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma17; RV32-NEXT: vfabs.v v9, v818; RV32-NEXT: vmflt.vf v0, v9, fa519; RV32-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t20; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t21; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu22; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t23; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma24; RV32-NEXT: vfncvt.rtz.x.f.w v9, v825; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma26; RV32-NEXT: vnsrl.wi v8, v9, 027; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma28; RV32-NEXT: vnsrl.wi v8, v8, 029; RV32-NEXT: ret30;31; RV64-LABEL: trunc_nxv1f64_to_si8:32; RV64: # %bb.0:33; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma34; RV64-NEXT: vfabs.v v9, v835; RV64-NEXT: li a0, 107536; RV64-NEXT: slli a0, a0, 5237; RV64-NEXT: fmv.d.x fa5, a038; RV64-NEXT: vmflt.vf v0, v9, fa539; RV64-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t40; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t41; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu42; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t43; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma44; RV64-NEXT: vfncvt.rtz.x.f.w v9, v845; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma46; RV64-NEXT: vnsrl.wi v8, v9, 047; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma48; RV64-NEXT: vnsrl.wi v8, v8, 049; RV64-NEXT: ret50 %a = call <vscale x 1 x double> @llvm.trunc.nxv1f64(<vscale x 1 x double> %x)51 %b = fptosi <vscale x 1 x double> %a to <vscale x 1 x i8>52 ret <vscale x 1 x i8> %b53}54 55define <vscale x 1 x i8> @trunc_nxv1f64_to_ui8(<vscale x 1 x double> %x) {56; RV32-LABEL: trunc_nxv1f64_to_ui8:57; RV32: # %bb.0:58; RV32-NEXT: lui a0, %hi(.LCPI1_0)59; RV32-NEXT: fld fa5, %lo(.LCPI1_0)(a0)60; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma61; RV32-NEXT: vfabs.v v9, v862; RV32-NEXT: vmflt.vf v0, v9, fa563; RV32-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t64; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t65; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu66; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t67; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma68; RV32-NEXT: vfncvt.rtz.xu.f.w v9, v869; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma70; RV32-NEXT: vnsrl.wi v8, v9, 071; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma72; RV32-NEXT: vnsrl.wi v8, v8, 073; RV32-NEXT: ret74;75; RV64-LABEL: trunc_nxv1f64_to_ui8:76; RV64: # %bb.0:77; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma78; RV64-NEXT: vfabs.v v9, v879; RV64-NEXT: li a0, 107580; RV64-NEXT: slli a0, a0, 5281; RV64-NEXT: fmv.d.x fa5, a082; RV64-NEXT: vmflt.vf v0, v9, fa583; RV64-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t84; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t85; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu86; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t87; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma88; RV64-NEXT: vfncvt.rtz.xu.f.w v9, v889; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma90; RV64-NEXT: vnsrl.wi v8, v9, 091; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma92; RV64-NEXT: vnsrl.wi v8, v8, 093; RV64-NEXT: ret94 %a = call <vscale x 1 x double> @llvm.trunc.nxv1f64(<vscale x 1 x double> %x)95 %b = fptoui <vscale x 1 x double> %a to <vscale x 1 x i8>96 ret <vscale x 1 x i8> %b97}98 99define <vscale x 1 x i16> @trunc_nxv1f64_to_si16(<vscale x 1 x double> %x) {100; RV32-LABEL: trunc_nxv1f64_to_si16:101; RV32: # %bb.0:102; RV32-NEXT: lui a0, %hi(.LCPI2_0)103; RV32-NEXT: fld fa5, %lo(.LCPI2_0)(a0)104; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma105; RV32-NEXT: vfabs.v v9, v8106; RV32-NEXT: vmflt.vf v0, v9, fa5107; RV32-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t108; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t109; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu110; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t111; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma112; RV32-NEXT: vfncvt.rtz.x.f.w v9, v8113; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma114; RV32-NEXT: vnsrl.wi v8, v9, 0115; RV32-NEXT: ret116;117; RV64-LABEL: trunc_nxv1f64_to_si16:118; RV64: # %bb.0:119; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma120; RV64-NEXT: vfabs.v v9, v8121; RV64-NEXT: li a0, 1075122; RV64-NEXT: slli a0, a0, 52123; RV64-NEXT: fmv.d.x fa5, a0124; RV64-NEXT: vmflt.vf v0, v9, fa5125; RV64-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t126; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t127; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu128; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t129; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma130; RV64-NEXT: vfncvt.rtz.x.f.w v9, v8131; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma132; RV64-NEXT: vnsrl.wi v8, v9, 0133; RV64-NEXT: ret134 %a = call <vscale x 1 x double> @llvm.trunc.nxv1f64(<vscale x 1 x double> %x)135 %b = fptosi <vscale x 1 x double> %a to <vscale x 1 x i16>136 ret <vscale x 1 x i16> %b137}138 139define <vscale x 1 x i16> @trunc_nxv1f64_to_ui16(<vscale x 1 x double> %x) {140; RV32-LABEL: trunc_nxv1f64_to_ui16:141; RV32: # %bb.0:142; RV32-NEXT: lui a0, %hi(.LCPI3_0)143; RV32-NEXT: fld fa5, %lo(.LCPI3_0)(a0)144; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma145; RV32-NEXT: vfabs.v v9, v8146; RV32-NEXT: vmflt.vf v0, v9, fa5147; RV32-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t148; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t149; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu150; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t151; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma152; RV32-NEXT: vfncvt.rtz.xu.f.w v9, v8153; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma154; RV32-NEXT: vnsrl.wi v8, v9, 0155; RV32-NEXT: ret156;157; RV64-LABEL: trunc_nxv1f64_to_ui16:158; RV64: # %bb.0:159; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma160; RV64-NEXT: vfabs.v v9, v8161; RV64-NEXT: li a0, 1075162; RV64-NEXT: slli a0, a0, 52163; RV64-NEXT: fmv.d.x fa5, a0164; RV64-NEXT: vmflt.vf v0, v9, fa5165; RV64-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t166; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t167; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu168; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t169; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma170; RV64-NEXT: vfncvt.rtz.xu.f.w v9, v8171; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma172; RV64-NEXT: vnsrl.wi v8, v9, 0173; RV64-NEXT: ret174 %a = call <vscale x 1 x double> @llvm.trunc.nxv1f64(<vscale x 1 x double> %x)175 %b = fptoui <vscale x 1 x double> %a to <vscale x 1 x i16>176 ret <vscale x 1 x i16> %b177}178 179define <vscale x 1 x i32> @trunc_nxv1f64_to_si32(<vscale x 1 x double> %x) {180; RV32-LABEL: trunc_nxv1f64_to_si32:181; RV32: # %bb.0:182; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma183; RV32-NEXT: vfncvt.rtz.x.f.w v9, v8184; RV32-NEXT: vmv1r.v v8, v9185; RV32-NEXT: ret186;187; RV64-LABEL: trunc_nxv1f64_to_si32:188; RV64: # %bb.0:189; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma190; RV64-NEXT: vfncvt.rtz.x.f.w v9, v8191; RV64-NEXT: vmv1r.v v8, v9192; RV64-NEXT: ret193 %a = call <vscale x 1 x double> @llvm.trunc.nxv1f64(<vscale x 1 x double> %x)194 %b = fptosi <vscale x 1 x double> %a to <vscale x 1 x i32>195 ret <vscale x 1 x i32> %b196}197 198define <vscale x 1 x i32> @trunc_nxv1f64_to_ui32(<vscale x 1 x double> %x) {199; RV32-LABEL: trunc_nxv1f64_to_ui32:200; RV32: # %bb.0:201; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma202; RV32-NEXT: vfncvt.rtz.xu.f.w v9, v8203; RV32-NEXT: vmv1r.v v8, v9204; RV32-NEXT: ret205;206; RV64-LABEL: trunc_nxv1f64_to_ui32:207; RV64: # %bb.0:208; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma209; RV64-NEXT: vfncvt.rtz.xu.f.w v9, v8210; RV64-NEXT: vmv1r.v v8, v9211; RV64-NEXT: ret212 %a = call <vscale x 1 x double> @llvm.trunc.nxv1f64(<vscale x 1 x double> %x)213 %b = fptoui <vscale x 1 x double> %a to <vscale x 1 x i32>214 ret <vscale x 1 x i32> %b215}216 217define <vscale x 1 x i64> @trunc_nxv1f64_to_si64(<vscale x 1 x double> %x) {218; RV32-LABEL: trunc_nxv1f64_to_si64:219; RV32: # %bb.0:220; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma221; RV32-NEXT: vfcvt.rtz.x.f.v v8, v8222; RV32-NEXT: ret223;224; RV64-LABEL: trunc_nxv1f64_to_si64:225; RV64: # %bb.0:226; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma227; RV64-NEXT: vfcvt.rtz.x.f.v v8, v8228; RV64-NEXT: ret229 %a = call <vscale x 1 x double> @llvm.trunc.nxv1f64(<vscale x 1 x double> %x)230 %b = fptosi <vscale x 1 x double> %a to <vscale x 1 x i64>231 ret <vscale x 1 x i64> %b232}233 234define <vscale x 1 x i64> @trunc_nxv1f64_to_ui64(<vscale x 1 x double> %x) {235; RV32-LABEL: trunc_nxv1f64_to_ui64:236; RV32: # %bb.0:237; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma238; RV32-NEXT: vfcvt.rtz.xu.f.v v8, v8239; RV32-NEXT: ret240;241; RV64-LABEL: trunc_nxv1f64_to_ui64:242; RV64: # %bb.0:243; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma244; RV64-NEXT: vfcvt.rtz.xu.f.v v8, v8245; RV64-NEXT: ret246 %a = call <vscale x 1 x double> @llvm.trunc.nxv1f64(<vscale x 1 x double> %x)247 %b = fptoui <vscale x 1 x double> %a to <vscale x 1 x i64>248 ret <vscale x 1 x i64> %b249}250 251; ================================================================================252; trunc <vscale x 4 x double>253; ================================================================================254 255define <vscale x 4 x i8> @trunc_nxv4f64_to_si8(<vscale x 4 x double> %x) {256; RV32-LABEL: trunc_nxv4f64_to_si8:257; RV32: # %bb.0:258; RV32-NEXT: lui a0, %hi(.LCPI8_0)259; RV32-NEXT: fld fa5, %lo(.LCPI8_0)(a0)260; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma261; RV32-NEXT: vfabs.v v12, v8262; RV32-NEXT: vmflt.vf v0, v12, fa5263; RV32-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t264; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t265; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu266; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t267; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma268; RV32-NEXT: vfncvt.rtz.x.f.w v12, v8269; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma270; RV32-NEXT: vnsrl.wi v8, v12, 0271; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma272; RV32-NEXT: vnsrl.wi v8, v8, 0273; RV32-NEXT: ret274;275; RV64-LABEL: trunc_nxv4f64_to_si8:276; RV64: # %bb.0:277; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma278; RV64-NEXT: vfabs.v v12, v8279; RV64-NEXT: li a0, 1075280; RV64-NEXT: slli a0, a0, 52281; RV64-NEXT: fmv.d.x fa5, a0282; RV64-NEXT: vmflt.vf v0, v12, fa5283; RV64-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t284; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t285; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu286; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t287; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma288; RV64-NEXT: vfncvt.rtz.x.f.w v12, v8289; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma290; RV64-NEXT: vnsrl.wi v8, v12, 0291; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, ma292; RV64-NEXT: vnsrl.wi v8, v8, 0293; RV64-NEXT: ret294 %a = call <vscale x 4 x double> @llvm.trunc.nxv4f64(<vscale x 4 x double> %x)295 %b = fptosi <vscale x 4 x double> %a to <vscale x 4 x i8>296 ret <vscale x 4 x i8> %b297}298 299define <vscale x 4 x i8> @trunc_nxv4f64_to_ui8(<vscale x 4 x double> %x) {300; RV32-LABEL: trunc_nxv4f64_to_ui8:301; RV32: # %bb.0:302; RV32-NEXT: lui a0, %hi(.LCPI9_0)303; RV32-NEXT: fld fa5, %lo(.LCPI9_0)(a0)304; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma305; RV32-NEXT: vfabs.v v12, v8306; RV32-NEXT: vmflt.vf v0, v12, fa5307; RV32-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t308; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t309; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu310; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t311; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma312; RV32-NEXT: vfncvt.rtz.xu.f.w v12, v8313; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma314; RV32-NEXT: vnsrl.wi v8, v12, 0315; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma316; RV32-NEXT: vnsrl.wi v8, v8, 0317; RV32-NEXT: ret318;319; RV64-LABEL: trunc_nxv4f64_to_ui8:320; RV64: # %bb.0:321; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma322; RV64-NEXT: vfabs.v v12, v8323; RV64-NEXT: li a0, 1075324; RV64-NEXT: slli a0, a0, 52325; RV64-NEXT: fmv.d.x fa5, a0326; RV64-NEXT: vmflt.vf v0, v12, fa5327; RV64-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t328; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t329; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu330; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t331; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma332; RV64-NEXT: vfncvt.rtz.xu.f.w v12, v8333; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma334; RV64-NEXT: vnsrl.wi v8, v12, 0335; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, ma336; RV64-NEXT: vnsrl.wi v8, v8, 0337; RV64-NEXT: ret338 %a = call <vscale x 4 x double> @llvm.trunc.nxv4f64(<vscale x 4 x double> %x)339 %b = fptoui <vscale x 4 x double> %a to <vscale x 4 x i8>340 ret <vscale x 4 x i8> %b341}342 343define <vscale x 4 x i16> @trunc_nxv4f64_to_si16(<vscale x 4 x double> %x) {344; RV32-LABEL: trunc_nxv4f64_to_si16:345; RV32: # %bb.0:346; RV32-NEXT: lui a0, %hi(.LCPI10_0)347; RV32-NEXT: fld fa5, %lo(.LCPI10_0)(a0)348; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma349; RV32-NEXT: vfabs.v v12, v8350; RV32-NEXT: vmflt.vf v0, v12, fa5351; RV32-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t352; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t353; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu354; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t355; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma356; RV32-NEXT: vfncvt.rtz.x.f.w v12, v8357; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma358; RV32-NEXT: vnsrl.wi v8, v12, 0359; RV32-NEXT: ret360;361; RV64-LABEL: trunc_nxv4f64_to_si16:362; RV64: # %bb.0:363; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma364; RV64-NEXT: vfabs.v v12, v8365; RV64-NEXT: li a0, 1075366; RV64-NEXT: slli a0, a0, 52367; RV64-NEXT: fmv.d.x fa5, a0368; RV64-NEXT: vmflt.vf v0, v12, fa5369; RV64-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t370; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t371; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu372; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t373; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma374; RV64-NEXT: vfncvt.rtz.x.f.w v12, v8375; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma376; RV64-NEXT: vnsrl.wi v8, v12, 0377; RV64-NEXT: ret378 %a = call <vscale x 4 x double> @llvm.trunc.nxv4f64(<vscale x 4 x double> %x)379 %b = fptosi <vscale x 4 x double> %a to <vscale x 4 x i16>380 ret <vscale x 4 x i16> %b381}382 383define <vscale x 4 x i16> @trunc_nxv4f64_to_ui16(<vscale x 4 x double> %x) {384; RV32-LABEL: trunc_nxv4f64_to_ui16:385; RV32: # %bb.0:386; RV32-NEXT: lui a0, %hi(.LCPI11_0)387; RV32-NEXT: fld fa5, %lo(.LCPI11_0)(a0)388; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma389; RV32-NEXT: vfabs.v v12, v8390; RV32-NEXT: vmflt.vf v0, v12, fa5391; RV32-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t392; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t393; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu394; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t395; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma396; RV32-NEXT: vfncvt.rtz.xu.f.w v12, v8397; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma398; RV32-NEXT: vnsrl.wi v8, v12, 0399; RV32-NEXT: ret400;401; RV64-LABEL: trunc_nxv4f64_to_ui16:402; RV64: # %bb.0:403; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma404; RV64-NEXT: vfabs.v v12, v8405; RV64-NEXT: li a0, 1075406; RV64-NEXT: slli a0, a0, 52407; RV64-NEXT: fmv.d.x fa5, a0408; RV64-NEXT: vmflt.vf v0, v12, fa5409; RV64-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t410; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t411; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu412; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t413; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma414; RV64-NEXT: vfncvt.rtz.xu.f.w v12, v8415; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma416; RV64-NEXT: vnsrl.wi v8, v12, 0417; RV64-NEXT: ret418 %a = call <vscale x 4 x double> @llvm.trunc.nxv4f64(<vscale x 4 x double> %x)419 %b = fptoui <vscale x 4 x double> %a to <vscale x 4 x i16>420 ret <vscale x 4 x i16> %b421}422 423define <vscale x 4 x i32> @trunc_nxv4f64_to_si32(<vscale x 4 x double> %x) {424; RV32-LABEL: trunc_nxv4f64_to_si32:425; RV32: # %bb.0:426; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma427; RV32-NEXT: vfncvt.rtz.x.f.w v12, v8428; RV32-NEXT: vmv.v.v v8, v12429; RV32-NEXT: ret430;431; RV64-LABEL: trunc_nxv4f64_to_si32:432; RV64: # %bb.0:433; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma434; RV64-NEXT: vfncvt.rtz.x.f.w v12, v8435; RV64-NEXT: vmv.v.v v8, v12436; RV64-NEXT: ret437 %a = call <vscale x 4 x double> @llvm.trunc.nxv4f64(<vscale x 4 x double> %x)438 %b = fptosi <vscale x 4 x double> %a to <vscale x 4 x i32>439 ret <vscale x 4 x i32> %b440}441 442define <vscale x 4 x i32> @trunc_nxv4f64_to_ui32(<vscale x 4 x double> %x) {443; RV32-LABEL: trunc_nxv4f64_to_ui32:444; RV32: # %bb.0:445; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma446; RV32-NEXT: vfncvt.rtz.xu.f.w v12, v8447; RV32-NEXT: vmv.v.v v8, v12448; RV32-NEXT: ret449;450; RV64-LABEL: trunc_nxv4f64_to_ui32:451; RV64: # %bb.0:452; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma453; RV64-NEXT: vfncvt.rtz.xu.f.w v12, v8454; RV64-NEXT: vmv.v.v v8, v12455; RV64-NEXT: ret456 %a = call <vscale x 4 x double> @llvm.trunc.nxv4f64(<vscale x 4 x double> %x)457 %b = fptoui <vscale x 4 x double> %a to <vscale x 4 x i32>458 ret <vscale x 4 x i32> %b459}460 461define <vscale x 4 x i64> @trunc_nxv4f64_to_si64(<vscale x 4 x double> %x) {462; RV32-LABEL: trunc_nxv4f64_to_si64:463; RV32: # %bb.0:464; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma465; RV32-NEXT: vfcvt.rtz.x.f.v v8, v8466; RV32-NEXT: ret467;468; RV64-LABEL: trunc_nxv4f64_to_si64:469; RV64: # %bb.0:470; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma471; RV64-NEXT: vfcvt.rtz.x.f.v v8, v8472; RV64-NEXT: ret473 %a = call <vscale x 4 x double> @llvm.trunc.nxv4f64(<vscale x 4 x double> %x)474 %b = fptosi <vscale x 4 x double> %a to <vscale x 4 x i64>475 ret <vscale x 4 x i64> %b476}477 478define <vscale x 4 x i64> @trunc_nxv4f64_to_ui64(<vscale x 4 x double> %x) {479; RV32-LABEL: trunc_nxv4f64_to_ui64:480; RV32: # %bb.0:481; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma482; RV32-NEXT: vfcvt.rtz.xu.f.v v8, v8483; RV32-NEXT: ret484;485; RV64-LABEL: trunc_nxv4f64_to_ui64:486; RV64: # %bb.0:487; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma488; RV64-NEXT: vfcvt.rtz.xu.f.v v8, v8489; RV64-NEXT: ret490 %a = call <vscale x 4 x double> @llvm.trunc.nxv4f64(<vscale x 4 x double> %x)491 %b = fptoui <vscale x 4 x double> %a to <vscale x 4 x i64>492 ret <vscale x 4 x i64> %b493}494 495; ================================================================================496; ceil <vscale x 1 x double>497; ================================================================================498 499define <vscale x 1 x i8> @ceil_nxv1f64_to_si8(<vscale x 1 x double> %x) {500; RV32-LABEL: ceil_nxv1f64_to_si8:501; RV32: # %bb.0:502; RV32-NEXT: lui a0, %hi(.LCPI16_0)503; RV32-NEXT: fld fa5, %lo(.LCPI16_0)(a0)504; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma505; RV32-NEXT: vfabs.v v9, v8506; RV32-NEXT: vmflt.vf v0, v9, fa5507; RV32-NEXT: fsrmi a0, 3508; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t509; RV32-NEXT: fsrm a0510; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t511; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu512; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t513; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma514; RV32-NEXT: vfncvt.rtz.x.f.w v9, v8515; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma516; RV32-NEXT: vnsrl.wi v8, v9, 0517; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma518; RV32-NEXT: vnsrl.wi v8, v8, 0519; RV32-NEXT: ret520;521; RV64-LABEL: ceil_nxv1f64_to_si8:522; RV64: # %bb.0:523; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma524; RV64-NEXT: vfabs.v v9, v8525; RV64-NEXT: li a0, 1075526; RV64-NEXT: slli a0, a0, 52527; RV64-NEXT: fmv.d.x fa5, a0528; RV64-NEXT: vmflt.vf v0, v9, fa5529; RV64-NEXT: fsrmi a0, 3530; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t531; RV64-NEXT: fsrm a0532; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t533; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu534; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t535; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma536; RV64-NEXT: vfncvt.rtz.x.f.w v9, v8537; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma538; RV64-NEXT: vnsrl.wi v8, v9, 0539; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma540; RV64-NEXT: vnsrl.wi v8, v8, 0541; RV64-NEXT: ret542 %a = call <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double> %x)543 %b = fptosi <vscale x 1 x double> %a to <vscale x 1 x i8>544 ret <vscale x 1 x i8> %b545}546 547define <vscale x 1 x i8> @ceil_nxv1f64_to_ui8(<vscale x 1 x double> %x) {548; RV32-LABEL: ceil_nxv1f64_to_ui8:549; RV32: # %bb.0:550; RV32-NEXT: lui a0, %hi(.LCPI17_0)551; RV32-NEXT: fld fa5, %lo(.LCPI17_0)(a0)552; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma553; RV32-NEXT: vfabs.v v9, v8554; RV32-NEXT: vmflt.vf v0, v9, fa5555; RV32-NEXT: fsrmi a0, 3556; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t557; RV32-NEXT: fsrm a0558; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t559; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu560; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t561; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma562; RV32-NEXT: vfncvt.rtz.xu.f.w v9, v8563; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma564; RV32-NEXT: vnsrl.wi v8, v9, 0565; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma566; RV32-NEXT: vnsrl.wi v8, v8, 0567; RV32-NEXT: ret568;569; RV64-LABEL: ceil_nxv1f64_to_ui8:570; RV64: # %bb.0:571; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma572; RV64-NEXT: vfabs.v v9, v8573; RV64-NEXT: li a0, 1075574; RV64-NEXT: slli a0, a0, 52575; RV64-NEXT: fmv.d.x fa5, a0576; RV64-NEXT: vmflt.vf v0, v9, fa5577; RV64-NEXT: fsrmi a0, 3578; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t579; RV64-NEXT: fsrm a0580; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t581; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu582; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t583; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma584; RV64-NEXT: vfncvt.rtz.xu.f.w v9, v8585; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma586; RV64-NEXT: vnsrl.wi v8, v9, 0587; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma588; RV64-NEXT: vnsrl.wi v8, v8, 0589; RV64-NEXT: ret590 %a = call <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double> %x)591 %b = fptoui <vscale x 1 x double> %a to <vscale x 1 x i8>592 ret <vscale x 1 x i8> %b593}594 595define <vscale x 1 x i16> @ceil_nxv1f64_to_si16(<vscale x 1 x double> %x) {596; RV32-LABEL: ceil_nxv1f64_to_si16:597; RV32: # %bb.0:598; RV32-NEXT: lui a0, %hi(.LCPI18_0)599; RV32-NEXT: fld fa5, %lo(.LCPI18_0)(a0)600; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma601; RV32-NEXT: vfabs.v v9, v8602; RV32-NEXT: vmflt.vf v0, v9, fa5603; RV32-NEXT: fsrmi a0, 3604; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t605; RV32-NEXT: fsrm a0606; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t607; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu608; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t609; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma610; RV32-NEXT: vfncvt.rtz.x.f.w v9, v8611; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma612; RV32-NEXT: vnsrl.wi v8, v9, 0613; RV32-NEXT: ret614;615; RV64-LABEL: ceil_nxv1f64_to_si16:616; RV64: # %bb.0:617; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma618; RV64-NEXT: vfabs.v v9, v8619; RV64-NEXT: li a0, 1075620; RV64-NEXT: slli a0, a0, 52621; RV64-NEXT: fmv.d.x fa5, a0622; RV64-NEXT: vmflt.vf v0, v9, fa5623; RV64-NEXT: fsrmi a0, 3624; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t625; RV64-NEXT: fsrm a0626; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t627; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu628; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t629; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma630; RV64-NEXT: vfncvt.rtz.x.f.w v9, v8631; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma632; RV64-NEXT: vnsrl.wi v8, v9, 0633; RV64-NEXT: ret634 %a = call <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double> %x)635 %b = fptosi <vscale x 1 x double> %a to <vscale x 1 x i16>636 ret <vscale x 1 x i16> %b637}638 639define <vscale x 1 x i16> @ceil_nxv1f64_to_ui16(<vscale x 1 x double> %x) {640; RV32-LABEL: ceil_nxv1f64_to_ui16:641; RV32: # %bb.0:642; RV32-NEXT: lui a0, %hi(.LCPI19_0)643; RV32-NEXT: fld fa5, %lo(.LCPI19_0)(a0)644; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma645; RV32-NEXT: vfabs.v v9, v8646; RV32-NEXT: vmflt.vf v0, v9, fa5647; RV32-NEXT: fsrmi a0, 3648; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t649; RV32-NEXT: fsrm a0650; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t651; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu652; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t653; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma654; RV32-NEXT: vfncvt.rtz.xu.f.w v9, v8655; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma656; RV32-NEXT: vnsrl.wi v8, v9, 0657; RV32-NEXT: ret658;659; RV64-LABEL: ceil_nxv1f64_to_ui16:660; RV64: # %bb.0:661; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma662; RV64-NEXT: vfabs.v v9, v8663; RV64-NEXT: li a0, 1075664; RV64-NEXT: slli a0, a0, 52665; RV64-NEXT: fmv.d.x fa5, a0666; RV64-NEXT: vmflt.vf v0, v9, fa5667; RV64-NEXT: fsrmi a0, 3668; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t669; RV64-NEXT: fsrm a0670; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t671; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu672; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t673; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma674; RV64-NEXT: vfncvt.rtz.xu.f.w v9, v8675; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma676; RV64-NEXT: vnsrl.wi v8, v9, 0677; RV64-NEXT: ret678 %a = call <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double> %x)679 %b = fptoui <vscale x 1 x double> %a to <vscale x 1 x i16>680 ret <vscale x 1 x i16> %b681}682 683define <vscale x 1 x i32> @ceil_nxv1f64_to_si32(<vscale x 1 x double> %x) {684; RV32-LABEL: ceil_nxv1f64_to_si32:685; RV32: # %bb.0:686; RV32-NEXT: fsrmi a0, 3687; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma688; RV32-NEXT: vfncvt.x.f.w v9, v8689; RV32-NEXT: fsrm a0690; RV32-NEXT: vmv1r.v v8, v9691; RV32-NEXT: ret692;693; RV64-LABEL: ceil_nxv1f64_to_si32:694; RV64: # %bb.0:695; RV64-NEXT: fsrmi a0, 3696; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma697; RV64-NEXT: vfncvt.x.f.w v9, v8698; RV64-NEXT: fsrm a0699; RV64-NEXT: vmv1r.v v8, v9700; RV64-NEXT: ret701 %a = call <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double> %x)702 %b = fptosi <vscale x 1 x double> %a to <vscale x 1 x i32>703 ret <vscale x 1 x i32> %b704}705 706define <vscale x 1 x i32> @ceil_nxv1f64_to_ui32(<vscale x 1 x double> %x) {707; RV32-LABEL: ceil_nxv1f64_to_ui32:708; RV32: # %bb.0:709; RV32-NEXT: fsrmi a0, 3710; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma711; RV32-NEXT: vfncvt.xu.f.w v9, v8712; RV32-NEXT: fsrm a0713; RV32-NEXT: vmv1r.v v8, v9714; RV32-NEXT: ret715;716; RV64-LABEL: ceil_nxv1f64_to_ui32:717; RV64: # %bb.0:718; RV64-NEXT: fsrmi a0, 3719; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma720; RV64-NEXT: vfncvt.xu.f.w v9, v8721; RV64-NEXT: fsrm a0722; RV64-NEXT: vmv1r.v v8, v9723; RV64-NEXT: ret724 %a = call <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double> %x)725 %b = fptoui <vscale x 1 x double> %a to <vscale x 1 x i32>726 ret <vscale x 1 x i32> %b727}728 729define <vscale x 1 x i64> @ceil_nxv1f64_to_si64(<vscale x 1 x double> %x) {730; RV32-LABEL: ceil_nxv1f64_to_si64:731; RV32: # %bb.0:732; RV32-NEXT: fsrmi a0, 3733; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma734; RV32-NEXT: vfcvt.x.f.v v8, v8735; RV32-NEXT: fsrm a0736; RV32-NEXT: ret737;738; RV64-LABEL: ceil_nxv1f64_to_si64:739; RV64: # %bb.0:740; RV64-NEXT: fsrmi a0, 3741; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma742; RV64-NEXT: vfcvt.x.f.v v8, v8743; RV64-NEXT: fsrm a0744; RV64-NEXT: ret745 %a = call <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double> %x)746 %b = fptosi <vscale x 1 x double> %a to <vscale x 1 x i64>747 ret <vscale x 1 x i64> %b748}749 750define <vscale x 1 x i64> @ceil_nxv1f64_to_ui64(<vscale x 1 x double> %x) {751; RV32-LABEL: ceil_nxv1f64_to_ui64:752; RV32: # %bb.0:753; RV32-NEXT: fsrmi a0, 3754; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma755; RV32-NEXT: vfcvt.xu.f.v v8, v8756; RV32-NEXT: fsrm a0757; RV32-NEXT: ret758;759; RV64-LABEL: ceil_nxv1f64_to_ui64:760; RV64: # %bb.0:761; RV64-NEXT: fsrmi a0, 3762; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma763; RV64-NEXT: vfcvt.xu.f.v v8, v8764; RV64-NEXT: fsrm a0765; RV64-NEXT: ret766 %a = call <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double> %x)767 %b = fptoui <vscale x 1 x double> %a to <vscale x 1 x i64>768 ret <vscale x 1 x i64> %b769}770 771; ================================================================================772; ceil <vscale x 4 x double>773; ================================================================================774 775define <vscale x 4 x i8> @ceil_nxv4f64_to_si8(<vscale x 4 x double> %x) {776; RV32-LABEL: ceil_nxv4f64_to_si8:777; RV32: # %bb.0:778; RV32-NEXT: lui a0, %hi(.LCPI24_0)779; RV32-NEXT: fld fa5, %lo(.LCPI24_0)(a0)780; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma781; RV32-NEXT: vfabs.v v12, v8782; RV32-NEXT: vmflt.vf v0, v12, fa5783; RV32-NEXT: fsrmi a0, 3784; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t785; RV32-NEXT: fsrm a0786; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t787; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu788; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t789; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma790; RV32-NEXT: vfncvt.rtz.x.f.w v12, v8791; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma792; RV32-NEXT: vnsrl.wi v8, v12, 0793; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma794; RV32-NEXT: vnsrl.wi v8, v8, 0795; RV32-NEXT: ret796;797; RV64-LABEL: ceil_nxv4f64_to_si8:798; RV64: # %bb.0:799; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma800; RV64-NEXT: vfabs.v v12, v8801; RV64-NEXT: li a0, 1075802; RV64-NEXT: slli a0, a0, 52803; RV64-NEXT: fmv.d.x fa5, a0804; RV64-NEXT: vmflt.vf v0, v12, fa5805; RV64-NEXT: fsrmi a0, 3806; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t807; RV64-NEXT: fsrm a0808; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t809; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu810; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t811; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma812; RV64-NEXT: vfncvt.rtz.x.f.w v12, v8813; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma814; RV64-NEXT: vnsrl.wi v8, v12, 0815; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, ma816; RV64-NEXT: vnsrl.wi v8, v8, 0817; RV64-NEXT: ret818 %a = call <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double> %x)819 %b = fptosi <vscale x 4 x double> %a to <vscale x 4 x i8>820 ret <vscale x 4 x i8> %b821}822 823define <vscale x 4 x i8> @ceil_nxv4f64_to_ui8(<vscale x 4 x double> %x) {824; RV32-LABEL: ceil_nxv4f64_to_ui8:825; RV32: # %bb.0:826; RV32-NEXT: lui a0, %hi(.LCPI25_0)827; RV32-NEXT: fld fa5, %lo(.LCPI25_0)(a0)828; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma829; RV32-NEXT: vfabs.v v12, v8830; RV32-NEXT: vmflt.vf v0, v12, fa5831; RV32-NEXT: fsrmi a0, 3832; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t833; RV32-NEXT: fsrm a0834; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t835; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu836; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t837; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma838; RV32-NEXT: vfncvt.rtz.xu.f.w v12, v8839; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma840; RV32-NEXT: vnsrl.wi v8, v12, 0841; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma842; RV32-NEXT: vnsrl.wi v8, v8, 0843; RV32-NEXT: ret844;845; RV64-LABEL: ceil_nxv4f64_to_ui8:846; RV64: # %bb.0:847; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma848; RV64-NEXT: vfabs.v v12, v8849; RV64-NEXT: li a0, 1075850; RV64-NEXT: slli a0, a0, 52851; RV64-NEXT: fmv.d.x fa5, a0852; RV64-NEXT: vmflt.vf v0, v12, fa5853; RV64-NEXT: fsrmi a0, 3854; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t855; RV64-NEXT: fsrm a0856; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t857; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu858; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t859; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma860; RV64-NEXT: vfncvt.rtz.xu.f.w v12, v8861; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma862; RV64-NEXT: vnsrl.wi v8, v12, 0863; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, ma864; RV64-NEXT: vnsrl.wi v8, v8, 0865; RV64-NEXT: ret866 %a = call <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double> %x)867 %b = fptoui <vscale x 4 x double> %a to <vscale x 4 x i8>868 ret <vscale x 4 x i8> %b869}870 871define <vscale x 4 x i16> @ceil_nxv4f64_to_si16(<vscale x 4 x double> %x) {872; RV32-LABEL: ceil_nxv4f64_to_si16:873; RV32: # %bb.0:874; RV32-NEXT: lui a0, %hi(.LCPI26_0)875; RV32-NEXT: fld fa5, %lo(.LCPI26_0)(a0)876; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma877; RV32-NEXT: vfabs.v v12, v8878; RV32-NEXT: vmflt.vf v0, v12, fa5879; RV32-NEXT: fsrmi a0, 3880; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t881; RV32-NEXT: fsrm a0882; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t883; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu884; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t885; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma886; RV32-NEXT: vfncvt.rtz.x.f.w v12, v8887; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma888; RV32-NEXT: vnsrl.wi v8, v12, 0889; RV32-NEXT: ret890;891; RV64-LABEL: ceil_nxv4f64_to_si16:892; RV64: # %bb.0:893; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma894; RV64-NEXT: vfabs.v v12, v8895; RV64-NEXT: li a0, 1075896; RV64-NEXT: slli a0, a0, 52897; RV64-NEXT: fmv.d.x fa5, a0898; RV64-NEXT: vmflt.vf v0, v12, fa5899; RV64-NEXT: fsrmi a0, 3900; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t901; RV64-NEXT: fsrm a0902; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t903; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu904; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t905; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma906; RV64-NEXT: vfncvt.rtz.x.f.w v12, v8907; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma908; RV64-NEXT: vnsrl.wi v8, v12, 0909; RV64-NEXT: ret910 %a = call <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double> %x)911 %b = fptosi <vscale x 4 x double> %a to <vscale x 4 x i16>912 ret <vscale x 4 x i16> %b913}914 915define <vscale x 4 x i16> @ceil_nxv4f64_to_ui16(<vscale x 4 x double> %x) {916; RV32-LABEL: ceil_nxv4f64_to_ui16:917; RV32: # %bb.0:918; RV32-NEXT: lui a0, %hi(.LCPI27_0)919; RV32-NEXT: fld fa5, %lo(.LCPI27_0)(a0)920; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma921; RV32-NEXT: vfabs.v v12, v8922; RV32-NEXT: vmflt.vf v0, v12, fa5923; RV32-NEXT: fsrmi a0, 3924; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t925; RV32-NEXT: fsrm a0926; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t927; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu928; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t929; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma930; RV32-NEXT: vfncvt.rtz.xu.f.w v12, v8931; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma932; RV32-NEXT: vnsrl.wi v8, v12, 0933; RV32-NEXT: ret934;935; RV64-LABEL: ceil_nxv4f64_to_ui16:936; RV64: # %bb.0:937; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma938; RV64-NEXT: vfabs.v v12, v8939; RV64-NEXT: li a0, 1075940; RV64-NEXT: slli a0, a0, 52941; RV64-NEXT: fmv.d.x fa5, a0942; RV64-NEXT: vmflt.vf v0, v12, fa5943; RV64-NEXT: fsrmi a0, 3944; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t945; RV64-NEXT: fsrm a0946; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t947; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu948; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t949; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma950; RV64-NEXT: vfncvt.rtz.xu.f.w v12, v8951; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma952; RV64-NEXT: vnsrl.wi v8, v12, 0953; RV64-NEXT: ret954 %a = call <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double> %x)955 %b = fptoui <vscale x 4 x double> %a to <vscale x 4 x i16>956 ret <vscale x 4 x i16> %b957}958 959define <vscale x 4 x i32> @ceil_nxv4f64_to_si32(<vscale x 4 x double> %x) {960; RV32-LABEL: ceil_nxv4f64_to_si32:961; RV32: # %bb.0:962; RV32-NEXT: fsrmi a0, 3963; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma964; RV32-NEXT: vfncvt.x.f.w v12, v8965; RV32-NEXT: fsrm a0966; RV32-NEXT: vmv.v.v v8, v12967; RV32-NEXT: ret968;969; RV64-LABEL: ceil_nxv4f64_to_si32:970; RV64: # %bb.0:971; RV64-NEXT: fsrmi a0, 3972; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma973; RV64-NEXT: vfncvt.x.f.w v12, v8974; RV64-NEXT: fsrm a0975; RV64-NEXT: vmv.v.v v8, v12976; RV64-NEXT: ret977 %a = call <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double> %x)978 %b = fptosi <vscale x 4 x double> %a to <vscale x 4 x i32>979 ret <vscale x 4 x i32> %b980}981 982define <vscale x 4 x i32> @ceil_nxv4f64_to_ui32(<vscale x 4 x double> %x) {983; RV32-LABEL: ceil_nxv4f64_to_ui32:984; RV32: # %bb.0:985; RV32-NEXT: fsrmi a0, 3986; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma987; RV32-NEXT: vfncvt.xu.f.w v12, v8988; RV32-NEXT: fsrm a0989; RV32-NEXT: vmv.v.v v8, v12990; RV32-NEXT: ret991;992; RV64-LABEL: ceil_nxv4f64_to_ui32:993; RV64: # %bb.0:994; RV64-NEXT: fsrmi a0, 3995; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma996; RV64-NEXT: vfncvt.xu.f.w v12, v8997; RV64-NEXT: fsrm a0998; RV64-NEXT: vmv.v.v v8, v12999; RV64-NEXT: ret1000 %a = call <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double> %x)1001 %b = fptoui <vscale x 4 x double> %a to <vscale x 4 x i32>1002 ret <vscale x 4 x i32> %b1003}1004 1005define <vscale x 4 x i64> @ceil_nxv4f64_to_si64(<vscale x 4 x double> %x) {1006; RV32-LABEL: ceil_nxv4f64_to_si64:1007; RV32: # %bb.0:1008; RV32-NEXT: fsrmi a0, 31009; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma1010; RV32-NEXT: vfcvt.x.f.v v8, v81011; RV32-NEXT: fsrm a01012; RV32-NEXT: ret1013;1014; RV64-LABEL: ceil_nxv4f64_to_si64:1015; RV64: # %bb.0:1016; RV64-NEXT: fsrmi a0, 31017; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma1018; RV64-NEXT: vfcvt.x.f.v v8, v81019; RV64-NEXT: fsrm a01020; RV64-NEXT: ret1021 %a = call <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double> %x)1022 %b = fptosi <vscale x 4 x double> %a to <vscale x 4 x i64>1023 ret <vscale x 4 x i64> %b1024}1025 1026define <vscale x 4 x i64> @ceil_nxv4f64_to_ui64(<vscale x 4 x double> %x) {1027; RV32-LABEL: ceil_nxv4f64_to_ui64:1028; RV32: # %bb.0:1029; RV32-NEXT: fsrmi a0, 31030; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma1031; RV32-NEXT: vfcvt.xu.f.v v8, v81032; RV32-NEXT: fsrm a01033; RV32-NEXT: ret1034;1035; RV64-LABEL: ceil_nxv4f64_to_ui64:1036; RV64: # %bb.0:1037; RV64-NEXT: fsrmi a0, 31038; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma1039; RV64-NEXT: vfcvt.xu.f.v v8, v81040; RV64-NEXT: fsrm a01041; RV64-NEXT: ret1042 %a = call <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double> %x)1043 %b = fptoui <vscale x 4 x double> %a to <vscale x 4 x i64>1044 ret <vscale x 4 x i64> %b1045}1046 1047; ================================================================================1048; rint <vscale x 1 x double>1049; ================================================================================1050 1051define <vscale x 1 x i8> @rint_nxv1f64_to_si8(<vscale x 1 x double> %x) {1052; RV32-LABEL: rint_nxv1f64_to_si8:1053; RV32: # %bb.0:1054; RV32-NEXT: lui a0, %hi(.LCPI32_0)1055; RV32-NEXT: fld fa5, %lo(.LCPI32_0)(a0)1056; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma1057; RV32-NEXT: vfabs.v v9, v81058; RV32-NEXT: vmflt.vf v0, v9, fa51059; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t1060; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t1061; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu1062; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t1063; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1064; RV32-NEXT: vfncvt.rtz.x.f.w v9, v81065; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma1066; RV32-NEXT: vnsrl.wi v8, v9, 01067; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma1068; RV32-NEXT: vnsrl.wi v8, v8, 01069; RV32-NEXT: ret1070;1071; RV64-LABEL: rint_nxv1f64_to_si8:1072; RV64: # %bb.0:1073; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1074; RV64-NEXT: vfabs.v v9, v81075; RV64-NEXT: li a0, 10751076; RV64-NEXT: slli a0, a0, 521077; RV64-NEXT: fmv.d.x fa5, a01078; RV64-NEXT: vmflt.vf v0, v9, fa51079; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t1080; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t1081; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu1082; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t1083; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1084; RV64-NEXT: vfncvt.rtz.x.f.w v9, v81085; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma1086; RV64-NEXT: vnsrl.wi v8, v9, 01087; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma1088; RV64-NEXT: vnsrl.wi v8, v8, 01089; RV64-NEXT: ret1090 %a = call <vscale x 1 x double> @llvm.rint.nxv1f64(<vscale x 1 x double> %x)1091 %b = fptosi <vscale x 1 x double> %a to <vscale x 1 x i8>1092 ret <vscale x 1 x i8> %b1093}1094 1095define <vscale x 1 x i8> @rint_nxv1f64_to_ui8(<vscale x 1 x double> %x) {1096; RV32-LABEL: rint_nxv1f64_to_ui8:1097; RV32: # %bb.0:1098; RV32-NEXT: lui a0, %hi(.LCPI33_0)1099; RV32-NEXT: fld fa5, %lo(.LCPI33_0)(a0)1100; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma1101; RV32-NEXT: vfabs.v v9, v81102; RV32-NEXT: vmflt.vf v0, v9, fa51103; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t1104; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t1105; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu1106; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t1107; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1108; RV32-NEXT: vfncvt.rtz.xu.f.w v9, v81109; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma1110; RV32-NEXT: vnsrl.wi v8, v9, 01111; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma1112; RV32-NEXT: vnsrl.wi v8, v8, 01113; RV32-NEXT: ret1114;1115; RV64-LABEL: rint_nxv1f64_to_ui8:1116; RV64: # %bb.0:1117; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1118; RV64-NEXT: vfabs.v v9, v81119; RV64-NEXT: li a0, 10751120; RV64-NEXT: slli a0, a0, 521121; RV64-NEXT: fmv.d.x fa5, a01122; RV64-NEXT: vmflt.vf v0, v9, fa51123; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t1124; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t1125; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu1126; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t1127; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1128; RV64-NEXT: vfncvt.rtz.xu.f.w v9, v81129; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma1130; RV64-NEXT: vnsrl.wi v8, v9, 01131; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma1132; RV64-NEXT: vnsrl.wi v8, v8, 01133; RV64-NEXT: ret1134 %a = call <vscale x 1 x double> @llvm.rint.nxv1f64(<vscale x 1 x double> %x)1135 %b = fptoui <vscale x 1 x double> %a to <vscale x 1 x i8>1136 ret <vscale x 1 x i8> %b1137}1138 1139define <vscale x 1 x i16> @rint_nxv1f64_to_si16(<vscale x 1 x double> %x) {1140; RV32-LABEL: rint_nxv1f64_to_si16:1141; RV32: # %bb.0:1142; RV32-NEXT: lui a0, %hi(.LCPI34_0)1143; RV32-NEXT: fld fa5, %lo(.LCPI34_0)(a0)1144; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma1145; RV32-NEXT: vfabs.v v9, v81146; RV32-NEXT: vmflt.vf v0, v9, fa51147; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t1148; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t1149; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu1150; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t1151; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1152; RV32-NEXT: vfncvt.rtz.x.f.w v9, v81153; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma1154; RV32-NEXT: vnsrl.wi v8, v9, 01155; RV32-NEXT: ret1156;1157; RV64-LABEL: rint_nxv1f64_to_si16:1158; RV64: # %bb.0:1159; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1160; RV64-NEXT: vfabs.v v9, v81161; RV64-NEXT: li a0, 10751162; RV64-NEXT: slli a0, a0, 521163; RV64-NEXT: fmv.d.x fa5, a01164; RV64-NEXT: vmflt.vf v0, v9, fa51165; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t1166; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t1167; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu1168; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t1169; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1170; RV64-NEXT: vfncvt.rtz.x.f.w v9, v81171; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma1172; RV64-NEXT: vnsrl.wi v8, v9, 01173; RV64-NEXT: ret1174 %a = call <vscale x 1 x double> @llvm.rint.nxv1f64(<vscale x 1 x double> %x)1175 %b = fptosi <vscale x 1 x double> %a to <vscale x 1 x i16>1176 ret <vscale x 1 x i16> %b1177}1178 1179define <vscale x 1 x i16> @rint_nxv1f64_to_ui16(<vscale x 1 x double> %x) {1180; RV32-LABEL: rint_nxv1f64_to_ui16:1181; RV32: # %bb.0:1182; RV32-NEXT: lui a0, %hi(.LCPI35_0)1183; RV32-NEXT: fld fa5, %lo(.LCPI35_0)(a0)1184; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma1185; RV32-NEXT: vfabs.v v9, v81186; RV32-NEXT: vmflt.vf v0, v9, fa51187; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t1188; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t1189; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu1190; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t1191; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1192; RV32-NEXT: vfncvt.rtz.xu.f.w v9, v81193; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma1194; RV32-NEXT: vnsrl.wi v8, v9, 01195; RV32-NEXT: ret1196;1197; RV64-LABEL: rint_nxv1f64_to_ui16:1198; RV64: # %bb.0:1199; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1200; RV64-NEXT: vfabs.v v9, v81201; RV64-NEXT: li a0, 10751202; RV64-NEXT: slli a0, a0, 521203; RV64-NEXT: fmv.d.x fa5, a01204; RV64-NEXT: vmflt.vf v0, v9, fa51205; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t1206; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t1207; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu1208; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t1209; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1210; RV64-NEXT: vfncvt.rtz.xu.f.w v9, v81211; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma1212; RV64-NEXT: vnsrl.wi v8, v9, 01213; RV64-NEXT: ret1214 %a = call <vscale x 1 x double> @llvm.rint.nxv1f64(<vscale x 1 x double> %x)1215 %b = fptoui <vscale x 1 x double> %a to <vscale x 1 x i16>1216 ret <vscale x 1 x i16> %b1217}1218 1219define <vscale x 1 x i32> @rint_nxv1f64_to_si32(<vscale x 1 x double> %x) {1220; RV32-LABEL: rint_nxv1f64_to_si32:1221; RV32: # %bb.0:1222; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1223; RV32-NEXT: vfncvt.x.f.w v9, v81224; RV32-NEXT: vmv1r.v v8, v91225; RV32-NEXT: ret1226;1227; RV64-LABEL: rint_nxv1f64_to_si32:1228; RV64: # %bb.0:1229; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1230; RV64-NEXT: vfncvt.x.f.w v9, v81231; RV64-NEXT: vmv1r.v v8, v91232; RV64-NEXT: ret1233 %a = call <vscale x 1 x double> @llvm.rint.nxv1f64(<vscale x 1 x double> %x)1234 %b = fptosi <vscale x 1 x double> %a to <vscale x 1 x i32>1235 ret <vscale x 1 x i32> %b1236}1237 1238define <vscale x 1 x i32> @rint_nxv1f64_to_ui32(<vscale x 1 x double> %x) {1239; RV32-LABEL: rint_nxv1f64_to_ui32:1240; RV32: # %bb.0:1241; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1242; RV32-NEXT: vfncvt.xu.f.w v9, v81243; RV32-NEXT: vmv1r.v v8, v91244; RV32-NEXT: ret1245;1246; RV64-LABEL: rint_nxv1f64_to_ui32:1247; RV64: # %bb.0:1248; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1249; RV64-NEXT: vfncvt.xu.f.w v9, v81250; RV64-NEXT: vmv1r.v v8, v91251; RV64-NEXT: ret1252 %a = call <vscale x 1 x double> @llvm.rint.nxv1f64(<vscale x 1 x double> %x)1253 %b = fptoui <vscale x 1 x double> %a to <vscale x 1 x i32>1254 ret <vscale x 1 x i32> %b1255}1256 1257define <vscale x 1 x i64> @rint_nxv1f64_to_si64(<vscale x 1 x double> %x) {1258; RV32-LABEL: rint_nxv1f64_to_si64:1259; RV32: # %bb.0:1260; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma1261; RV32-NEXT: vfcvt.x.f.v v8, v81262; RV32-NEXT: ret1263;1264; RV64-LABEL: rint_nxv1f64_to_si64:1265; RV64: # %bb.0:1266; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1267; RV64-NEXT: vfcvt.x.f.v v8, v81268; RV64-NEXT: ret1269 %a = call <vscale x 1 x double> @llvm.rint.nxv1f64(<vscale x 1 x double> %x)1270 %b = fptosi <vscale x 1 x double> %a to <vscale x 1 x i64>1271 ret <vscale x 1 x i64> %b1272}1273 1274define <vscale x 1 x i64> @rint_nxv1f64_to_ui64(<vscale x 1 x double> %x) {1275; RV32-LABEL: rint_nxv1f64_to_ui64:1276; RV32: # %bb.0:1277; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma1278; RV32-NEXT: vfcvt.xu.f.v v8, v81279; RV32-NEXT: ret1280;1281; RV64-LABEL: rint_nxv1f64_to_ui64:1282; RV64: # %bb.0:1283; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1284; RV64-NEXT: vfcvt.xu.f.v v8, v81285; RV64-NEXT: ret1286 %a = call <vscale x 1 x double> @llvm.rint.nxv1f64(<vscale x 1 x double> %x)1287 %b = fptoui <vscale x 1 x double> %a to <vscale x 1 x i64>1288 ret <vscale x 1 x i64> %b1289}1290 1291; ================================================================================1292; rint <vscale x 4 x double>1293; ================================================================================1294 1295define <vscale x 4 x i8> @rint_nxv4f64_to_si8(<vscale x 4 x double> %x) {1296; RV32-LABEL: rint_nxv4f64_to_si8:1297; RV32: # %bb.0:1298; RV32-NEXT: lui a0, %hi(.LCPI40_0)1299; RV32-NEXT: fld fa5, %lo(.LCPI40_0)(a0)1300; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1301; RV32-NEXT: vfabs.v v12, v81302; RV32-NEXT: vmflt.vf v0, v12, fa51303; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t1304; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t1305; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu1306; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t1307; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma1308; RV32-NEXT: vfncvt.rtz.x.f.w v12, v81309; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma1310; RV32-NEXT: vnsrl.wi v8, v12, 01311; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma1312; RV32-NEXT: vnsrl.wi v8, v8, 01313; RV32-NEXT: ret1314;1315; RV64-LABEL: rint_nxv4f64_to_si8:1316; RV64: # %bb.0:1317; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma1318; RV64-NEXT: vfabs.v v12, v81319; RV64-NEXT: li a0, 10751320; RV64-NEXT: slli a0, a0, 521321; RV64-NEXT: fmv.d.x fa5, a01322; RV64-NEXT: vmflt.vf v0, v12, fa51323; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t1324; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t1325; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu1326; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t1327; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma1328; RV64-NEXT: vfncvt.rtz.x.f.w v12, v81329; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma1330; RV64-NEXT: vnsrl.wi v8, v12, 01331; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, ma1332; RV64-NEXT: vnsrl.wi v8, v8, 01333; RV64-NEXT: ret1334 %a = call <vscale x 4 x double> @llvm.rint.nxv4f64(<vscale x 4 x double> %x)1335 %b = fptosi <vscale x 4 x double> %a to <vscale x 4 x i8>1336 ret <vscale x 4 x i8> %b1337}1338 1339define <vscale x 4 x i8> @rint_nxv4f64_to_ui8(<vscale x 4 x double> %x) {1340; RV32-LABEL: rint_nxv4f64_to_ui8:1341; RV32: # %bb.0:1342; RV32-NEXT: lui a0, %hi(.LCPI41_0)1343; RV32-NEXT: fld fa5, %lo(.LCPI41_0)(a0)1344; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1345; RV32-NEXT: vfabs.v v12, v81346; RV32-NEXT: vmflt.vf v0, v12, fa51347; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t1348; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t1349; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu1350; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t1351; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma1352; RV32-NEXT: vfncvt.rtz.xu.f.w v12, v81353; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma1354; RV32-NEXT: vnsrl.wi v8, v12, 01355; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma1356; RV32-NEXT: vnsrl.wi v8, v8, 01357; RV32-NEXT: ret1358;1359; RV64-LABEL: rint_nxv4f64_to_ui8:1360; RV64: # %bb.0:1361; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma1362; RV64-NEXT: vfabs.v v12, v81363; RV64-NEXT: li a0, 10751364; RV64-NEXT: slli a0, a0, 521365; RV64-NEXT: fmv.d.x fa5, a01366; RV64-NEXT: vmflt.vf v0, v12, fa51367; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t1368; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t1369; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu1370; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t1371; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma1372; RV64-NEXT: vfncvt.rtz.xu.f.w v12, v81373; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma1374; RV64-NEXT: vnsrl.wi v8, v12, 01375; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, ma1376; RV64-NEXT: vnsrl.wi v8, v8, 01377; RV64-NEXT: ret1378 %a = call <vscale x 4 x double> @llvm.rint.nxv4f64(<vscale x 4 x double> %x)1379 %b = fptoui <vscale x 4 x double> %a to <vscale x 4 x i8>1380 ret <vscale x 4 x i8> %b1381}1382 1383define <vscale x 4 x i16> @rint_nxv4f64_to_si16(<vscale x 4 x double> %x) {1384; RV32-LABEL: rint_nxv4f64_to_si16:1385; RV32: # %bb.0:1386; RV32-NEXT: lui a0, %hi(.LCPI42_0)1387; RV32-NEXT: fld fa5, %lo(.LCPI42_0)(a0)1388; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1389; RV32-NEXT: vfabs.v v12, v81390; RV32-NEXT: vmflt.vf v0, v12, fa51391; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t1392; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t1393; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu1394; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t1395; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma1396; RV32-NEXT: vfncvt.rtz.x.f.w v12, v81397; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma1398; RV32-NEXT: vnsrl.wi v8, v12, 01399; RV32-NEXT: ret1400;1401; RV64-LABEL: rint_nxv4f64_to_si16:1402; RV64: # %bb.0:1403; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma1404; RV64-NEXT: vfabs.v v12, v81405; RV64-NEXT: li a0, 10751406; RV64-NEXT: slli a0, a0, 521407; RV64-NEXT: fmv.d.x fa5, a01408; RV64-NEXT: vmflt.vf v0, v12, fa51409; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t1410; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t1411; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu1412; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t1413; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma1414; RV64-NEXT: vfncvt.rtz.x.f.w v12, v81415; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma1416; RV64-NEXT: vnsrl.wi v8, v12, 01417; RV64-NEXT: ret1418 %a = call <vscale x 4 x double> @llvm.rint.nxv4f64(<vscale x 4 x double> %x)1419 %b = fptosi <vscale x 4 x double> %a to <vscale x 4 x i16>1420 ret <vscale x 4 x i16> %b1421}1422 1423define <vscale x 4 x i16> @rint_nxv4f64_to_ui16(<vscale x 4 x double> %x) {1424; RV32-LABEL: rint_nxv4f64_to_ui16:1425; RV32: # %bb.0:1426; RV32-NEXT: lui a0, %hi(.LCPI43_0)1427; RV32-NEXT: fld fa5, %lo(.LCPI43_0)(a0)1428; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1429; RV32-NEXT: vfabs.v v12, v81430; RV32-NEXT: vmflt.vf v0, v12, fa51431; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t1432; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t1433; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu1434; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t1435; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma1436; RV32-NEXT: vfncvt.rtz.xu.f.w v12, v81437; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma1438; RV32-NEXT: vnsrl.wi v8, v12, 01439; RV32-NEXT: ret1440;1441; RV64-LABEL: rint_nxv4f64_to_ui16:1442; RV64: # %bb.0:1443; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma1444; RV64-NEXT: vfabs.v v12, v81445; RV64-NEXT: li a0, 10751446; RV64-NEXT: slli a0, a0, 521447; RV64-NEXT: fmv.d.x fa5, a01448; RV64-NEXT: vmflt.vf v0, v12, fa51449; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t1450; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t1451; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu1452; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t1453; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma1454; RV64-NEXT: vfncvt.rtz.xu.f.w v12, v81455; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma1456; RV64-NEXT: vnsrl.wi v8, v12, 01457; RV64-NEXT: ret1458 %a = call <vscale x 4 x double> @llvm.rint.nxv4f64(<vscale x 4 x double> %x)1459 %b = fptoui <vscale x 4 x double> %a to <vscale x 4 x i16>1460 ret <vscale x 4 x i16> %b1461}1462 1463define <vscale x 4 x i32> @rint_nxv4f64_to_si32(<vscale x 4 x double> %x) {1464; RV32-LABEL: rint_nxv4f64_to_si32:1465; RV32: # %bb.0:1466; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma1467; RV32-NEXT: vfncvt.x.f.w v12, v81468; RV32-NEXT: vmv.v.v v8, v121469; RV32-NEXT: ret1470;1471; RV64-LABEL: rint_nxv4f64_to_si32:1472; RV64: # %bb.0:1473; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma1474; RV64-NEXT: vfncvt.x.f.w v12, v81475; RV64-NEXT: vmv.v.v v8, v121476; RV64-NEXT: ret1477 %a = call <vscale x 4 x double> @llvm.rint.nxv4f64(<vscale x 4 x double> %x)1478 %b = fptosi <vscale x 4 x double> %a to <vscale x 4 x i32>1479 ret <vscale x 4 x i32> %b1480}1481 1482define <vscale x 4 x i32> @rint_nxv4f64_to_ui32(<vscale x 4 x double> %x) {1483; RV32-LABEL: rint_nxv4f64_to_ui32:1484; RV32: # %bb.0:1485; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma1486; RV32-NEXT: vfncvt.xu.f.w v12, v81487; RV32-NEXT: vmv.v.v v8, v121488; RV32-NEXT: ret1489;1490; RV64-LABEL: rint_nxv4f64_to_ui32:1491; RV64: # %bb.0:1492; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma1493; RV64-NEXT: vfncvt.xu.f.w v12, v81494; RV64-NEXT: vmv.v.v v8, v121495; RV64-NEXT: ret1496 %a = call <vscale x 4 x double> @llvm.rint.nxv4f64(<vscale x 4 x double> %x)1497 %b = fptoui <vscale x 4 x double> %a to <vscale x 4 x i32>1498 ret <vscale x 4 x i32> %b1499}1500 1501define <vscale x 4 x i64> @rint_nxv4f64_to_si64(<vscale x 4 x double> %x) {1502; RV32-LABEL: rint_nxv4f64_to_si64:1503; RV32: # %bb.0:1504; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1505; RV32-NEXT: vfcvt.x.f.v v8, v81506; RV32-NEXT: ret1507;1508; RV64-LABEL: rint_nxv4f64_to_si64:1509; RV64: # %bb.0:1510; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma1511; RV64-NEXT: vfcvt.x.f.v v8, v81512; RV64-NEXT: ret1513 %a = call <vscale x 4 x double> @llvm.rint.nxv4f64(<vscale x 4 x double> %x)1514 %b = fptosi <vscale x 4 x double> %a to <vscale x 4 x i64>1515 ret <vscale x 4 x i64> %b1516}1517 1518define <vscale x 4 x i64> @rint_nxv4f64_to_ui64(<vscale x 4 x double> %x) {1519; RV32-LABEL: rint_nxv4f64_to_ui64:1520; RV32: # %bb.0:1521; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1522; RV32-NEXT: vfcvt.xu.f.v v8, v81523; RV32-NEXT: ret1524;1525; RV64-LABEL: rint_nxv4f64_to_ui64:1526; RV64: # %bb.0:1527; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma1528; RV64-NEXT: vfcvt.xu.f.v v8, v81529; RV64-NEXT: ret1530 %a = call <vscale x 4 x double> @llvm.rint.nxv4f64(<vscale x 4 x double> %x)1531 %b = fptoui <vscale x 4 x double> %a to <vscale x 4 x i64>1532 ret <vscale x 4 x i64> %b1533}1534