80 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV323; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV644; Should expand to scalar instructions and do not crash5 6define i32 @vpreduce_add_v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) {7; RV32-LABEL: vpreduce_add_v4i32:8; RV32: # %bb.0:9; RV32-NEXT: lw a4, 0(a1)10; RV32-NEXT: lw a5, 4(a1)11; RV32-NEXT: lw a6, 8(a1)12; RV32-NEXT: lw a1, 12(a1)13; RV32-NEXT: lw a7, 0(a2)14; RV32-NEXT: lw t0, 4(a2)15; RV32-NEXT: lw t1, 8(a2)16; RV32-NEXT: lw a2, 12(a2)17; RV32-NEXT: snez t2, a318; RV32-NEXT: sltiu t3, a3, 319; RV32-NEXT: sltiu t4, a3, 420; RV32-NEXT: sltiu a3, a3, 221; RV32-NEXT: xori t3, t3, 122; RV32-NEXT: xori t4, t4, 123; RV32-NEXT: xori a3, a3, 124; RV32-NEXT: and a3, a3, t025; RV32-NEXT: and a2, t4, a226; RV32-NEXT: and t0, t3, t127; RV32-NEXT: and a7, t2, a728; RV32-NEXT: neg a7, a729; RV32-NEXT: neg t0, t030; RV32-NEXT: neg a2, a231; RV32-NEXT: neg a3, a332; RV32-NEXT: and a4, a7, a433; RV32-NEXT: and a6, t0, a634; RV32-NEXT: and a1, a2, a135; RV32-NEXT: and a3, a3, a536; RV32-NEXT: add a1, a3, a137; RV32-NEXT: add a4, a4, a638; RV32-NEXT: add a1, a4, a139; RV32-NEXT: add a0, a1, a040; RV32-NEXT: ret41;42; RV64-LABEL: vpreduce_add_v4i32:43; RV64: # %bb.0:44; RV64-NEXT: lw a4, 0(a1)45; RV64-NEXT: lw a5, 8(a1)46; RV64-NEXT: lw a6, 16(a1)47; RV64-NEXT: lw a1, 24(a1)48; RV64-NEXT: ld a7, 0(a2)49; RV64-NEXT: ld t0, 8(a2)50; RV64-NEXT: ld t1, 16(a2)51; RV64-NEXT: ld a2, 24(a2)52; RV64-NEXT: sext.w a3, a353; RV64-NEXT: snez t2, a354; RV64-NEXT: sltiu t3, a3, 355; RV64-NEXT: sltiu t4, a3, 456; RV64-NEXT: sltiu a3, a3, 257; RV64-NEXT: xori t3, t3, 158; RV64-NEXT: xori t4, t4, 159; RV64-NEXT: xori a3, a3, 160; RV64-NEXT: and a3, a3, t061; RV64-NEXT: and a2, t4, a262; RV64-NEXT: and t0, t3, t163; RV64-NEXT: and a7, t2, a764; RV64-NEXT: neg a7, a765; RV64-NEXT: neg t0, t066; RV64-NEXT: neg a2, a267; RV64-NEXT: neg a3, a368; RV64-NEXT: and a4, a7, a469; RV64-NEXT: and a6, t0, a670; RV64-NEXT: and a1, a2, a171; RV64-NEXT: and a3, a3, a572; RV64-NEXT: add a1, a3, a173; RV64-NEXT: add a4, a4, a674; RV64-NEXT: add a1, a4, a175; RV64-NEXT: addw a0, a1, a076; RV64-NEXT: ret77 %r = call i32 @llvm.vp.reduce.add.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)78 ret i32 %r79}80