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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 1 x i8> @sextload_nxv1i1_nxv1i8(ptr %x) {6; CHECK-LABEL: sextload_nxv1i1_nxv1i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma9; CHECK-NEXT: vlm.v v0, (a0)10; CHECK-NEXT: vmv.v.i v8, 011; CHECK-NEXT: vmerge.vim v8, v8, -1, v012; CHECK-NEXT: ret13 %y = load <vscale x 1 x i1>, ptr %x14 %z = sext <vscale x 1 x i1> %y to <vscale x 1 x i8>15 ret <vscale x 1 x i8> %z16}17 18define <vscale x 1 x i16> @sextload_nxv1i8_nxv1i16(ptr %x) {19; CHECK-LABEL: sextload_nxv1i8_nxv1i16:20; CHECK: # %bb.0:21; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma22; CHECK-NEXT: vle8.v v9, (a0)23; CHECK-NEXT: vsext.vf2 v8, v924; CHECK-NEXT: ret25 %y = load <vscale x 1 x i8>, ptr %x26 %z = sext <vscale x 1 x i8> %y to <vscale x 1 x i16>27 ret <vscale x 1 x i16> %z28}29 30define <vscale x 1 x i16> @zextload_nxv1i8_nxv1i16(ptr %x) {31; CHECK-LABEL: zextload_nxv1i8_nxv1i16:32; CHECK: # %bb.0:33; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma34; CHECK-NEXT: vle8.v v9, (a0)35; CHECK-NEXT: vzext.vf2 v8, v936; CHECK-NEXT: ret37 %y = load <vscale x 1 x i8>, ptr %x38 %z = zext <vscale x 1 x i8> %y to <vscale x 1 x i16>39 ret <vscale x 1 x i16> %z40}41 42define <vscale x 1 x i32> @sextload_nxv1i8_nxv1i32(ptr %x) {43; CHECK-LABEL: sextload_nxv1i8_nxv1i32:44; CHECK: # %bb.0:45; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma46; CHECK-NEXT: vle8.v v9, (a0)47; CHECK-NEXT: vsext.vf4 v8, v948; CHECK-NEXT: ret49 %y = load <vscale x 1 x i8>, ptr %x50 %z = sext <vscale x 1 x i8> %y to <vscale x 1 x i32>51 ret <vscale x 1 x i32> %z52}53 54define <vscale x 1 x i32> @zextload_nxv1i8_nxv1i32(ptr %x) {55; CHECK-LABEL: zextload_nxv1i8_nxv1i32:56; CHECK: # %bb.0:57; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma58; CHECK-NEXT: vle8.v v9, (a0)59; CHECK-NEXT: vzext.vf4 v8, v960; CHECK-NEXT: ret61 %y = load <vscale x 1 x i8>, ptr %x62 %z = zext <vscale x 1 x i8> %y to <vscale x 1 x i32>63 ret <vscale x 1 x i32> %z64}65 66define <vscale x 1 x i64> @sextload_nxv1i8_nxv1i64(ptr %x) {67; CHECK-LABEL: sextload_nxv1i8_nxv1i64:68; CHECK: # %bb.0:69; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma70; CHECK-NEXT: vle8.v v9, (a0)71; CHECK-NEXT: vsext.vf8 v8, v972; CHECK-NEXT: ret73 %y = load <vscale x 1 x i8>, ptr %x74 %z = sext <vscale x 1 x i8> %y to <vscale x 1 x i64>75 ret <vscale x 1 x i64> %z76}77 78define <vscale x 1 x i64> @zextload_nxv1i8_nxv1i64(ptr %x) {79; CHECK-LABEL: zextload_nxv1i8_nxv1i64:80; CHECK: # %bb.0:81; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma82; CHECK-NEXT: vle8.v v9, (a0)83; CHECK-NEXT: vzext.vf8 v8, v984; CHECK-NEXT: ret85 %y = load <vscale x 1 x i8>, ptr %x86 %z = zext <vscale x 1 x i8> %y to <vscale x 1 x i64>87 ret <vscale x 1 x i64> %z88}89 90define <vscale x 2 x i16> @sextload_nxv2i8_nxv2i16(ptr %x) {91; CHECK-LABEL: sextload_nxv2i8_nxv2i16:92; CHECK: # %bb.0:93; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma94; CHECK-NEXT: vle8.v v9, (a0)95; CHECK-NEXT: vsext.vf2 v8, v996; CHECK-NEXT: ret97 %y = load <vscale x 2 x i8>, ptr %x98 %z = sext <vscale x 2 x i8> %y to <vscale x 2 x i16>99 ret <vscale x 2 x i16> %z100}101 102define <vscale x 2 x i16> @zextload_nxv2i8_nxv2i16(ptr %x) {103; CHECK-LABEL: zextload_nxv2i8_nxv2i16:104; CHECK: # %bb.0:105; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma106; CHECK-NEXT: vle8.v v9, (a0)107; CHECK-NEXT: vzext.vf2 v8, v9108; CHECK-NEXT: ret109 %y = load <vscale x 2 x i8>, ptr %x110 %z = zext <vscale x 2 x i8> %y to <vscale x 2 x i16>111 ret <vscale x 2 x i16> %z112}113 114define <vscale x 2 x i32> @sextload_nxv2i8_nxv2i32(ptr %x) {115; CHECK-LABEL: sextload_nxv2i8_nxv2i32:116; CHECK: # %bb.0:117; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma118; CHECK-NEXT: vle8.v v9, (a0)119; CHECK-NEXT: vsext.vf4 v8, v9120; CHECK-NEXT: ret121 %y = load <vscale x 2 x i8>, ptr %x122 %z = sext <vscale x 2 x i8> %y to <vscale x 2 x i32>123 ret <vscale x 2 x i32> %z124}125 126define <vscale x 2 x i32> @zextload_nxv2i8_nxv2i32(ptr %x) {127; CHECK-LABEL: zextload_nxv2i8_nxv2i32:128; CHECK: # %bb.0:129; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma130; CHECK-NEXT: vle8.v v9, (a0)131; CHECK-NEXT: vzext.vf4 v8, v9132; CHECK-NEXT: ret133 %y = load <vscale x 2 x i8>, ptr %x134 %z = zext <vscale x 2 x i8> %y to <vscale x 2 x i32>135 ret <vscale x 2 x i32> %z136}137 138define <vscale x 2 x i64> @sextload_nxv2i8_nxv2i64(ptr %x) {139; CHECK-LABEL: sextload_nxv2i8_nxv2i64:140; CHECK: # %bb.0:141; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma142; CHECK-NEXT: vle8.v v10, (a0)143; CHECK-NEXT: vsext.vf8 v8, v10144; CHECK-NEXT: ret145 %y = load <vscale x 2 x i8>, ptr %x146 %z = sext <vscale x 2 x i8> %y to <vscale x 2 x i64>147 ret <vscale x 2 x i64> %z148}149 150define <vscale x 2 x i64> @zextload_nxv2i8_nxv2i64(ptr %x) {151; CHECK-LABEL: zextload_nxv2i8_nxv2i64:152; CHECK: # %bb.0:153; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma154; CHECK-NEXT: vle8.v v10, (a0)155; CHECK-NEXT: vzext.vf8 v8, v10156; CHECK-NEXT: ret157 %y = load <vscale x 2 x i8>, ptr %x158 %z = zext <vscale x 2 x i8> %y to <vscale x 2 x i64>159 ret <vscale x 2 x i64> %z160}161 162define <vscale x 4 x i16> @sextload_nxv4i8_nxv4i16(ptr %x) {163; CHECK-LABEL: sextload_nxv4i8_nxv4i16:164; CHECK: # %bb.0:165; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma166; CHECK-NEXT: vle8.v v9, (a0)167; CHECK-NEXT: vsext.vf2 v8, v9168; CHECK-NEXT: ret169 %y = load <vscale x 4 x i8>, ptr %x170 %z = sext <vscale x 4 x i8> %y to <vscale x 4 x i16>171 ret <vscale x 4 x i16> %z172}173 174define <vscale x 4 x i16> @zextload_nxv4i8_nxv4i16(ptr %x) {175; CHECK-LABEL: zextload_nxv4i8_nxv4i16:176; CHECK: # %bb.0:177; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma178; CHECK-NEXT: vle8.v v9, (a0)179; CHECK-NEXT: vzext.vf2 v8, v9180; CHECK-NEXT: ret181 %y = load <vscale x 4 x i8>, ptr %x182 %z = zext <vscale x 4 x i8> %y to <vscale x 4 x i16>183 ret <vscale x 4 x i16> %z184}185 186define <vscale x 4 x i32> @sextload_nxv4i8_nxv4i32(ptr %x) {187; CHECK-LABEL: sextload_nxv4i8_nxv4i32:188; CHECK: # %bb.0:189; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma190; CHECK-NEXT: vle8.v v10, (a0)191; CHECK-NEXT: vsext.vf4 v8, v10192; CHECK-NEXT: ret193 %y = load <vscale x 4 x i8>, ptr %x194 %z = sext <vscale x 4 x i8> %y to <vscale x 4 x i32>195 ret <vscale x 4 x i32> %z196}197 198define <vscale x 4 x i32> @zextload_nxv4i8_nxv4i32(ptr %x) {199; CHECK-LABEL: zextload_nxv4i8_nxv4i32:200; CHECK: # %bb.0:201; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma202; CHECK-NEXT: vle8.v v10, (a0)203; CHECK-NEXT: vzext.vf4 v8, v10204; CHECK-NEXT: ret205 %y = load <vscale x 4 x i8>, ptr %x206 %z = zext <vscale x 4 x i8> %y to <vscale x 4 x i32>207 ret <vscale x 4 x i32> %z208}209 210define <vscale x 4 x i64> @sextload_nxv4i8_nxv4i64(ptr %x) {211; CHECK-LABEL: sextload_nxv4i8_nxv4i64:212; CHECK: # %bb.0:213; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma214; CHECK-NEXT: vle8.v v12, (a0)215; CHECK-NEXT: vsext.vf8 v8, v12216; CHECK-NEXT: ret217 %y = load <vscale x 4 x i8>, ptr %x218 %z = sext <vscale x 4 x i8> %y to <vscale x 4 x i64>219 ret <vscale x 4 x i64> %z220}221 222define <vscale x 4 x i64> @zextload_nxv4i8_nxv4i64(ptr %x) {223; CHECK-LABEL: zextload_nxv4i8_nxv4i64:224; CHECK: # %bb.0:225; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma226; CHECK-NEXT: vle8.v v12, (a0)227; CHECK-NEXT: vzext.vf8 v8, v12228; CHECK-NEXT: ret229 %y = load <vscale x 4 x i8>, ptr %x230 %z = zext <vscale x 4 x i8> %y to <vscale x 4 x i64>231 ret <vscale x 4 x i64> %z232}233 234define <vscale x 8 x i16> @sextload_nxv8i8_nxv8i16(ptr %x) {235; CHECK-LABEL: sextload_nxv8i8_nxv8i16:236; CHECK: # %bb.0:237; CHECK-NEXT: vl1r.v v10, (a0)238; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma239; CHECK-NEXT: vsext.vf2 v8, v10240; CHECK-NEXT: ret241 %y = load <vscale x 8 x i8>, ptr %x242 %z = sext <vscale x 8 x i8> %y to <vscale x 8 x i16>243 ret <vscale x 8 x i16> %z244}245 246define <vscale x 8 x i16> @zextload_nxv8i8_nxv8i16(ptr %x) {247; CHECK-LABEL: zextload_nxv8i8_nxv8i16:248; CHECK: # %bb.0:249; CHECK-NEXT: vl1r.v v10, (a0)250; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma251; CHECK-NEXT: vzext.vf2 v8, v10252; CHECK-NEXT: ret253 %y = load <vscale x 8 x i8>, ptr %x254 %z = zext <vscale x 8 x i8> %y to <vscale x 8 x i16>255 ret <vscale x 8 x i16> %z256}257 258define <vscale x 8 x i32> @sextload_nxv8i8_nxv8i32(ptr %x) {259; CHECK-LABEL: sextload_nxv8i8_nxv8i32:260; CHECK: # %bb.0:261; CHECK-NEXT: vl1r.v v12, (a0)262; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma263; CHECK-NEXT: vsext.vf4 v8, v12264; CHECK-NEXT: ret265 %y = load <vscale x 8 x i8>, ptr %x266 %z = sext <vscale x 8 x i8> %y to <vscale x 8 x i32>267 ret <vscale x 8 x i32> %z268}269 270define <vscale x 8 x i32> @zextload_nxv8i8_nxv8i32(ptr %x) {271; CHECK-LABEL: zextload_nxv8i8_nxv8i32:272; CHECK: # %bb.0:273; CHECK-NEXT: vl1r.v v12, (a0)274; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma275; CHECK-NEXT: vzext.vf4 v8, v12276; CHECK-NEXT: ret277 %y = load <vscale x 8 x i8>, ptr %x278 %z = zext <vscale x 8 x i8> %y to <vscale x 8 x i32>279 ret <vscale x 8 x i32> %z280}281 282define <vscale x 8 x i64> @sextload_nxv8i8_nxv8i64(ptr %x) {283; CHECK-LABEL: sextload_nxv8i8_nxv8i64:284; CHECK: # %bb.0:285; CHECK-NEXT: vl1r.v v16, (a0)286; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma287; CHECK-NEXT: vsext.vf8 v8, v16288; CHECK-NEXT: ret289 %y = load <vscale x 8 x i8>, ptr %x290 %z = sext <vscale x 8 x i8> %y to <vscale x 8 x i64>291 ret <vscale x 8 x i64> %z292}293 294define <vscale x 8 x i64> @zextload_nxv8i8_nxv8i64(ptr %x) {295; CHECK-LABEL: zextload_nxv8i8_nxv8i64:296; CHECK: # %bb.0:297; CHECK-NEXT: vl1r.v v16, (a0)298; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma299; CHECK-NEXT: vzext.vf8 v8, v16300; CHECK-NEXT: ret301 %y = load <vscale x 8 x i8>, ptr %x302 %z = zext <vscale x 8 x i8> %y to <vscale x 8 x i64>303 ret <vscale x 8 x i64> %z304}305 306define <vscale x 16 x i16> @sextload_nxv16i8_nxv16i16(ptr %x) {307; CHECK-LABEL: sextload_nxv16i8_nxv16i16:308; CHECK: # %bb.0:309; CHECK-NEXT: vl2r.v v12, (a0)310; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma311; CHECK-NEXT: vsext.vf2 v8, v12312; CHECK-NEXT: ret313 %y = load <vscale x 16 x i8>, ptr %x314 %z = sext <vscale x 16 x i8> %y to <vscale x 16 x i16>315 ret <vscale x 16 x i16> %z316}317 318define <vscale x 16 x i16> @zextload_nxv16i8_nxv16i16(ptr %x) {319; CHECK-LABEL: zextload_nxv16i8_nxv16i16:320; CHECK: # %bb.0:321; CHECK-NEXT: vl2r.v v12, (a0)322; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma323; CHECK-NEXT: vzext.vf2 v8, v12324; CHECK-NEXT: ret325 %y = load <vscale x 16 x i8>, ptr %x326 %z = zext <vscale x 16 x i8> %y to <vscale x 16 x i16>327 ret <vscale x 16 x i16> %z328}329 330define <vscale x 16 x i32> @sextload_nxv16i8_nxv16i32(ptr %x) {331; CHECK-LABEL: sextload_nxv16i8_nxv16i32:332; CHECK: # %bb.0:333; CHECK-NEXT: vl2r.v v16, (a0)334; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma335; CHECK-NEXT: vsext.vf4 v8, v16336; CHECK-NEXT: ret337 %y = load <vscale x 16 x i8>, ptr %x338 %z = sext <vscale x 16 x i8> %y to <vscale x 16 x i32>339 ret <vscale x 16 x i32> %z340}341 342define <vscale x 16 x i32> @zextload_nxv16i8_nxv16i32(ptr %x) {343; CHECK-LABEL: zextload_nxv16i8_nxv16i32:344; CHECK: # %bb.0:345; CHECK-NEXT: vl2r.v v16, (a0)346; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma347; CHECK-NEXT: vzext.vf4 v8, v16348; CHECK-NEXT: ret349 %y = load <vscale x 16 x i8>, ptr %x350 %z = zext <vscale x 16 x i8> %y to <vscale x 16 x i32>351 ret <vscale x 16 x i32> %z352}353 354define <vscale x 32 x i16> @sextload_nxv32i8_nxv32i16(ptr %x) {355; CHECK-LABEL: sextload_nxv32i8_nxv32i16:356; CHECK: # %bb.0:357; CHECK-NEXT: vl4r.v v16, (a0)358; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma359; CHECK-NEXT: vsext.vf2 v8, v16360; CHECK-NEXT: ret361 %y = load <vscale x 32 x i8>, ptr %x362 %z = sext <vscale x 32 x i8> %y to <vscale x 32 x i16>363 ret <vscale x 32 x i16> %z364}365 366define <vscale x 32 x i16> @zextload_nxv32i8_nxv32i16(ptr %x) {367; CHECK-LABEL: zextload_nxv32i8_nxv32i16:368; CHECK: # %bb.0:369; CHECK-NEXT: vl4r.v v16, (a0)370; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma371; CHECK-NEXT: vzext.vf2 v8, v16372; CHECK-NEXT: ret373 %y = load <vscale x 32 x i8>, ptr %x374 %z = zext <vscale x 32 x i8> %y to <vscale x 32 x i16>375 ret <vscale x 32 x i16> %z376}377 378define void @truncstore_nxv1i8_nxv1i1(<vscale x 1 x i8> %x, ptr %z) {379; CHECK-LABEL: truncstore_nxv1i8_nxv1i1:380; CHECK: # %bb.0:381; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma382; CHECK-NEXT: vand.vi v8, v8, 1383; CHECK-NEXT: vmsne.vi v8, v8, 0384; CHECK-NEXT: vsm.v v8, (a0)385; CHECK-NEXT: ret386 %y = trunc <vscale x 1 x i8> %x to <vscale x 1 x i1>387 store <vscale x 1 x i1> %y, ptr %z388 ret void389}390 391define void @truncstore_nxv1i16_nxv1i8(<vscale x 1 x i16> %x, ptr %z) {392; CHECK-LABEL: truncstore_nxv1i16_nxv1i8:393; CHECK: # %bb.0:394; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma395; CHECK-NEXT: vnsrl.wi v8, v8, 0396; CHECK-NEXT: vse8.v v8, (a0)397; CHECK-NEXT: ret398 %y = trunc <vscale x 1 x i16> %x to <vscale x 1 x i8>399 store <vscale x 1 x i8> %y, ptr %z400 ret void401}402 403define <vscale x 1 x i32> @sextload_nxv1i16_nxv1i32(ptr %x) {404; CHECK-LABEL: sextload_nxv1i16_nxv1i32:405; CHECK: # %bb.0:406; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma407; CHECK-NEXT: vle16.v v9, (a0)408; CHECK-NEXT: vsext.vf2 v8, v9409; CHECK-NEXT: ret410 %y = load <vscale x 1 x i16>, ptr %x411 %z = sext <vscale x 1 x i16> %y to <vscale x 1 x i32>412 ret <vscale x 1 x i32> %z413}414 415define <vscale x 1 x i32> @zextload_nxv1i16_nxv1i32(ptr %x) {416; CHECK-LABEL: zextload_nxv1i16_nxv1i32:417; CHECK: # %bb.0:418; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma419; CHECK-NEXT: vle16.v v9, (a0)420; CHECK-NEXT: vzext.vf2 v8, v9421; CHECK-NEXT: ret422 %y = load <vscale x 1 x i16>, ptr %x423 %z = zext <vscale x 1 x i16> %y to <vscale x 1 x i32>424 ret <vscale x 1 x i32> %z425}426 427define <vscale x 1 x i64> @sextload_nxv1i16_nxv1i64(ptr %x) {428; CHECK-LABEL: sextload_nxv1i16_nxv1i64:429; CHECK: # %bb.0:430; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma431; CHECK-NEXT: vle16.v v9, (a0)432; CHECK-NEXT: vsext.vf4 v8, v9433; CHECK-NEXT: ret434 %y = load <vscale x 1 x i16>, ptr %x435 %z = sext <vscale x 1 x i16> %y to <vscale x 1 x i64>436 ret <vscale x 1 x i64> %z437}438 439define <vscale x 1 x i64> @zextload_nxv1i16_nxv1i64(ptr %x) {440; CHECK-LABEL: zextload_nxv1i16_nxv1i64:441; CHECK: # %bb.0:442; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma443; CHECK-NEXT: vle16.v v9, (a0)444; CHECK-NEXT: vzext.vf4 v8, v9445; CHECK-NEXT: ret446 %y = load <vscale x 1 x i16>, ptr %x447 %z = zext <vscale x 1 x i16> %y to <vscale x 1 x i64>448 ret <vscale x 1 x i64> %z449}450 451define void @truncstore_nxv2i16_nxv2i8(<vscale x 2 x i16> %x, ptr %z) {452; CHECK-LABEL: truncstore_nxv2i16_nxv2i8:453; CHECK: # %bb.0:454; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma455; CHECK-NEXT: vnsrl.wi v8, v8, 0456; CHECK-NEXT: vse8.v v8, (a0)457; CHECK-NEXT: ret458 %y = trunc <vscale x 2 x i16> %x to <vscale x 2 x i8>459 store <vscale x 2 x i8> %y, ptr %z460 ret void461}462 463define <vscale x 2 x i32> @sextload_nxv2i16_nxv2i32(ptr %x) {464; CHECK-LABEL: sextload_nxv2i16_nxv2i32:465; CHECK: # %bb.0:466; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma467; CHECK-NEXT: vle16.v v9, (a0)468; CHECK-NEXT: vsext.vf2 v8, v9469; CHECK-NEXT: ret470 %y = load <vscale x 2 x i16>, ptr %x471 %z = sext <vscale x 2 x i16> %y to <vscale x 2 x i32>472 ret <vscale x 2 x i32> %z473}474 475define <vscale x 2 x i32> @zextload_nxv2i16_nxv2i32(ptr %x) {476; CHECK-LABEL: zextload_nxv2i16_nxv2i32:477; CHECK: # %bb.0:478; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma479; CHECK-NEXT: vle16.v v9, (a0)480; CHECK-NEXT: vzext.vf2 v8, v9481; CHECK-NEXT: ret482 %y = load <vscale x 2 x i16>, ptr %x483 %z = zext <vscale x 2 x i16> %y to <vscale x 2 x i32>484 ret <vscale x 2 x i32> %z485}486 487define <vscale x 2 x i64> @sextload_nxv2i16_nxv2i64(ptr %x) {488; CHECK-LABEL: sextload_nxv2i16_nxv2i64:489; CHECK: # %bb.0:490; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma491; CHECK-NEXT: vle16.v v10, (a0)492; CHECK-NEXT: vsext.vf4 v8, v10493; CHECK-NEXT: ret494 %y = load <vscale x 2 x i16>, ptr %x495 %z = sext <vscale x 2 x i16> %y to <vscale x 2 x i64>496 ret <vscale x 2 x i64> %z497}498 499define <vscale x 2 x i64> @zextload_nxv2i16_nxv2i64(ptr %x) {500; CHECK-LABEL: zextload_nxv2i16_nxv2i64:501; CHECK: # %bb.0:502; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma503; CHECK-NEXT: vle16.v v10, (a0)504; CHECK-NEXT: vzext.vf4 v8, v10505; CHECK-NEXT: ret506 %y = load <vscale x 2 x i16>, ptr %x507 %z = zext <vscale x 2 x i16> %y to <vscale x 2 x i64>508 ret <vscale x 2 x i64> %z509}510 511define void @truncstore_nxv4i16_nxv4i8(<vscale x 4 x i16> %x, ptr %z) {512; CHECK-LABEL: truncstore_nxv4i16_nxv4i8:513; CHECK: # %bb.0:514; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma515; CHECK-NEXT: vnsrl.wi v8, v8, 0516; CHECK-NEXT: vse8.v v8, (a0)517; CHECK-NEXT: ret518 %y = trunc <vscale x 4 x i16> %x to <vscale x 4 x i8>519 store <vscale x 4 x i8> %y, ptr %z520 ret void521}522 523define <vscale x 4 x i32> @sextload_nxv4i16_nxv4i32(ptr %x) {524; CHECK-LABEL: sextload_nxv4i16_nxv4i32:525; CHECK: # %bb.0:526; CHECK-NEXT: vl1re16.v v10, (a0)527; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma528; CHECK-NEXT: vsext.vf2 v8, v10529; CHECK-NEXT: ret530 %y = load <vscale x 4 x i16>, ptr %x531 %z = sext <vscale x 4 x i16> %y to <vscale x 4 x i32>532 ret <vscale x 4 x i32> %z533}534 535define <vscale x 4 x i32> @zextload_nxv4i16_nxv4i32(ptr %x) {536; CHECK-LABEL: zextload_nxv4i16_nxv4i32:537; CHECK: # %bb.0:538; CHECK-NEXT: vl1re16.v v10, (a0)539; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma540; CHECK-NEXT: vzext.vf2 v8, v10541; CHECK-NEXT: ret542 %y = load <vscale x 4 x i16>, ptr %x543 %z = zext <vscale x 4 x i16> %y to <vscale x 4 x i32>544 ret <vscale x 4 x i32> %z545}546 547define <vscale x 4 x i64> @sextload_nxv4i16_nxv4i64(ptr %x) {548; CHECK-LABEL: sextload_nxv4i16_nxv4i64:549; CHECK: # %bb.0:550; CHECK-NEXT: vl1re16.v v12, (a0)551; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma552; CHECK-NEXT: vsext.vf4 v8, v12553; CHECK-NEXT: ret554 %y = load <vscale x 4 x i16>, ptr %x555 %z = sext <vscale x 4 x i16> %y to <vscale x 4 x i64>556 ret <vscale x 4 x i64> %z557}558 559define <vscale x 4 x i64> @zextload_nxv4i16_nxv4i64(ptr %x) {560; CHECK-LABEL: zextload_nxv4i16_nxv4i64:561; CHECK: # %bb.0:562; CHECK-NEXT: vl1re16.v v12, (a0)563; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma564; CHECK-NEXT: vzext.vf4 v8, v12565; CHECK-NEXT: ret566 %y = load <vscale x 4 x i16>, ptr %x567 %z = zext <vscale x 4 x i16> %y to <vscale x 4 x i64>568 ret <vscale x 4 x i64> %z569}570 571define void @truncstore_nxv8i16_nxv8i8(<vscale x 8 x i16> %x, ptr %z) {572; CHECK-LABEL: truncstore_nxv8i16_nxv8i8:573; CHECK: # %bb.0:574; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma575; CHECK-NEXT: vnsrl.wi v10, v8, 0576; CHECK-NEXT: vs1r.v v10, (a0)577; CHECK-NEXT: ret578 %y = trunc <vscale x 8 x i16> %x to <vscale x 8 x i8>579 store <vscale x 8 x i8> %y, ptr %z580 ret void581}582 583define <vscale x 8 x i32> @sextload_nxv8i16_nxv8i32(ptr %x) {584; CHECK-LABEL: sextload_nxv8i16_nxv8i32:585; CHECK: # %bb.0:586; CHECK-NEXT: vl2re16.v v12, (a0)587; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma588; CHECK-NEXT: vsext.vf2 v8, v12589; CHECK-NEXT: ret590 %y = load <vscale x 8 x i16>, ptr %x591 %z = sext <vscale x 8 x i16> %y to <vscale x 8 x i32>592 ret <vscale x 8 x i32> %z593}594 595define <vscale x 8 x i32> @zextload_nxv8i16_nxv8i32(ptr %x) {596; CHECK-LABEL: zextload_nxv8i16_nxv8i32:597; CHECK: # %bb.0:598; CHECK-NEXT: vl2re16.v v12, (a0)599; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma600; CHECK-NEXT: vzext.vf2 v8, v12601; CHECK-NEXT: ret602 %y = load <vscale x 8 x i16>, ptr %x603 %z = zext <vscale x 8 x i16> %y to <vscale x 8 x i32>604 ret <vscale x 8 x i32> %z605}606 607define <vscale x 8 x i64> @sextload_nxv8i16_nxv8i64(ptr %x) {608; CHECK-LABEL: sextload_nxv8i16_nxv8i64:609; CHECK: # %bb.0:610; CHECK-NEXT: vl2re16.v v16, (a0)611; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma612; CHECK-NEXT: vsext.vf4 v8, v16613; CHECK-NEXT: ret614 %y = load <vscale x 8 x i16>, ptr %x615 %z = sext <vscale x 8 x i16> %y to <vscale x 8 x i64>616 ret <vscale x 8 x i64> %z617}618 619define <vscale x 8 x i64> @zextload_nxv8i16_nxv8i64(ptr %x) {620; CHECK-LABEL: zextload_nxv8i16_nxv8i64:621; CHECK: # %bb.0:622; CHECK-NEXT: vl2re16.v v16, (a0)623; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma624; CHECK-NEXT: vzext.vf4 v8, v16625; CHECK-NEXT: ret626 %y = load <vscale x 8 x i16>, ptr %x627 %z = zext <vscale x 8 x i16> %y to <vscale x 8 x i64>628 ret <vscale x 8 x i64> %z629}630 631define void @truncstore_nxv16i16_nxv16i8(<vscale x 16 x i16> %x, ptr %z) {632; CHECK-LABEL: truncstore_nxv16i16_nxv16i8:633; CHECK: # %bb.0:634; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma635; CHECK-NEXT: vnsrl.wi v12, v8, 0636; CHECK-NEXT: vs2r.v v12, (a0)637; CHECK-NEXT: ret638 %y = trunc <vscale x 16 x i16> %x to <vscale x 16 x i8>639 store <vscale x 16 x i8> %y, ptr %z640 ret void641}642 643define <vscale x 16 x i32> @sextload_nxv16i16_nxv16i32(ptr %x) {644; CHECK-LABEL: sextload_nxv16i16_nxv16i32:645; CHECK: # %bb.0:646; CHECK-NEXT: vl4re16.v v16, (a0)647; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma648; CHECK-NEXT: vsext.vf2 v8, v16649; CHECK-NEXT: ret650 %y = load <vscale x 16 x i16>, ptr %x651 %z = sext <vscale x 16 x i16> %y to <vscale x 16 x i32>652 ret <vscale x 16 x i32> %z653}654 655define <vscale x 16 x i32> @zextload_nxv16i16_nxv16i32(ptr %x) {656; CHECK-LABEL: zextload_nxv16i16_nxv16i32:657; CHECK: # %bb.0:658; CHECK-NEXT: vl4re16.v v16, (a0)659; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma660; CHECK-NEXT: vzext.vf2 v8, v16661; CHECK-NEXT: ret662 %y = load <vscale x 16 x i16>, ptr %x663 %z = zext <vscale x 16 x i16> %y to <vscale x 16 x i32>664 ret <vscale x 16 x i32> %z665}666 667define void @truncstore_nxv32i16_nxv32i8(<vscale x 32 x i16> %x, ptr %z) {668; CHECK-LABEL: truncstore_nxv32i16_nxv32i8:669; CHECK: # %bb.0:670; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma671; CHECK-NEXT: vnsrl.wi v16, v8, 0672; CHECK-NEXT: vs4r.v v16, (a0)673; CHECK-NEXT: ret674 %y = trunc <vscale x 32 x i16> %x to <vscale x 32 x i8>675 store <vscale x 32 x i8> %y, ptr %z676 ret void677}678 679define void @truncstore_nxv1i32_nxv1i8(<vscale x 1 x i32> %x, ptr %z) {680; CHECK-LABEL: truncstore_nxv1i32_nxv1i8:681; CHECK: # %bb.0:682; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma683; CHECK-NEXT: vnsrl.wi v8, v8, 0684; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma685; CHECK-NEXT: vnsrl.wi v8, v8, 0686; CHECK-NEXT: vse8.v v8, (a0)687; CHECK-NEXT: ret688 %y = trunc <vscale x 1 x i32> %x to <vscale x 1 x i8>689 store <vscale x 1 x i8> %y, ptr %z690 ret void691}692 693define void @truncstore_nxv1i32_nxv1i16(<vscale x 1 x i32> %x, ptr %z) {694; CHECK-LABEL: truncstore_nxv1i32_nxv1i16:695; CHECK: # %bb.0:696; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma697; CHECK-NEXT: vnsrl.wi v8, v8, 0698; CHECK-NEXT: vse16.v v8, (a0)699; CHECK-NEXT: ret700 %y = trunc <vscale x 1 x i32> %x to <vscale x 1 x i16>701 store <vscale x 1 x i16> %y, ptr %z702 ret void703}704 705define <vscale x 1 x i64> @sextload_nxv1i32_nxv1i64(ptr %x) {706; CHECK-LABEL: sextload_nxv1i32_nxv1i64:707; CHECK: # %bb.0:708; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma709; CHECK-NEXT: vle32.v v9, (a0)710; CHECK-NEXT: vsext.vf2 v8, v9711; CHECK-NEXT: ret712 %y = load <vscale x 1 x i32>, ptr %x713 %z = sext <vscale x 1 x i32> %y to <vscale x 1 x i64>714 ret <vscale x 1 x i64> %z715}716 717define <vscale x 1 x i64> @zextload_nxv1i32_nxv1i64(ptr %x) {718; CHECK-LABEL: zextload_nxv1i32_nxv1i64:719; CHECK: # %bb.0:720; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma721; CHECK-NEXT: vle32.v v9, (a0)722; CHECK-NEXT: vzext.vf2 v8, v9723; CHECK-NEXT: ret724 %y = load <vscale x 1 x i32>, ptr %x725 %z = zext <vscale x 1 x i32> %y to <vscale x 1 x i64>726 ret <vscale x 1 x i64> %z727}728 729define void @truncstore_nxv2i32_nxv2i8(<vscale x 2 x i32> %x, ptr %z) {730; CHECK-LABEL: truncstore_nxv2i32_nxv2i8:731; CHECK: # %bb.0:732; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma733; CHECK-NEXT: vnsrl.wi v8, v8, 0734; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma735; CHECK-NEXT: vnsrl.wi v8, v8, 0736; CHECK-NEXT: vse8.v v8, (a0)737; CHECK-NEXT: ret738 %y = trunc <vscale x 2 x i32> %x to <vscale x 2 x i8>739 store <vscale x 2 x i8> %y, ptr %z740 ret void741}742 743define void @truncstore_nxv2i32_nxv2i16(<vscale x 2 x i32> %x, ptr %z) {744; CHECK-LABEL: truncstore_nxv2i32_nxv2i16:745; CHECK: # %bb.0:746; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma747; CHECK-NEXT: vnsrl.wi v8, v8, 0748; CHECK-NEXT: vse16.v v8, (a0)749; CHECK-NEXT: ret750 %y = trunc <vscale x 2 x i32> %x to <vscale x 2 x i16>751 store <vscale x 2 x i16> %y, ptr %z752 ret void753}754 755define <vscale x 2 x i64> @sextload_nxv2i32_nxv2i64(ptr %x) {756; CHECK-LABEL: sextload_nxv2i32_nxv2i64:757; CHECK: # %bb.0:758; CHECK-NEXT: vl1re32.v v10, (a0)759; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma760; CHECK-NEXT: vsext.vf2 v8, v10761; CHECK-NEXT: ret762 %y = load <vscale x 2 x i32>, ptr %x763 %z = sext <vscale x 2 x i32> %y to <vscale x 2 x i64>764 ret <vscale x 2 x i64> %z765}766 767define <vscale x 2 x i64> @zextload_nxv2i32_nxv2i64(ptr %x) {768; CHECK-LABEL: zextload_nxv2i32_nxv2i64:769; CHECK: # %bb.0:770; CHECK-NEXT: vl1re32.v v10, (a0)771; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma772; CHECK-NEXT: vzext.vf2 v8, v10773; CHECK-NEXT: ret774 %y = load <vscale x 2 x i32>, ptr %x775 %z = zext <vscale x 2 x i32> %y to <vscale x 2 x i64>776 ret <vscale x 2 x i64> %z777}778 779define void @truncstore_nxv4i32_nxv4i8(<vscale x 4 x i32> %x, ptr %z) {780; CHECK-LABEL: truncstore_nxv4i32_nxv4i8:781; CHECK: # %bb.0:782; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma783; CHECK-NEXT: vnsrl.wi v10, v8, 0784; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma785; CHECK-NEXT: vnsrl.wi v8, v10, 0786; CHECK-NEXT: vse8.v v8, (a0)787; CHECK-NEXT: ret788 %y = trunc <vscale x 4 x i32> %x to <vscale x 4 x i8>789 store <vscale x 4 x i8> %y, ptr %z790 ret void791}792 793define void @truncstore_nxv4i32_nxv4i16(<vscale x 4 x i32> %x, ptr %z) {794; CHECK-LABEL: truncstore_nxv4i32_nxv4i16:795; CHECK: # %bb.0:796; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma797; CHECK-NEXT: vnsrl.wi v10, v8, 0798; CHECK-NEXT: vs1r.v v10, (a0)799; CHECK-NEXT: ret800 %y = trunc <vscale x 4 x i32> %x to <vscale x 4 x i16>801 store <vscale x 4 x i16> %y, ptr %z802 ret void803}804 805define <vscale x 4 x i64> @sextload_nxv4i32_nxv4i64(ptr %x) {806; CHECK-LABEL: sextload_nxv4i32_nxv4i64:807; CHECK: # %bb.0:808; CHECK-NEXT: vl2re32.v v12, (a0)809; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma810; CHECK-NEXT: vsext.vf2 v8, v12811; CHECK-NEXT: ret812 %y = load <vscale x 4 x i32>, ptr %x813 %z = sext <vscale x 4 x i32> %y to <vscale x 4 x i64>814 ret <vscale x 4 x i64> %z815}816 817define <vscale x 4 x i64> @zextload_nxv4i32_nxv4i64(ptr %x) {818; CHECK-LABEL: zextload_nxv4i32_nxv4i64:819; CHECK: # %bb.0:820; CHECK-NEXT: vl2re32.v v12, (a0)821; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma822; CHECK-NEXT: vzext.vf2 v8, v12823; CHECK-NEXT: ret824 %y = load <vscale x 4 x i32>, ptr %x825 %z = zext <vscale x 4 x i32> %y to <vscale x 4 x i64>826 ret <vscale x 4 x i64> %z827}828 829define void @truncstore_nxv8i32_nxv8i8(<vscale x 8 x i32> %x, ptr %z) {830; CHECK-LABEL: truncstore_nxv8i32_nxv8i8:831; CHECK: # %bb.0:832; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma833; CHECK-NEXT: vnsrl.wi v12, v8, 0834; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma835; CHECK-NEXT: vnsrl.wi v8, v12, 0836; CHECK-NEXT: vs1r.v v8, (a0)837; CHECK-NEXT: ret838 %y = trunc <vscale x 8 x i32> %x to <vscale x 8 x i8>839 store <vscale x 8 x i8> %y, ptr %z840 ret void841}842 843define void @truncstore_nxv8i32_nxv8i16(<vscale x 8 x i32> %x, ptr %z) {844; CHECK-LABEL: truncstore_nxv8i32_nxv8i16:845; CHECK: # %bb.0:846; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma847; CHECK-NEXT: vnsrl.wi v12, v8, 0848; CHECK-NEXT: vs2r.v v12, (a0)849; CHECK-NEXT: ret850 %y = trunc <vscale x 8 x i32> %x to <vscale x 8 x i16>851 store <vscale x 8 x i16> %y, ptr %z852 ret void853}854 855define <vscale x 8 x i64> @sextload_nxv8i32_nxv8i64(ptr %x) {856; CHECK-LABEL: sextload_nxv8i32_nxv8i64:857; CHECK: # %bb.0:858; CHECK-NEXT: vl4re32.v v16, (a0)859; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma860; CHECK-NEXT: vsext.vf2 v8, v16861; CHECK-NEXT: ret862 %y = load <vscale x 8 x i32>, ptr %x863 %z = sext <vscale x 8 x i32> %y to <vscale x 8 x i64>864 ret <vscale x 8 x i64> %z865}866 867define <vscale x 8 x i64> @zextload_nxv8i32_nxv8i64(ptr %x) {868; CHECK-LABEL: zextload_nxv8i32_nxv8i64:869; CHECK: # %bb.0:870; CHECK-NEXT: vl4re32.v v16, (a0)871; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma872; CHECK-NEXT: vzext.vf2 v8, v16873; CHECK-NEXT: ret874 %y = load <vscale x 8 x i32>, ptr %x875 %z = zext <vscale x 8 x i32> %y to <vscale x 8 x i64>876 ret <vscale x 8 x i64> %z877}878 879define void @truncstore_nxv16i32_nxv16i8(<vscale x 16 x i32> %x, ptr %z) {880; CHECK-LABEL: truncstore_nxv16i32_nxv16i8:881; CHECK: # %bb.0:882; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma883; CHECK-NEXT: vnsrl.wi v16, v8, 0884; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma885; CHECK-NEXT: vnsrl.wi v8, v16, 0886; CHECK-NEXT: vs2r.v v8, (a0)887; CHECK-NEXT: ret888 %y = trunc <vscale x 16 x i32> %x to <vscale x 16 x i8>889 store <vscale x 16 x i8> %y, ptr %z890 ret void891}892 893define void @truncstore_nxv16i32_nxv16i16(<vscale x 16 x i32> %x, ptr %z) {894; CHECK-LABEL: truncstore_nxv16i32_nxv16i16:895; CHECK: # %bb.0:896; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma897; CHECK-NEXT: vnsrl.wi v16, v8, 0898; CHECK-NEXT: vs4r.v v16, (a0)899; CHECK-NEXT: ret900 %y = trunc <vscale x 16 x i32> %x to <vscale x 16 x i16>901 store <vscale x 16 x i16> %y, ptr %z902 ret void903}904 905define void @truncstore_nxv1i64_nxv1i8(<vscale x 1 x i64> %x, ptr %z) {906; CHECK-LABEL: truncstore_nxv1i64_nxv1i8:907; CHECK: # %bb.0:908; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma909; CHECK-NEXT: vnsrl.wi v8, v8, 0910; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma911; CHECK-NEXT: vnsrl.wi v8, v8, 0912; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma913; CHECK-NEXT: vnsrl.wi v8, v8, 0914; CHECK-NEXT: vse8.v v8, (a0)915; CHECK-NEXT: ret916 %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i8>917 store <vscale x 1 x i8> %y, ptr %z918 ret void919}920 921define void @truncstore_nxv1i64_nxv1i16(<vscale x 1 x i64> %x, ptr %z) {922; CHECK-LABEL: truncstore_nxv1i64_nxv1i16:923; CHECK: # %bb.0:924; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma925; CHECK-NEXT: vnsrl.wi v8, v8, 0926; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma927; CHECK-NEXT: vnsrl.wi v8, v8, 0928; CHECK-NEXT: vse16.v v8, (a0)929; CHECK-NEXT: ret930 %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i16>931 store <vscale x 1 x i16> %y, ptr %z932 ret void933}934 935define void @truncstore_nxv1i64_nxv1i32(<vscale x 1 x i64> %x, ptr %z) {936; CHECK-LABEL: truncstore_nxv1i64_nxv1i32:937; CHECK: # %bb.0:938; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma939; CHECK-NEXT: vnsrl.wi v8, v8, 0940; CHECK-NEXT: vse32.v v8, (a0)941; CHECK-NEXT: ret942 %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>943 store <vscale x 1 x i32> %y, ptr %z944 ret void945}946 947define void @truncstore_nxv2i64_nxv2i8(<vscale x 2 x i64> %x, ptr %z) {948; CHECK-LABEL: truncstore_nxv2i64_nxv2i8:949; CHECK: # %bb.0:950; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma951; CHECK-NEXT: vnsrl.wi v10, v8, 0952; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma953; CHECK-NEXT: vnsrl.wi v8, v10, 0954; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma955; CHECK-NEXT: vnsrl.wi v8, v8, 0956; CHECK-NEXT: vse8.v v8, (a0)957; CHECK-NEXT: ret958 %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i8>959 store <vscale x 2 x i8> %y, ptr %z960 ret void961}962 963define void @truncstore_nxv2i64_nxv2i16(<vscale x 2 x i64> %x, ptr %z) {964; CHECK-LABEL: truncstore_nxv2i64_nxv2i16:965; CHECK: # %bb.0:966; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma967; CHECK-NEXT: vnsrl.wi v10, v8, 0968; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma969; CHECK-NEXT: vnsrl.wi v8, v10, 0970; CHECK-NEXT: vse16.v v8, (a0)971; CHECK-NEXT: ret972 %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i16>973 store <vscale x 2 x i16> %y, ptr %z974 ret void975}976 977define void @truncstore_nxv2i64_nxv2i32(<vscale x 2 x i64> %x, ptr %z) {978; CHECK-LABEL: truncstore_nxv2i64_nxv2i32:979; CHECK: # %bb.0:980; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma981; CHECK-NEXT: vnsrl.wi v10, v8, 0982; CHECK-NEXT: vs1r.v v10, (a0)983; CHECK-NEXT: ret984 %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>985 store <vscale x 2 x i32> %y, ptr %z986 ret void987}988 989define void @truncstore_nxv4i64_nxv4i8(<vscale x 4 x i64> %x, ptr %z) {990; CHECK-LABEL: truncstore_nxv4i64_nxv4i8:991; CHECK: # %bb.0:992; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma993; CHECK-NEXT: vnsrl.wi v12, v8, 0994; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma995; CHECK-NEXT: vnsrl.wi v8, v12, 0996; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma997; CHECK-NEXT: vnsrl.wi v8, v8, 0998; CHECK-NEXT: vse8.v v8, (a0)999; CHECK-NEXT: ret1000 %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i8>1001 store <vscale x 4 x i8> %y, ptr %z1002 ret void1003}1004 1005define void @truncstore_nxv4i64_nxv4i16(<vscale x 4 x i64> %x, ptr %z) {1006; CHECK-LABEL: truncstore_nxv4i64_nxv4i16:1007; CHECK: # %bb.0:1008; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma1009; CHECK-NEXT: vnsrl.wi v12, v8, 01010; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma1011; CHECK-NEXT: vnsrl.wi v8, v12, 01012; CHECK-NEXT: vs1r.v v8, (a0)1013; CHECK-NEXT: ret1014 %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i16>1015 store <vscale x 4 x i16> %y, ptr %z1016 ret void1017}1018 1019define void @truncstore_nxv4i64_nxv4i32(<vscale x 4 x i64> %x, ptr %z) {1020; CHECK-LABEL: truncstore_nxv4i64_nxv4i32:1021; CHECK: # %bb.0:1022; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma1023; CHECK-NEXT: vnsrl.wi v12, v8, 01024; CHECK-NEXT: vs2r.v v12, (a0)1025; CHECK-NEXT: ret1026 %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>1027 store <vscale x 4 x i32> %y, ptr %z1028 ret void1029}1030 1031define void @truncstore_nxv8i64_nxv8i8(<vscale x 8 x i64> %x, ptr %z) {1032; CHECK-LABEL: truncstore_nxv8i64_nxv8i8:1033; CHECK: # %bb.0:1034; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma1035; CHECK-NEXT: vnsrl.wi v16, v8, 01036; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma1037; CHECK-NEXT: vnsrl.wi v8, v16, 01038; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma1039; CHECK-NEXT: vnsrl.wi v10, v8, 01040; CHECK-NEXT: vs1r.v v10, (a0)1041; CHECK-NEXT: ret1042 %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i8>1043 store <vscale x 8 x i8> %y, ptr %z1044 ret void1045}1046 1047define void @truncstore_nxv8i64_nxv8i16(<vscale x 8 x i64> %x, ptr %z) {1048; CHECK-LABEL: truncstore_nxv8i64_nxv8i16:1049; CHECK: # %bb.0:1050; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma1051; CHECK-NEXT: vnsrl.wi v16, v8, 01052; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma1053; CHECK-NEXT: vnsrl.wi v8, v16, 01054; CHECK-NEXT: vs2r.v v8, (a0)1055; CHECK-NEXT: ret1056 %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i16>1057 store <vscale x 8 x i16> %y, ptr %z1058 ret void1059}1060 1061define void @truncstore_nxv8i64_nxv8i32(<vscale x 8 x i64> %x, ptr %z) {1062; CHECK-LABEL: truncstore_nxv8i64_nxv8i32:1063; CHECK: # %bb.0:1064; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma1065; CHECK-NEXT: vnsrl.wi v16, v8, 01066; CHECK-NEXT: vs4r.v v16, (a0)1067; CHECK-NEXT: ret1068 %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>1069 store <vscale x 8 x i32> %y, ptr %z1070 ret void1071}1072 1073define <vscale x 1 x float> @extload_nxv1f16_nxv1f32(ptr %x) {1074; CHECK-LABEL: extload_nxv1f16_nxv1f32:1075; CHECK: # %bb.0:1076; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma1077; CHECK-NEXT: vle16.v v9, (a0)1078; CHECK-NEXT: vfwcvt.f.f.v v8, v91079; CHECK-NEXT: ret1080 %y = load <vscale x 1 x half>, ptr %x1081 %z = fpext <vscale x 1 x half> %y to <vscale x 1 x float>1082 ret <vscale x 1 x float> %z1083}1084 1085define <vscale x 1 x double> @extload_nxv1f16_nxv1f64(ptr %x) {1086; CHECK-LABEL: extload_nxv1f16_nxv1f64:1087; CHECK: # %bb.0:1088; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma1089; CHECK-NEXT: vle16.v v8, (a0)1090; CHECK-NEXT: vfwcvt.f.f.v v9, v81091; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1092; CHECK-NEXT: vfwcvt.f.f.v v8, v91093; CHECK-NEXT: ret1094 %y = load <vscale x 1 x half>, ptr %x1095 %z = fpext <vscale x 1 x half> %y to <vscale x 1 x double>1096 ret <vscale x 1 x double> %z1097}1098 1099define <vscale x 2 x float> @extload_nxv2f16_nxv2f32(ptr %x) {1100; CHECK-LABEL: extload_nxv2f16_nxv2f32:1101; CHECK: # %bb.0:1102; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma1103; CHECK-NEXT: vle16.v v9, (a0)1104; CHECK-NEXT: vfwcvt.f.f.v v8, v91105; CHECK-NEXT: ret1106 %y = load <vscale x 2 x half>, ptr %x1107 %z = fpext <vscale x 2 x half> %y to <vscale x 2 x float>1108 ret <vscale x 2 x float> %z1109}1110 1111define <vscale x 2 x double> @extload_nxv2f16_nxv2f64(ptr %x) {1112; CHECK-LABEL: extload_nxv2f16_nxv2f64:1113; CHECK: # %bb.0:1114; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma1115; CHECK-NEXT: vle16.v v8, (a0)1116; CHECK-NEXT: vfwcvt.f.f.v v10, v81117; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma1118; CHECK-NEXT: vfwcvt.f.f.v v8, v101119; CHECK-NEXT: ret1120 %y = load <vscale x 2 x half>, ptr %x1121 %z = fpext <vscale x 2 x half> %y to <vscale x 2 x double>1122 ret <vscale x 2 x double> %z1123}1124 1125define <vscale x 4 x float> @extload_nxv4f16_nxv4f32(ptr %x) {1126; CHECK-LABEL: extload_nxv4f16_nxv4f32:1127; CHECK: # %bb.0:1128; CHECK-NEXT: vl1re16.v v10, (a0)1129; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma1130; CHECK-NEXT: vfwcvt.f.f.v v8, v101131; CHECK-NEXT: ret1132 %y = load <vscale x 4 x half>, ptr %x1133 %z = fpext <vscale x 4 x half> %y to <vscale x 4 x float>1134 ret <vscale x 4 x float> %z1135}1136 1137define <vscale x 4 x double> @extload_nxv4f16_nxv4f64(ptr %x) {1138; CHECK-LABEL: extload_nxv4f16_nxv4f64:1139; CHECK: # %bb.0:1140; CHECK-NEXT: vl1re16.v v8, (a0)1141; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma1142; CHECK-NEXT: vfwcvt.f.f.v v12, v81143; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma1144; CHECK-NEXT: vfwcvt.f.f.v v8, v121145; CHECK-NEXT: ret1146 %y = load <vscale x 4 x half>, ptr %x1147 %z = fpext <vscale x 4 x half> %y to <vscale x 4 x double>1148 ret <vscale x 4 x double> %z1149}1150 1151define <vscale x 8 x float> @extload_nxv8f16_nxv8f32(ptr %x) {1152; CHECK-LABEL: extload_nxv8f16_nxv8f32:1153; CHECK: # %bb.0:1154; CHECK-NEXT: vl2re16.v v12, (a0)1155; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma1156; CHECK-NEXT: vfwcvt.f.f.v v8, v121157; CHECK-NEXT: ret1158 %y = load <vscale x 8 x half>, ptr %x1159 %z = fpext <vscale x 8 x half> %y to <vscale x 8 x float>1160 ret <vscale x 8 x float> %z1161}1162 1163define <vscale x 8 x double> @extload_nxv8f16_nxv8f64(ptr %x) {1164; CHECK-LABEL: extload_nxv8f16_nxv8f64:1165; CHECK: # %bb.0:1166; CHECK-NEXT: vl2re16.v v8, (a0)1167; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma1168; CHECK-NEXT: vfwcvt.f.f.v v16, v81169; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma1170; CHECK-NEXT: vfwcvt.f.f.v v8, v161171; CHECK-NEXT: ret1172 %y = load <vscale x 8 x half>, ptr %x1173 %z = fpext <vscale x 8 x half> %y to <vscale x 8 x double>1174 ret <vscale x 8 x double> %z1175}1176 1177define <vscale x 16 x float> @extload_nxv16f16_nxv16f32(ptr %x) {1178; CHECK-LABEL: extload_nxv16f16_nxv16f32:1179; CHECK: # %bb.0:1180; CHECK-NEXT: vl4re16.v v16, (a0)1181; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma1182; CHECK-NEXT: vfwcvt.f.f.v v8, v161183; CHECK-NEXT: ret1184 %y = load <vscale x 16 x half>, ptr %x1185 %z = fpext <vscale x 16 x half> %y to <vscale x 16 x float>1186 ret <vscale x 16 x float> %z1187}1188 1189define void @truncstore_nxv1f32_nxv1f16(<vscale x 1 x float> %x, ptr %z) {1190; CHECK-LABEL: truncstore_nxv1f32_nxv1f16:1191; CHECK: # %bb.0:1192; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma1193; CHECK-NEXT: vfncvt.f.f.w v9, v81194; CHECK-NEXT: vse16.v v9, (a0)1195; CHECK-NEXT: ret1196 %y = fptrunc <vscale x 1 x float> %x to <vscale x 1 x half>1197 store <vscale x 1 x half> %y, ptr %z1198 ret void1199}1200 1201define <vscale x 1 x double> @extload_nxv1f32_nxv1f64(ptr %x) {1202; CHECK-LABEL: extload_nxv1f32_nxv1f64:1203; CHECK: # %bb.0:1204; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma1205; CHECK-NEXT: vle32.v v9, (a0)1206; CHECK-NEXT: vfwcvt.f.f.v v8, v91207; CHECK-NEXT: ret1208 %y = load <vscale x 1 x float>, ptr %x1209 %z = fpext <vscale x 1 x float> %y to <vscale x 1 x double>1210 ret <vscale x 1 x double> %z1211}1212 1213define void @truncstore_nxv2f32_nxv2f16(<vscale x 2 x float> %x, ptr %z) {1214; CHECK-LABEL: truncstore_nxv2f32_nxv2f16:1215; CHECK: # %bb.0:1216; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma1217; CHECK-NEXT: vfncvt.f.f.w v9, v81218; CHECK-NEXT: vse16.v v9, (a0)1219; CHECK-NEXT: ret1220 %y = fptrunc <vscale x 2 x float> %x to <vscale x 2 x half>1221 store <vscale x 2 x half> %y, ptr %z1222 ret void1223}1224 1225define <vscale x 2 x double> @extload_nxv2f32_nxv2f64(ptr %x) {1226; CHECK-LABEL: extload_nxv2f32_nxv2f64:1227; CHECK: # %bb.0:1228; CHECK-NEXT: vl1re32.v v10, (a0)1229; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma1230; CHECK-NEXT: vfwcvt.f.f.v v8, v101231; CHECK-NEXT: ret1232 %y = load <vscale x 2 x float>, ptr %x1233 %z = fpext <vscale x 2 x float> %y to <vscale x 2 x double>1234 ret <vscale x 2 x double> %z1235}1236 1237define void @truncstore_nxv4f32_nxv4f16(<vscale x 4 x float> %x, ptr %z) {1238; CHECK-LABEL: truncstore_nxv4f32_nxv4f16:1239; CHECK: # %bb.0:1240; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma1241; CHECK-NEXT: vfncvt.f.f.w v10, v81242; CHECK-NEXT: vs1r.v v10, (a0)1243; CHECK-NEXT: ret1244 %y = fptrunc <vscale x 4 x float> %x to <vscale x 4 x half>1245 store <vscale x 4 x half> %y, ptr %z1246 ret void1247}1248 1249define <vscale x 4 x double> @extload_nxv4f32_nxv4f64(ptr %x) {1250; CHECK-LABEL: extload_nxv4f32_nxv4f64:1251; CHECK: # %bb.0:1252; CHECK-NEXT: vl2re32.v v12, (a0)1253; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma1254; CHECK-NEXT: vfwcvt.f.f.v v8, v121255; CHECK-NEXT: ret1256 %y = load <vscale x 4 x float>, ptr %x1257 %z = fpext <vscale x 4 x float> %y to <vscale x 4 x double>1258 ret <vscale x 4 x double> %z1259}1260 1261define void @truncstore_nxv8f32_nxv8f16(<vscale x 8 x float> %x, ptr %z) {1262; CHECK-LABEL: truncstore_nxv8f32_nxv8f16:1263; CHECK: # %bb.0:1264; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma1265; CHECK-NEXT: vfncvt.f.f.w v12, v81266; CHECK-NEXT: vs2r.v v12, (a0)1267; CHECK-NEXT: ret1268 %y = fptrunc <vscale x 8 x float> %x to <vscale x 8 x half>1269 store <vscale x 8 x half> %y, ptr %z1270 ret void1271}1272 1273define <vscale x 8 x double> @extload_nxv8f32_nxv8f64(ptr %x) {1274; CHECK-LABEL: extload_nxv8f32_nxv8f64:1275; CHECK: # %bb.0:1276; CHECK-NEXT: vl4re32.v v16, (a0)1277; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma1278; CHECK-NEXT: vfwcvt.f.f.v v8, v161279; CHECK-NEXT: ret1280 %y = load <vscale x 8 x float>, ptr %x1281 %z = fpext <vscale x 8 x float> %y to <vscale x 8 x double>1282 ret <vscale x 8 x double> %z1283}1284 1285define void @truncstore_nxv16f32_nxv16f16(<vscale x 16 x float> %x, ptr %z) {1286; CHECK-LABEL: truncstore_nxv16f32_nxv16f16:1287; CHECK: # %bb.0:1288; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma1289; CHECK-NEXT: vfncvt.f.f.w v16, v81290; CHECK-NEXT: vs4r.v v16, (a0)1291; CHECK-NEXT: ret1292 %y = fptrunc <vscale x 16 x float> %x to <vscale x 16 x half>1293 store <vscale x 16 x half> %y, ptr %z1294 ret void1295}1296 1297define void @truncstore_nxv1f64_nxv1f16(<vscale x 1 x double> %x, ptr %z) {1298; CHECK-LABEL: truncstore_nxv1f64_nxv1f16:1299; CHECK: # %bb.0:1300; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma1301; CHECK-NEXT: vfncvt.rod.f.f.w v9, v81302; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma1303; CHECK-NEXT: vfncvt.f.f.w v8, v91304; CHECK-NEXT: vse16.v v8, (a0)1305; CHECK-NEXT: ret1306 %y = fptrunc <vscale x 1 x double> %x to <vscale x 1 x half>1307 store <vscale x 1 x half> %y, ptr %z1308 ret void1309}1310 1311define void @truncstore_nxv1f64_nxv1f32(<vscale x 1 x double> %x, ptr %z) {1312; CHECK-LABEL: truncstore_nxv1f64_nxv1f32:1313; CHECK: # %bb.0:1314; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma1315; CHECK-NEXT: vfncvt.f.f.w v9, v81316; CHECK-NEXT: vse32.v v9, (a0)1317; CHECK-NEXT: ret1318 %y = fptrunc <vscale x 1 x double> %x to <vscale x 1 x float>1319 store <vscale x 1 x float> %y, ptr %z1320 ret void1321}1322 1323define void @truncstore_nxv2f64_nxv2f16(<vscale x 2 x double> %x, ptr %z) {1324; CHECK-LABEL: truncstore_nxv2f64_nxv2f16:1325; CHECK: # %bb.0:1326; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma1327; CHECK-NEXT: vfncvt.rod.f.f.w v10, v81328; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma1329; CHECK-NEXT: vfncvt.f.f.w v8, v101330; CHECK-NEXT: vse16.v v8, (a0)1331; CHECK-NEXT: ret1332 %y = fptrunc <vscale x 2 x double> %x to <vscale x 2 x half>1333 store <vscale x 2 x half> %y, ptr %z1334 ret void1335}1336 1337define void @truncstore_nxv2f64_nxv2f32(<vscale x 2 x double> %x, ptr %z) {1338; CHECK-LABEL: truncstore_nxv2f64_nxv2f32:1339; CHECK: # %bb.0:1340; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma1341; CHECK-NEXT: vfncvt.f.f.w v10, v81342; CHECK-NEXT: vs1r.v v10, (a0)1343; CHECK-NEXT: ret1344 %y = fptrunc <vscale x 2 x double> %x to <vscale x 2 x float>1345 store <vscale x 2 x float> %y, ptr %z1346 ret void1347}1348 1349define void @truncstore_nxv4f64_nxv4f16(<vscale x 4 x double> %x, ptr %z) {1350; CHECK-LABEL: truncstore_nxv4f64_nxv4f16:1351; CHECK: # %bb.0:1352; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma1353; CHECK-NEXT: vfncvt.rod.f.f.w v12, v81354; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma1355; CHECK-NEXT: vfncvt.f.f.w v8, v121356; CHECK-NEXT: vs1r.v v8, (a0)1357; CHECK-NEXT: ret1358 %y = fptrunc <vscale x 4 x double> %x to <vscale x 4 x half>1359 store <vscale x 4 x half> %y, ptr %z1360 ret void1361}1362 1363define void @truncstore_nxv4f64_nxv4f32(<vscale x 4 x double> %x, ptr %z) {1364; CHECK-LABEL: truncstore_nxv4f64_nxv4f32:1365; CHECK: # %bb.0:1366; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma1367; CHECK-NEXT: vfncvt.f.f.w v12, v81368; CHECK-NEXT: vs2r.v v12, (a0)1369; CHECK-NEXT: ret1370 %y = fptrunc <vscale x 4 x double> %x to <vscale x 4 x float>1371 store <vscale x 4 x float> %y, ptr %z1372 ret void1373}1374 1375define void @truncstore_nxv8f64_nxv8f16(<vscale x 8 x double> %x, ptr %z) {1376; CHECK-LABEL: truncstore_nxv8f64_nxv8f16:1377; CHECK: # %bb.0:1378; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma1379; CHECK-NEXT: vfncvt.rod.f.f.w v16, v81380; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma1381; CHECK-NEXT: vfncvt.f.f.w v8, v161382; CHECK-NEXT: vs2r.v v8, (a0)1383; CHECK-NEXT: ret1384 %y = fptrunc <vscale x 8 x double> %x to <vscale x 8 x half>1385 store <vscale x 8 x half> %y, ptr %z1386 ret void1387}1388 1389define void @truncstore_nxv8f64_nxv8f32(<vscale x 8 x double> %x, ptr %z) {1390; CHECK-LABEL: truncstore_nxv8f64_nxv8f32:1391; CHECK: # %bb.0:1392; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma1393; CHECK-NEXT: vfncvt.f.f.w v16, v81394; CHECK-NEXT: vs4r.v v16, (a0)1395; CHECK-NEXT: ret1396 %y = fptrunc <vscale x 8 x double> %x to <vscale x 8 x float>1397 store <vscale x 8 x float> %y, ptr %z1398 ret void1399}1400