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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple riscv32 -mattr=+m,+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple riscv64 -mattr=+m,+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec) {6; CHECK-LABEL: extract_nxv8i32_nxv4i32_0:7; CHECK: # %bb.0:8; CHECK-NEXT: ret9 %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0)10 ret <vscale x 4 x i32> %c11}12 13define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_4(<vscale x 8 x i32> %vec) {14; CHECK-LABEL: extract_nxv8i32_nxv4i32_4:15; CHECK: # %bb.0:16; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma17; CHECK-NEXT: vmv2r.v v8, v1018; CHECK-NEXT: ret19 %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 4)20 ret <vscale x 4 x i32> %c21}22 23define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_0(<vscale x 8 x i32> %vec) {24; CHECK-LABEL: extract_nxv8i32_nxv2i32_0:25; CHECK: # %bb.0:26; CHECK-NEXT: ret27 %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0)28 ret <vscale x 2 x i32> %c29}30 31define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_2(<vscale x 8 x i32> %vec) {32; CHECK-LABEL: extract_nxv8i32_nxv2i32_2:33; CHECK: # %bb.0:34; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma35; CHECK-NEXT: vmv1r.v v8, v936; CHECK-NEXT: ret37 %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 2)38 ret <vscale x 2 x i32> %c39}40 41define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_4(<vscale x 8 x i32> %vec) {42; CHECK-LABEL: extract_nxv8i32_nxv2i32_4:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma45; CHECK-NEXT: vmv1r.v v8, v1046; CHECK-NEXT: ret47 %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 4)48 ret <vscale x 2 x i32> %c49}50 51define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_6(<vscale x 8 x i32> %vec) {52; CHECK-LABEL: extract_nxv8i32_nxv2i32_6:53; CHECK: # %bb.0:54; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma55; CHECK-NEXT: vmv1r.v v8, v1156; CHECK-NEXT: ret57 %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 6)58 ret <vscale x 2 x i32> %c59}60 61define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec) {62; CHECK-LABEL: extract_nxv16i32_nxv8i32_0:63; CHECK: # %bb.0:64; CHECK-NEXT: ret65 %c = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)66 ret <vscale x 8 x i32> %c67}68 69define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_8(<vscale x 16 x i32> %vec) {70; CHECK-LABEL: extract_nxv16i32_nxv8i32_8:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma73; CHECK-NEXT: vmv4r.v v8, v1274; CHECK-NEXT: ret75 %c = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)76 ret <vscale x 8 x i32> %c77}78 79define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_0(<vscale x 16 x i32> %vec) {80; CHECK-LABEL: extract_nxv16i32_nxv4i32_0:81; CHECK: # %bb.0:82; CHECK-NEXT: ret83 %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)84 ret <vscale x 4 x i32> %c85}86 87define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_4(<vscale x 16 x i32> %vec) {88; CHECK-LABEL: extract_nxv16i32_nxv4i32_4:89; CHECK: # %bb.0:90; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma91; CHECK-NEXT: vmv2r.v v8, v1092; CHECK-NEXT: ret93 %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 4)94 ret <vscale x 4 x i32> %c95}96 97define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_8(<vscale x 16 x i32> %vec) {98; CHECK-LABEL: extract_nxv16i32_nxv4i32_8:99; CHECK: # %bb.0:100; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma101; CHECK-NEXT: vmv2r.v v8, v12102; CHECK-NEXT: ret103 %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)104 ret <vscale x 4 x i32> %c105}106 107define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_12(<vscale x 16 x i32> %vec) {108; CHECK-LABEL: extract_nxv16i32_nxv4i32_12:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma111; CHECK-NEXT: vmv2r.v v8, v14112; CHECK-NEXT: ret113 %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 12)114 ret <vscale x 4 x i32> %c115}116 117define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_0(<vscale x 16 x i32> %vec) {118; CHECK-LABEL: extract_nxv16i32_nxv2i32_0:119; CHECK: # %bb.0:120; CHECK-NEXT: ret121 %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)122 ret <vscale x 2 x i32> %c123}124 125define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_2(<vscale x 16 x i32> %vec) {126; CHECK-LABEL: extract_nxv16i32_nxv2i32_2:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma129; CHECK-NEXT: vmv1r.v v8, v9130; CHECK-NEXT: ret131 %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 2)132 ret <vscale x 2 x i32> %c133}134 135define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_4(<vscale x 16 x i32> %vec) {136; CHECK-LABEL: extract_nxv16i32_nxv2i32_4:137; CHECK: # %bb.0:138; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma139; CHECK-NEXT: vmv1r.v v8, v10140; CHECK-NEXT: ret141 %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 4)142 ret <vscale x 2 x i32> %c143}144 145define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_6(<vscale x 16 x i32> %vec) {146; CHECK-LABEL: extract_nxv16i32_nxv2i32_6:147; CHECK: # %bb.0:148; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma149; CHECK-NEXT: vmv1r.v v8, v11150; CHECK-NEXT: ret151 %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 6)152 ret <vscale x 2 x i32> %c153}154 155define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_8(<vscale x 16 x i32> %vec) {156; CHECK-LABEL: extract_nxv16i32_nxv2i32_8:157; CHECK: # %bb.0:158; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma159; CHECK-NEXT: vmv1r.v v8, v12160; CHECK-NEXT: ret161 %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)162 ret <vscale x 2 x i32> %c163}164 165define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_10(<vscale x 16 x i32> %vec) {166; CHECK-LABEL: extract_nxv16i32_nxv2i32_10:167; CHECK: # %bb.0:168; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma169; CHECK-NEXT: vmv1r.v v8, v13170; CHECK-NEXT: ret171 %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 10)172 ret <vscale x 2 x i32> %c173}174 175define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_12(<vscale x 16 x i32> %vec) {176; CHECK-LABEL: extract_nxv16i32_nxv2i32_12:177; CHECK: # %bb.0:178; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma179; CHECK-NEXT: vmv1r.v v8, v14180; CHECK-NEXT: ret181 %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 12)182 ret <vscale x 2 x i32> %c183}184 185define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_14(<vscale x 16 x i32> %vec) {186; CHECK-LABEL: extract_nxv16i32_nxv2i32_14:187; CHECK: # %bb.0:188; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma189; CHECK-NEXT: vmv1r.v v8, v15190; CHECK-NEXT: ret191 %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 14)192 ret <vscale x 2 x i32> %c193}194 195define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec) {196; CHECK-LABEL: extract_nxv16i32_nxv1i32_0:197; CHECK: # %bb.0:198; CHECK-NEXT: ret199 %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)200 ret <vscale x 1 x i32> %c201}202 203define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec) {204; CHECK-LABEL: extract_nxv16i32_nxv1i32_1:205; CHECK: # %bb.0:206; CHECK-NEXT: csrr a0, vlenb207; CHECK-NEXT: srli a0, a0, 3208; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma209; CHECK-NEXT: vslidedown.vx v8, v8, a0210; CHECK-NEXT: ret211 %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 1)212 ret <vscale x 1 x i32> %c213}214 215define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_3(<vscale x 16 x i32> %vec) {216; CHECK-LABEL: extract_nxv16i32_nxv1i32_3:217; CHECK: # %bb.0:218; CHECK-NEXT: csrr a0, vlenb219; CHECK-NEXT: srli a0, a0, 3220; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma221; CHECK-NEXT: vslidedown.vx v8, v9, a0222; CHECK-NEXT: ret223 %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 3)224 ret <vscale x 1 x i32> %c225}226 227define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_15(<vscale x 16 x i32> %vec) {228; CHECK-LABEL: extract_nxv16i32_nxv1i32_15:229; CHECK: # %bb.0:230; CHECK-NEXT: csrr a0, vlenb231; CHECK-NEXT: srli a0, a0, 3232; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma233; CHECK-NEXT: vslidedown.vx v8, v15, a0234; CHECK-NEXT: ret235 %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 15)236 ret <vscale x 1 x i32> %c237}238 239define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_2(<vscale x 16 x i32> %vec) {240; CHECK-LABEL: extract_nxv16i32_nxv1i32_2:241; CHECK: # %bb.0:242; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma243; CHECK-NEXT: vmv1r.v v8, v9244; CHECK-NEXT: ret245 %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 2)246 ret <vscale x 1 x i32> %c247}248 249define <vscale x 1 x i32> @extract_nxv2i32_nxv1i32_0(<vscale x 2 x i32> %vec) {250; CHECK-LABEL: extract_nxv2i32_nxv1i32_0:251; CHECK: # %bb.0:252; CHECK-NEXT: ret253 %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> %vec, i64 0)254 ret <vscale x 1 x i32> %c255}256 257define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_0(<vscale x 32 x i8> %vec) {258; CHECK-LABEL: extract_nxv32i8_nxv2i8_0:259; CHECK: # %bb.0:260; CHECK-NEXT: ret261 %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 0)262 ret <vscale x 2 x i8> %c263}264 265define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_2(<vscale x 32 x i8> %vec) {266; CHECK-LABEL: extract_nxv32i8_nxv2i8_2:267; CHECK: # %bb.0:268; CHECK-NEXT: csrr a0, vlenb269; CHECK-NEXT: srli a0, a0, 2270; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma271; CHECK-NEXT: vslidedown.vx v8, v8, a0272; CHECK-NEXT: ret273 %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 2)274 ret <vscale x 2 x i8> %c275}276 277define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_4(<vscale x 32 x i8> %vec) {278; CHECK-LABEL: extract_nxv32i8_nxv2i8_4:279; CHECK: # %bb.0:280; CHECK-NEXT: csrr a0, vlenb281; CHECK-NEXT: srli a0, a0, 1282; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma283; CHECK-NEXT: vslidedown.vx v8, v8, a0284; CHECK-NEXT: ret285 %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 4)286 ret <vscale x 2 x i8> %c287}288 289define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_6(<vscale x 32 x i8> %vec) {290; CHECK-LABEL: extract_nxv32i8_nxv2i8_6:291; CHECK: # %bb.0:292; CHECK-NEXT: csrr a0, vlenb293; CHECK-NEXT: srli a1, a0, 2294; CHECK-NEXT: sub a0, a0, a1295; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma296; CHECK-NEXT: vslidedown.vx v8, v8, a0297; CHECK-NEXT: ret298 %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 6)299 ret <vscale x 2 x i8> %c300}301 302define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_8(<vscale x 32 x i8> %vec) {303; CHECK-LABEL: extract_nxv32i8_nxv2i8_8:304; CHECK: # %bb.0:305; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma306; CHECK-NEXT: vmv1r.v v8, v9307; CHECK-NEXT: ret308 %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 8)309 ret <vscale x 2 x i8> %c310}311 312define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_22(<vscale x 32 x i8> %vec) {313; CHECK-LABEL: extract_nxv32i8_nxv2i8_22:314; CHECK: # %bb.0:315; CHECK-NEXT: csrr a0, vlenb316; CHECK-NEXT: srli a1, a0, 2317; CHECK-NEXT: sub a0, a0, a1318; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma319; CHECK-NEXT: vslidedown.vx v8, v10, a0320; CHECK-NEXT: ret321 %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 22)322 ret <vscale x 2 x i8> %c323}324 325define <vscale x 1 x i8> @extract_nxv8i8_nxv1i8_7(<vscale x 8 x i8> %vec) {326; CHECK-LABEL: extract_nxv8i8_nxv1i8_7:327; CHECK: # %bb.0:328; CHECK-NEXT: csrr a0, vlenb329; CHECK-NEXT: srli a1, a0, 3330; CHECK-NEXT: sub a0, a0, a1331; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma332; CHECK-NEXT: vslidedown.vx v8, v8, a0333; CHECK-NEXT: ret334 %c = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> %vec, i64 7)335 ret <vscale x 1 x i8> %c336}337 338define <vscale x 1 x i8> @extract_nxv4i8_nxv1i8_3(<vscale x 4 x i8> %vec) {339; CHECK-LABEL: extract_nxv4i8_nxv1i8_3:340; CHECK: # %bb.0:341; CHECK-NEXT: csrr a0, vlenb342; CHECK-NEXT: srli a1, a0, 3343; CHECK-NEXT: srli a0, a0, 2344; CHECK-NEXT: add a0, a0, a1345; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma346; CHECK-NEXT: vslidedown.vx v8, v8, a0347; CHECK-NEXT: ret348 %c = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, i64 3)349 ret <vscale x 1 x i8> %c350}351 352define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_0(<vscale x 16 x half> %vec) {353; CHECK-LABEL: extract_nxv2f16_nxv16f16_0:354; CHECK: # %bb.0:355; CHECK-NEXT: ret356 %c = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 0)357 ret <vscale x 2 x half> %c358}359 360define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_2(<vscale x 16 x half> %vec) {361; CHECK-LABEL: extract_nxv2f16_nxv16f16_2:362; CHECK: # %bb.0:363; CHECK-NEXT: csrr a0, vlenb364; CHECK-NEXT: srli a0, a0, 2365; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma366; CHECK-NEXT: vslidedown.vx v8, v8, a0367; CHECK-NEXT: ret368 %c = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 2)369 ret <vscale x 2 x half> %c370}371 372define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_4(<vscale x 16 x half> %vec) {373; CHECK-LABEL: extract_nxv2f16_nxv16f16_4:374; CHECK: # %bb.0:375; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma376; CHECK-NEXT: vmv1r.v v8, v9377; CHECK-NEXT: ret378 %c = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 4)379 ret <vscale x 2 x half> %c380}381 382define <vscale x 8 x i1> @extract_nxv64i1_nxv8i1_0(<vscale x 64 x i1> %mask) {383; CHECK-LABEL: extract_nxv64i1_nxv8i1_0:384; CHECK: # %bb.0:385; CHECK-NEXT: ret386 %c = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1(<vscale x 64 x i1> %mask, i64 0)387 ret <vscale x 8 x i1> %c388}389 390define <vscale x 8 x i1> @extract_nxv64i1_nxv8i1_8(<vscale x 64 x i1> %mask) {391; CHECK-LABEL: extract_nxv64i1_nxv8i1_8:392; CHECK: # %bb.0:393; CHECK-NEXT: csrr a0, vlenb394; CHECK-NEXT: srli a0, a0, 3395; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma396; CHECK-NEXT: vslidedown.vx v0, v0, a0397; CHECK-NEXT: ret398 %c = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1(<vscale x 64 x i1> %mask, i64 8)399 ret <vscale x 8 x i1> %c400}401 402define <vscale x 2 x i1> @extract_nxv64i1_nxv2i1_0(<vscale x 64 x i1> %mask) {403; CHECK-LABEL: extract_nxv64i1_nxv2i1_0:404; CHECK: # %bb.0:405; CHECK-NEXT: ret406 %c = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1(<vscale x 64 x i1> %mask, i64 0)407 ret <vscale x 2 x i1> %c408}409 410define <vscale x 2 x i1> @extract_nxv64i1_nxv2i1_2(<vscale x 64 x i1> %mask) {411; CHECK-LABEL: extract_nxv64i1_nxv2i1_2:412; CHECK: # %bb.0:413; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma414; CHECK-NEXT: vmv.v.i v8, 0415; CHECK-NEXT: csrr a0, vlenb416; CHECK-NEXT: vmerge.vim v8, v8, 1, v0417; CHECK-NEXT: srli a0, a0, 2418; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma419; CHECK-NEXT: vslidedown.vx v8, v8, a0420; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma421; CHECK-NEXT: vmsne.vi v0, v8, 0422; CHECK-NEXT: ret423 %c = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1(<vscale x 64 x i1> %mask, i64 2)424 ret <vscale x 2 x i1> %c425}426 427define <vscale x 4 x i1> @extract_nxv4i1_nxv32i1_0(<vscale x 32 x i1> %x) {428; CHECK-LABEL: extract_nxv4i1_nxv32i1_0:429; CHECK: # %bb.0:430; CHECK-NEXT: ret431 %c = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1(<vscale x 32 x i1> %x, i64 0)432 ret <vscale x 4 x i1> %c433}434 435define <vscale x 4 x i1> @extract_nxv4i1_nxv32i1_4(<vscale x 32 x i1> %x) {436; CHECK-LABEL: extract_nxv4i1_nxv32i1_4:437; CHECK: # %bb.0:438; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma439; CHECK-NEXT: vmv.v.i v8, 0440; CHECK-NEXT: csrr a0, vlenb441; CHECK-NEXT: vmerge.vim v8, v8, 1, v0442; CHECK-NEXT: srli a0, a0, 1443; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma444; CHECK-NEXT: vslidedown.vx v8, v8, a0445; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma446; CHECK-NEXT: vmsne.vi v0, v8, 0447; CHECK-NEXT: ret448 %c = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1(<vscale x 32 x i1> %x, i64 4)449 ret <vscale x 4 x i1> %c450}451 452define <vscale x 16 x i1> @extract_nxv16i1_nxv32i1_0(<vscale x 32 x i1> %x) {453; CHECK-LABEL: extract_nxv16i1_nxv32i1_0:454; CHECK: # %bb.0:455; CHECK-NEXT: ret456 %c = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1(<vscale x 32 x i1> %x, i64 0)457 ret <vscale x 16 x i1> %c458}459 460define <vscale x 16 x i1> @extract_nxv16i1_nxv32i1_16(<vscale x 32 x i1> %x) {461; CHECK-LABEL: extract_nxv16i1_nxv32i1_16:462; CHECK: # %bb.0:463; CHECK-NEXT: csrr a0, vlenb464; CHECK-NEXT: srli a0, a0, 2465; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma466; CHECK-NEXT: vslidedown.vx v0, v0, a0467; CHECK-NEXT: ret468 %c = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1(<vscale x 32 x i1> %x, i64 16)469 ret <vscale x 16 x i1> %c470}471 472;473; Extract f16 vector that needs widening from one that needs widening.474;475define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_0(<vscale x 12 x half> %in) {476; CHECK-LABEL: extract_nxv6f16_nxv12f16_0:477; CHECK: # %bb.0:478; CHECK-NEXT: ret479 %res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 0)480 ret <vscale x 6 x half> %res481}482 483define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_6(<vscale x 12 x half> %in) {484; CHECK-LABEL: extract_nxv6f16_nxv12f16_6:485; CHECK: # %bb.0:486; CHECK-NEXT: csrr a0, vlenb487; CHECK-NEXT: srli a0, a0, 2488; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma489; CHECK-NEXT: vslidedown.vx v13, v10, a0490; CHECK-NEXT: vslidedown.vx v12, v9, a0491; CHECK-NEXT: vslideup.vx v12, v10, a0492; CHECK-NEXT: vmv2r.v v8, v12493; CHECK-NEXT: ret494 %res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 6)495 ret <vscale x 6 x half> %res496}497 498define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv16bf16_0(<vscale x 16 x bfloat> %vec) {499; CHECK-LABEL: extract_nxv2bf16_nxv16bf16_0:500; CHECK: # %bb.0:501; CHECK-NEXT: ret502 %c = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> %vec, i64 0)503 ret <vscale x 2 x bfloat> %c504}505 506define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv16bf16_2(<vscale x 16 x bfloat> %vec) {507; CHECK-LABEL: extract_nxv2bf16_nxv16bf16_2:508; CHECK: # %bb.0:509; CHECK-NEXT: csrr a0, vlenb510; CHECK-NEXT: srli a0, a0, 2511; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma512; CHECK-NEXT: vslidedown.vx v8, v8, a0513; CHECK-NEXT: ret514 %c = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> %vec, i64 2)515 ret <vscale x 2 x bfloat> %c516}517 518define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv16bf16_4(<vscale x 16 x bfloat> %vec) {519; CHECK-LABEL: extract_nxv2bf16_nxv16bf16_4:520; CHECK: # %bb.0:521; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma522; CHECK-NEXT: vmv1r.v v8, v9523; CHECK-NEXT: ret524 %c = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> %vec, i64 4)525 ret <vscale x 2 x bfloat> %c526}527 528define <vscale x 6 x bfloat> @extract_nxv6bf16_nxv12bf16_0(<vscale x 12 x bfloat> %in) {529; CHECK-LABEL: extract_nxv6bf16_nxv12bf16_0:530; CHECK: # %bb.0:531; CHECK-NEXT: ret532 %res = call <vscale x 6 x bfloat> @llvm.vector.extract.nxv6bf16.nxv12bf16(<vscale x 12 x bfloat> %in, i64 0)533 ret <vscale x 6 x bfloat> %res534}535 536define <vscale x 6 x bfloat> @extract_nxv6bf16_nxv12bf16_6(<vscale x 12 x bfloat> %in) {537; CHECK-LABEL: extract_nxv6bf16_nxv12bf16_6:538; CHECK: # %bb.0:539; CHECK-NEXT: csrr a0, vlenb540; CHECK-NEXT: srli a0, a0, 2541; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma542; CHECK-NEXT: vslidedown.vx v13, v10, a0543; CHECK-NEXT: vslidedown.vx v12, v9, a0544; CHECK-NEXT: vslideup.vx v12, v10, a0545; CHECK-NEXT: vmv2r.v v8, v12546; CHECK-NEXT: ret547 %res = call <vscale x 6 x bfloat> @llvm.vector.extract.nxv6bf16.nxv12bf16(<vscale x 12 x bfloat> %in, i64 6)548 ret <vscale x 6 x bfloat> %res549}550 551