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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define i1 @extractelt_nxv1i1(ptr %x, i64 %idx) nounwind {6; CHECK-LABEL: extractelt_nxv1i1:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma9; CHECK-NEXT: vle8.v v8, (a0)10; CHECK-NEXT: vmseq.vi v0, v8, 011; CHECK-NEXT: vmv.v.i v8, 012; CHECK-NEXT: vmerge.vim v8, v8, 1, v013; CHECK-NEXT: vslidedown.vx v8, v8, a114; CHECK-NEXT: vmv.x.s a0, v815; CHECK-NEXT: ret16 %a = load <vscale x 1 x i8>, ptr %x17 %b = icmp eq <vscale x 1 x i8> %a, zeroinitializer18 %c = extractelement <vscale x 1 x i1> %b, i64 %idx19 ret i1 %c20}21 22define i1 @extractelt_nxv2i1(ptr %x, i64 %idx) nounwind {23; CHECK-LABEL: extractelt_nxv2i1:24; CHECK: # %bb.0:25; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, ma26; CHECK-NEXT: vle8.v v8, (a0)27; CHECK-NEXT: vmseq.vi v0, v8, 028; CHECK-NEXT: vmv.v.i v8, 029; CHECK-NEXT: vmerge.vim v8, v8, 1, v030; CHECK-NEXT: vslidedown.vx v8, v8, a131; CHECK-NEXT: vmv.x.s a0, v832; CHECK-NEXT: ret33 %a = load <vscale x 2 x i8>, ptr %x34 %b = icmp eq <vscale x 2 x i8> %a, zeroinitializer35 %c = extractelement <vscale x 2 x i1> %b, i64 %idx36 ret i1 %c37}38 39define i1 @extractelt_nxv4i1(ptr %x, i64 %idx) nounwind {40; CHECK-LABEL: extractelt_nxv4i1:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma43; CHECK-NEXT: vle8.v v8, (a0)44; CHECK-NEXT: vmseq.vi v0, v8, 045; CHECK-NEXT: vmv.v.i v8, 046; CHECK-NEXT: vmerge.vim v8, v8, 1, v047; CHECK-NEXT: vslidedown.vx v8, v8, a148; CHECK-NEXT: vmv.x.s a0, v849; CHECK-NEXT: ret50 %a = load <vscale x 4 x i8>, ptr %x51 %b = icmp eq <vscale x 4 x i8> %a, zeroinitializer52 %c = extractelement <vscale x 4 x i1> %b, i64 %idx53 ret i1 %c54}55 56define i1 @extractelt_nxv8i1(ptr %x, i64 %idx) nounwind {57; CHECK-LABEL: extractelt_nxv8i1:58; CHECK: # %bb.0:59; CHECK-NEXT: vl1r.v v8, (a0)60; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma61; CHECK-NEXT: vmseq.vi v0, v8, 062; CHECK-NEXT: vmv.v.i v8, 063; CHECK-NEXT: vmerge.vim v8, v8, 1, v064; CHECK-NEXT: vslidedown.vx v8, v8, a165; CHECK-NEXT: vmv.x.s a0, v866; CHECK-NEXT: ret67 %a = load <vscale x 8 x i8>, ptr %x68 %b = icmp eq <vscale x 8 x i8> %a, zeroinitializer69 %c = extractelement <vscale x 8 x i1> %b, i64 %idx70 ret i1 %c71}72 73define i1 @extractelt_nxv16i1(ptr %x, i64 %idx) nounwind {74; CHECK-LABEL: extractelt_nxv16i1:75; CHECK: # %bb.0:76; CHECK-NEXT: vl2r.v v8, (a0)77; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma78; CHECK-NEXT: vmseq.vi v0, v8, 079; CHECK-NEXT: vmv.v.i v8, 080; CHECK-NEXT: vmerge.vim v8, v8, 1, v081; CHECK-NEXT: vslidedown.vx v8, v8, a182; CHECK-NEXT: vmv.x.s a0, v883; CHECK-NEXT: ret84 %a = load <vscale x 16 x i8>, ptr %x85 %b = icmp eq <vscale x 16 x i8> %a, zeroinitializer86 %c = extractelement <vscale x 16 x i1> %b, i64 %idx87 ret i1 %c88}89 90define i1 @extractelt_nxv32i1(ptr %x, i64 %idx) nounwind {91; CHECK-LABEL: extractelt_nxv32i1:92; CHECK: # %bb.0:93; CHECK-NEXT: vl4r.v v8, (a0)94; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma95; CHECK-NEXT: vmseq.vi v0, v8, 096; CHECK-NEXT: vmv.v.i v8, 097; CHECK-NEXT: vmerge.vim v8, v8, 1, v098; CHECK-NEXT: vslidedown.vx v8, v8, a199; CHECK-NEXT: vmv.x.s a0, v8100; CHECK-NEXT: ret101 %a = load <vscale x 32 x i8>, ptr %x102 %b = icmp eq <vscale x 32 x i8> %a, zeroinitializer103 %c = extractelement <vscale x 32 x i1> %b, i64 %idx104 ret i1 %c105}106 107define i1 @extractelt_nxv64i1(ptr %x, i64 %idx) nounwind {108; CHECK-LABEL: extractelt_nxv64i1:109; CHECK: # %bb.0:110; CHECK-NEXT: vl8r.v v8, (a0)111; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma112; CHECK-NEXT: vmseq.vi v0, v8, 0113; CHECK-NEXT: vmv.v.i v8, 0114; CHECK-NEXT: vmerge.vim v8, v8, 1, v0115; CHECK-NEXT: vslidedown.vx v8, v8, a1116; CHECK-NEXT: vmv.x.s a0, v8117; CHECK-NEXT: ret118 %a = load <vscale x 64 x i8>, ptr %x119 %b = icmp eq <vscale x 64 x i8> %a, zeroinitializer120 %c = extractelement <vscale x 64 x i1> %b, i64 %idx121 ret i1 %c122}123 124define i1 @extractelt_nxv128i1(ptr %x, i64 %idx) nounwind {125; RV32-LABEL: extractelt_nxv128i1:126; RV32: # %bb.0:127; RV32-NEXT: csrr a2, vlenb128; RV32-NEXT: slli a3, a2, 4129; RV32-NEXT: addi a3, a3, -1130; RV32-NEXT: bltu a1, a3, .LBB7_2131; RV32-NEXT: # %bb.1:132; RV32-NEXT: mv a1, a3133; RV32-NEXT: .LBB7_2:134; RV32-NEXT: addi sp, sp, -80135; RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill136; RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill137; RV32-NEXT: addi s0, sp, 80138; RV32-NEXT: csrr a3, vlenb139; RV32-NEXT: slli a3, a3, 4140; RV32-NEXT: sub sp, sp, a3141; RV32-NEXT: andi sp, sp, -64142; RV32-NEXT: vl8r.v v8, (a0)143; RV32-NEXT: slli a2, a2, 3144; RV32-NEXT: add a0, a0, a2145; RV32-NEXT: vl8r.v v16, (a0)146; RV32-NEXT: vsetvli a0, zero, e8, m8, ta, ma147; RV32-NEXT: vmseq.vi v0, v8, 0148; RV32-NEXT: vmv.v.i v8, 0149; RV32-NEXT: vmerge.vim v24, v8, 1, v0150; RV32-NEXT: vmseq.vi v0, v16, 0151; RV32-NEXT: addi a0, sp, 64152; RV32-NEXT: add a1, a0, a1153; RV32-NEXT: add a2, a0, a2154; RV32-NEXT: vs8r.v v24, (a0)155; RV32-NEXT: vmerge.vim v8, v8, 1, v0156; RV32-NEXT: vs8r.v v8, (a2)157; RV32-NEXT: lbu a0, 0(a1)158; RV32-NEXT: addi sp, s0, -80159; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload160; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload161; RV32-NEXT: addi sp, sp, 80162; RV32-NEXT: ret163;164; RV64-LABEL: extractelt_nxv128i1:165; RV64: # %bb.0:166; RV64-NEXT: csrr a2, vlenb167; RV64-NEXT: slli a3, a2, 4168; RV64-NEXT: addi a3, a3, -1169; RV64-NEXT: bltu a1, a3, .LBB7_2170; RV64-NEXT: # %bb.1:171; RV64-NEXT: mv a1, a3172; RV64-NEXT: .LBB7_2:173; RV64-NEXT: addi sp, sp, -80174; RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill175; RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill176; RV64-NEXT: addi s0, sp, 80177; RV64-NEXT: csrr a3, vlenb178; RV64-NEXT: slli a3, a3, 4179; RV64-NEXT: sub sp, sp, a3180; RV64-NEXT: andi sp, sp, -64181; RV64-NEXT: vl8r.v v8, (a0)182; RV64-NEXT: slli a2, a2, 3183; RV64-NEXT: add a0, a0, a2184; RV64-NEXT: vl8r.v v16, (a0)185; RV64-NEXT: vsetvli a0, zero, e8, m8, ta, ma186; RV64-NEXT: vmseq.vi v0, v8, 0187; RV64-NEXT: vmv.v.i v8, 0188; RV64-NEXT: vmerge.vim v24, v8, 1, v0189; RV64-NEXT: vmseq.vi v0, v16, 0190; RV64-NEXT: addi a0, sp, 64191; RV64-NEXT: add a1, a0, a1192; RV64-NEXT: add a2, a0, a2193; RV64-NEXT: vs8r.v v24, (a0)194; RV64-NEXT: vmerge.vim v8, v8, 1, v0195; RV64-NEXT: vs8r.v v8, (a2)196; RV64-NEXT: lbu a0, 0(a1)197; RV64-NEXT: addi sp, s0, -80198; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload199; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload200; RV64-NEXT: addi sp, sp, 80201; RV64-NEXT: ret202 %a = load <vscale x 128 x i8>, ptr %x203 %b = icmp eq <vscale x 128 x i8> %a, zeroinitializer204 %c = extractelement <vscale x 128 x i1> %b, i64 %idx205 ret i1 %c206}207 208define i1 @extractelt_nxv1i1_idx0(ptr %x) nounwind {209; CHECK-LABEL: extractelt_nxv1i1_idx0:210; CHECK: # %bb.0:211; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma212; CHECK-NEXT: vle8.v v8, (a0)213; CHECK-NEXT: vmseq.vi v8, v8, 0214; CHECK-NEXT: vfirst.m a0, v8215; CHECK-NEXT: seqz a0, a0216; CHECK-NEXT: ret217 %a = load <vscale x 1 x i8>, ptr %x218 %b = icmp eq <vscale x 1 x i8> %a, zeroinitializer219 %c = extractelement <vscale x 1 x i1> %b, i64 0220 ret i1 %c221}222 223define i1 @extractelt_nxv2i1_idx0(ptr %x) nounwind {224; CHECK-LABEL: extractelt_nxv2i1_idx0:225; CHECK: # %bb.0:226; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma227; CHECK-NEXT: vle8.v v8, (a0)228; CHECK-NEXT: vmseq.vi v8, v8, 0229; CHECK-NEXT: vfirst.m a0, v8230; CHECK-NEXT: seqz a0, a0231; CHECK-NEXT: ret232 %a = load <vscale x 2 x i8>, ptr %x233 %b = icmp eq <vscale x 2 x i8> %a, zeroinitializer234 %c = extractelement <vscale x 2 x i1> %b, i64 0235 ret i1 %c236}237 238define i1 @extractelt_nxv4i1_idx0(ptr %x) nounwind {239; CHECK-LABEL: extractelt_nxv4i1_idx0:240; CHECK: # %bb.0:241; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma242; CHECK-NEXT: vle8.v v8, (a0)243; CHECK-NEXT: vmseq.vi v8, v8, 0244; CHECK-NEXT: vfirst.m a0, v8245; CHECK-NEXT: seqz a0, a0246; CHECK-NEXT: ret247 %a = load <vscale x 4 x i8>, ptr %x248 %b = icmp eq <vscale x 4 x i8> %a, zeroinitializer249 %c = extractelement <vscale x 4 x i1> %b, i64 0250 ret i1 %c251}252 253define i1 @extractelt_nxv8i1_idx0(ptr %x) nounwind {254; CHECK-LABEL: extractelt_nxv8i1_idx0:255; CHECK: # %bb.0:256; CHECK-NEXT: vl1r.v v8, (a0)257; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma258; CHECK-NEXT: vmseq.vi v8, v8, 0259; CHECK-NEXT: vfirst.m a0, v8260; CHECK-NEXT: seqz a0, a0261; CHECK-NEXT: ret262 %a = load <vscale x 8 x i8>, ptr %x263 %b = icmp eq <vscale x 8 x i8> %a, zeroinitializer264 %c = extractelement <vscale x 8 x i1> %b, i64 0265 ret i1 %c266}267 268define i1 @extractelt_nxv16i1_idx0(ptr %x) nounwind {269; CHECK-LABEL: extractelt_nxv16i1_idx0:270; CHECK: # %bb.0:271; CHECK-NEXT: vl2r.v v8, (a0)272; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma273; CHECK-NEXT: vmseq.vi v10, v8, 0274; CHECK-NEXT: vfirst.m a0, v10275; CHECK-NEXT: seqz a0, a0276; CHECK-NEXT: ret277 %a = load <vscale x 16 x i8>, ptr %x278 %b = icmp eq <vscale x 16 x i8> %a, zeroinitializer279 %c = extractelement <vscale x 16 x i1> %b, i64 0280 ret i1 %c281}282 283define i1 @extractelt_nxv32i1_idx0(ptr %x) nounwind {284; CHECK-LABEL: extractelt_nxv32i1_idx0:285; CHECK: # %bb.0:286; CHECK-NEXT: vl4r.v v8, (a0)287; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma288; CHECK-NEXT: vmseq.vi v12, v8, 0289; CHECK-NEXT: vfirst.m a0, v12290; CHECK-NEXT: seqz a0, a0291; CHECK-NEXT: ret292 %a = load <vscale x 32 x i8>, ptr %x293 %b = icmp eq <vscale x 32 x i8> %a, zeroinitializer294 %c = extractelement <vscale x 32 x i1> %b, i64 0295 ret i1 %c296}297 298define i1 @extractelt_nxv64i1_idx0(ptr %x) nounwind {299; CHECK-LABEL: extractelt_nxv64i1_idx0:300; CHECK: # %bb.0:301; CHECK-NEXT: vl8r.v v8, (a0)302; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma303; CHECK-NEXT: vmseq.vi v16, v8, 0304; CHECK-NEXT: vfirst.m a0, v16305; CHECK-NEXT: seqz a0, a0306; CHECK-NEXT: ret307 %a = load <vscale x 64 x i8>, ptr %x308 %b = icmp eq <vscale x 64 x i8> %a, zeroinitializer309 %c = extractelement <vscale x 64 x i1> %b, i64 0310 ret i1 %c311}312