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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32NOM4; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32M6 7 8define signext i8 @extractelt_nxv1i8_0(<vscale x 1 x i8> %v) {9; CHECK-LABEL: extractelt_nxv1i8_0:10; CHECK: # %bb.0:11; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma12; CHECK-NEXT: vmv.x.s a0, v813; CHECK-NEXT: ret14 %r = extractelement <vscale x 1 x i8> %v, i32 015 ret i8 %r16}17 18define signext i8 @extractelt_nxv1i8_imm(<vscale x 1 x i8> %v) {19; CHECK-LABEL: extractelt_nxv1i8_imm:20; CHECK: # %bb.0:21; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma22; CHECK-NEXT: vslidedown.vi v8, v8, 223; CHECK-NEXT: vmv.x.s a0, v824; CHECK-NEXT: ret25 %r = extractelement <vscale x 1 x i8> %v, i32 226 ret i8 %r27}28 29define signext i8 @extractelt_nxv1i8_idx(<vscale x 1 x i8> %v, i32 %idx) {30; CHECK-LABEL: extractelt_nxv1i8_idx:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma33; CHECK-NEXT: vslidedown.vx v8, v8, a034; CHECK-NEXT: vmv.x.s a0, v835; CHECK-NEXT: ret36 %r = extractelement <vscale x 1 x i8> %v, i32 %idx37 ret i8 %r38}39 40define signext i8 @extractelt_nxv2i8_0(<vscale x 2 x i8> %v) {41; CHECK-LABEL: extractelt_nxv2i8_0:42; CHECK: # %bb.0:43; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma44; CHECK-NEXT: vmv.x.s a0, v845; CHECK-NEXT: ret46 %r = extractelement <vscale x 2 x i8> %v, i32 047 ret i8 %r48}49 50define signext i8 @extractelt_nxv2i8_imm(<vscale x 2 x i8> %v) {51; CHECK-LABEL: extractelt_nxv2i8_imm:52; CHECK: # %bb.0:53; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma54; CHECK-NEXT: vslidedown.vi v8, v8, 255; CHECK-NEXT: vmv.x.s a0, v856; CHECK-NEXT: ret57 %r = extractelement <vscale x 2 x i8> %v, i32 258 ret i8 %r59}60 61define signext i8 @extractelt_nxv2i8_idx(<vscale x 2 x i8> %v, i32 %idx) {62; CHECK-LABEL: extractelt_nxv2i8_idx:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma65; CHECK-NEXT: vslidedown.vx v8, v8, a066; CHECK-NEXT: vmv.x.s a0, v867; CHECK-NEXT: ret68 %r = extractelement <vscale x 2 x i8> %v, i32 %idx69 ret i8 %r70}71 72define signext i8 @extractelt_nxv4i8_0(<vscale x 4 x i8> %v) {73; CHECK-LABEL: extractelt_nxv4i8_0:74; CHECK: # %bb.0:75; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma76; CHECK-NEXT: vmv.x.s a0, v877; CHECK-NEXT: ret78 %r = extractelement <vscale x 4 x i8> %v, i32 079 ret i8 %r80}81 82define signext i8 @extractelt_nxv4i8_imm(<vscale x 4 x i8> %v) {83; CHECK-LABEL: extractelt_nxv4i8_imm:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma86; CHECK-NEXT: vslidedown.vi v8, v8, 287; CHECK-NEXT: vmv.x.s a0, v888; CHECK-NEXT: ret89 %r = extractelement <vscale x 4 x i8> %v, i32 290 ret i8 %r91}92 93define signext i8 @extractelt_nxv4i8_idx(<vscale x 4 x i8> %v, i32 %idx) {94; CHECK-LABEL: extractelt_nxv4i8_idx:95; CHECK: # %bb.0:96; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma97; CHECK-NEXT: vslidedown.vx v8, v8, a098; CHECK-NEXT: vmv.x.s a0, v899; CHECK-NEXT: ret100 %r = extractelement <vscale x 4 x i8> %v, i32 %idx101 ret i8 %r102}103 104define signext i8 @extractelt_nxv8i8_0(<vscale x 8 x i8> %v) {105; CHECK-LABEL: extractelt_nxv8i8_0:106; CHECK: # %bb.0:107; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma108; CHECK-NEXT: vmv.x.s a0, v8109; CHECK-NEXT: ret110 %r = extractelement <vscale x 8 x i8> %v, i32 0111 ret i8 %r112}113 114define signext i8 @extractelt_nxv8i8_imm(<vscale x 8 x i8> %v) {115; CHECK-LABEL: extractelt_nxv8i8_imm:116; CHECK: # %bb.0:117; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma118; CHECK-NEXT: vslidedown.vi v8, v8, 2119; CHECK-NEXT: vmv.x.s a0, v8120; CHECK-NEXT: ret121 %r = extractelement <vscale x 8 x i8> %v, i32 2122 ret i8 %r123}124 125define signext i8 @extractelt_nxv8i8_idx(<vscale x 8 x i8> %v, i32 %idx) {126; CHECK-LABEL: extractelt_nxv8i8_idx:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma129; CHECK-NEXT: vslidedown.vx v8, v8, a0130; CHECK-NEXT: vmv.x.s a0, v8131; CHECK-NEXT: ret132 %r = extractelement <vscale x 8 x i8> %v, i32 %idx133 ret i8 %r134}135 136define signext i8 @extractelt_nxv16i8_0(<vscale x 16 x i8> %v) {137; CHECK-LABEL: extractelt_nxv16i8_0:138; CHECK: # %bb.0:139; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma140; CHECK-NEXT: vmv.x.s a0, v8141; CHECK-NEXT: ret142 %r = extractelement <vscale x 16 x i8> %v, i32 0143 ret i8 %r144}145 146define signext i8 @extractelt_nxv16i8_imm(<vscale x 16 x i8> %v) {147; CHECK-LABEL: extractelt_nxv16i8_imm:148; CHECK: # %bb.0:149; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma150; CHECK-NEXT: vslidedown.vi v8, v8, 2151; CHECK-NEXT: vmv.x.s a0, v8152; CHECK-NEXT: ret153 %r = extractelement <vscale x 16 x i8> %v, i32 2154 ret i8 %r155}156 157define signext i8 @extractelt_nxv16i8_idx(<vscale x 16 x i8> %v, i32 %idx) {158; CHECK-LABEL: extractelt_nxv16i8_idx:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, ma161; CHECK-NEXT: vslidedown.vx v8, v8, a0162; CHECK-NEXT: vmv.x.s a0, v8163; CHECK-NEXT: ret164 %r = extractelement <vscale x 16 x i8> %v, i32 %idx165 ret i8 %r166}167 168define signext i8 @extractelt_nxv32i8_0(<vscale x 32 x i8> %v) {169; CHECK-LABEL: extractelt_nxv32i8_0:170; CHECK: # %bb.0:171; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma172; CHECK-NEXT: vmv.x.s a0, v8173; CHECK-NEXT: ret174 %r = extractelement <vscale x 32 x i8> %v, i32 0175 ret i8 %r176}177 178define signext i8 @extractelt_nxv32i8_imm(<vscale x 32 x i8> %v) {179; CHECK-LABEL: extractelt_nxv32i8_imm:180; CHECK: # %bb.0:181; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma182; CHECK-NEXT: vslidedown.vi v8, v8, 2183; CHECK-NEXT: vmv.x.s a0, v8184; CHECK-NEXT: ret185 %r = extractelement <vscale x 32 x i8> %v, i32 2186 ret i8 %r187}188 189define signext i8 @extractelt_nxv32i8_idx(<vscale x 32 x i8> %v, i32 %idx) {190; CHECK-LABEL: extractelt_nxv32i8_idx:191; CHECK: # %bb.0:192; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, ma193; CHECK-NEXT: vslidedown.vx v8, v8, a0194; CHECK-NEXT: vmv.x.s a0, v8195; CHECK-NEXT: ret196 %r = extractelement <vscale x 32 x i8> %v, i32 %idx197 ret i8 %r198}199 200define signext i8 @extractelt_nxv64i8_0(<vscale x 64 x i8> %v) {201; CHECK-LABEL: extractelt_nxv64i8_0:202; CHECK: # %bb.0:203; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma204; CHECK-NEXT: vmv.x.s a0, v8205; CHECK-NEXT: ret206 %r = extractelement <vscale x 64 x i8> %v, i32 0207 ret i8 %r208}209 210define signext i8 @extractelt_nxv64i8_imm(<vscale x 64 x i8> %v) {211; CHECK-LABEL: extractelt_nxv64i8_imm:212; CHECK: # %bb.0:213; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma214; CHECK-NEXT: vslidedown.vi v8, v8, 2215; CHECK-NEXT: vmv.x.s a0, v8216; CHECK-NEXT: ret217 %r = extractelement <vscale x 64 x i8> %v, i32 2218 ret i8 %r219}220 221define signext i8 @extractelt_nxv64i8_idx(<vscale x 64 x i8> %v, i32 %idx) {222; CHECK-LABEL: extractelt_nxv64i8_idx:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma225; CHECK-NEXT: vslidedown.vx v8, v8, a0226; CHECK-NEXT: vmv.x.s a0, v8227; CHECK-NEXT: ret228 %r = extractelement <vscale x 64 x i8> %v, i32 %idx229 ret i8 %r230}231 232define signext i16 @extractelt_nxv1i16_0(<vscale x 1 x i16> %v) {233; CHECK-LABEL: extractelt_nxv1i16_0:234; CHECK: # %bb.0:235; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma236; CHECK-NEXT: vmv.x.s a0, v8237; CHECK-NEXT: ret238 %r = extractelement <vscale x 1 x i16> %v, i32 0239 ret i16 %r240}241 242define signext i16 @extractelt_nxv1i16_imm(<vscale x 1 x i16> %v) {243; CHECK-LABEL: extractelt_nxv1i16_imm:244; CHECK: # %bb.0:245; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma246; CHECK-NEXT: vslidedown.vi v8, v8, 2247; CHECK-NEXT: vmv.x.s a0, v8248; CHECK-NEXT: ret249 %r = extractelement <vscale x 1 x i16> %v, i32 2250 ret i16 %r251}252 253define signext i16 @extractelt_nxv1i16_idx(<vscale x 1 x i16> %v, i32 %idx) {254; CHECK-LABEL: extractelt_nxv1i16_idx:255; CHECK: # %bb.0:256; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma257; CHECK-NEXT: vslidedown.vx v8, v8, a0258; CHECK-NEXT: vmv.x.s a0, v8259; CHECK-NEXT: ret260 %r = extractelement <vscale x 1 x i16> %v, i32 %idx261 ret i16 %r262}263 264define signext i16 @extractelt_nxv2i16_0(<vscale x 2 x i16> %v) {265; CHECK-LABEL: extractelt_nxv2i16_0:266; CHECK: # %bb.0:267; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma268; CHECK-NEXT: vmv.x.s a0, v8269; CHECK-NEXT: ret270 %r = extractelement <vscale x 2 x i16> %v, i32 0271 ret i16 %r272}273 274define signext i16 @extractelt_nxv2i16_imm(<vscale x 2 x i16> %v) {275; CHECK-LABEL: extractelt_nxv2i16_imm:276; CHECK: # %bb.0:277; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma278; CHECK-NEXT: vslidedown.vi v8, v8, 2279; CHECK-NEXT: vmv.x.s a0, v8280; CHECK-NEXT: ret281 %r = extractelement <vscale x 2 x i16> %v, i32 2282 ret i16 %r283}284 285define signext i16 @extractelt_nxv2i16_idx(<vscale x 2 x i16> %v, i32 %idx) {286; CHECK-LABEL: extractelt_nxv2i16_idx:287; CHECK: # %bb.0:288; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma289; CHECK-NEXT: vslidedown.vx v8, v8, a0290; CHECK-NEXT: vmv.x.s a0, v8291; CHECK-NEXT: ret292 %r = extractelement <vscale x 2 x i16> %v, i32 %idx293 ret i16 %r294}295 296define signext i16 @extractelt_nxv4i16_0(<vscale x 4 x i16> %v) {297; CHECK-LABEL: extractelt_nxv4i16_0:298; CHECK: # %bb.0:299; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma300; CHECK-NEXT: vmv.x.s a0, v8301; CHECK-NEXT: ret302 %r = extractelement <vscale x 4 x i16> %v, i32 0303 ret i16 %r304}305 306define signext i16 @extractelt_nxv4i16_imm(<vscale x 4 x i16> %v) {307; CHECK-LABEL: extractelt_nxv4i16_imm:308; CHECK: # %bb.0:309; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma310; CHECK-NEXT: vslidedown.vi v8, v8, 2311; CHECK-NEXT: vmv.x.s a0, v8312; CHECK-NEXT: ret313 %r = extractelement <vscale x 4 x i16> %v, i32 2314 ret i16 %r315}316 317define signext i16 @extractelt_nxv4i16_idx(<vscale x 4 x i16> %v, i32 %idx) {318; CHECK-LABEL: extractelt_nxv4i16_idx:319; CHECK: # %bb.0:320; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma321; CHECK-NEXT: vslidedown.vx v8, v8, a0322; CHECK-NEXT: vmv.x.s a0, v8323; CHECK-NEXT: ret324 %r = extractelement <vscale x 4 x i16> %v, i32 %idx325 ret i16 %r326}327 328define signext i16 @extractelt_nxv8i16_0(<vscale x 8 x i16> %v) {329; CHECK-LABEL: extractelt_nxv8i16_0:330; CHECK: # %bb.0:331; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma332; CHECK-NEXT: vmv.x.s a0, v8333; CHECK-NEXT: ret334 %r = extractelement <vscale x 8 x i16> %v, i32 0335 ret i16 %r336}337 338define signext i16 @extractelt_nxv8i16_imm(<vscale x 8 x i16> %v) {339; CHECK-LABEL: extractelt_nxv8i16_imm:340; CHECK: # %bb.0:341; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma342; CHECK-NEXT: vslidedown.vi v8, v8, 2343; CHECK-NEXT: vmv.x.s a0, v8344; CHECK-NEXT: ret345 %r = extractelement <vscale x 8 x i16> %v, i32 2346 ret i16 %r347}348 349define signext i16 @extractelt_nxv8i16_idx(<vscale x 8 x i16> %v, i32 %idx) {350; CHECK-LABEL: extractelt_nxv8i16_idx:351; CHECK: # %bb.0:352; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, ma353; CHECK-NEXT: vslidedown.vx v8, v8, a0354; CHECK-NEXT: vmv.x.s a0, v8355; CHECK-NEXT: ret356 %r = extractelement <vscale x 8 x i16> %v, i32 %idx357 ret i16 %r358}359 360define signext i16 @extractelt_nxv16i16_0(<vscale x 16 x i16> %v) {361; CHECK-LABEL: extractelt_nxv16i16_0:362; CHECK: # %bb.0:363; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma364; CHECK-NEXT: vmv.x.s a0, v8365; CHECK-NEXT: ret366 %r = extractelement <vscale x 16 x i16> %v, i32 0367 ret i16 %r368}369 370define signext i16 @extractelt_nxv16i16_imm(<vscale x 16 x i16> %v) {371; CHECK-LABEL: extractelt_nxv16i16_imm:372; CHECK: # %bb.0:373; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma374; CHECK-NEXT: vslidedown.vi v8, v8, 2375; CHECK-NEXT: vmv.x.s a0, v8376; CHECK-NEXT: ret377 %r = extractelement <vscale x 16 x i16> %v, i32 2378 ret i16 %r379}380 381define signext i16 @extractelt_nxv16i16_idx(<vscale x 16 x i16> %v, i32 %idx) {382; CHECK-LABEL: extractelt_nxv16i16_idx:383; CHECK: # %bb.0:384; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, ma385; CHECK-NEXT: vslidedown.vx v8, v8, a0386; CHECK-NEXT: vmv.x.s a0, v8387; CHECK-NEXT: ret388 %r = extractelement <vscale x 16 x i16> %v, i32 %idx389 ret i16 %r390}391 392define signext i16 @extractelt_nxv32i16_0(<vscale x 32 x i16> %v) {393; CHECK-LABEL: extractelt_nxv32i16_0:394; CHECK: # %bb.0:395; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma396; CHECK-NEXT: vmv.x.s a0, v8397; CHECK-NEXT: ret398 %r = extractelement <vscale x 32 x i16> %v, i32 0399 ret i16 %r400}401 402define signext i16 @extractelt_nxv32i16_imm(<vscale x 32 x i16> %v) {403; CHECK-LABEL: extractelt_nxv32i16_imm:404; CHECK: # %bb.0:405; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma406; CHECK-NEXT: vslidedown.vi v8, v8, 2407; CHECK-NEXT: vmv.x.s a0, v8408; CHECK-NEXT: ret409 %r = extractelement <vscale x 32 x i16> %v, i32 2410 ret i16 %r411}412 413define signext i16 @extractelt_nxv32i16_idx(<vscale x 32 x i16> %v, i32 %idx) {414; CHECK-LABEL: extractelt_nxv32i16_idx:415; CHECK: # %bb.0:416; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, ma417; CHECK-NEXT: vslidedown.vx v8, v8, a0418; CHECK-NEXT: vmv.x.s a0, v8419; CHECK-NEXT: ret420 %r = extractelement <vscale x 32 x i16> %v, i32 %idx421 ret i16 %r422}423 424define i32 @extractelt_nxv1i32_0(<vscale x 1 x i32> %v) {425; CHECK-LABEL: extractelt_nxv1i32_0:426; CHECK: # %bb.0:427; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma428; CHECK-NEXT: vmv.x.s a0, v8429; CHECK-NEXT: ret430 %r = extractelement <vscale x 1 x i32> %v, i32 0431 ret i32 %r432}433 434define i32 @extractelt_nxv1i32_imm(<vscale x 1 x i32> %v) {435; CHECK-LABEL: extractelt_nxv1i32_imm:436; CHECK: # %bb.0:437; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma438; CHECK-NEXT: vslidedown.vi v8, v8, 2439; CHECK-NEXT: vmv.x.s a0, v8440; CHECK-NEXT: ret441 %r = extractelement <vscale x 1 x i32> %v, i32 2442 ret i32 %r443}444 445define i32 @extractelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 %idx) {446; CHECK-LABEL: extractelt_nxv1i32_idx:447; CHECK: # %bb.0:448; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma449; CHECK-NEXT: vslidedown.vx v8, v8, a0450; CHECK-NEXT: vmv.x.s a0, v8451; CHECK-NEXT: ret452 %r = extractelement <vscale x 1 x i32> %v, i32 %idx453 ret i32 %r454}455 456define i32 @extractelt_nxv2i32_0(<vscale x 2 x i32> %v) {457; CHECK-LABEL: extractelt_nxv2i32_0:458; CHECK: # %bb.0:459; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma460; CHECK-NEXT: vmv.x.s a0, v8461; CHECK-NEXT: ret462 %r = extractelement <vscale x 2 x i32> %v, i32 0463 ret i32 %r464}465 466define i32 @extractelt_nxv2i32_imm(<vscale x 2 x i32> %v) {467; CHECK-LABEL: extractelt_nxv2i32_imm:468; CHECK: # %bb.0:469; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma470; CHECK-NEXT: vslidedown.vi v8, v8, 2471; CHECK-NEXT: vmv.x.s a0, v8472; CHECK-NEXT: ret473 %r = extractelement <vscale x 2 x i32> %v, i32 2474 ret i32 %r475}476 477define i32 @extractelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 %idx) {478; CHECK-LABEL: extractelt_nxv2i32_idx:479; CHECK: # %bb.0:480; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma481; CHECK-NEXT: vslidedown.vx v8, v8, a0482; CHECK-NEXT: vmv.x.s a0, v8483; CHECK-NEXT: ret484 %r = extractelement <vscale x 2 x i32> %v, i32 %idx485 ret i32 %r486}487 488define i32 @extractelt_nxv4i32_0(<vscale x 4 x i32> %v) {489; CHECK-LABEL: extractelt_nxv4i32_0:490; CHECK: # %bb.0:491; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma492; CHECK-NEXT: vmv.x.s a0, v8493; CHECK-NEXT: ret494 %r = extractelement <vscale x 4 x i32> %v, i32 0495 ret i32 %r496}497 498define i32 @extractelt_nxv4i32_imm(<vscale x 4 x i32> %v) {499; CHECK-LABEL: extractelt_nxv4i32_imm:500; CHECK: # %bb.0:501; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma502; CHECK-NEXT: vslidedown.vi v8, v8, 2503; CHECK-NEXT: vmv.x.s a0, v8504; CHECK-NEXT: ret505 %r = extractelement <vscale x 4 x i32> %v, i32 2506 ret i32 %r507}508 509define i32 @extractelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 %idx) {510; CHECK-LABEL: extractelt_nxv4i32_idx:511; CHECK: # %bb.0:512; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma513; CHECK-NEXT: vslidedown.vx v8, v8, a0514; CHECK-NEXT: vmv.x.s a0, v8515; CHECK-NEXT: ret516 %r = extractelement <vscale x 4 x i32> %v, i32 %idx517 ret i32 %r518}519 520define i32 @extractelt_nxv8i32_0(<vscale x 8 x i32> %v) {521; CHECK-LABEL: extractelt_nxv8i32_0:522; CHECK: # %bb.0:523; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma524; CHECK-NEXT: vmv.x.s a0, v8525; CHECK-NEXT: ret526 %r = extractelement <vscale x 8 x i32> %v, i32 0527 ret i32 %r528}529 530define i32 @extractelt_nxv8i32_imm(<vscale x 8 x i32> %v) {531; CHECK-LABEL: extractelt_nxv8i32_imm:532; CHECK: # %bb.0:533; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma534; CHECK-NEXT: vslidedown.vi v8, v8, 2535; CHECK-NEXT: vmv.x.s a0, v8536; CHECK-NEXT: ret537 %r = extractelement <vscale x 8 x i32> %v, i32 2538 ret i32 %r539}540 541define i32 @extractelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 %idx) {542; CHECK-LABEL: extractelt_nxv8i32_idx:543; CHECK: # %bb.0:544; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, ma545; CHECK-NEXT: vslidedown.vx v8, v8, a0546; CHECK-NEXT: vmv.x.s a0, v8547; CHECK-NEXT: ret548 %r = extractelement <vscale x 8 x i32> %v, i32 %idx549 ret i32 %r550}551 552define i32 @extractelt_nxv16i32_0(<vscale x 16 x i32> %v) {553; CHECK-LABEL: extractelt_nxv16i32_0:554; CHECK: # %bb.0:555; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma556; CHECK-NEXT: vmv.x.s a0, v8557; CHECK-NEXT: ret558 %r = extractelement <vscale x 16 x i32> %v, i32 0559 ret i32 %r560}561 562define i32 @extractelt_nxv16i32_imm(<vscale x 16 x i32> %v) {563; CHECK-LABEL: extractelt_nxv16i32_imm:564; CHECK: # %bb.0:565; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma566; CHECK-NEXT: vslidedown.vi v8, v8, 2567; CHECK-NEXT: vmv.x.s a0, v8568; CHECK-NEXT: ret569 %r = extractelement <vscale x 16 x i32> %v, i32 2570 ret i32 %r571}572 573define i32 @extractelt_nxv16i32_idx(<vscale x 16 x i32> %v, i32 %idx) {574; CHECK-LABEL: extractelt_nxv16i32_idx:575; CHECK: # %bb.0:576; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, ma577; CHECK-NEXT: vslidedown.vx v8, v8, a0578; CHECK-NEXT: vmv.x.s a0, v8579; CHECK-NEXT: ret580 %r = extractelement <vscale x 16 x i32> %v, i32 %idx581 ret i32 %r582}583 584define i64 @extractelt_nxv1i64_0(<vscale x 1 x i64> %v) {585; CHECK-LABEL: extractelt_nxv1i64_0:586; CHECK: # %bb.0:587; CHECK-NEXT: li a0, 32588; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma589; CHECK-NEXT: vsrl.vx v9, v8, a0590; CHECK-NEXT: vmv.x.s a1, v9591; CHECK-NEXT: vmv.x.s a0, v8592; CHECK-NEXT: ret593 %r = extractelement <vscale x 1 x i64> %v, i32 0594 ret i64 %r595}596 597define i64 @extractelt_nxv1i64_imm(<vscale x 1 x i64> %v) {598; CHECK-LABEL: extractelt_nxv1i64_imm:599; CHECK: # %bb.0:600; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma601; CHECK-NEXT: vslidedown.vi v8, v8, 2602; CHECK-NEXT: li a0, 32603; CHECK-NEXT: vsrl.vx v9, v8, a0604; CHECK-NEXT: vmv.x.s a1, v9605; CHECK-NEXT: vmv.x.s a0, v8606; CHECK-NEXT: ret607 %r = extractelement <vscale x 1 x i64> %v, i32 2608 ret i64 %r609}610 611define i64 @extractelt_nxv1i64_idx(<vscale x 1 x i64> %v, i32 %idx) {612; CHECK-LABEL: extractelt_nxv1i64_idx:613; CHECK: # %bb.0:614; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma615; CHECK-NEXT: vslidedown.vx v8, v8, a0616; CHECK-NEXT: li a1, 32617; CHECK-NEXT: vmv.x.s a0, v8618; CHECK-NEXT: vsrl.vx v8, v8, a1619; CHECK-NEXT: vmv.x.s a1, v8620; CHECK-NEXT: ret621 %r = extractelement <vscale x 1 x i64> %v, i32 %idx622 ret i64 %r623}624 625define i64 @extractelt_nxv2i64_0(<vscale x 2 x i64> %v) {626; CHECK-LABEL: extractelt_nxv2i64_0:627; CHECK: # %bb.0:628; CHECK-NEXT: li a0, 32629; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, ma630; CHECK-NEXT: vsrl.vx v10, v8, a0631; CHECK-NEXT: vmv.x.s a1, v10632; CHECK-NEXT: vmv.x.s a0, v8633; CHECK-NEXT: ret634 %r = extractelement <vscale x 2 x i64> %v, i32 0635 ret i64 %r636}637 638define i64 @extractelt_nxv2i64_imm(<vscale x 2 x i64> %v) {639; CHECK-LABEL: extractelt_nxv2i64_imm:640; CHECK: # %bb.0:641; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, ma642; CHECK-NEXT: vslidedown.vi v8, v8, 2643; CHECK-NEXT: li a0, 32644; CHECK-NEXT: vsrl.vx v10, v8, a0645; CHECK-NEXT: vmv.x.s a1, v10646; CHECK-NEXT: vmv.x.s a0, v8647; CHECK-NEXT: ret648 %r = extractelement <vscale x 2 x i64> %v, i32 2649 ret i64 %r650}651 652define i64 @extractelt_nxv2i64_idx(<vscale x 2 x i64> %v, i32 %idx) {653; CHECK-LABEL: extractelt_nxv2i64_idx:654; CHECK: # %bb.0:655; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, ma656; CHECK-NEXT: vslidedown.vx v8, v8, a0657; CHECK-NEXT: li a1, 32658; CHECK-NEXT: vmv.x.s a0, v8659; CHECK-NEXT: vsrl.vx v8, v8, a1660; CHECK-NEXT: vmv.x.s a1, v8661; CHECK-NEXT: ret662 %r = extractelement <vscale x 2 x i64> %v, i32 %idx663 ret i64 %r664}665 666define i64 @extractelt_nxv4i64_0(<vscale x 4 x i64> %v) {667; CHECK-LABEL: extractelt_nxv4i64_0:668; CHECK: # %bb.0:669; CHECK-NEXT: li a0, 32670; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, ma671; CHECK-NEXT: vsrl.vx v12, v8, a0672; CHECK-NEXT: vmv.x.s a1, v12673; CHECK-NEXT: vmv.x.s a0, v8674; CHECK-NEXT: ret675 %r = extractelement <vscale x 4 x i64> %v, i32 0676 ret i64 %r677}678 679define i64 @extractelt_nxv4i64_imm(<vscale x 4 x i64> %v) {680; CHECK-LABEL: extractelt_nxv4i64_imm:681; CHECK: # %bb.0:682; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, ma683; CHECK-NEXT: vslidedown.vi v8, v8, 2684; CHECK-NEXT: li a0, 32685; CHECK-NEXT: vsrl.vx v12, v8, a0686; CHECK-NEXT: vmv.x.s a1, v12687; CHECK-NEXT: vmv.x.s a0, v8688; CHECK-NEXT: ret689 %r = extractelement <vscale x 4 x i64> %v, i32 2690 ret i64 %r691}692 693define i64 @extractelt_nxv4i64_idx(<vscale x 4 x i64> %v, i32 %idx) {694; CHECK-LABEL: extractelt_nxv4i64_idx:695; CHECK: # %bb.0:696; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, ma697; CHECK-NEXT: vslidedown.vx v8, v8, a0698; CHECK-NEXT: li a1, 32699; CHECK-NEXT: vmv.x.s a0, v8700; CHECK-NEXT: vsrl.vx v8, v8, a1701; CHECK-NEXT: vmv.x.s a1, v8702; CHECK-NEXT: ret703 %r = extractelement <vscale x 4 x i64> %v, i32 %idx704 ret i64 %r705}706 707define i64 @extractelt_nxv8i64_0(<vscale x 8 x i64> %v) {708; CHECK-LABEL: extractelt_nxv8i64_0:709; CHECK: # %bb.0:710; CHECK-NEXT: li a0, 32711; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, ma712; CHECK-NEXT: vsrl.vx v16, v8, a0713; CHECK-NEXT: vmv.x.s a1, v16714; CHECK-NEXT: vmv.x.s a0, v8715; CHECK-NEXT: ret716 %r = extractelement <vscale x 8 x i64> %v, i32 0717 ret i64 %r718}719 720define i64 @extractelt_nxv8i64_imm(<vscale x 8 x i64> %v) {721; CHECK-LABEL: extractelt_nxv8i64_imm:722; CHECK: # %bb.0:723; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, ma724; CHECK-NEXT: vslidedown.vi v8, v8, 2725; CHECK-NEXT: li a0, 32726; CHECK-NEXT: vsrl.vx v16, v8, a0727; CHECK-NEXT: vmv.x.s a1, v16728; CHECK-NEXT: vmv.x.s a0, v8729; CHECK-NEXT: ret730 %r = extractelement <vscale x 8 x i64> %v, i32 2731 ret i64 %r732}733 734define i64 @extractelt_nxv8i64_idx(<vscale x 8 x i64> %v, i32 %idx) {735; CHECK-LABEL: extractelt_nxv8i64_idx:736; CHECK: # %bb.0:737; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, ma738; CHECK-NEXT: vslidedown.vx v8, v8, a0739; CHECK-NEXT: li a1, 32740; CHECK-NEXT: vmv.x.s a0, v8741; CHECK-NEXT: vsrl.vx v8, v8, a1742; CHECK-NEXT: vmv.x.s a1, v8743; CHECK-NEXT: ret744 %r = extractelement <vscale x 8 x i64> %v, i32 %idx745 ret i64 %r746}747 748define i32 @extractelt_add_nxv4i32_splat(<vscale x 4 x i32> %x) {749; CHECK-LABEL: extractelt_add_nxv4i32_splat:750; CHECK: # %bb.0:751; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma752; CHECK-NEXT: vslidedown.vi v8, v8, 2753; CHECK-NEXT: vmv.x.s a0, v8754; CHECK-NEXT: addi a0, a0, 3755; CHECK-NEXT: ret756 %bo = add <vscale x 4 x i32> %x, splat (i32 3)757 %ext = extractelement <vscale x 4 x i32> %bo, i32 2758 ret i32 %ext759}760 761define i32 @extractelt_sub_nxv4i32_splat(<vscale x 4 x i32> %x) {762; CHECK-LABEL: extractelt_sub_nxv4i32_splat:763; CHECK: # %bb.0:764; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma765; CHECK-NEXT: vslidedown.vi v8, v8, 1766; CHECK-NEXT: vmv.x.s a0, v8767; CHECK-NEXT: li a1, 3768; CHECK-NEXT: sub a0, a1, a0769; CHECK-NEXT: ret770 %bo = sub <vscale x 4 x i32> splat (i32 3), %x771 %ext = extractelement <vscale x 4 x i32> %bo, i32 1772 ret i32 %ext773}774 775define i32 @extractelt_mul_nxv4i32_splat(<vscale x 4 x i32> %x) {776; RV32NOM-LABEL: extractelt_mul_nxv4i32_splat:777; RV32NOM: # %bb.0:778; RV32NOM-NEXT: li a0, 3779; RV32NOM-NEXT: vsetvli a1, zero, e32, m2, ta, ma780; RV32NOM-NEXT: vmul.vx v8, v8, a0781; RV32NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma782; RV32NOM-NEXT: vslidedown.vi v8, v8, 3783; RV32NOM-NEXT: vmv.x.s a0, v8784; RV32NOM-NEXT: ret785;786; RV32M-LABEL: extractelt_mul_nxv4i32_splat:787; RV32M: # %bb.0:788; RV32M-NEXT: vsetivli zero, 1, e32, m1, ta, ma789; RV32M-NEXT: vslidedown.vi v8, v8, 3790; RV32M-NEXT: vmv.x.s a0, v8791; RV32M-NEXT: slli a1, a0, 1792; RV32M-NEXT: add a0, a1, a0793; RV32M-NEXT: ret794 %bo = mul <vscale x 4 x i32> %x, splat (i32 3)795 %ext = extractelement <vscale x 4 x i32> %bo, i32 3796 ret i32 %ext797}798 799define i32 @extractelt_sdiv_nxv4i32_splat(<vscale x 4 x i32> %x) {800; RV32NOM-LABEL: extractelt_sdiv_nxv4i32_splat:801; RV32NOM: # %bb.0:802; RV32NOM-NEXT: lui a0, 349525803; RV32NOM-NEXT: addi a0, a0, 1366804; RV32NOM-NEXT: vsetvli a1, zero, e32, m2, ta, ma805; RV32NOM-NEXT: vmulh.vx v8, v8, a0806; RV32NOM-NEXT: vsrl.vi v10, v8, 31807; RV32NOM-NEXT: vadd.vv v8, v8, v10808; RV32NOM-NEXT: vmv.x.s a0, v8809; RV32NOM-NEXT: ret810;811; RV32M-LABEL: extractelt_sdiv_nxv4i32_splat:812; RV32M: # %bb.0:813; RV32M-NEXT: vsetivli zero, 1, e32, m1, ta, ma814; RV32M-NEXT: vmv.x.s a0, v8815; RV32M-NEXT: lui a1, 349525816; RV32M-NEXT: addi a1, a1, 1366817; RV32M-NEXT: mulh a0, a0, a1818; RV32M-NEXT: srli a1, a0, 31819; RV32M-NEXT: add a0, a0, a1820; RV32M-NEXT: ret821 %bo = sdiv <vscale x 4 x i32> %x, splat (i32 3)822 %ext = extractelement <vscale x 4 x i32> %bo, i32 0823 ret i32 %ext824}825 826define i32 @extractelt_udiv_nxv4i32_splat(<vscale x 4 x i32> %x) {827; RV32NOM-LABEL: extractelt_udiv_nxv4i32_splat:828; RV32NOM: # %bb.0:829; RV32NOM-NEXT: lui a0, 349525830; RV32NOM-NEXT: addi a0, a0, 1366831; RV32NOM-NEXT: vsetvli a1, zero, e32, m2, ta, ma832; RV32NOM-NEXT: vmulh.vx v8, v8, a0833; RV32NOM-NEXT: vsrl.vi v10, v8, 31834; RV32NOM-NEXT: vadd.vv v8, v8, v10835; RV32NOM-NEXT: vmv.x.s a0, v8836; RV32NOM-NEXT: ret837;838; RV32M-LABEL: extractelt_udiv_nxv4i32_splat:839; RV32M: # %bb.0:840; RV32M-NEXT: vsetivli zero, 1, e32, m1, ta, ma841; RV32M-NEXT: vmv.x.s a0, v8842; RV32M-NEXT: lui a1, 349525843; RV32M-NEXT: addi a1, a1, 1366844; RV32M-NEXT: mulh a0, a0, a1845; RV32M-NEXT: srli a1, a0, 31846; RV32M-NEXT: add a0, a0, a1847; RV32M-NEXT: ret848 %bo = sdiv <vscale x 4 x i32> %x, splat (i32 3)849 %ext = extractelement <vscale x 4 x i32> %bo, i32 0850 ret i32 %ext851}852 853define i32 @extractelt_nxv32i32_0(<vscale x 32 x i32> %v) {854; CHECK-LABEL: extractelt_nxv32i32_0:855; CHECK: # %bb.0:856; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma857; CHECK-NEXT: vmv.x.s a0, v8858; CHECK-NEXT: ret859 %r = extractelement <vscale x 32 x i32> %v, i32 0860 ret i32 %r861}862 863define i32 @extractelt_nxv32i32_neg1(<vscale x 32 x i32> %v) {864; CHECK-LABEL: extractelt_nxv32i32_neg1:865; CHECK: # %bb.0:866; CHECK-NEXT: addi sp, sp, -80867; CHECK-NEXT: .cfi_def_cfa_offset 80868; CHECK-NEXT: sw ra, 76(sp) # 4-byte Folded Spill869; CHECK-NEXT: sw s0, 72(sp) # 4-byte Folded Spill870; CHECK-NEXT: .cfi_offset ra, -4871; CHECK-NEXT: .cfi_offset s0, -8872; CHECK-NEXT: addi s0, sp, 80873; CHECK-NEXT: .cfi_def_cfa s0, 0874; CHECK-NEXT: csrr a0, vlenb875; CHECK-NEXT: slli a0, a0, 4876; CHECK-NEXT: sub sp, sp, a0877; CHECK-NEXT: andi sp, sp, -64878; CHECK-NEXT: addi a0, sp, 64879; CHECK-NEXT: csrr a1, vlenb880; CHECK-NEXT: vs8r.v v8, (a0)881; CHECK-NEXT: slli a2, a1, 3882; CHECK-NEXT: slli a1, a1, 4883; CHECK-NEXT: add a2, a0, a2884; CHECK-NEXT: vs8r.v v16, (a2)885; CHECK-NEXT: add a0, a1, a0886; CHECK-NEXT: lw a0, -4(a0)887; CHECK-NEXT: addi sp, s0, -80888; CHECK-NEXT: .cfi_def_cfa sp, 80889; CHECK-NEXT: lw ra, 76(sp) # 4-byte Folded Reload890; CHECK-NEXT: lw s0, 72(sp) # 4-byte Folded Reload891; CHECK-NEXT: .cfi_restore ra892; CHECK-NEXT: .cfi_restore s0893; CHECK-NEXT: addi sp, sp, 80894; CHECK-NEXT: .cfi_def_cfa_offset 0895; CHECK-NEXT: ret896 %r = extractelement <vscale x 32 x i32> %v, i32 -1897 ret i32 %r898}899 900define i32 @extractelt_nxv32i32_imm(<vscale x 32 x i32> %v) {901; CHECK-LABEL: extractelt_nxv32i32_imm:902; CHECK: # %bb.0:903; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma904; CHECK-NEXT: vslidedown.vi v8, v8, 2905; CHECK-NEXT: vmv.x.s a0, v8906; CHECK-NEXT: ret907 %r = extractelement <vscale x 32 x i32> %v, i32 2908 ret i32 %r909}910 911define i32 @extractelt_nxv32i32_idx(<vscale x 32 x i32> %v, i32 %idx) {912; CHECK-LABEL: extractelt_nxv32i32_idx:913; CHECK: # %bb.0:914; CHECK-NEXT: csrr a1, vlenb915; CHECK-NEXT: slli a2, a1, 2916; CHECK-NEXT: addi a2, a2, -1917; CHECK-NEXT: bltu a0, a2, .LBB74_2918; CHECK-NEXT: # %bb.1:919; CHECK-NEXT: mv a0, a2920; CHECK-NEXT: .LBB74_2:921; CHECK-NEXT: addi sp, sp, -80922; CHECK-NEXT: .cfi_def_cfa_offset 80923; CHECK-NEXT: sw ra, 76(sp) # 4-byte Folded Spill924; CHECK-NEXT: sw s0, 72(sp) # 4-byte Folded Spill925; CHECK-NEXT: .cfi_offset ra, -4926; CHECK-NEXT: .cfi_offset s0, -8927; CHECK-NEXT: addi s0, sp, 80928; CHECK-NEXT: .cfi_def_cfa s0, 0929; CHECK-NEXT: csrr a2, vlenb930; CHECK-NEXT: slli a2, a2, 4931; CHECK-NEXT: sub sp, sp, a2932; CHECK-NEXT: andi sp, sp, -64933; CHECK-NEXT: slli a0, a0, 2934; CHECK-NEXT: addi a2, sp, 64935; CHECK-NEXT: slli a1, a1, 3936; CHECK-NEXT: add a0, a2, a0937; CHECK-NEXT: vs8r.v v8, (a2)938; CHECK-NEXT: add a1, a2, a1939; CHECK-NEXT: vs8r.v v16, (a1)940; CHECK-NEXT: lw a0, 0(a0)941; CHECK-NEXT: addi sp, s0, -80942; CHECK-NEXT: .cfi_def_cfa sp, 80943; CHECK-NEXT: lw ra, 76(sp) # 4-byte Folded Reload944; CHECK-NEXT: lw s0, 72(sp) # 4-byte Folded Reload945; CHECK-NEXT: .cfi_restore ra946; CHECK-NEXT: .cfi_restore s0947; CHECK-NEXT: addi sp, sp, 80948; CHECK-NEXT: .cfi_def_cfa_offset 0949; CHECK-NEXT: ret950 %r = extractelement <vscale x 32 x i32> %v, i32 %idx951 ret i32 %r952}953 954define i64 @extractelt_nxv16i64_0(<vscale x 16 x i64> %v) {955; CHECK-LABEL: extractelt_nxv16i64_0:956; CHECK: # %bb.0:957; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma958; CHECK-NEXT: vmv.x.s a0, v8959; CHECK-NEXT: vslidedown.vi v8, v8, 1960; CHECK-NEXT: vmv.x.s a1, v8961; CHECK-NEXT: ret962 %r = extractelement <vscale x 16 x i64> %v, i32 0963 ret i64 %r964}965