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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64d \3; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64NOM4; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64M6 7define signext i8 @extractelt_nxv1i8_0(<vscale x 1 x i8> %v) {8; CHECK-LABEL: extractelt_nxv1i8_0:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma11; CHECK-NEXT: vmv.x.s a0, v812; CHECK-NEXT: ret13 %r = extractelement <vscale x 1 x i8> %v, i32 014 ret i8 %r15}16 17define signext i8 @extractelt_nxv1i8_imm(<vscale x 1 x i8> %v) {18; CHECK-LABEL: extractelt_nxv1i8_imm:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma21; CHECK-NEXT: vslidedown.vi v8, v8, 222; CHECK-NEXT: vmv.x.s a0, v823; CHECK-NEXT: ret24 %r = extractelement <vscale x 1 x i8> %v, i32 225 ret i8 %r26}27 28define signext i8 @extractelt_nxv1i8_idx(<vscale x 1 x i8> %v, i32 zeroext %idx) {29; CHECK-LABEL: extractelt_nxv1i8_idx:30; CHECK: # %bb.0:31; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma32; CHECK-NEXT: vslidedown.vx v8, v8, a033; CHECK-NEXT: vmv.x.s a0, v834; CHECK-NEXT: ret35 %r = extractelement <vscale x 1 x i8> %v, i32 %idx36 ret i8 %r37}38 39define signext i8 @extractelt_nxv2i8_0(<vscale x 2 x i8> %v) {40; CHECK-LABEL: extractelt_nxv2i8_0:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma43; CHECK-NEXT: vmv.x.s a0, v844; CHECK-NEXT: ret45 %r = extractelement <vscale x 2 x i8> %v, i32 046 ret i8 %r47}48 49define signext i8 @extractelt_nxv2i8_imm(<vscale x 2 x i8> %v) {50; CHECK-LABEL: extractelt_nxv2i8_imm:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma53; CHECK-NEXT: vslidedown.vi v8, v8, 254; CHECK-NEXT: vmv.x.s a0, v855; CHECK-NEXT: ret56 %r = extractelement <vscale x 2 x i8> %v, i32 257 ret i8 %r58}59 60define signext i8 @extractelt_nxv2i8_idx(<vscale x 2 x i8> %v, i32 zeroext %idx) {61; CHECK-LABEL: extractelt_nxv2i8_idx:62; CHECK: # %bb.0:63; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma64; CHECK-NEXT: vslidedown.vx v8, v8, a065; CHECK-NEXT: vmv.x.s a0, v866; CHECK-NEXT: ret67 %r = extractelement <vscale x 2 x i8> %v, i32 %idx68 ret i8 %r69}70 71define signext i8 @extractelt_nxv4i8_0(<vscale x 4 x i8> %v) {72; CHECK-LABEL: extractelt_nxv4i8_0:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma75; CHECK-NEXT: vmv.x.s a0, v876; CHECK-NEXT: ret77 %r = extractelement <vscale x 4 x i8> %v, i32 078 ret i8 %r79}80 81define signext i8 @extractelt_nxv4i8_imm(<vscale x 4 x i8> %v) {82; CHECK-LABEL: extractelt_nxv4i8_imm:83; CHECK: # %bb.0:84; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma85; CHECK-NEXT: vslidedown.vi v8, v8, 286; CHECK-NEXT: vmv.x.s a0, v887; CHECK-NEXT: ret88 %r = extractelement <vscale x 4 x i8> %v, i32 289 ret i8 %r90}91 92define signext i8 @extractelt_nxv4i8_idx(<vscale x 4 x i8> %v, i32 zeroext %idx) {93; CHECK-LABEL: extractelt_nxv4i8_idx:94; CHECK: # %bb.0:95; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma96; CHECK-NEXT: vslidedown.vx v8, v8, a097; CHECK-NEXT: vmv.x.s a0, v898; CHECK-NEXT: ret99 %r = extractelement <vscale x 4 x i8> %v, i32 %idx100 ret i8 %r101}102 103define signext i8 @extractelt_nxv8i8_0(<vscale x 8 x i8> %v) {104; CHECK-LABEL: extractelt_nxv8i8_0:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma107; CHECK-NEXT: vmv.x.s a0, v8108; CHECK-NEXT: ret109 %r = extractelement <vscale x 8 x i8> %v, i32 0110 ret i8 %r111}112 113define signext i8 @extractelt_nxv8i8_imm(<vscale x 8 x i8> %v) {114; CHECK-LABEL: extractelt_nxv8i8_imm:115; CHECK: # %bb.0:116; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma117; CHECK-NEXT: vslidedown.vi v8, v8, 2118; CHECK-NEXT: vmv.x.s a0, v8119; CHECK-NEXT: ret120 %r = extractelement <vscale x 8 x i8> %v, i32 2121 ret i8 %r122}123 124define signext i8 @extractelt_nxv8i8_idx(<vscale x 8 x i8> %v, i32 zeroext %idx) {125; CHECK-LABEL: extractelt_nxv8i8_idx:126; CHECK: # %bb.0:127; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma128; CHECK-NEXT: vslidedown.vx v8, v8, a0129; CHECK-NEXT: vmv.x.s a0, v8130; CHECK-NEXT: ret131 %r = extractelement <vscale x 8 x i8> %v, i32 %idx132 ret i8 %r133}134 135define signext i8 @extractelt_nxv16i8_0(<vscale x 16 x i8> %v) {136; CHECK-LABEL: extractelt_nxv16i8_0:137; CHECK: # %bb.0:138; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma139; CHECK-NEXT: vmv.x.s a0, v8140; CHECK-NEXT: ret141 %r = extractelement <vscale x 16 x i8> %v, i32 0142 ret i8 %r143}144 145define signext i8 @extractelt_nxv16i8_imm(<vscale x 16 x i8> %v) {146; CHECK-LABEL: extractelt_nxv16i8_imm:147; CHECK: # %bb.0:148; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma149; CHECK-NEXT: vslidedown.vi v8, v8, 2150; CHECK-NEXT: vmv.x.s a0, v8151; CHECK-NEXT: ret152 %r = extractelement <vscale x 16 x i8> %v, i32 2153 ret i8 %r154}155 156define signext i8 @extractelt_nxv16i8_idx(<vscale x 16 x i8> %v, i32 zeroext %idx) {157; CHECK-LABEL: extractelt_nxv16i8_idx:158; CHECK: # %bb.0:159; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, ma160; CHECK-NEXT: vslidedown.vx v8, v8, a0161; CHECK-NEXT: vmv.x.s a0, v8162; CHECK-NEXT: ret163 %r = extractelement <vscale x 16 x i8> %v, i32 %idx164 ret i8 %r165}166 167define signext i8 @extractelt_nxv32i8_0(<vscale x 32 x i8> %v) {168; CHECK-LABEL: extractelt_nxv32i8_0:169; CHECK: # %bb.0:170; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma171; CHECK-NEXT: vmv.x.s a0, v8172; CHECK-NEXT: ret173 %r = extractelement <vscale x 32 x i8> %v, i32 0174 ret i8 %r175}176 177define signext i8 @extractelt_nxv32i8_imm(<vscale x 32 x i8> %v) {178; CHECK-LABEL: extractelt_nxv32i8_imm:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma181; CHECK-NEXT: vslidedown.vi v8, v8, 2182; CHECK-NEXT: vmv.x.s a0, v8183; CHECK-NEXT: ret184 %r = extractelement <vscale x 32 x i8> %v, i32 2185 ret i8 %r186}187 188define signext i8 @extractelt_nxv32i8_idx(<vscale x 32 x i8> %v, i32 zeroext %idx) {189; CHECK-LABEL: extractelt_nxv32i8_idx:190; CHECK: # %bb.0:191; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, ma192; CHECK-NEXT: vslidedown.vx v8, v8, a0193; CHECK-NEXT: vmv.x.s a0, v8194; CHECK-NEXT: ret195 %r = extractelement <vscale x 32 x i8> %v, i32 %idx196 ret i8 %r197}198 199define signext i8 @extractelt_nxv64i8_0(<vscale x 64 x i8> %v) {200; CHECK-LABEL: extractelt_nxv64i8_0:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma203; CHECK-NEXT: vmv.x.s a0, v8204; CHECK-NEXT: ret205 %r = extractelement <vscale x 64 x i8> %v, i32 0206 ret i8 %r207}208 209define signext i8 @extractelt_nxv64i8_imm(<vscale x 64 x i8> %v) {210; CHECK-LABEL: extractelt_nxv64i8_imm:211; CHECK: # %bb.0:212; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma213; CHECK-NEXT: vslidedown.vi v8, v8, 2214; CHECK-NEXT: vmv.x.s a0, v8215; CHECK-NEXT: ret216 %r = extractelement <vscale x 64 x i8> %v, i32 2217 ret i8 %r218}219 220define signext i8 @extractelt_nxv64i8_idx(<vscale x 64 x i8> %v, i32 zeroext %idx) {221; CHECK-LABEL: extractelt_nxv64i8_idx:222; CHECK: # %bb.0:223; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma224; CHECK-NEXT: vslidedown.vx v8, v8, a0225; CHECK-NEXT: vmv.x.s a0, v8226; CHECK-NEXT: ret227 %r = extractelement <vscale x 64 x i8> %v, i32 %idx228 ret i8 %r229}230 231define signext i16 @extractelt_nxv1i16_0(<vscale x 1 x i16> %v) {232; CHECK-LABEL: extractelt_nxv1i16_0:233; CHECK: # %bb.0:234; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma235; CHECK-NEXT: vmv.x.s a0, v8236; CHECK-NEXT: ret237 %r = extractelement <vscale x 1 x i16> %v, i32 0238 ret i16 %r239}240 241define signext i16 @extractelt_nxv1i16_imm(<vscale x 1 x i16> %v) {242; CHECK-LABEL: extractelt_nxv1i16_imm:243; CHECK: # %bb.0:244; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma245; CHECK-NEXT: vslidedown.vi v8, v8, 2246; CHECK-NEXT: vmv.x.s a0, v8247; CHECK-NEXT: ret248 %r = extractelement <vscale x 1 x i16> %v, i32 2249 ret i16 %r250}251 252define signext i16 @extractelt_nxv1i16_idx(<vscale x 1 x i16> %v, i32 zeroext %idx) {253; CHECK-LABEL: extractelt_nxv1i16_idx:254; CHECK: # %bb.0:255; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma256; CHECK-NEXT: vslidedown.vx v8, v8, a0257; CHECK-NEXT: vmv.x.s a0, v8258; CHECK-NEXT: ret259 %r = extractelement <vscale x 1 x i16> %v, i32 %idx260 ret i16 %r261}262 263define signext i16 @extractelt_nxv2i16_0(<vscale x 2 x i16> %v) {264; CHECK-LABEL: extractelt_nxv2i16_0:265; CHECK: # %bb.0:266; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma267; CHECK-NEXT: vmv.x.s a0, v8268; CHECK-NEXT: ret269 %r = extractelement <vscale x 2 x i16> %v, i32 0270 ret i16 %r271}272 273define signext i16 @extractelt_nxv2i16_imm(<vscale x 2 x i16> %v) {274; CHECK-LABEL: extractelt_nxv2i16_imm:275; CHECK: # %bb.0:276; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma277; CHECK-NEXT: vslidedown.vi v8, v8, 2278; CHECK-NEXT: vmv.x.s a0, v8279; CHECK-NEXT: ret280 %r = extractelement <vscale x 2 x i16> %v, i32 2281 ret i16 %r282}283 284define signext i16 @extractelt_nxv2i16_idx(<vscale x 2 x i16> %v, i32 zeroext %idx) {285; CHECK-LABEL: extractelt_nxv2i16_idx:286; CHECK: # %bb.0:287; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma288; CHECK-NEXT: vslidedown.vx v8, v8, a0289; CHECK-NEXT: vmv.x.s a0, v8290; CHECK-NEXT: ret291 %r = extractelement <vscale x 2 x i16> %v, i32 %idx292 ret i16 %r293}294 295define signext i16 @extractelt_nxv4i16_0(<vscale x 4 x i16> %v) {296; CHECK-LABEL: extractelt_nxv4i16_0:297; CHECK: # %bb.0:298; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma299; CHECK-NEXT: vmv.x.s a0, v8300; CHECK-NEXT: ret301 %r = extractelement <vscale x 4 x i16> %v, i32 0302 ret i16 %r303}304 305define signext i16 @extractelt_nxv4i16_imm(<vscale x 4 x i16> %v) {306; CHECK-LABEL: extractelt_nxv4i16_imm:307; CHECK: # %bb.0:308; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma309; CHECK-NEXT: vslidedown.vi v8, v8, 2310; CHECK-NEXT: vmv.x.s a0, v8311; CHECK-NEXT: ret312 %r = extractelement <vscale x 4 x i16> %v, i32 2313 ret i16 %r314}315 316define signext i16 @extractelt_nxv4i16_idx(<vscale x 4 x i16> %v, i32 zeroext %idx) {317; CHECK-LABEL: extractelt_nxv4i16_idx:318; CHECK: # %bb.0:319; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma320; CHECK-NEXT: vslidedown.vx v8, v8, a0321; CHECK-NEXT: vmv.x.s a0, v8322; CHECK-NEXT: ret323 %r = extractelement <vscale x 4 x i16> %v, i32 %idx324 ret i16 %r325}326 327define signext i16 @extractelt_nxv8i16_0(<vscale x 8 x i16> %v) {328; CHECK-LABEL: extractelt_nxv8i16_0:329; CHECK: # %bb.0:330; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma331; CHECK-NEXT: vmv.x.s a0, v8332; CHECK-NEXT: ret333 %r = extractelement <vscale x 8 x i16> %v, i32 0334 ret i16 %r335}336 337define signext i16 @extractelt_nxv8i16_imm(<vscale x 8 x i16> %v) {338; CHECK-LABEL: extractelt_nxv8i16_imm:339; CHECK: # %bb.0:340; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma341; CHECK-NEXT: vslidedown.vi v8, v8, 2342; CHECK-NEXT: vmv.x.s a0, v8343; CHECK-NEXT: ret344 %r = extractelement <vscale x 8 x i16> %v, i32 2345 ret i16 %r346}347 348define signext i16 @extractelt_nxv8i16_idx(<vscale x 8 x i16> %v, i32 zeroext %idx) {349; CHECK-LABEL: extractelt_nxv8i16_idx:350; CHECK: # %bb.0:351; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, ma352; CHECK-NEXT: vslidedown.vx v8, v8, a0353; CHECK-NEXT: vmv.x.s a0, v8354; CHECK-NEXT: ret355 %r = extractelement <vscale x 8 x i16> %v, i32 %idx356 ret i16 %r357}358 359define signext i16 @extractelt_nxv16i16_0(<vscale x 16 x i16> %v) {360; CHECK-LABEL: extractelt_nxv16i16_0:361; CHECK: # %bb.0:362; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma363; CHECK-NEXT: vmv.x.s a0, v8364; CHECK-NEXT: ret365 %r = extractelement <vscale x 16 x i16> %v, i32 0366 ret i16 %r367}368 369define signext i16 @extractelt_nxv16i16_imm(<vscale x 16 x i16> %v) {370; CHECK-LABEL: extractelt_nxv16i16_imm:371; CHECK: # %bb.0:372; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma373; CHECK-NEXT: vslidedown.vi v8, v8, 2374; CHECK-NEXT: vmv.x.s a0, v8375; CHECK-NEXT: ret376 %r = extractelement <vscale x 16 x i16> %v, i32 2377 ret i16 %r378}379 380define signext i16 @extractelt_nxv16i16_idx(<vscale x 16 x i16> %v, i32 zeroext %idx) {381; CHECK-LABEL: extractelt_nxv16i16_idx:382; CHECK: # %bb.0:383; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, ma384; CHECK-NEXT: vslidedown.vx v8, v8, a0385; CHECK-NEXT: vmv.x.s a0, v8386; CHECK-NEXT: ret387 %r = extractelement <vscale x 16 x i16> %v, i32 %idx388 ret i16 %r389}390 391define signext i16 @extractelt_nxv32i16_0(<vscale x 32 x i16> %v) {392; CHECK-LABEL: extractelt_nxv32i16_0:393; CHECK: # %bb.0:394; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma395; CHECK-NEXT: vmv.x.s a0, v8396; CHECK-NEXT: ret397 %r = extractelement <vscale x 32 x i16> %v, i32 0398 ret i16 %r399}400 401define signext i16 @extractelt_nxv32i16_imm(<vscale x 32 x i16> %v) {402; CHECK-LABEL: extractelt_nxv32i16_imm:403; CHECK: # %bb.0:404; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma405; CHECK-NEXT: vslidedown.vi v8, v8, 2406; CHECK-NEXT: vmv.x.s a0, v8407; CHECK-NEXT: ret408 %r = extractelement <vscale x 32 x i16> %v, i32 2409 ret i16 %r410}411 412define signext i16 @extractelt_nxv32i16_idx(<vscale x 32 x i16> %v, i32 zeroext %idx) {413; CHECK-LABEL: extractelt_nxv32i16_idx:414; CHECK: # %bb.0:415; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, ma416; CHECK-NEXT: vslidedown.vx v8, v8, a0417; CHECK-NEXT: vmv.x.s a0, v8418; CHECK-NEXT: ret419 %r = extractelement <vscale x 32 x i16> %v, i32 %idx420 ret i16 %r421}422 423define signext i32 @extractelt_nxv1i32_0(<vscale x 1 x i32> %v) {424; CHECK-LABEL: extractelt_nxv1i32_0:425; CHECK: # %bb.0:426; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma427; CHECK-NEXT: vmv.x.s a0, v8428; CHECK-NEXT: ret429 %r = extractelement <vscale x 1 x i32> %v, i32 0430 ret i32 %r431}432 433define signext i32 @extractelt_nxv1i32_imm(<vscale x 1 x i32> %v) {434; CHECK-LABEL: extractelt_nxv1i32_imm:435; CHECK: # %bb.0:436; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma437; CHECK-NEXT: vslidedown.vi v8, v8, 2438; CHECK-NEXT: vmv.x.s a0, v8439; CHECK-NEXT: ret440 %r = extractelement <vscale x 1 x i32> %v, i32 2441 ret i32 %r442}443 444define signext i32 @extractelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 zeroext %idx) {445; CHECK-LABEL: extractelt_nxv1i32_idx:446; CHECK: # %bb.0:447; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma448; CHECK-NEXT: vslidedown.vx v8, v8, a0449; CHECK-NEXT: vmv.x.s a0, v8450; CHECK-NEXT: ret451 %r = extractelement <vscale x 1 x i32> %v, i32 %idx452 ret i32 %r453}454 455define signext i32 @extractelt_nxv2i32_0(<vscale x 2 x i32> %v) {456; CHECK-LABEL: extractelt_nxv2i32_0:457; CHECK: # %bb.0:458; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma459; CHECK-NEXT: vmv.x.s a0, v8460; CHECK-NEXT: ret461 %r = extractelement <vscale x 2 x i32> %v, i32 0462 ret i32 %r463}464 465define signext i32 @extractelt_nxv2i32_imm(<vscale x 2 x i32> %v) {466; CHECK-LABEL: extractelt_nxv2i32_imm:467; CHECK: # %bb.0:468; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma469; CHECK-NEXT: vslidedown.vi v8, v8, 2470; CHECK-NEXT: vmv.x.s a0, v8471; CHECK-NEXT: ret472 %r = extractelement <vscale x 2 x i32> %v, i32 2473 ret i32 %r474}475 476define signext i32 @extractelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 zeroext %idx) {477; CHECK-LABEL: extractelt_nxv2i32_idx:478; CHECK: # %bb.0:479; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma480; CHECK-NEXT: vslidedown.vx v8, v8, a0481; CHECK-NEXT: vmv.x.s a0, v8482; CHECK-NEXT: ret483 %r = extractelement <vscale x 2 x i32> %v, i32 %idx484 ret i32 %r485}486 487define signext i32 @extractelt_nxv4i32_0(<vscale x 4 x i32> %v) {488; CHECK-LABEL: extractelt_nxv4i32_0:489; CHECK: # %bb.0:490; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma491; CHECK-NEXT: vmv.x.s a0, v8492; CHECK-NEXT: ret493 %r = extractelement <vscale x 4 x i32> %v, i32 0494 ret i32 %r495}496 497define signext i32 @extractelt_nxv4i32_imm(<vscale x 4 x i32> %v) {498; CHECK-LABEL: extractelt_nxv4i32_imm:499; CHECK: # %bb.0:500; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma501; CHECK-NEXT: vslidedown.vi v8, v8, 2502; CHECK-NEXT: vmv.x.s a0, v8503; CHECK-NEXT: ret504 %r = extractelement <vscale x 4 x i32> %v, i32 2505 ret i32 %r506}507 508define signext i32 @extractelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 zeroext %idx) {509; CHECK-LABEL: extractelt_nxv4i32_idx:510; CHECK: # %bb.0:511; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma512; CHECK-NEXT: vslidedown.vx v8, v8, a0513; CHECK-NEXT: vmv.x.s a0, v8514; CHECK-NEXT: ret515 %r = extractelement <vscale x 4 x i32> %v, i32 %idx516 ret i32 %r517}518 519define signext i32 @extractelt_nxv8i32_0(<vscale x 8 x i32> %v) {520; CHECK-LABEL: extractelt_nxv8i32_0:521; CHECK: # %bb.0:522; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma523; CHECK-NEXT: vmv.x.s a0, v8524; CHECK-NEXT: ret525 %r = extractelement <vscale x 8 x i32> %v, i32 0526 ret i32 %r527}528 529define signext i32 @extractelt_nxv8i32_imm(<vscale x 8 x i32> %v) {530; CHECK-LABEL: extractelt_nxv8i32_imm:531; CHECK: # %bb.0:532; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma533; CHECK-NEXT: vslidedown.vi v8, v8, 2534; CHECK-NEXT: vmv.x.s a0, v8535; CHECK-NEXT: ret536 %r = extractelement <vscale x 8 x i32> %v, i32 2537 ret i32 %r538}539 540define signext i32 @extractelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 zeroext %idx) {541; CHECK-LABEL: extractelt_nxv8i32_idx:542; CHECK: # %bb.0:543; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, ma544; CHECK-NEXT: vslidedown.vx v8, v8, a0545; CHECK-NEXT: vmv.x.s a0, v8546; CHECK-NEXT: ret547 %r = extractelement <vscale x 8 x i32> %v, i32 %idx548 ret i32 %r549}550 551define signext i32 @extractelt_nxv16i32_0(<vscale x 16 x i32> %v) {552; CHECK-LABEL: extractelt_nxv16i32_0:553; CHECK: # %bb.0:554; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma555; CHECK-NEXT: vmv.x.s a0, v8556; CHECK-NEXT: ret557 %r = extractelement <vscale x 16 x i32> %v, i32 0558 ret i32 %r559}560 561define signext i32 @extractelt_nxv16i32_imm(<vscale x 16 x i32> %v) {562; CHECK-LABEL: extractelt_nxv16i32_imm:563; CHECK: # %bb.0:564; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma565; CHECK-NEXT: vslidedown.vi v8, v8, 2566; CHECK-NEXT: vmv.x.s a0, v8567; CHECK-NEXT: ret568 %r = extractelement <vscale x 16 x i32> %v, i32 2569 ret i32 %r570}571 572define signext i32 @extractelt_nxv16i32_idx(<vscale x 16 x i32> %v, i32 zeroext %idx) {573; CHECK-LABEL: extractelt_nxv16i32_idx:574; CHECK: # %bb.0:575; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, ma576; CHECK-NEXT: vslidedown.vx v8, v8, a0577; CHECK-NEXT: vmv.x.s a0, v8578; CHECK-NEXT: ret579 %r = extractelement <vscale x 16 x i32> %v, i32 %idx580 ret i32 %r581}582 583define i64 @extractelt_nxv1i64_0(<vscale x 1 x i64> %v) {584; CHECK-LABEL: extractelt_nxv1i64_0:585; CHECK: # %bb.0:586; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma587; CHECK-NEXT: vmv.x.s a0, v8588; CHECK-NEXT: ret589 %r = extractelement <vscale x 1 x i64> %v, i32 0590 ret i64 %r591}592 593define i64 @extractelt_nxv1i64_imm(<vscale x 1 x i64> %v) {594; CHECK-LABEL: extractelt_nxv1i64_imm:595; CHECK: # %bb.0:596; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma597; CHECK-NEXT: vslidedown.vi v8, v8, 2598; CHECK-NEXT: vmv.x.s a0, v8599; CHECK-NEXT: ret600 %r = extractelement <vscale x 1 x i64> %v, i32 2601 ret i64 %r602}603 604define i64 @extractelt_nxv1i64_idx(<vscale x 1 x i64> %v, i32 zeroext %idx) {605; CHECK-LABEL: extractelt_nxv1i64_idx:606; CHECK: # %bb.0:607; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma608; CHECK-NEXT: vslidedown.vx v8, v8, a0609; CHECK-NEXT: vmv.x.s a0, v8610; CHECK-NEXT: ret611 %r = extractelement <vscale x 1 x i64> %v, i32 %idx612 ret i64 %r613}614 615define i64 @extractelt_nxv2i64_0(<vscale x 2 x i64> %v) {616; CHECK-LABEL: extractelt_nxv2i64_0:617; CHECK: # %bb.0:618; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma619; CHECK-NEXT: vmv.x.s a0, v8620; CHECK-NEXT: ret621 %r = extractelement <vscale x 2 x i64> %v, i32 0622 ret i64 %r623}624 625define i64 @extractelt_nxv2i64_imm(<vscale x 2 x i64> %v) {626; CHECK-LABEL: extractelt_nxv2i64_imm:627; CHECK: # %bb.0:628; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, ma629; CHECK-NEXT: vslidedown.vi v8, v8, 2630; CHECK-NEXT: vmv.x.s a0, v8631; CHECK-NEXT: ret632 %r = extractelement <vscale x 2 x i64> %v, i32 2633 ret i64 %r634}635 636define i64 @extractelt_nxv2i64_idx(<vscale x 2 x i64> %v, i32 zeroext %idx) {637; CHECK-LABEL: extractelt_nxv2i64_idx:638; CHECK: # %bb.0:639; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, ma640; CHECK-NEXT: vslidedown.vx v8, v8, a0641; CHECK-NEXT: vmv.x.s a0, v8642; CHECK-NEXT: ret643 %r = extractelement <vscale x 2 x i64> %v, i32 %idx644 ret i64 %r645}646 647define i64 @extractelt_nxv4i64_0(<vscale x 4 x i64> %v) {648; CHECK-LABEL: extractelt_nxv4i64_0:649; CHECK: # %bb.0:650; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma651; CHECK-NEXT: vmv.x.s a0, v8652; CHECK-NEXT: ret653 %r = extractelement <vscale x 4 x i64> %v, i32 0654 ret i64 %r655}656 657define i64 @extractelt_nxv4i64_imm(<vscale x 4 x i64> %v) {658; CHECK-LABEL: extractelt_nxv4i64_imm:659; CHECK: # %bb.0:660; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, ma661; CHECK-NEXT: vslidedown.vi v8, v8, 2662; CHECK-NEXT: vmv.x.s a0, v8663; CHECK-NEXT: ret664 %r = extractelement <vscale x 4 x i64> %v, i32 2665 ret i64 %r666}667 668define i64 @extractelt_nxv4i64_idx(<vscale x 4 x i64> %v, i32 zeroext %idx) {669; CHECK-LABEL: extractelt_nxv4i64_idx:670; CHECK: # %bb.0:671; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, ma672; CHECK-NEXT: vslidedown.vx v8, v8, a0673; CHECK-NEXT: vmv.x.s a0, v8674; CHECK-NEXT: ret675 %r = extractelement <vscale x 4 x i64> %v, i32 %idx676 ret i64 %r677}678 679define i64 @extractelt_nxv8i64_0(<vscale x 8 x i64> %v) {680; CHECK-LABEL: extractelt_nxv8i64_0:681; CHECK: # %bb.0:682; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma683; CHECK-NEXT: vmv.x.s a0, v8684; CHECK-NEXT: ret685 %r = extractelement <vscale x 8 x i64> %v, i32 0686 ret i64 %r687}688 689define i64 @extractelt_nxv8i64_imm(<vscale x 8 x i64> %v) {690; CHECK-LABEL: extractelt_nxv8i64_imm:691; CHECK: # %bb.0:692; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, ma693; CHECK-NEXT: vslidedown.vi v8, v8, 2694; CHECK-NEXT: vmv.x.s a0, v8695; CHECK-NEXT: ret696 %r = extractelement <vscale x 8 x i64> %v, i32 2697 ret i64 %r698}699 700define i64 @extractelt_nxv8i64_2_exact_vlen(<vscale x 8 x i64> %v) vscale_range(2,2) {701; CHECK-LABEL: extractelt_nxv8i64_2_exact_vlen:702; CHECK: # %bb.0:703; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma704; CHECK-NEXT: vmv.x.s a0, v9705; CHECK-NEXT: ret706 %r = extractelement <vscale x 8 x i64> %v, i32 2707 ret i64 %r708}709 710define i64 @extractelt_nxv8i64_15_exact_vlen(<vscale x 8 x i64> %v) vscale_range(2,2) {711; CHECK-LABEL: extractelt_nxv8i64_15_exact_vlen:712; CHECK: # %bb.0:713; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma714; CHECK-NEXT: vslidedown.vi v8, v15, 1715; CHECK-NEXT: vmv.x.s a0, v8716; CHECK-NEXT: ret717 %r = extractelement <vscale x 8 x i64> %v, i32 15718 ret i64 %r719}720 721define i64 @extractelt_nxv8i64_idx(<vscale x 8 x i64> %v, i32 zeroext %idx) {722; CHECK-LABEL: extractelt_nxv8i64_idx:723; CHECK: # %bb.0:724; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, ma725; CHECK-NEXT: vslidedown.vx v8, v8, a0726; CHECK-NEXT: vmv.x.s a0, v8727; CHECK-NEXT: ret728 %r = extractelement <vscale x 8 x i64> %v, i32 %idx729 ret i64 %r730}731 732define i32 @extractelt_add_nxv4i32_splat(<vscale x 4 x i32> %x) {733; CHECK-LABEL: extractelt_add_nxv4i32_splat:734; CHECK: # %bb.0:735; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma736; CHECK-NEXT: vslidedown.vi v8, v8, 2737; CHECK-NEXT: vmv.x.s a0, v8738; CHECK-NEXT: addiw a0, a0, 3739; CHECK-NEXT: ret740 %bo = add <vscale x 4 x i32> %x, splat (i32 3)741 %ext = extractelement <vscale x 4 x i32> %bo, i32 2742 ret i32 %ext743}744 745define i32 @extractelt_sub_nxv4i32_splat(<vscale x 4 x i32> %x) {746; CHECK-LABEL: extractelt_sub_nxv4i32_splat:747; CHECK: # %bb.0:748; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma749; CHECK-NEXT: vslidedown.vi v8, v8, 1750; CHECK-NEXT: vmv.x.s a0, v8751; CHECK-NEXT: li a1, 3752; CHECK-NEXT: subw a0, a1, a0753; CHECK-NEXT: ret754 %bo = sub <vscale x 4 x i32> splat (i32 3), %x755 %ext = extractelement <vscale x 4 x i32> %bo, i32 1756 ret i32 %ext757}758 759define i32 @extractelt_mul_nxv4i32_splat(<vscale x 4 x i32> %x) {760; RV64NOM-LABEL: extractelt_mul_nxv4i32_splat:761; RV64NOM: # %bb.0:762; RV64NOM-NEXT: li a0, 3763; RV64NOM-NEXT: vsetvli a1, zero, e32, m2, ta, ma764; RV64NOM-NEXT: vmul.vx v8, v8, a0765; RV64NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma766; RV64NOM-NEXT: vslidedown.vi v8, v8, 3767; RV64NOM-NEXT: vmv.x.s a0, v8768; RV64NOM-NEXT: ret769;770; RV64M-LABEL: extractelt_mul_nxv4i32_splat:771; RV64M: # %bb.0:772; RV64M-NEXT: vsetivli zero, 1, e32, m1, ta, ma773; RV64M-NEXT: vslidedown.vi v8, v8, 3774; RV64M-NEXT: vmv.x.s a0, v8775; RV64M-NEXT: slli a1, a0, 1776; RV64M-NEXT: addw a0, a1, a0777; RV64M-NEXT: ret778 %bo = mul <vscale x 4 x i32> %x, splat (i32 3)779 %ext = extractelement <vscale x 4 x i32> %bo, i32 3780 ret i32 %ext781}782 783define i32 @extractelt_sdiv_nxv4i32_splat(<vscale x 4 x i32> %x) {784; RV64NOM-LABEL: extractelt_sdiv_nxv4i32_splat:785; RV64NOM: # %bb.0:786; RV64NOM-NEXT: lui a0, 349525787; RV64NOM-NEXT: addi a0, a0, 1366788; RV64NOM-NEXT: vsetvli a1, zero, e32, m2, ta, ma789; RV64NOM-NEXT: vmulh.vx v8, v8, a0790; RV64NOM-NEXT: vsrl.vi v10, v8, 31791; RV64NOM-NEXT: vadd.vv v8, v8, v10792; RV64NOM-NEXT: vmv.x.s a0, v8793; RV64NOM-NEXT: ret794;795; RV64M-LABEL: extractelt_sdiv_nxv4i32_splat:796; RV64M: # %bb.0:797; RV64M-NEXT: vsetivli zero, 1, e32, m1, ta, ma798; RV64M-NEXT: vmv.x.s a0, v8799; RV64M-NEXT: lui a1, 349525800; RV64M-NEXT: addi a1, a1, 1366801; RV64M-NEXT: mul a0, a0, a1802; RV64M-NEXT: srli a1, a0, 63803; RV64M-NEXT: srli a0, a0, 32804; RV64M-NEXT: addw a0, a0, a1805; RV64M-NEXT: ret806 %bo = sdiv <vscale x 4 x i32> %x, splat (i32 3)807 %ext = extractelement <vscale x 4 x i32> %bo, i32 0808 ret i32 %ext809}810 811define i32 @extractelt_udiv_nxv4i32_splat(<vscale x 4 x i32> %x) {812; RV64NOM-LABEL: extractelt_udiv_nxv4i32_splat:813; RV64NOM: # %bb.0:814; RV64NOM-NEXT: lui a0, 349525815; RV64NOM-NEXT: addi a0, a0, 1366816; RV64NOM-NEXT: vsetvli a1, zero, e32, m2, ta, ma817; RV64NOM-NEXT: vmulh.vx v8, v8, a0818; RV64NOM-NEXT: vsrl.vi v10, v8, 31819; RV64NOM-NEXT: vadd.vv v8, v8, v10820; RV64NOM-NEXT: vmv.x.s a0, v8821; RV64NOM-NEXT: ret822;823; RV64M-LABEL: extractelt_udiv_nxv4i32_splat:824; RV64M: # %bb.0:825; RV64M-NEXT: vsetivli zero, 1, e32, m1, ta, ma826; RV64M-NEXT: vmv.x.s a0, v8827; RV64M-NEXT: lui a1, 349525828; RV64M-NEXT: addi a1, a1, 1366829; RV64M-NEXT: mul a0, a0, a1830; RV64M-NEXT: srli a1, a0, 63831; RV64M-NEXT: srli a0, a0, 32832; RV64M-NEXT: addw a0, a0, a1833; RV64M-NEXT: ret834 %bo = sdiv <vscale x 4 x i32> %x, splat (i32 3)835 %ext = extractelement <vscale x 4 x i32> %bo, i32 0836 ret i32 %ext837}838 839define i64 @extractelt_nxv16i64_0(<vscale x 16 x i64> %v) {840; CHECK-LABEL: extractelt_nxv16i64_0:841; CHECK: # %bb.0:842; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma843; CHECK-NEXT: vmv.x.s a0, v8844; CHECK-NEXT: ret845 %r = extractelement <vscale x 16 x i64> %v, i32 0846 ret i64 %r847}848 849define i64 @extractelt_nxv16i64_neg1(<vscale x 16 x i64> %v) {850; CHECK-LABEL: extractelt_nxv16i64_neg1:851; CHECK: # %bb.0:852; CHECK-NEXT: addi sp, sp, -80853; CHECK-NEXT: .cfi_def_cfa_offset 80854; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill855; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill856; CHECK-NEXT: .cfi_offset ra, -8857; CHECK-NEXT: .cfi_offset s0, -16858; CHECK-NEXT: addi s0, sp, 80859; CHECK-NEXT: .cfi_def_cfa s0, 0860; CHECK-NEXT: csrr a0, vlenb861; CHECK-NEXT: slli a0, a0, 4862; CHECK-NEXT: sub sp, sp, a0863; CHECK-NEXT: andi sp, sp, -64864; CHECK-NEXT: addi a0, sp, 64865; CHECK-NEXT: csrr a2, vlenb866; CHECK-NEXT: li a1, -1867; CHECK-NEXT: vs8r.v v8, (a0)868; CHECK-NEXT: slli a3, a2, 3869; CHECK-NEXT: srli a1, a1, 32870; CHECK-NEXT: slli a2, a2, 1871; CHECK-NEXT: add a3, a0, a3872; CHECK-NEXT: addi a2, a2, -1873; CHECK-NEXT: vs8r.v v16, (a3)874; CHECK-NEXT: bltu a2, a1, .LBB74_2875; CHECK-NEXT: # %bb.1:876; CHECK-NEXT: mv a2, a1877; CHECK-NEXT: .LBB74_2:878; CHECK-NEXT: slli a2, a2, 3879; CHECK-NEXT: add a0, a0, a2880; CHECK-NEXT: ld a0, 0(a0)881; CHECK-NEXT: addi sp, s0, -80882; CHECK-NEXT: .cfi_def_cfa sp, 80883; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload884; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload885; CHECK-NEXT: .cfi_restore ra886; CHECK-NEXT: .cfi_restore s0887; CHECK-NEXT: addi sp, sp, 80888; CHECK-NEXT: .cfi_def_cfa_offset 0889; CHECK-NEXT: ret890 %r = extractelement <vscale x 16 x i64> %v, i32 -1891 ret i64 %r892}893 894define i64 @extractelt_nxv16i64_imm(<vscale x 16 x i64> %v) {895; CHECK-LABEL: extractelt_nxv16i64_imm:896; CHECK: # %bb.0:897; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, ma898; CHECK-NEXT: vslidedown.vi v8, v8, 2899; CHECK-NEXT: vmv.x.s a0, v8900; CHECK-NEXT: ret901 %r = extractelement <vscale x 16 x i64> %v, i32 2902 ret i64 %r903}904 905define i64 @extractelt_nxv16i64_idx(<vscale x 16 x i64> %v, i32 zeroext %idx) {906; CHECK-LABEL: extractelt_nxv16i64_idx:907; CHECK: # %bb.0:908; CHECK-NEXT: csrr a1, vlenb909; CHECK-NEXT: slli a2, a1, 1910; CHECK-NEXT: addi a2, a2, -1911; CHECK-NEXT: bltu a0, a2, .LBB76_2912; CHECK-NEXT: # %bb.1:913; CHECK-NEXT: mv a0, a2914; CHECK-NEXT: .LBB76_2:915; CHECK-NEXT: addi sp, sp, -80916; CHECK-NEXT: .cfi_def_cfa_offset 80917; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill918; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill919; CHECK-NEXT: .cfi_offset ra, -8920; CHECK-NEXT: .cfi_offset s0, -16921; CHECK-NEXT: addi s0, sp, 80922; CHECK-NEXT: .cfi_def_cfa s0, 0923; CHECK-NEXT: csrr a2, vlenb924; CHECK-NEXT: slli a2, a2, 4925; CHECK-NEXT: sub sp, sp, a2926; CHECK-NEXT: andi sp, sp, -64927; CHECK-NEXT: slli a0, a0, 3928; CHECK-NEXT: addi a2, sp, 64929; CHECK-NEXT: slli a1, a1, 3930; CHECK-NEXT: add a0, a2, a0931; CHECK-NEXT: vs8r.v v8, (a2)932; CHECK-NEXT: add a1, a2, a1933; CHECK-NEXT: vs8r.v v16, (a1)934; CHECK-NEXT: ld a0, 0(a0)935; CHECK-NEXT: addi sp, s0, -80936; CHECK-NEXT: .cfi_def_cfa sp, 80937; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload938; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload939; CHECK-NEXT: .cfi_restore ra940; CHECK-NEXT: .cfi_restore s0941; CHECK-NEXT: addi sp, sp, 80942; CHECK-NEXT: .cfi_def_cfa_offset 0943; CHECK-NEXT: ret944 %r = extractelement <vscale x 16 x i64> %v, i32 %idx945 ret i64 %r946}947