418 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV32 %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64 %s6 7define <vscale x 1 x half> @ceil_nxv1f16(<vscale x 1 x half> %x) strictfp {8; CHECK-LABEL: ceil_nxv1f16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu11; CHECK-NEXT: vmfne.vv v0, v8, v812; CHECK-NEXT: li a0, 2513; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t14; CHECK-NEXT: slli a0, a0, 1015; CHECK-NEXT: vfabs.v v9, v816; CHECK-NEXT: fmv.h.x fa5, a017; CHECK-NEXT: vmflt.vf v0, v9, fa518; CHECK-NEXT: fsrmi a0, 319; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma20; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t21; CHECK-NEXT: fsrm a022; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t23; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu24; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t25; CHECK-NEXT: ret26 %a = call <vscale x 1 x half> @llvm.experimental.constrained.ceil.nxv1f16(<vscale x 1 x half> %x, metadata !"fpexcept.strict")27 ret <vscale x 1 x half> %a28}29 30define <vscale x 2 x half> @ceil_nxv2f16(<vscale x 2 x half> %x) strictfp {31; CHECK-LABEL: ceil_nxv2f16:32; CHECK: # %bb.0:33; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu34; CHECK-NEXT: vmfne.vv v0, v8, v835; CHECK-NEXT: li a0, 2536; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t37; CHECK-NEXT: slli a0, a0, 1038; CHECK-NEXT: vfabs.v v9, v839; CHECK-NEXT: fmv.h.x fa5, a040; CHECK-NEXT: vmflt.vf v0, v9, fa541; CHECK-NEXT: fsrmi a0, 342; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma43; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t44; CHECK-NEXT: fsrm a045; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t46; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu47; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t48; CHECK-NEXT: ret49 %a = call <vscale x 2 x half> @llvm.experimental.constrained.ceil.nxv2f16(<vscale x 2 x half> %x, metadata !"fpexcept.strict")50 ret <vscale x 2 x half> %a51}52 53define <vscale x 4 x half> @ceil_nxv4f16(<vscale x 4 x half> %x) strictfp {54; CHECK-LABEL: ceil_nxv4f16:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu57; CHECK-NEXT: vmfne.vv v0, v8, v858; CHECK-NEXT: li a0, 2559; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t60; CHECK-NEXT: slli a0, a0, 1061; CHECK-NEXT: vfabs.v v9, v862; CHECK-NEXT: fmv.h.x fa5, a063; CHECK-NEXT: vmflt.vf v0, v9, fa564; CHECK-NEXT: fsrmi a0, 365; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma66; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t67; CHECK-NEXT: fsrm a068; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t69; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu70; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t71; CHECK-NEXT: ret72 %a = call <vscale x 4 x half> @llvm.experimental.constrained.ceil.nxv4f16(<vscale x 4 x half> %x, metadata !"fpexcept.strict")73 ret <vscale x 4 x half> %a74}75 76define <vscale x 8 x half> @ceil_nxv8f16(<vscale x 8 x half> %x) strictfp {77; CHECK-LABEL: ceil_nxv8f16:78; CHECK: # %bb.0:79; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu80; CHECK-NEXT: vmfne.vv v0, v8, v881; CHECK-NEXT: li a0, 2582; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t83; CHECK-NEXT: slli a0, a0, 1084; CHECK-NEXT: vfabs.v v10, v885; CHECK-NEXT: fmv.h.x fa5, a086; CHECK-NEXT: vmflt.vf v0, v10, fa587; CHECK-NEXT: fsrmi a0, 388; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma89; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t90; CHECK-NEXT: fsrm a091; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t92; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu93; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t94; CHECK-NEXT: ret95 %a = call <vscale x 8 x half> @llvm.experimental.constrained.ceil.nxv8f16(<vscale x 8 x half> %x, metadata !"fpexcept.strict")96 ret <vscale x 8 x half> %a97}98 99define <vscale x 16 x half> @ceil_nxv16f16(<vscale x 16 x half> %x) strictfp {100; CHECK-LABEL: ceil_nxv16f16:101; CHECK: # %bb.0:102; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu103; CHECK-NEXT: vmfne.vv v0, v8, v8104; CHECK-NEXT: li a0, 25105; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t106; CHECK-NEXT: slli a0, a0, 10107; CHECK-NEXT: vfabs.v v12, v8108; CHECK-NEXT: fmv.h.x fa5, a0109; CHECK-NEXT: vmflt.vf v0, v12, fa5110; CHECK-NEXT: fsrmi a0, 3111; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma112; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t113; CHECK-NEXT: fsrm a0114; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t115; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu116; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t117; CHECK-NEXT: ret118 %a = call <vscale x 16 x half> @llvm.experimental.constrained.ceil.nxv16f16(<vscale x 16 x half> %x, metadata !"fpexcept.strict")119 ret <vscale x 16 x half> %a120}121 122define <vscale x 32 x half> @ceil_nxv32f16(<vscale x 32 x half> %x) strictfp {123; CHECK-LABEL: ceil_nxv32f16:124; CHECK: # %bb.0:125; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu126; CHECK-NEXT: vmfne.vv v0, v8, v8127; CHECK-NEXT: li a0, 25128; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t129; CHECK-NEXT: slli a0, a0, 10130; CHECK-NEXT: vfabs.v v16, v8131; CHECK-NEXT: fmv.h.x fa5, a0132; CHECK-NEXT: vmflt.vf v0, v16, fa5133; CHECK-NEXT: fsrmi a0, 3134; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma135; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t136; CHECK-NEXT: fsrm a0137; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t138; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, mu139; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t140; CHECK-NEXT: ret141 %a = call <vscale x 32 x half> @llvm.experimental.constrained.ceil.nxv32f16(<vscale x 32 x half> %x, metadata !"fpexcept.strict")142 ret <vscale x 32 x half> %a143}144 145define <vscale x 1 x float> @ceil_nxv1f32(<vscale x 1 x float> %x) strictfp {146; CHECK-LABEL: ceil_nxv1f32:147; CHECK: # %bb.0:148; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu149; CHECK-NEXT: vmfne.vv v0, v8, v8150; CHECK-NEXT: lui a0, 307200151; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t152; CHECK-NEXT: fmv.w.x fa5, a0153; CHECK-NEXT: vfabs.v v9, v8154; CHECK-NEXT: vmflt.vf v0, v9, fa5155; CHECK-NEXT: fsrmi a0, 3156; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma157; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t158; CHECK-NEXT: fsrm a0159; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t160; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu161; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t162; CHECK-NEXT: ret163 %a = call <vscale x 1 x float> @llvm.experimental.constrained.ceil.nxv1f32(<vscale x 1 x float> %x, metadata !"fpexcept.strict")164 ret <vscale x 1 x float> %a165}166 167define <vscale x 2 x float> @ceil_nxv2f32(<vscale x 2 x float> %x) strictfp {168; CHECK-LABEL: ceil_nxv2f32:169; CHECK: # %bb.0:170; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu171; CHECK-NEXT: vmfne.vv v0, v8, v8172; CHECK-NEXT: lui a0, 307200173; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t174; CHECK-NEXT: fmv.w.x fa5, a0175; CHECK-NEXT: vfabs.v v9, v8176; CHECK-NEXT: vmflt.vf v0, v9, fa5177; CHECK-NEXT: fsrmi a0, 3178; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma179; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t180; CHECK-NEXT: fsrm a0181; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t182; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu183; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t184; CHECK-NEXT: ret185 %a = call <vscale x 2 x float> @llvm.experimental.constrained.ceil.nxv2f32(<vscale x 2 x float> %x, metadata !"fpexcept.strict")186 ret <vscale x 2 x float> %a187}188 189define <vscale x 4 x float> @ceil_nxv4f32(<vscale x 4 x float> %x) strictfp {190; CHECK-LABEL: ceil_nxv4f32:191; CHECK: # %bb.0:192; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu193; CHECK-NEXT: vmfne.vv v0, v8, v8194; CHECK-NEXT: lui a0, 307200195; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t196; CHECK-NEXT: fmv.w.x fa5, a0197; CHECK-NEXT: vfabs.v v10, v8198; CHECK-NEXT: vmflt.vf v0, v10, fa5199; CHECK-NEXT: fsrmi a0, 3200; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma201; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t202; CHECK-NEXT: fsrm a0203; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t204; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu205; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t206; CHECK-NEXT: ret207 %a = call <vscale x 4 x float> @llvm.experimental.constrained.ceil.nxv4f32(<vscale x 4 x float> %x, metadata !"fpexcept.strict")208 ret <vscale x 4 x float> %a209}210 211define <vscale x 8 x float> @ceil_nxv8f32(<vscale x 8 x float> %x) strictfp {212; CHECK-LABEL: ceil_nxv8f32:213; CHECK: # %bb.0:214; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu215; CHECK-NEXT: vmfne.vv v0, v8, v8216; CHECK-NEXT: lui a0, 307200217; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t218; CHECK-NEXT: fmv.w.x fa5, a0219; CHECK-NEXT: vfabs.v v12, v8220; CHECK-NEXT: vmflt.vf v0, v12, fa5221; CHECK-NEXT: fsrmi a0, 3222; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma223; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t224; CHECK-NEXT: fsrm a0225; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t226; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu227; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t228; CHECK-NEXT: ret229 %a = call <vscale x 8 x float> @llvm.experimental.constrained.ceil.nxv8f32(<vscale x 8 x float> %x, metadata !"fpexcept.strict")230 ret <vscale x 8 x float> %a231}232 233define <vscale x 16 x float> @ceil_nxv16f32(<vscale x 16 x float> %x) strictfp {234; CHECK-LABEL: ceil_nxv16f32:235; CHECK: # %bb.0:236; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu237; CHECK-NEXT: vmfne.vv v0, v8, v8238; CHECK-NEXT: lui a0, 307200239; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t240; CHECK-NEXT: fmv.w.x fa5, a0241; CHECK-NEXT: vfabs.v v16, v8242; CHECK-NEXT: vmflt.vf v0, v16, fa5243; CHECK-NEXT: fsrmi a0, 3244; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma245; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t246; CHECK-NEXT: fsrm a0247; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t248; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu249; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t250; CHECK-NEXT: ret251 %a = call <vscale x 16 x float> @llvm.experimental.constrained.ceil.nxv16f32(<vscale x 16 x float> %x, metadata !"fpexcept.strict")252 ret <vscale x 16 x float> %a253}254 255define <vscale x 1 x double> @ceil_nxv1f64(<vscale x 1 x double> %x) strictfp {256; RV32-LABEL: ceil_nxv1f64:257; RV32: # %bb.0:258; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu259; RV32-NEXT: vmfne.vv v0, v8, v8260; RV32-NEXT: lui a0, %hi(.LCPI11_0)261; RV32-NEXT: fld fa5, %lo(.LCPI11_0)(a0)262; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t263; RV32-NEXT: vfabs.v v9, v8264; RV32-NEXT: vmflt.vf v0, v9, fa5265; RV32-NEXT: fsrmi a0, 3266; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma267; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t268; RV32-NEXT: fsrm a0269; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t270; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu271; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t272; RV32-NEXT: ret273;274; RV64-LABEL: ceil_nxv1f64:275; RV64: # %bb.0:276; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu277; RV64-NEXT: vmfne.vv v0, v8, v8278; RV64-NEXT: li a0, 1075279; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t280; RV64-NEXT: slli a0, a0, 52281; RV64-NEXT: vfabs.v v9, v8282; RV64-NEXT: fmv.d.x fa5, a0283; RV64-NEXT: vmflt.vf v0, v9, fa5284; RV64-NEXT: fsrmi a0, 3285; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma286; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t287; RV64-NEXT: fsrm a0288; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t289; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu290; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t291; RV64-NEXT: ret292 %a = call <vscale x 1 x double> @llvm.experimental.constrained.ceil.nxv1f64(<vscale x 1 x double> %x, metadata !"fpexcept.strict")293 ret <vscale x 1 x double> %a294}295 296define <vscale x 2 x double> @ceil_nxv2f64(<vscale x 2 x double> %x) strictfp {297; RV32-LABEL: ceil_nxv2f64:298; RV32: # %bb.0:299; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu300; RV32-NEXT: vmfne.vv v0, v8, v8301; RV32-NEXT: lui a0, %hi(.LCPI12_0)302; RV32-NEXT: fld fa5, %lo(.LCPI12_0)(a0)303; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t304; RV32-NEXT: vfabs.v v10, v8305; RV32-NEXT: vmflt.vf v0, v10, fa5306; RV32-NEXT: fsrmi a0, 3307; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma308; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t309; RV32-NEXT: fsrm a0310; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t311; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu312; RV32-NEXT: vfsgnj.vv v8, v10, v8, v0.t313; RV32-NEXT: ret314;315; RV64-LABEL: ceil_nxv2f64:316; RV64: # %bb.0:317; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu318; RV64-NEXT: vmfne.vv v0, v8, v8319; RV64-NEXT: li a0, 1075320; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t321; RV64-NEXT: slli a0, a0, 52322; RV64-NEXT: vfabs.v v10, v8323; RV64-NEXT: fmv.d.x fa5, a0324; RV64-NEXT: vmflt.vf v0, v10, fa5325; RV64-NEXT: fsrmi a0, 3326; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma327; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t328; RV64-NEXT: fsrm a0329; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t330; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu331; RV64-NEXT: vfsgnj.vv v8, v10, v8, v0.t332; RV64-NEXT: ret333 %a = call <vscale x 2 x double> @llvm.experimental.constrained.ceil.nxv2f64(<vscale x 2 x double> %x, metadata !"fpexcept.strict")334 ret <vscale x 2 x double> %a335}336 337define <vscale x 4 x double> @ceil_nxv4f64(<vscale x 4 x double> %x) strictfp {338; RV32-LABEL: ceil_nxv4f64:339; RV32: # %bb.0:340; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu341; RV32-NEXT: vmfne.vv v0, v8, v8342; RV32-NEXT: lui a0, %hi(.LCPI13_0)343; RV32-NEXT: fld fa5, %lo(.LCPI13_0)(a0)344; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t345; RV32-NEXT: vfabs.v v12, v8346; RV32-NEXT: vmflt.vf v0, v12, fa5347; RV32-NEXT: fsrmi a0, 3348; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma349; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t350; RV32-NEXT: fsrm a0351; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t352; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu353; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t354; RV32-NEXT: ret355;356; RV64-LABEL: ceil_nxv4f64:357; RV64: # %bb.0:358; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, mu359; RV64-NEXT: vmfne.vv v0, v8, v8360; RV64-NEXT: li a0, 1075361; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t362; RV64-NEXT: slli a0, a0, 52363; RV64-NEXT: vfabs.v v12, v8364; RV64-NEXT: fmv.d.x fa5, a0365; RV64-NEXT: vmflt.vf v0, v12, fa5366; RV64-NEXT: fsrmi a0, 3367; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma368; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t369; RV64-NEXT: fsrm a0370; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t371; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu372; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t373; RV64-NEXT: ret374 %a = call <vscale x 4 x double> @llvm.experimental.constrained.ceil.nxv4f64(<vscale x 4 x double> %x, metadata !"fpexcept.strict")375 ret <vscale x 4 x double> %a376}377 378define <vscale x 8 x double> @ceil_nxv8f64(<vscale x 8 x double> %x) strictfp {379; RV32-LABEL: ceil_nxv8f64:380; RV32: # %bb.0:381; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu382; RV32-NEXT: vmfne.vv v0, v8, v8383; RV32-NEXT: lui a0, %hi(.LCPI14_0)384; RV32-NEXT: fld fa5, %lo(.LCPI14_0)(a0)385; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t386; RV32-NEXT: vfabs.v v16, v8387; RV32-NEXT: vmflt.vf v0, v16, fa5388; RV32-NEXT: fsrmi a0, 3389; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma390; RV32-NEXT: vfcvt.x.f.v v16, v8, v0.t391; RV32-NEXT: fsrm a0392; RV32-NEXT: vfcvt.f.x.v v16, v16, v0.t393; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu394; RV32-NEXT: vfsgnj.vv v8, v16, v8, v0.t395; RV32-NEXT: ret396;397; RV64-LABEL: ceil_nxv8f64:398; RV64: # %bb.0:399; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, mu400; RV64-NEXT: vmfne.vv v0, v8, v8401; RV64-NEXT: li a0, 1075402; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t403; RV64-NEXT: slli a0, a0, 52404; RV64-NEXT: vfabs.v v16, v8405; RV64-NEXT: fmv.d.x fa5, a0406; RV64-NEXT: vmflt.vf v0, v16, fa5407; RV64-NEXT: fsrmi a0, 3408; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma409; RV64-NEXT: vfcvt.x.f.v v16, v8, v0.t410; RV64-NEXT: fsrm a0411; RV64-NEXT: vfcvt.f.x.v v16, v16, v0.t412; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu413; RV64-NEXT: vfsgnj.vv v8, v16, v8, v0.t414; RV64-NEXT: ret415 %a = call <vscale x 8 x double> @llvm.experimental.constrained.ceil.nxv8f64(<vscale x 8 x double> %x, metadata !"fpexcept.strict")416 ret <vscale x 8 x double> %a417}418