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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \3; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \4; RUN: --check-prefixes=CHECK,ZVFH,RV32ZFH5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \6; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \7; RUN: --check-prefixes=CHECK,ZVFH,RV64ZFH8; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \9; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \10; RUN: --check-prefixes=CHECK,ZVFHMIN,RV32ZFHMIN11; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \12; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \13; RUN: --check-prefixes=CHECK,ZVFHMIN,RV64ZFHMIN14 15define <vscale x 1 x bfloat> @floor_nxv1bf16(<vscale x 1 x bfloat> %x) {16; CHECK-LABEL: floor_nxv1bf16:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma19; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v820; CHECK-NEXT: lui a0, 30720021; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma22; CHECK-NEXT: vfabs.v v8, v923; CHECK-NEXT: fmv.w.x fa5, a024; CHECK-NEXT: vmflt.vf v0, v8, fa525; CHECK-NEXT: fsrmi a0, 226; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t27; CHECK-NEXT: fsrm a028; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t29; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu30; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t31; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma32; CHECK-NEXT: vfncvtbf16.f.f.w v8, v933; CHECK-NEXT: ret34 %a = call <vscale x 1 x bfloat> @llvm.floor.nxv1bf16(<vscale x 1 x bfloat> %x)35 ret <vscale x 1 x bfloat> %a36}37 38define <vscale x 2 x bfloat> @floor_nxv2bf16(<vscale x 2 x bfloat> %x) {39; CHECK-LABEL: floor_nxv2bf16:40; CHECK: # %bb.0:41; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma42; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v843; CHECK-NEXT: lui a0, 30720044; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma45; CHECK-NEXT: vfabs.v v8, v946; CHECK-NEXT: fmv.w.x fa5, a047; CHECK-NEXT: vmflt.vf v0, v8, fa548; CHECK-NEXT: fsrmi a0, 249; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t50; CHECK-NEXT: fsrm a051; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t52; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu53; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t54; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma55; CHECK-NEXT: vfncvtbf16.f.f.w v8, v956; CHECK-NEXT: ret57 %a = call <vscale x 2 x bfloat> @llvm.floor.nxv2bf16(<vscale x 2 x bfloat> %x)58 ret <vscale x 2 x bfloat> %a59}60 61define <vscale x 4 x bfloat> @floor_nxv4bf16(<vscale x 4 x bfloat> %x) {62; CHECK-LABEL: floor_nxv4bf16:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma65; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v866; CHECK-NEXT: lui a0, 30720067; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma68; CHECK-NEXT: vfabs.v v8, v1069; CHECK-NEXT: fmv.w.x fa5, a070; CHECK-NEXT: vmflt.vf v0, v8, fa571; CHECK-NEXT: fsrmi a0, 272; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t73; CHECK-NEXT: fsrm a074; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t75; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu76; CHECK-NEXT: vfsgnj.vv v10, v8, v10, v0.t77; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma78; CHECK-NEXT: vfncvtbf16.f.f.w v8, v1079; CHECK-NEXT: ret80 %a = call <vscale x 4 x bfloat> @llvm.floor.nxv4bf16(<vscale x 4 x bfloat> %x)81 ret <vscale x 4 x bfloat> %a82}83 84define <vscale x 8 x bfloat> @floor_nxv8bf16(<vscale x 8 x bfloat> %x) {85; CHECK-LABEL: floor_nxv8bf16:86; CHECK: # %bb.0:87; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma88; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v889; CHECK-NEXT: lui a0, 30720090; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma91; CHECK-NEXT: vfabs.v v8, v1292; CHECK-NEXT: fmv.w.x fa5, a093; CHECK-NEXT: vmflt.vf v0, v8, fa594; CHECK-NEXT: fsrmi a0, 295; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t96; CHECK-NEXT: fsrm a097; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t98; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu99; CHECK-NEXT: vfsgnj.vv v12, v8, v12, v0.t100; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma101; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12102; CHECK-NEXT: ret103 %a = call <vscale x 8 x bfloat> @llvm.floor.nxv8bf16(<vscale x 8 x bfloat> %x)104 ret <vscale x 8 x bfloat> %a105}106 107define <vscale x 16 x bfloat> @floor_nxv16bf16(<vscale x 16 x bfloat> %x) {108; CHECK-LABEL: floor_nxv16bf16:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma111; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8112; CHECK-NEXT: lui a0, 307200113; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma114; CHECK-NEXT: vfabs.v v8, v16115; CHECK-NEXT: fmv.w.x fa5, a0116; CHECK-NEXT: vmflt.vf v0, v8, fa5117; CHECK-NEXT: fsrmi a0, 2118; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t119; CHECK-NEXT: fsrm a0120; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t121; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu122; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t123; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma124; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16125; CHECK-NEXT: ret126 %a = call <vscale x 16 x bfloat> @llvm.floor.nxv16bf16(<vscale x 16 x bfloat> %x)127 ret <vscale x 16 x bfloat> %a128}129 130define <vscale x 32 x bfloat> @floor_nxv32bf16(<vscale x 32 x bfloat> %x) {131; CHECK-LABEL: floor_nxv32bf16:132; CHECK: # %bb.0:133; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma134; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8135; CHECK-NEXT: lui a0, 307200136; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma137; CHECK-NEXT: vfabs.v v24, v16138; CHECK-NEXT: fmv.w.x fa5, a0139; CHECK-NEXT: vmflt.vf v0, v24, fa5140; CHECK-NEXT: fsrmi a0, 2141; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t142; CHECK-NEXT: fsrm a0143; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t144; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu145; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t146; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma147; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12148; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma149; CHECK-NEXT: vfabs.v v8, v24150; CHECK-NEXT: vmflt.vf v0, v8, fa5151; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma152; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16153; CHECK-NEXT: fsrmi a0, 2154; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma155; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t156; CHECK-NEXT: fsrm a0157; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t158; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu159; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t160; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma161; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24162; CHECK-NEXT: ret163 %a = call <vscale x 32 x bfloat> @llvm.floor.nxv32bf16(<vscale x 32 x bfloat> %x)164 ret <vscale x 32 x bfloat> %a165}166 167define <vscale x 1 x half> @floor_nxv1f16(<vscale x 1 x half> %x) {168; ZVFH-LABEL: floor_nxv1f16:169; ZVFH: # %bb.0:170; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma171; ZVFH-NEXT: vfabs.v v9, v8172; ZVFH-NEXT: li a0, 25173; ZVFH-NEXT: slli a0, a0, 10174; ZVFH-NEXT: fmv.h.x fa5, a0175; ZVFH-NEXT: vmflt.vf v0, v9, fa5176; ZVFH-NEXT: fsrmi a0, 2177; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t178; ZVFH-NEXT: fsrm a0179; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t180; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu181; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t182; ZVFH-NEXT: ret183;184; ZVFHMIN-LABEL: floor_nxv1f16:185; ZVFHMIN: # %bb.0:186; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma187; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8188; ZVFHMIN-NEXT: lui a0, 307200189; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma190; ZVFHMIN-NEXT: vfabs.v v8, v9191; ZVFHMIN-NEXT: fmv.w.x fa5, a0192; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5193; ZVFHMIN-NEXT: fsrmi a0, 2194; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t195; ZVFHMIN-NEXT: fsrm a0196; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t197; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu198; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t199; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma200; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9201; ZVFHMIN-NEXT: ret202 %a = call <vscale x 1 x half> @llvm.floor.nxv1f16(<vscale x 1 x half> %x)203 ret <vscale x 1 x half> %a204}205 206define <vscale x 2 x half> @floor_nxv2f16(<vscale x 2 x half> %x) {207; ZVFH-LABEL: floor_nxv2f16:208; ZVFH: # %bb.0:209; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma210; ZVFH-NEXT: vfabs.v v9, v8211; ZVFH-NEXT: li a0, 25212; ZVFH-NEXT: slli a0, a0, 10213; ZVFH-NEXT: fmv.h.x fa5, a0214; ZVFH-NEXT: vmflt.vf v0, v9, fa5215; ZVFH-NEXT: fsrmi a0, 2216; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t217; ZVFH-NEXT: fsrm a0218; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t219; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu220; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t221; ZVFH-NEXT: ret222;223; ZVFHMIN-LABEL: floor_nxv2f16:224; ZVFHMIN: # %bb.0:225; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma226; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8227; ZVFHMIN-NEXT: lui a0, 307200228; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma229; ZVFHMIN-NEXT: vfabs.v v8, v9230; ZVFHMIN-NEXT: fmv.w.x fa5, a0231; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5232; ZVFHMIN-NEXT: fsrmi a0, 2233; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t234; ZVFHMIN-NEXT: fsrm a0235; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t236; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu237; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t238; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma239; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9240; ZVFHMIN-NEXT: ret241 %a = call <vscale x 2 x half> @llvm.floor.nxv2f16(<vscale x 2 x half> %x)242 ret <vscale x 2 x half> %a243}244 245define <vscale x 4 x half> @floor_nxv4f16(<vscale x 4 x half> %x) {246; ZVFH-LABEL: floor_nxv4f16:247; ZVFH: # %bb.0:248; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma249; ZVFH-NEXT: vfabs.v v9, v8250; ZVFH-NEXT: li a0, 25251; ZVFH-NEXT: slli a0, a0, 10252; ZVFH-NEXT: fmv.h.x fa5, a0253; ZVFH-NEXT: vmflt.vf v0, v9, fa5254; ZVFH-NEXT: fsrmi a0, 2255; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t256; ZVFH-NEXT: fsrm a0257; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t258; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu259; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t260; ZVFH-NEXT: ret261;262; ZVFHMIN-LABEL: floor_nxv4f16:263; ZVFHMIN: # %bb.0:264; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma265; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8266; ZVFHMIN-NEXT: lui a0, 307200267; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma268; ZVFHMIN-NEXT: vfabs.v v8, v10269; ZVFHMIN-NEXT: fmv.w.x fa5, a0270; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5271; ZVFHMIN-NEXT: fsrmi a0, 2272; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t273; ZVFHMIN-NEXT: fsrm a0274; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t275; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu276; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t277; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma278; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10279; ZVFHMIN-NEXT: ret280 %a = call <vscale x 4 x half> @llvm.floor.nxv4f16(<vscale x 4 x half> %x)281 ret <vscale x 4 x half> %a282}283 284define <vscale x 8 x half> @floor_nxv8f16(<vscale x 8 x half> %x) {285; ZVFH-LABEL: floor_nxv8f16:286; ZVFH: # %bb.0:287; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma288; ZVFH-NEXT: vfabs.v v10, v8289; ZVFH-NEXT: li a0, 25290; ZVFH-NEXT: slli a0, a0, 10291; ZVFH-NEXT: fmv.h.x fa5, a0292; ZVFH-NEXT: vmflt.vf v0, v10, fa5293; ZVFH-NEXT: fsrmi a0, 2294; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t295; ZVFH-NEXT: fsrm a0296; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t297; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu298; ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t299; ZVFH-NEXT: ret300;301; ZVFHMIN-LABEL: floor_nxv8f16:302; ZVFHMIN: # %bb.0:303; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma304; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8305; ZVFHMIN-NEXT: lui a0, 307200306; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma307; ZVFHMIN-NEXT: vfabs.v v8, v12308; ZVFHMIN-NEXT: fmv.w.x fa5, a0309; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5310; ZVFHMIN-NEXT: fsrmi a0, 2311; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t312; ZVFHMIN-NEXT: fsrm a0313; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t314; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu315; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t316; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma317; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12318; ZVFHMIN-NEXT: ret319 %a = call <vscale x 8 x half> @llvm.floor.nxv8f16(<vscale x 8 x half> %x)320 ret <vscale x 8 x half> %a321}322 323define <vscale x 16 x half> @floor_nxv16f16(<vscale x 16 x half> %x) {324; ZVFH-LABEL: floor_nxv16f16:325; ZVFH: # %bb.0:326; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma327; ZVFH-NEXT: vfabs.v v12, v8328; ZVFH-NEXT: li a0, 25329; ZVFH-NEXT: slli a0, a0, 10330; ZVFH-NEXT: fmv.h.x fa5, a0331; ZVFH-NEXT: vmflt.vf v0, v12, fa5332; ZVFH-NEXT: fsrmi a0, 2333; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t334; ZVFH-NEXT: fsrm a0335; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t336; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu337; ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t338; ZVFH-NEXT: ret339;340; ZVFHMIN-LABEL: floor_nxv16f16:341; ZVFHMIN: # %bb.0:342; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma343; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8344; ZVFHMIN-NEXT: lui a0, 307200345; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma346; ZVFHMIN-NEXT: vfabs.v v8, v16347; ZVFHMIN-NEXT: fmv.w.x fa5, a0348; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5349; ZVFHMIN-NEXT: fsrmi a0, 2350; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t351; ZVFHMIN-NEXT: fsrm a0352; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t353; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu354; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t355; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma356; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16357; ZVFHMIN-NEXT: ret358 %a = call <vscale x 16 x half> @llvm.floor.nxv16f16(<vscale x 16 x half> %x)359 ret <vscale x 16 x half> %a360}361 362define <vscale x 32 x half> @floor_nxv32f16(<vscale x 32 x half> %x) {363; ZVFH-LABEL: floor_nxv32f16:364; ZVFH: # %bb.0:365; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma366; ZVFH-NEXT: vfabs.v v16, v8367; ZVFH-NEXT: li a0, 25368; ZVFH-NEXT: slli a0, a0, 10369; ZVFH-NEXT: fmv.h.x fa5, a0370; ZVFH-NEXT: vmflt.vf v0, v16, fa5371; ZVFH-NEXT: fsrmi a0, 2372; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t373; ZVFH-NEXT: fsrm a0374; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t375; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu376; ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t377; ZVFH-NEXT: ret378;379; ZVFHMIN-LABEL: floor_nxv32f16:380; ZVFHMIN: # %bb.0:381; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma382; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8383; ZVFHMIN-NEXT: lui a0, 307200384; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma385; ZVFHMIN-NEXT: vfabs.v v24, v16386; ZVFHMIN-NEXT: fmv.w.x fa5, a0387; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5388; ZVFHMIN-NEXT: fsrmi a0, 2389; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t390; ZVFHMIN-NEXT: fsrm a0391; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t392; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu393; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t394; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma395; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12396; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma397; ZVFHMIN-NEXT: vfabs.v v8, v24398; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5399; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma400; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16401; ZVFHMIN-NEXT: fsrmi a0, 2402; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma403; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t404; ZVFHMIN-NEXT: fsrm a0405; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t406; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu407; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t408; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma409; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24410; ZVFHMIN-NEXT: ret411 %a = call <vscale x 32 x half> @llvm.floor.nxv32f16(<vscale x 32 x half> %x)412 ret <vscale x 32 x half> %a413}414 415define <vscale x 1 x float> @floor_nxv1f32(<vscale x 1 x float> %x) {416; CHECK-LABEL: floor_nxv1f32:417; CHECK: # %bb.0:418; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma419; CHECK-NEXT: vfabs.v v9, v8420; CHECK-NEXT: lui a0, 307200421; CHECK-NEXT: fmv.w.x fa5, a0422; CHECK-NEXT: vmflt.vf v0, v9, fa5423; CHECK-NEXT: fsrmi a0, 2424; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t425; CHECK-NEXT: fsrm a0426; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t427; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu428; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t429; CHECK-NEXT: ret430 %a = call <vscale x 1 x float> @llvm.floor.nxv1f32(<vscale x 1 x float> %x)431 ret <vscale x 1 x float> %a432}433 434define <vscale x 2 x float> @floor_nxv2f32(<vscale x 2 x float> %x) {435; CHECK-LABEL: floor_nxv2f32:436; CHECK: # %bb.0:437; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma438; CHECK-NEXT: vfabs.v v9, v8439; CHECK-NEXT: lui a0, 307200440; CHECK-NEXT: fmv.w.x fa5, a0441; CHECK-NEXT: vmflt.vf v0, v9, fa5442; CHECK-NEXT: fsrmi a0, 2443; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t444; CHECK-NEXT: fsrm a0445; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t446; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu447; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t448; CHECK-NEXT: ret449 %a = call <vscale x 2 x float> @llvm.floor.nxv2f32(<vscale x 2 x float> %x)450 ret <vscale x 2 x float> %a451}452 453define <vscale x 4 x float> @floor_nxv4f32(<vscale x 4 x float> %x) {454; CHECK-LABEL: floor_nxv4f32:455; CHECK: # %bb.0:456; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma457; CHECK-NEXT: vfabs.v v10, v8458; CHECK-NEXT: lui a0, 307200459; CHECK-NEXT: fmv.w.x fa5, a0460; CHECK-NEXT: vmflt.vf v0, v10, fa5461; CHECK-NEXT: fsrmi a0, 2462; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t463; CHECK-NEXT: fsrm a0464; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t465; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu466; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t467; CHECK-NEXT: ret468 %a = call <vscale x 4 x float> @llvm.floor.nxv4f32(<vscale x 4 x float> %x)469 ret <vscale x 4 x float> %a470}471 472define <vscale x 8 x float> @floor_nxv8f32(<vscale x 8 x float> %x) {473; CHECK-LABEL: floor_nxv8f32:474; CHECK: # %bb.0:475; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma476; CHECK-NEXT: vfabs.v v12, v8477; CHECK-NEXT: lui a0, 307200478; CHECK-NEXT: fmv.w.x fa5, a0479; CHECK-NEXT: vmflt.vf v0, v12, fa5480; CHECK-NEXT: fsrmi a0, 2481; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t482; CHECK-NEXT: fsrm a0483; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t484; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu485; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t486; CHECK-NEXT: ret487 %a = call <vscale x 8 x float> @llvm.floor.nxv8f32(<vscale x 8 x float> %x)488 ret <vscale x 8 x float> %a489}490 491define <vscale x 16 x float> @floor_nxv16f32(<vscale x 16 x float> %x) {492; CHECK-LABEL: floor_nxv16f32:493; CHECK: # %bb.0:494; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma495; CHECK-NEXT: vfabs.v v16, v8496; CHECK-NEXT: lui a0, 307200497; CHECK-NEXT: fmv.w.x fa5, a0498; CHECK-NEXT: vmflt.vf v0, v16, fa5499; CHECK-NEXT: fsrmi a0, 2500; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t501; CHECK-NEXT: fsrm a0502; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t503; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu504; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t505; CHECK-NEXT: ret506 %a = call <vscale x 16 x float> @llvm.floor.nxv16f32(<vscale x 16 x float> %x)507 ret <vscale x 16 x float> %a508}509 510define <vscale x 1 x double> @floor_nxv1f64(<vscale x 1 x double> %x) {511; RV32ZFH-LABEL: floor_nxv1f64:512; RV32ZFH: # %bb.0:513; RV32ZFH-NEXT: lui a0, %hi(.LCPI17_0)514; RV32ZFH-NEXT: fld fa5, %lo(.LCPI17_0)(a0)515; RV32ZFH-NEXT: vsetvli a0, zero, e64, m1, ta, ma516; RV32ZFH-NEXT: vfabs.v v9, v8517; RV32ZFH-NEXT: vmflt.vf v0, v9, fa5518; RV32ZFH-NEXT: fsrmi a0, 2519; RV32ZFH-NEXT: vfcvt.x.f.v v9, v8, v0.t520; RV32ZFH-NEXT: fsrm a0521; RV32ZFH-NEXT: vfcvt.f.x.v v9, v9, v0.t522; RV32ZFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu523; RV32ZFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t524; RV32ZFH-NEXT: ret525;526; RV64ZFH-LABEL: floor_nxv1f64:527; RV64ZFH: # %bb.0:528; RV64ZFH-NEXT: vsetvli a0, zero, e64, m1, ta, ma529; RV64ZFH-NEXT: vfabs.v v9, v8530; RV64ZFH-NEXT: li a0, 1075531; RV64ZFH-NEXT: slli a0, a0, 52532; RV64ZFH-NEXT: fmv.d.x fa5, a0533; RV64ZFH-NEXT: vmflt.vf v0, v9, fa5534; RV64ZFH-NEXT: fsrmi a0, 2535; RV64ZFH-NEXT: vfcvt.x.f.v v9, v8, v0.t536; RV64ZFH-NEXT: fsrm a0537; RV64ZFH-NEXT: vfcvt.f.x.v v9, v9, v0.t538; RV64ZFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu539; RV64ZFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t540; RV64ZFH-NEXT: ret541;542; RV32ZFHMIN-LABEL: floor_nxv1f64:543; RV32ZFHMIN: # %bb.0:544; RV32ZFHMIN-NEXT: lui a0, %hi(.LCPI17_0)545; RV32ZFHMIN-NEXT: fld fa5, %lo(.LCPI17_0)(a0)546; RV32ZFHMIN-NEXT: vsetvli a0, zero, e64, m1, ta, ma547; RV32ZFHMIN-NEXT: vfabs.v v9, v8548; RV32ZFHMIN-NEXT: vmflt.vf v0, v9, fa5549; RV32ZFHMIN-NEXT: fsrmi a0, 2550; RV32ZFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t551; RV32ZFHMIN-NEXT: fsrm a0552; RV32ZFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t553; RV32ZFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu554; RV32ZFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t555; RV32ZFHMIN-NEXT: ret556;557; RV64ZFHMIN-LABEL: floor_nxv1f64:558; RV64ZFHMIN: # %bb.0:559; RV64ZFHMIN-NEXT: vsetvli a0, zero, e64, m1, ta, ma560; RV64ZFHMIN-NEXT: vfabs.v v9, v8561; RV64ZFHMIN-NEXT: li a0, 1075562; RV64ZFHMIN-NEXT: slli a0, a0, 52563; RV64ZFHMIN-NEXT: fmv.d.x fa5, a0564; RV64ZFHMIN-NEXT: vmflt.vf v0, v9, fa5565; RV64ZFHMIN-NEXT: fsrmi a0, 2566; RV64ZFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t567; RV64ZFHMIN-NEXT: fsrm a0568; RV64ZFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t569; RV64ZFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu570; RV64ZFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t571; RV64ZFHMIN-NEXT: ret572 %a = call <vscale x 1 x double> @llvm.floor.nxv1f64(<vscale x 1 x double> %x)573 ret <vscale x 1 x double> %a574}575 576define <vscale x 2 x double> @floor_nxv2f64(<vscale x 2 x double> %x) {577; RV32ZFH-LABEL: floor_nxv2f64:578; RV32ZFH: # %bb.0:579; RV32ZFH-NEXT: lui a0, %hi(.LCPI18_0)580; RV32ZFH-NEXT: fld fa5, %lo(.LCPI18_0)(a0)581; RV32ZFH-NEXT: vsetvli a0, zero, e64, m2, ta, ma582; RV32ZFH-NEXT: vfabs.v v10, v8583; RV32ZFH-NEXT: vmflt.vf v0, v10, fa5584; RV32ZFH-NEXT: fsrmi a0, 2585; RV32ZFH-NEXT: vfcvt.x.f.v v10, v8, v0.t586; RV32ZFH-NEXT: fsrm a0587; RV32ZFH-NEXT: vfcvt.f.x.v v10, v10, v0.t588; RV32ZFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu589; RV32ZFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t590; RV32ZFH-NEXT: ret591;592; RV64ZFH-LABEL: floor_nxv2f64:593; RV64ZFH: # %bb.0:594; RV64ZFH-NEXT: vsetvli a0, zero, e64, m2, ta, ma595; RV64ZFH-NEXT: vfabs.v v10, v8596; RV64ZFH-NEXT: li a0, 1075597; RV64ZFH-NEXT: slli a0, a0, 52598; RV64ZFH-NEXT: fmv.d.x fa5, a0599; RV64ZFH-NEXT: vmflt.vf v0, v10, fa5600; RV64ZFH-NEXT: fsrmi a0, 2601; RV64ZFH-NEXT: vfcvt.x.f.v v10, v8, v0.t602; RV64ZFH-NEXT: fsrm a0603; RV64ZFH-NEXT: vfcvt.f.x.v v10, v10, v0.t604; RV64ZFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu605; RV64ZFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t606; RV64ZFH-NEXT: ret607;608; RV32ZFHMIN-LABEL: floor_nxv2f64:609; RV32ZFHMIN: # %bb.0:610; RV32ZFHMIN-NEXT: lui a0, %hi(.LCPI18_0)611; RV32ZFHMIN-NEXT: fld fa5, %lo(.LCPI18_0)(a0)612; RV32ZFHMIN-NEXT: vsetvli a0, zero, e64, m2, ta, ma613; RV32ZFHMIN-NEXT: vfabs.v v10, v8614; RV32ZFHMIN-NEXT: vmflt.vf v0, v10, fa5615; RV32ZFHMIN-NEXT: fsrmi a0, 2616; RV32ZFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t617; RV32ZFHMIN-NEXT: fsrm a0618; RV32ZFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t619; RV32ZFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu620; RV32ZFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t621; RV32ZFHMIN-NEXT: ret622;623; RV64ZFHMIN-LABEL: floor_nxv2f64:624; RV64ZFHMIN: # %bb.0:625; RV64ZFHMIN-NEXT: vsetvli a0, zero, e64, m2, ta, ma626; RV64ZFHMIN-NEXT: vfabs.v v10, v8627; RV64ZFHMIN-NEXT: li a0, 1075628; RV64ZFHMIN-NEXT: slli a0, a0, 52629; RV64ZFHMIN-NEXT: fmv.d.x fa5, a0630; RV64ZFHMIN-NEXT: vmflt.vf v0, v10, fa5631; RV64ZFHMIN-NEXT: fsrmi a0, 2632; RV64ZFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t633; RV64ZFHMIN-NEXT: fsrm a0634; RV64ZFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t635; RV64ZFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu636; RV64ZFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t637; RV64ZFHMIN-NEXT: ret638 %a = call <vscale x 2 x double> @llvm.floor.nxv2f64(<vscale x 2 x double> %x)639 ret <vscale x 2 x double> %a640}641 642define <vscale x 4 x double> @floor_nxv4f64(<vscale x 4 x double> %x) {643; RV32ZFH-LABEL: floor_nxv4f64:644; RV32ZFH: # %bb.0:645; RV32ZFH-NEXT: lui a0, %hi(.LCPI19_0)646; RV32ZFH-NEXT: fld fa5, %lo(.LCPI19_0)(a0)647; RV32ZFH-NEXT: vsetvli a0, zero, e64, m4, ta, ma648; RV32ZFH-NEXT: vfabs.v v12, v8649; RV32ZFH-NEXT: vmflt.vf v0, v12, fa5650; RV32ZFH-NEXT: fsrmi a0, 2651; RV32ZFH-NEXT: vfcvt.x.f.v v12, v8, v0.t652; RV32ZFH-NEXT: fsrm a0653; RV32ZFH-NEXT: vfcvt.f.x.v v12, v12, v0.t654; RV32ZFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu655; RV32ZFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t656; RV32ZFH-NEXT: ret657;658; RV64ZFH-LABEL: floor_nxv4f64:659; RV64ZFH: # %bb.0:660; RV64ZFH-NEXT: vsetvli a0, zero, e64, m4, ta, ma661; RV64ZFH-NEXT: vfabs.v v12, v8662; RV64ZFH-NEXT: li a0, 1075663; RV64ZFH-NEXT: slli a0, a0, 52664; RV64ZFH-NEXT: fmv.d.x fa5, a0665; RV64ZFH-NEXT: vmflt.vf v0, v12, fa5666; RV64ZFH-NEXT: fsrmi a0, 2667; RV64ZFH-NEXT: vfcvt.x.f.v v12, v8, v0.t668; RV64ZFH-NEXT: fsrm a0669; RV64ZFH-NEXT: vfcvt.f.x.v v12, v12, v0.t670; RV64ZFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu671; RV64ZFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t672; RV64ZFH-NEXT: ret673;674; RV32ZFHMIN-LABEL: floor_nxv4f64:675; RV32ZFHMIN: # %bb.0:676; RV32ZFHMIN-NEXT: lui a0, %hi(.LCPI19_0)677; RV32ZFHMIN-NEXT: fld fa5, %lo(.LCPI19_0)(a0)678; RV32ZFHMIN-NEXT: vsetvli a0, zero, e64, m4, ta, ma679; RV32ZFHMIN-NEXT: vfabs.v v12, v8680; RV32ZFHMIN-NEXT: vmflt.vf v0, v12, fa5681; RV32ZFHMIN-NEXT: fsrmi a0, 2682; RV32ZFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t683; RV32ZFHMIN-NEXT: fsrm a0684; RV32ZFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t685; RV32ZFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu686; RV32ZFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t687; RV32ZFHMIN-NEXT: ret688;689; RV64ZFHMIN-LABEL: floor_nxv4f64:690; RV64ZFHMIN: # %bb.0:691; RV64ZFHMIN-NEXT: vsetvli a0, zero, e64, m4, ta, ma692; RV64ZFHMIN-NEXT: vfabs.v v12, v8693; RV64ZFHMIN-NEXT: li a0, 1075694; RV64ZFHMIN-NEXT: slli a0, a0, 52695; RV64ZFHMIN-NEXT: fmv.d.x fa5, a0696; RV64ZFHMIN-NEXT: vmflt.vf v0, v12, fa5697; RV64ZFHMIN-NEXT: fsrmi a0, 2698; RV64ZFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t699; RV64ZFHMIN-NEXT: fsrm a0700; RV64ZFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t701; RV64ZFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu702; RV64ZFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t703; RV64ZFHMIN-NEXT: ret704 %a = call <vscale x 4 x double> @llvm.floor.nxv4f64(<vscale x 4 x double> %x)705 ret <vscale x 4 x double> %a706}707 708define <vscale x 8 x double> @floor_nxv8f64(<vscale x 8 x double> %x) {709; RV32ZFH-LABEL: floor_nxv8f64:710; RV32ZFH: # %bb.0:711; RV32ZFH-NEXT: lui a0, %hi(.LCPI20_0)712; RV32ZFH-NEXT: fld fa5, %lo(.LCPI20_0)(a0)713; RV32ZFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma714; RV32ZFH-NEXT: vfabs.v v16, v8715; RV32ZFH-NEXT: vmflt.vf v0, v16, fa5716; RV32ZFH-NEXT: fsrmi a0, 2717; RV32ZFH-NEXT: vfcvt.x.f.v v16, v8, v0.t718; RV32ZFH-NEXT: fsrm a0719; RV32ZFH-NEXT: vfcvt.f.x.v v16, v16, v0.t720; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu721; RV32ZFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t722; RV32ZFH-NEXT: ret723;724; RV64ZFH-LABEL: floor_nxv8f64:725; RV64ZFH: # %bb.0:726; RV64ZFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma727; RV64ZFH-NEXT: vfabs.v v16, v8728; RV64ZFH-NEXT: li a0, 1075729; RV64ZFH-NEXT: slli a0, a0, 52730; RV64ZFH-NEXT: fmv.d.x fa5, a0731; RV64ZFH-NEXT: vmflt.vf v0, v16, fa5732; RV64ZFH-NEXT: fsrmi a0, 2733; RV64ZFH-NEXT: vfcvt.x.f.v v16, v8, v0.t734; RV64ZFH-NEXT: fsrm a0735; RV64ZFH-NEXT: vfcvt.f.x.v v16, v16, v0.t736; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu737; RV64ZFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t738; RV64ZFH-NEXT: ret739;740; RV32ZFHMIN-LABEL: floor_nxv8f64:741; RV32ZFHMIN: # %bb.0:742; RV32ZFHMIN-NEXT: lui a0, %hi(.LCPI20_0)743; RV32ZFHMIN-NEXT: fld fa5, %lo(.LCPI20_0)(a0)744; RV32ZFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma745; RV32ZFHMIN-NEXT: vfabs.v v16, v8746; RV32ZFHMIN-NEXT: vmflt.vf v0, v16, fa5747; RV32ZFHMIN-NEXT: fsrmi a0, 2748; RV32ZFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t749; RV32ZFHMIN-NEXT: fsrm a0750; RV32ZFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t751; RV32ZFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu752; RV32ZFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t753; RV32ZFHMIN-NEXT: ret754;755; RV64ZFHMIN-LABEL: floor_nxv8f64:756; RV64ZFHMIN: # %bb.0:757; RV64ZFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma758; RV64ZFHMIN-NEXT: vfabs.v v16, v8759; RV64ZFHMIN-NEXT: li a0, 1075760; RV64ZFHMIN-NEXT: slli a0, a0, 52761; RV64ZFHMIN-NEXT: fmv.d.x fa5, a0762; RV64ZFHMIN-NEXT: vmflt.vf v0, v16, fa5763; RV64ZFHMIN-NEXT: fsrmi a0, 2764; RV64ZFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t765; RV64ZFHMIN-NEXT: fsrm a0766; RV64ZFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t767; RV64ZFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu768; RV64ZFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t769; RV64ZFHMIN-NEXT: ret770 %a = call <vscale x 8 x double> @llvm.floor.nxv8f64(<vscale x 8 x double> %x)771 ret <vscale x 8 x double> %a772}773