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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644;5; SABD6;7 8define <8 x i8> @sabd_8b_as_16b(<8 x i8> %a, <8 x i8> %b) {9;10; CHECK-LABEL: sabd_8b_as_16b:11; CHECK: # %bb.0:12; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma13; CHECK-NEXT: vmin.vv v10, v8, v914; CHECK-NEXT: vmax.vv v8, v8, v915; CHECK-NEXT: vsub.vv v8, v8, v1016; CHECK-NEXT: ret17 %a.sext = sext <8 x i8> %a to <8 x i16>18 %b.sext = sext <8 x i8> %b to <8 x i16>19 %sub = sub <8 x i16> %a.sext, %b.sext20 %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)21 %trunc = trunc <8 x i16> %abs to <8 x i8>22 ret <8 x i8> %trunc23}24 25define <8 x i8> @sabd_8b_as_32b(<8 x i8> %a, <8 x i8> %b) {26;27; CHECK-LABEL: sabd_8b_as_32b:28; CHECK: # %bb.0:29; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma30; CHECK-NEXT: vmin.vv v10, v8, v931; CHECK-NEXT: vmax.vv v8, v8, v932; CHECK-NEXT: vsub.vv v8, v8, v1033; CHECK-NEXT: ret34 %a.sext = sext <8 x i8> %a to <8 x i32>35 %b.sext = sext <8 x i8> %b to <8 x i32>36 %sub = sub <8 x i32> %a.sext, %b.sext37 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 true)38 %trunc = trunc <8 x i32> %abs to <8 x i8>39 ret <8 x i8> %trunc40}41 42define <16 x i8> @sabd_16b(<16 x i8> %a, <16 x i8> %b) {43;44; CHECK-LABEL: sabd_16b:45; CHECK: # %bb.0:46; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma47; CHECK-NEXT: vmin.vv v10, v8, v948; CHECK-NEXT: vmax.vv v8, v8, v949; CHECK-NEXT: vsub.vv v8, v8, v1050; CHECK-NEXT: ret51 %a.sext = sext <16 x i8> %a to <16 x i16>52 %b.sext = sext <16 x i8> %b to <16 x i16>53 %sub = sub <16 x i16> %a.sext, %b.sext54 %abs = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %sub, i1 true)55 %trunc = trunc <16 x i16> %abs to <16 x i8>56 ret <16 x i8> %trunc57}58 59define <4 x i16> @sabd_4h(<4 x i16> %a, <4 x i16> %b) {60;61; CHECK-LABEL: sabd_4h:62; CHECK: # %bb.0:63; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma64; CHECK-NEXT: vmin.vv v10, v8, v965; CHECK-NEXT: vmax.vv v8, v8, v966; CHECK-NEXT: vsub.vv v8, v8, v1067; CHECK-NEXT: ret68 %a.sext = sext <4 x i16> %a to <4 x i32>69 %b.sext = sext <4 x i16> %b to <4 x i32>70 %sub = sub <4 x i32> %a.sext, %b.sext71 %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)72 %trunc = trunc <4 x i32> %abs to <4 x i16>73 ret <4 x i16> %trunc74}75 76define <4 x i16> @sabd_4h_promoted_ops(<4 x i8> %a, <4 x i8> %b) {77;78; CHECK-LABEL: sabd_4h_promoted_ops:79; CHECK: # %bb.0:80; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma81; CHECK-NEXT: vmin.vv v10, v8, v982; CHECK-NEXT: vmax.vv v8, v8, v983; CHECK-NEXT: vsub.vv v9, v8, v1084; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma85; CHECK-NEXT: vzext.vf2 v8, v986; CHECK-NEXT: ret87 %a.sext = sext <4 x i8> %a to <4 x i16>88 %b.sext = sext <4 x i8> %b to <4 x i16>89 %sub = sub <4 x i16> %a.sext, %b.sext90 %abs = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %sub, i1 true)91 ret <4 x i16> %abs92}93 94define <8 x i16> @sabd_8h(<8 x i16> %a, <8 x i16> %b) {95;96; CHECK-LABEL: sabd_8h:97; CHECK: # %bb.0:98; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma99; CHECK-NEXT: vmin.vv v10, v8, v9100; CHECK-NEXT: vmax.vv v8, v8, v9101; CHECK-NEXT: vsub.vv v8, v8, v10102; CHECK-NEXT: ret103 %a.sext = sext <8 x i16> %a to <8 x i32>104 %b.sext = sext <8 x i16> %b to <8 x i32>105 %sub = sub <8 x i32> %a.sext, %b.sext106 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 true)107 %trunc = trunc <8 x i32> %abs to <8 x i16>108 ret <8 x i16> %trunc109}110 111define <8 x i16> @sabd_8h_promoted_ops(<8 x i8> %a, <8 x i8> %b) {112;113; CHECK-LABEL: sabd_8h_promoted_ops:114; CHECK: # %bb.0:115; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma116; CHECK-NEXT: vmin.vv v10, v8, v9117; CHECK-NEXT: vmax.vv v8, v8, v9118; CHECK-NEXT: vsub.vv v9, v8, v10119; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma120; CHECK-NEXT: vzext.vf2 v8, v9121; CHECK-NEXT: ret122 %a.sext = sext <8 x i8> %a to <8 x i16>123 %b.sext = sext <8 x i8> %b to <8 x i16>124 %sub = sub <8 x i16> %a.sext, %b.sext125 %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)126 ret <8 x i16> %abs127}128 129define <2 x i32> @sabd_2s(<2 x i32> %a, <2 x i32> %b) {130;131; CHECK-LABEL: sabd_2s:132; CHECK: # %bb.0:133; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma134; CHECK-NEXT: vmin.vv v10, v8, v9135; CHECK-NEXT: vmax.vv v8, v8, v9136; CHECK-NEXT: vsub.vv v8, v8, v10137; CHECK-NEXT: ret138 %a.sext = sext <2 x i32> %a to <2 x i64>139 %b.sext = sext <2 x i32> %b to <2 x i64>140 %sub = sub <2 x i64> %a.sext, %b.sext141 %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)142 %trunc = trunc <2 x i64> %abs to <2 x i32>143 ret <2 x i32> %trunc144}145 146define <2 x i32> @sabd_2s_promoted_ops(<2 x i16> %a, <2 x i16> %b) {147;148; CHECK-LABEL: sabd_2s_promoted_ops:149; CHECK: # %bb.0:150; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma151; CHECK-NEXT: vmin.vv v10, v8, v9152; CHECK-NEXT: vmax.vv v8, v8, v9153; CHECK-NEXT: vsub.vv v9, v8, v10154; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma155; CHECK-NEXT: vzext.vf2 v8, v9156; CHECK-NEXT: ret157 %a.sext = sext <2 x i16> %a to <2 x i32>158 %b.sext = sext <2 x i16> %b to <2 x i32>159 %sub = sub <2 x i32> %a.sext, %b.sext160 %abs = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %sub, i1 true)161 ret <2 x i32> %abs162}163 164define <4 x i32> @sabd_4s(<4 x i32> %a, <4 x i32> %b) {165;166; CHECK-LABEL: sabd_4s:167; CHECK: # %bb.0:168; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma169; CHECK-NEXT: vmin.vv v10, v8, v9170; CHECK-NEXT: vmax.vv v8, v8, v9171; CHECK-NEXT: vsub.vv v8, v8, v10172; CHECK-NEXT: ret173 %a.sext = sext <4 x i32> %a to <4 x i64>174 %b.sext = sext <4 x i32> %b to <4 x i64>175 %sub = sub <4 x i64> %a.sext, %b.sext176 %abs = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %sub, i1 true)177 %trunc = trunc <4 x i64> %abs to <4 x i32>178 ret <4 x i32> %trunc179}180 181define <4 x i32> @sabd_4s_promoted_ops(<4 x i16> %a, <4 x i16> %b) {182;183; CHECK-LABEL: sabd_4s_promoted_ops:184; CHECK: # %bb.0:185; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma186; CHECK-NEXT: vmin.vv v10, v8, v9187; CHECK-NEXT: vmax.vv v8, v8, v9188; CHECK-NEXT: vsub.vv v9, v8, v10189; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma190; CHECK-NEXT: vzext.vf2 v8, v9191; CHECK-NEXT: ret192 %a.sext = sext <4 x i16> %a to <4 x i32>193 %b.sext = sext <4 x i16> %b to <4 x i32>194 %sub = sub <4 x i32> %a.sext, %b.sext195 %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)196 ret <4 x i32> %abs197}198 199define <2 x i64> @sabd_2d(<2 x i64> %a, <2 x i64> %b) {200; CHECK-LABEL: sabd_2d:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma203; CHECK-NEXT: vmin.vv v10, v8, v9204; CHECK-NEXT: vmax.vv v8, v8, v9205; CHECK-NEXT: vsub.vv v8, v8, v10206; CHECK-NEXT: ret207 %a.sext = sext <2 x i64> %a to <2 x i128>208 %b.sext = sext <2 x i64> %b to <2 x i128>209 %sub = sub <2 x i128> %a.sext, %b.sext210 %abs = call <2 x i128> @llvm.abs.v2i128(<2 x i128> %sub, i1 true)211 %trunc = trunc <2 x i128> %abs to <2 x i64>212 ret <2 x i64> %trunc213}214 215define <2 x i64> @sabd_2d_promoted_ops(<2 x i32> %a, <2 x i32> %b) {216;217; CHECK-LABEL: sabd_2d_promoted_ops:218; CHECK: # %bb.0:219; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma220; CHECK-NEXT: vmin.vv v10, v8, v9221; CHECK-NEXT: vmax.vv v8, v8, v9222; CHECK-NEXT: vsub.vv v9, v8, v10223; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma224; CHECK-NEXT: vzext.vf2 v8, v9225; CHECK-NEXT: ret226 %a.sext = sext <2 x i32> %a to <2 x i64>227 %b.sext = sext <2 x i32> %b to <2 x i64>228 %sub = sub <2 x i64> %a.sext, %b.sext229 %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)230 ret <2 x i64> %abs231}232 233;234; UABD235;236 237define <8 x i8> @uabd_8b(<8 x i8> %a, <8 x i8> %b) {238;239; CHECK-LABEL: uabd_8b:240; CHECK: # %bb.0:241; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma242; CHECK-NEXT: vminu.vv v10, v8, v9243; CHECK-NEXT: vmaxu.vv v8, v8, v9244; CHECK-NEXT: vsub.vv v8, v8, v10245; CHECK-NEXT: ret246 %a.zext = zext <8 x i8> %a to <8 x i16>247 %b.zext = zext <8 x i8> %b to <8 x i16>248 %sub = sub <8 x i16> %a.zext, %b.zext249 %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)250 %trunc = trunc <8 x i16> %abs to <8 x i8>251 ret <8 x i8> %trunc252}253 254define <16 x i8> @uabd_16b(<16 x i8> %a, <16 x i8> %b) {255;256; CHECK-LABEL: uabd_16b:257; CHECK: # %bb.0:258; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma259; CHECK-NEXT: vminu.vv v10, v8, v9260; CHECK-NEXT: vmaxu.vv v8, v8, v9261; CHECK-NEXT: vsub.vv v8, v8, v10262; CHECK-NEXT: ret263 %a.zext = zext <16 x i8> %a to <16 x i16>264 %b.zext = zext <16 x i8> %b to <16 x i16>265 %sub = sub <16 x i16> %a.zext, %b.zext266 %abs = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %sub, i1 true)267 %trunc = trunc <16 x i16> %abs to <16 x i8>268 ret <16 x i8> %trunc269}270 271define <4 x i16> @uabd_4h(<4 x i16> %a, <4 x i16> %b) {272;273; CHECK-LABEL: uabd_4h:274; CHECK: # %bb.0:275; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma276; CHECK-NEXT: vminu.vv v10, v8, v9277; CHECK-NEXT: vmaxu.vv v8, v8, v9278; CHECK-NEXT: vsub.vv v8, v8, v10279; CHECK-NEXT: ret280 %a.zext = zext <4 x i16> %a to <4 x i32>281 %b.zext = zext <4 x i16> %b to <4 x i32>282 %sub = sub <4 x i32> %a.zext, %b.zext283 %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)284 %trunc = trunc <4 x i32> %abs to <4 x i16>285 ret <4 x i16> %trunc286}287 288define <4 x i16> @uabd_4h_promoted_ops(<4 x i8> %a, <4 x i8> %b) {289;290; CHECK-LABEL: uabd_4h_promoted_ops:291; CHECK: # %bb.0:292; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma293; CHECK-NEXT: vminu.vv v10, v8, v9294; CHECK-NEXT: vmaxu.vv v8, v8, v9295; CHECK-NEXT: vsub.vv v9, v8, v10296; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma297; CHECK-NEXT: vzext.vf2 v8, v9298; CHECK-NEXT: ret299 %a.zext = zext <4 x i8> %a to <4 x i16>300 %b.zext = zext <4 x i8> %b to <4 x i16>301 %sub = sub <4 x i16> %a.zext, %b.zext302 %abs = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %sub, i1 true)303 ret <4 x i16> %abs304}305 306define <8 x i16> @uabd_8h(<8 x i16> %a, <8 x i16> %b) {307;308; CHECK-LABEL: uabd_8h:309; CHECK: # %bb.0:310; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma311; CHECK-NEXT: vminu.vv v10, v8, v9312; CHECK-NEXT: vmaxu.vv v8, v8, v9313; CHECK-NEXT: vsub.vv v8, v8, v10314; CHECK-NEXT: ret315 %a.zext = zext <8 x i16> %a to <8 x i32>316 %b.zext = zext <8 x i16> %b to <8 x i32>317 %sub = sub <8 x i32> %a.zext, %b.zext318 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 true)319 %trunc = trunc <8 x i32> %abs to <8 x i16>320 ret <8 x i16> %trunc321}322 323define <8 x i16> @uabd_8h_promoted_ops(<8 x i8> %a, <8 x i8> %b) {324;325; CHECK-LABEL: uabd_8h_promoted_ops:326; CHECK: # %bb.0:327; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma328; CHECK-NEXT: vminu.vv v10, v8, v9329; CHECK-NEXT: vmaxu.vv v8, v8, v9330; CHECK-NEXT: vsub.vv v9, v8, v10331; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma332; CHECK-NEXT: vzext.vf2 v8, v9333; CHECK-NEXT: ret334 %a.zext = zext <8 x i8> %a to <8 x i16>335 %b.zext = zext <8 x i8> %b to <8 x i16>336 %sub = sub <8 x i16> %a.zext, %b.zext337 %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)338 ret <8 x i16> %abs339}340 341define <2 x i32> @uabd_2s(<2 x i32> %a, <2 x i32> %b) {342;343; CHECK-LABEL: uabd_2s:344; CHECK: # %bb.0:345; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma346; CHECK-NEXT: vminu.vv v10, v8, v9347; CHECK-NEXT: vmaxu.vv v8, v8, v9348; CHECK-NEXT: vsub.vv v8, v8, v10349; CHECK-NEXT: ret350 %a.zext = zext <2 x i32> %a to <2 x i64>351 %b.zext = zext <2 x i32> %b to <2 x i64>352 %sub = sub <2 x i64> %a.zext, %b.zext353 %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)354 %trunc = trunc <2 x i64> %abs to <2 x i32>355 ret <2 x i32> %trunc356}357 358define <2 x i32> @uabd_2s_promoted_ops(<2 x i16> %a, <2 x i16> %b) {359;360; CHECK-LABEL: uabd_2s_promoted_ops:361; CHECK: # %bb.0:362; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma363; CHECK-NEXT: vminu.vv v10, v8, v9364; CHECK-NEXT: vmaxu.vv v8, v8, v9365; CHECK-NEXT: vsub.vv v9, v8, v10366; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma367; CHECK-NEXT: vzext.vf2 v8, v9368; CHECK-NEXT: ret369 %a.zext = zext <2 x i16> %a to <2 x i32>370 %b.zext = zext <2 x i16> %b to <2 x i32>371 %sub = sub <2 x i32> %a.zext, %b.zext372 %abs = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %sub, i1 true)373 ret <2 x i32> %abs374}375 376define <4 x i32> @uabd_4s(<4 x i32> %a, <4 x i32> %b) {377;378; CHECK-LABEL: uabd_4s:379; CHECK: # %bb.0:380; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma381; CHECK-NEXT: vminu.vv v10, v8, v9382; CHECK-NEXT: vmaxu.vv v8, v8, v9383; CHECK-NEXT: vsub.vv v8, v8, v10384; CHECK-NEXT: ret385 %a.zext = zext <4 x i32> %a to <4 x i64>386 %b.zext = zext <4 x i32> %b to <4 x i64>387 %sub = sub <4 x i64> %a.zext, %b.zext388 %abs = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %sub, i1 true)389 %trunc = trunc <4 x i64> %abs to <4 x i32>390 ret <4 x i32> %trunc391}392 393define <4 x i32> @uabd_4s_promoted_ops(<4 x i16> %a, <4 x i16> %b) {394;395; CHECK-LABEL: uabd_4s_promoted_ops:396; CHECK: # %bb.0:397; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma398; CHECK-NEXT: vminu.vv v10, v8, v9399; CHECK-NEXT: vmaxu.vv v8, v8, v9400; CHECK-NEXT: vsub.vv v9, v8, v10401; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma402; CHECK-NEXT: vzext.vf2 v8, v9403; CHECK-NEXT: ret404 %a.zext = zext <4 x i16> %a to <4 x i32>405 %b.zext = zext <4 x i16> %b to <4 x i32>406 %sub = sub <4 x i32> %a.zext, %b.zext407 %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)408 ret <4 x i32> %abs409}410 411define <2 x i64> @uabd_2d(<2 x i64> %a, <2 x i64> %b) {412; CHECK-LABEL: uabd_2d:413; CHECK: # %bb.0:414; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma415; CHECK-NEXT: vminu.vv v10, v8, v9416; CHECK-NEXT: vmaxu.vv v8, v8, v9417; CHECK-NEXT: vsub.vv v8, v8, v10418; CHECK-NEXT: ret419 %a.zext = zext <2 x i64> %a to <2 x i128>420 %b.zext = zext <2 x i64> %b to <2 x i128>421 %sub = sub <2 x i128> %a.zext, %b.zext422 %abs = call <2 x i128> @llvm.abs.v2i128(<2 x i128> %sub, i1 true)423 %trunc = trunc <2 x i128> %abs to <2 x i64>424 ret <2 x i64> %trunc425}426 427define <2 x i64> @uabd_2d_promoted_ops(<2 x i32> %a, <2 x i32> %b) {428;429; CHECK-LABEL: uabd_2d_promoted_ops:430; CHECK: # %bb.0:431; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma432; CHECK-NEXT: vminu.vv v10, v8, v9433; CHECK-NEXT: vmaxu.vv v8, v8, v9434; CHECK-NEXT: vsub.vv v9, v8, v10435; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma436; CHECK-NEXT: vzext.vf2 v8, v9437; CHECK-NEXT: ret438 %a.zext = zext <2 x i32> %a to <2 x i64>439 %b.zext = zext <2 x i32> %b to <2 x i64>440 %sub = sub <2 x i64> %a.zext, %b.zext441 %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)442 ret <2 x i64> %abs443}444 445define <16 x i8> @uabd_v16i8_nuw(<16 x i8> %a, <16 x i8> %b) {446;447; CHECK-LABEL: uabd_v16i8_nuw:448; CHECK: # %bb.0:449; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma450; CHECK-NEXT: vsub.vv v8, v8, v9451; CHECK-NEXT: vrsub.vi v9, v8, 0452; CHECK-NEXT: vmax.vv v8, v8, v9453; CHECK-NEXT: ret454 %sub = sub nuw <16 x i8> %a, %b455 %abs = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %sub, i1 true)456 ret <16 x i8> %abs457}458 459define <8 x i16> @uabd_v8i16_nuw(<8 x i16> %a, <8 x i16> %b) {460;461; CHECK-LABEL: uabd_v8i16_nuw:462; CHECK: # %bb.0:463; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma464; CHECK-NEXT: vsub.vv v8, v8, v9465; CHECK-NEXT: vrsub.vi v9, v8, 0466; CHECK-NEXT: vmax.vv v8, v8, v9467; CHECK-NEXT: ret468 %sub = sub nuw <8 x i16> %a, %b469 %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)470 ret <8 x i16> %abs471}472 473define <4 x i32> @uabd_v4i32_nuw(<4 x i32> %a, <4 x i32> %b) {474;475; CHECK-LABEL: uabd_v4i32_nuw:476; CHECK: # %bb.0:477; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma478; CHECK-NEXT: vsub.vv v8, v8, v9479; CHECK-NEXT: vrsub.vi v9, v8, 0480; CHECK-NEXT: vmax.vv v8, v8, v9481; CHECK-NEXT: ret482 %sub = sub nuw <4 x i32> %a, %b483 %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)484 ret <4 x i32> %abs485}486 487define <2 x i64> @uabd_v2i64_nuw(<2 x i64> %a, <2 x i64> %b) {488;489; CHECK-LABEL: uabd_v2i64_nuw:490; CHECK: # %bb.0:491; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma492; CHECK-NEXT: vsub.vv v8, v8, v9493; CHECK-NEXT: vrsub.vi v9, v8, 0494; CHECK-NEXT: vmax.vv v8, v8, v9495; CHECK-NEXT: ret496 %sub = sub nuw <2 x i64> %a, %b497 %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)498 ret <2 x i64> %abs499}500 501define <16 x i8> @sabd_v16i8_nsw(<16 x i8> %a, <16 x i8> %b) {502;503; CHECK-LABEL: sabd_v16i8_nsw:504; CHECK: # %bb.0:505; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma506; CHECK-NEXT: vmin.vv v10, v8, v9507; CHECK-NEXT: vmax.vv v8, v8, v9508; CHECK-NEXT: vsub.vv v8, v8, v10509; CHECK-NEXT: ret510 %sub = sub nsw <16 x i8> %a, %b511 %abs = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %sub, i1 true)512 ret <16 x i8> %abs513}514 515define <8 x i16> @sabd_v8i16_nsw(<8 x i16> %a, <8 x i16> %b) {516;517; CHECK-LABEL: sabd_v8i16_nsw:518; CHECK: # %bb.0:519; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma520; CHECK-NEXT: vmin.vv v10, v8, v9521; CHECK-NEXT: vmax.vv v8, v8, v9522; CHECK-NEXT: vsub.vv v8, v8, v10523; CHECK-NEXT: ret524 %sub = sub nsw <8 x i16> %a, %b525 %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)526 ret <8 x i16> %abs527}528 529define <4 x i32> @sabd_v4i32_nsw(<4 x i32> %a, <4 x i32> %b) {530;531; CHECK-LABEL: sabd_v4i32_nsw:532; CHECK: # %bb.0:533; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma534; CHECK-NEXT: vmin.vv v10, v8, v9535; CHECK-NEXT: vmax.vv v8, v8, v9536; CHECK-NEXT: vsub.vv v8, v8, v10537; CHECK-NEXT: ret538 %sub = sub nsw <4 x i32> %a, %b539 %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)540 ret <4 x i32> %abs541}542 543define <2 x i64> @sabd_v2i64_nsw(<2 x i64> %a, <2 x i64> %b) {544;545; CHECK-LABEL: sabd_v2i64_nsw:546; CHECK: # %bb.0:547; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma548; CHECK-NEXT: vmin.vv v10, v8, v9549; CHECK-NEXT: vmax.vv v8, v8, v9550; CHECK-NEXT: vsub.vv v8, v8, v10551; CHECK-NEXT: ret552 %sub = sub nsw <2 x i64> %a, %b553 %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)554 ret <2 x i64> %abs555}556 557define <16 x i8> @smaxmin_v16i8(<16 x i8> %0, <16 x i8> %1) {558;559; CHECK-LABEL: smaxmin_v16i8:560; CHECK: # %bb.0:561; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma562; CHECK-NEXT: vmin.vv v10, v8, v9563; CHECK-NEXT: vmax.vv v8, v8, v9564; CHECK-NEXT: vsub.vv v8, v8, v10565; CHECK-NEXT: ret566 %a = tail call <16 x i8> @llvm.smax.v16i8(<16 x i8> %0, <16 x i8> %1)567 %b = tail call <16 x i8> @llvm.smin.v16i8(<16 x i8> %0, <16 x i8> %1)568 %sub = sub <16 x i8> %a, %b569 ret <16 x i8> %sub570}571 572define <8 x i16> @smaxmin_v8i16(<8 x i16> %0, <8 x i16> %1) {573;574; CHECK-LABEL: smaxmin_v8i16:575; CHECK: # %bb.0:576; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma577; CHECK-NEXT: vmin.vv v10, v8, v9578; CHECK-NEXT: vmax.vv v8, v8, v9579; CHECK-NEXT: vsub.vv v8, v8, v10580; CHECK-NEXT: ret581 %a = tail call <8 x i16> @llvm.smax.v8i16(<8 x i16> %0, <8 x i16> %1)582 %b = tail call <8 x i16> @llvm.smin.v8i16(<8 x i16> %0, <8 x i16> %1)583 %sub = sub <8 x i16> %a, %b584 ret <8 x i16> %sub585}586 587define <4 x i32> @smaxmin_v4i32(<4 x i32> %0, <4 x i32> %1) {588;589; CHECK-LABEL: smaxmin_v4i32:590; CHECK: # %bb.0:591; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma592; CHECK-NEXT: vmin.vv v10, v8, v9593; CHECK-NEXT: vmax.vv v8, v8, v9594; CHECK-NEXT: vsub.vv v8, v8, v10595; CHECK-NEXT: ret596 %a = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> %0, <4 x i32> %1)597 %b = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> %0, <4 x i32> %1)598 %sub = sub <4 x i32> %a, %b599 ret <4 x i32> %sub600}601 602define <2 x i64> @smaxmin_v2i64(<2 x i64> %0, <2 x i64> %1) {603;604; CHECK-LABEL: smaxmin_v2i64:605; CHECK: # %bb.0:606; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma607; CHECK-NEXT: vmin.vv v10, v8, v9608; CHECK-NEXT: vmax.vv v8, v8, v9609; CHECK-NEXT: vsub.vv v8, v8, v10610; CHECK-NEXT: ret611 %a = tail call <2 x i64> @llvm.smax.v2i64(<2 x i64> %0, <2 x i64> %1)612 %b = tail call <2 x i64> @llvm.smin.v2i64(<2 x i64> %0, <2 x i64> %1)613 %sub = sub <2 x i64> %a, %b614 ret <2 x i64> %sub615}616 617define <16 x i8> @umaxmin_v16i8(<16 x i8> %0, <16 x i8> %1) {618;619; CHECK-LABEL: umaxmin_v16i8:620; CHECK: # %bb.0:621; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma622; CHECK-NEXT: vminu.vv v10, v8, v9623; CHECK-NEXT: vmaxu.vv v8, v8, v9624; CHECK-NEXT: vsub.vv v8, v8, v10625; CHECK-NEXT: ret626 %a = tail call <16 x i8> @llvm.umax.v16i8(<16 x i8> %0, <16 x i8> %1)627 %b = tail call <16 x i8> @llvm.umin.v16i8(<16 x i8> %0, <16 x i8> %1)628 %sub = sub <16 x i8> %a, %b629 ret <16 x i8> %sub630}631 632define <8 x i16> @umaxmin_v8i16(<8 x i16> %0, <8 x i16> %1) {633;634; CHECK-LABEL: umaxmin_v8i16:635; CHECK: # %bb.0:636; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma637; CHECK-NEXT: vminu.vv v10, v8, v9638; CHECK-NEXT: vmaxu.vv v8, v8, v9639; CHECK-NEXT: vsub.vv v8, v8, v10640; CHECK-NEXT: ret641 %a = tail call <8 x i16> @llvm.umax.v8i16(<8 x i16> %0, <8 x i16> %1)642 %b = tail call <8 x i16> @llvm.umin.v8i16(<8 x i16> %0, <8 x i16> %1)643 %sub = sub <8 x i16> %a, %b644 ret <8 x i16> %sub645}646 647define <4 x i32> @umaxmin_v4i32(<4 x i32> %0, <4 x i32> %1) {648;649; CHECK-LABEL: umaxmin_v4i32:650; CHECK: # %bb.0:651; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma652; CHECK-NEXT: vminu.vv v10, v8, v9653; CHECK-NEXT: vmaxu.vv v8, v8, v9654; CHECK-NEXT: vsub.vv v8, v8, v10655; CHECK-NEXT: ret656 %a = tail call <4 x i32> @llvm.umax.v4i32(<4 x i32> %0, <4 x i32> %1)657 %b = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> %0, <4 x i32> %1)658 %sub = sub <4 x i32> %a, %b659 ret <4 x i32> %sub660}661 662define <2 x i64> @umaxmin_v2i64(<2 x i64> %0, <2 x i64> %1) {663;664; CHECK-LABEL: umaxmin_v2i64:665; CHECK: # %bb.0:666; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma667; CHECK-NEXT: vminu.vv v10, v8, v9668; CHECK-NEXT: vmaxu.vv v8, v8, v9669; CHECK-NEXT: vsub.vv v8, v8, v10670; CHECK-NEXT: ret671 %a = tail call <2 x i64> @llvm.umax.v2i64(<2 x i64> %0, <2 x i64> %1)672 %b = tail call <2 x i64> @llvm.umin.v2i64(<2 x i64> %0, <2 x i64> %1)673 %sub = sub <2 x i64> %a, %b674 ret <2 x i64> %sub675}676 677define <16 x i8> @umaxmin_v16i8_com1(<16 x i8> %0, <16 x i8> %1) {678;679; CHECK-LABEL: umaxmin_v16i8_com1:680; CHECK: # %bb.0:681; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma682; CHECK-NEXT: vminu.vv v10, v8, v9683; CHECK-NEXT: vmaxu.vv v8, v8, v9684; CHECK-NEXT: vsub.vv v8, v8, v10685; CHECK-NEXT: ret686 %a = tail call <16 x i8> @llvm.umax.v16i8(<16 x i8> %0, <16 x i8> %1)687 %b = tail call <16 x i8> @llvm.umin.v16i8(<16 x i8> %1, <16 x i8> %0)688 %sub = sub <16 x i8> %a, %b689 ret <16 x i8> %sub690}691 692;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:693; RV32: {{.*}}694; RV64: {{.*}}695