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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK4; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK6 7define <2 x i8> @vp_abs_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vp_abs_v2i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t12; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t13; CHECK-NEXT: ret14 %v = call <2 x i8> @llvm.vp.abs.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl)15 ret <2 x i8> %v16}17 18define <2 x i8> @vp_abs_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {19; CHECK-LABEL: vp_abs_v2i8_unmasked:20; CHECK: # %bb.0:21; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma22; CHECK-NEXT: vrsub.vi v9, v8, 023; CHECK-NEXT: vmax.vv v8, v8, v924; CHECK-NEXT: ret25 %v = call <2 x i8> @llvm.vp.abs.v2i8(<2 x i8> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl)26 ret <2 x i8> %v27}28 29define <4 x i8> @vp_abs_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {30; CHECK-LABEL: vp_abs_v4i8:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma33; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t34; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t35; CHECK-NEXT: ret36 %v = call <4 x i8> @llvm.vp.abs.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl)37 ret <4 x i8> %v38}39 40define <4 x i8> @vp_abs_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {41; CHECK-LABEL: vp_abs_v4i8_unmasked:42; CHECK: # %bb.0:43; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma44; CHECK-NEXT: vrsub.vi v9, v8, 045; CHECK-NEXT: vmax.vv v8, v8, v946; CHECK-NEXT: ret47 %v = call <4 x i8> @llvm.vp.abs.v4i8(<4 x i8> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl)48 ret <4 x i8> %v49}50 51define <8 x i8> @vp_abs_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {52; CHECK-LABEL: vp_abs_v8i8:53; CHECK: # %bb.0:54; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma55; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t56; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t57; CHECK-NEXT: ret58 %v = call <8 x i8> @llvm.vp.abs.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl)59 ret <8 x i8> %v60}61 62define <8 x i8> @vp_abs_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {63; CHECK-LABEL: vp_abs_v8i8_unmasked:64; CHECK: # %bb.0:65; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma66; CHECK-NEXT: vrsub.vi v9, v8, 067; CHECK-NEXT: vmax.vv v8, v8, v968; CHECK-NEXT: ret69 %v = call <8 x i8> @llvm.vp.abs.v8i8(<8 x i8> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl)70 ret <8 x i8> %v71}72 73define <16 x i8> @vp_abs_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {74; CHECK-LABEL: vp_abs_v16i8:75; CHECK: # %bb.0:76; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma77; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t78; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t79; CHECK-NEXT: ret80 %v = call <16 x i8> @llvm.vp.abs.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl)81 ret <16 x i8> %v82}83 84define <16 x i8> @vp_abs_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {85; CHECK-LABEL: vp_abs_v16i8_unmasked:86; CHECK: # %bb.0:87; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma88; CHECK-NEXT: vrsub.vi v9, v8, 089; CHECK-NEXT: vmax.vv v8, v8, v990; CHECK-NEXT: ret91 %v = call <16 x i8> @llvm.vp.abs.v16i8(<16 x i8> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl)92 ret <16 x i8> %v93}94 95define <2 x i16> @vp_abs_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {96; CHECK-LABEL: vp_abs_v2i16:97; CHECK: # %bb.0:98; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma99; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t100; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t101; CHECK-NEXT: ret102 %v = call <2 x i16> @llvm.vp.abs.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl)103 ret <2 x i16> %v104}105 106define <2 x i16> @vp_abs_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {107; CHECK-LABEL: vp_abs_v2i16_unmasked:108; CHECK: # %bb.0:109; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma110; CHECK-NEXT: vrsub.vi v9, v8, 0111; CHECK-NEXT: vmax.vv v8, v8, v9112; CHECK-NEXT: ret113 %v = call <2 x i16> @llvm.vp.abs.v2i16(<2 x i16> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl)114 ret <2 x i16> %v115}116 117define <4 x i16> @vp_abs_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {118; CHECK-LABEL: vp_abs_v4i16:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma121; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t122; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t123; CHECK-NEXT: ret124 %v = call <4 x i16> @llvm.vp.abs.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl)125 ret <4 x i16> %v126}127 128define <4 x i16> @vp_abs_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {129; CHECK-LABEL: vp_abs_v4i16_unmasked:130; CHECK: # %bb.0:131; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma132; CHECK-NEXT: vrsub.vi v9, v8, 0133; CHECK-NEXT: vmax.vv v8, v8, v9134; CHECK-NEXT: ret135 %v = call <4 x i16> @llvm.vp.abs.v4i16(<4 x i16> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl)136 ret <4 x i16> %v137}138 139define <8 x i16> @vp_abs_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {140; CHECK-LABEL: vp_abs_v8i16:141; CHECK: # %bb.0:142; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma143; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t144; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t145; CHECK-NEXT: ret146 %v = call <8 x i16> @llvm.vp.abs.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl)147 ret <8 x i16> %v148}149 150define <8 x i16> @vp_abs_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {151; CHECK-LABEL: vp_abs_v8i16_unmasked:152; CHECK: # %bb.0:153; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma154; CHECK-NEXT: vrsub.vi v9, v8, 0155; CHECK-NEXT: vmax.vv v8, v8, v9156; CHECK-NEXT: ret157 %v = call <8 x i16> @llvm.vp.abs.v8i16(<8 x i16> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl)158 ret <8 x i16> %v159}160 161define <16 x i16> @vp_abs_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {162; CHECK-LABEL: vp_abs_v16i16:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma165; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t166; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t167; CHECK-NEXT: ret168 %v = call <16 x i16> @llvm.vp.abs.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl)169 ret <16 x i16> %v170}171 172define <16 x i16> @vp_abs_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {173; CHECK-LABEL: vp_abs_v16i16_unmasked:174; CHECK: # %bb.0:175; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma176; CHECK-NEXT: vrsub.vi v10, v8, 0177; CHECK-NEXT: vmax.vv v8, v8, v10178; CHECK-NEXT: ret179 %v = call <16 x i16> @llvm.vp.abs.v16i16(<16 x i16> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl)180 ret <16 x i16> %v181}182 183define <2 x i32> @vp_abs_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {184; CHECK-LABEL: vp_abs_v2i32:185; CHECK: # %bb.0:186; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma187; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t188; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t189; CHECK-NEXT: ret190 %v = call <2 x i32> @llvm.vp.abs.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl)191 ret <2 x i32> %v192}193 194define <2 x i32> @vp_abs_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {195; CHECK-LABEL: vp_abs_v2i32_unmasked:196; CHECK: # %bb.0:197; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma198; CHECK-NEXT: vrsub.vi v9, v8, 0199; CHECK-NEXT: vmax.vv v8, v8, v9200; CHECK-NEXT: ret201 %v = call <2 x i32> @llvm.vp.abs.v2i32(<2 x i32> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl)202 ret <2 x i32> %v203}204 205define <4 x i32> @vp_abs_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {206; CHECK-LABEL: vp_abs_v4i32:207; CHECK: # %bb.0:208; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma209; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t210; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t211; CHECK-NEXT: ret212 %v = call <4 x i32> @llvm.vp.abs.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl)213 ret <4 x i32> %v214}215 216define <4 x i32> @vp_abs_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {217; CHECK-LABEL: vp_abs_v4i32_unmasked:218; CHECK: # %bb.0:219; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma220; CHECK-NEXT: vrsub.vi v9, v8, 0221; CHECK-NEXT: vmax.vv v8, v8, v9222; CHECK-NEXT: ret223 %v = call <4 x i32> @llvm.vp.abs.v4i32(<4 x i32> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl)224 ret <4 x i32> %v225}226 227define <8 x i32> @vp_abs_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {228; CHECK-LABEL: vp_abs_v8i32:229; CHECK: # %bb.0:230; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma231; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t232; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t233; CHECK-NEXT: ret234 %v = call <8 x i32> @llvm.vp.abs.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl)235 ret <8 x i32> %v236}237 238define <8 x i32> @vp_abs_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {239; CHECK-LABEL: vp_abs_v8i32_unmasked:240; CHECK: # %bb.0:241; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma242; CHECK-NEXT: vrsub.vi v10, v8, 0243; CHECK-NEXT: vmax.vv v8, v8, v10244; CHECK-NEXT: ret245 %v = call <8 x i32> @llvm.vp.abs.v8i32(<8 x i32> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl)246 ret <8 x i32> %v247}248 249define <16 x i32> @vp_abs_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {250; CHECK-LABEL: vp_abs_v16i32:251; CHECK: # %bb.0:252; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma253; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t254; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t255; CHECK-NEXT: ret256 %v = call <16 x i32> @llvm.vp.abs.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl)257 ret <16 x i32> %v258}259 260define <16 x i32> @vp_abs_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {261; CHECK-LABEL: vp_abs_v16i32_unmasked:262; CHECK: # %bb.0:263; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma264; CHECK-NEXT: vrsub.vi v12, v8, 0265; CHECK-NEXT: vmax.vv v8, v8, v12266; CHECK-NEXT: ret267 %v = call <16 x i32> @llvm.vp.abs.v16i32(<16 x i32> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl)268 ret <16 x i32> %v269}270 271define <2 x i64> @vp_abs_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {272; CHECK-LABEL: vp_abs_v2i64:273; CHECK: # %bb.0:274; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma275; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t276; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t277; CHECK-NEXT: ret278 %v = call <2 x i64> @llvm.vp.abs.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl)279 ret <2 x i64> %v280}281 282define <2 x i64> @vp_abs_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {283; CHECK-LABEL: vp_abs_v2i64_unmasked:284; CHECK: # %bb.0:285; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma286; CHECK-NEXT: vrsub.vi v9, v8, 0287; CHECK-NEXT: vmax.vv v8, v8, v9288; CHECK-NEXT: ret289 %v = call <2 x i64> @llvm.vp.abs.v2i64(<2 x i64> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl)290 ret <2 x i64> %v291}292 293define <4 x i64> @vp_abs_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {294; CHECK-LABEL: vp_abs_v4i64:295; CHECK: # %bb.0:296; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma297; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t298; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t299; CHECK-NEXT: ret300 %v = call <4 x i64> @llvm.vp.abs.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl)301 ret <4 x i64> %v302}303 304define <4 x i64> @vp_abs_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {305; CHECK-LABEL: vp_abs_v4i64_unmasked:306; CHECK: # %bb.0:307; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma308; CHECK-NEXT: vrsub.vi v10, v8, 0309; CHECK-NEXT: vmax.vv v8, v8, v10310; CHECK-NEXT: ret311 %v = call <4 x i64> @llvm.vp.abs.v4i64(<4 x i64> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl)312 ret <4 x i64> %v313}314 315define <8 x i64> @vp_abs_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {316; CHECK-LABEL: vp_abs_v8i64:317; CHECK: # %bb.0:318; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma319; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t320; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t321; CHECK-NEXT: ret322 %v = call <8 x i64> @llvm.vp.abs.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl)323 ret <8 x i64> %v324}325 326define <8 x i64> @vp_abs_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {327; CHECK-LABEL: vp_abs_v8i64_unmasked:328; CHECK: # %bb.0:329; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma330; CHECK-NEXT: vrsub.vi v12, v8, 0331; CHECK-NEXT: vmax.vv v8, v8, v12332; CHECK-NEXT: ret333 %v = call <8 x i64> @llvm.vp.abs.v8i64(<8 x i64> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl)334 ret <8 x i64> %v335}336 337define <15 x i64> @vp_abs_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {338; CHECK-LABEL: vp_abs_v15i64:339; CHECK: # %bb.0:340; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma341; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t342; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t343; CHECK-NEXT: ret344 %v = call <15 x i64> @llvm.vp.abs.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl)345 ret <15 x i64> %v346}347 348define <15 x i64> @vp_abs_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {349; CHECK-LABEL: vp_abs_v15i64_unmasked:350; CHECK: # %bb.0:351; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma352; CHECK-NEXT: vrsub.vi v16, v8, 0353; CHECK-NEXT: vmax.vv v8, v8, v16354; CHECK-NEXT: ret355 %v = call <15 x i64> @llvm.vp.abs.v15i64(<15 x i64> %va, i1 false, <15 x i1> splat (i1 true), i32 %evl)356 ret <15 x i64> %v357}358 359define <16 x i64> @vp_abs_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {360; CHECK-LABEL: vp_abs_v16i64:361; CHECK: # %bb.0:362; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma363; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t364; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t365; CHECK-NEXT: ret366 %v = call <16 x i64> @llvm.vp.abs.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl)367 ret <16 x i64> %v368}369 370define <16 x i64> @vp_abs_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {371; CHECK-LABEL: vp_abs_v16i64_unmasked:372; CHECK: # %bb.0:373; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma374; CHECK-NEXT: vrsub.vi v16, v8, 0375; CHECK-NEXT: vmax.vv v8, v8, v16376; CHECK-NEXT: ret377 %v = call <16 x i64> @llvm.vp.abs.v16i64(<16 x i64> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl)378 ret <16 x i64> %v379}380 381define <32 x i64> @vp_abs_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {382; CHECK-LABEL: vp_abs_v32i64:383; CHECK: # %bb.0:384; CHECK-NEXT: li a2, 16385; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma386; CHECK-NEXT: vslidedown.vi v7, v0, 2387; CHECK-NEXT: mv a1, a0388; CHECK-NEXT: bltu a0, a2, .LBB34_2389; CHECK-NEXT: # %bb.1:390; CHECK-NEXT: li a1, 16391; CHECK-NEXT: .LBB34_2:392; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma393; CHECK-NEXT: vrsub.vi v24, v8, 0, v0.t394; CHECK-NEXT: vmax.vv v8, v8, v24, v0.t395; CHECK-NEXT: addi a1, a0, -16396; CHECK-NEXT: sltu a0, a0, a1397; CHECK-NEXT: addi a0, a0, -1398; CHECK-NEXT: and a0, a0, a1399; CHECK-NEXT: vmv1r.v v0, v7400; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma401; CHECK-NEXT: vrsub.vi v24, v16, 0, v0.t402; CHECK-NEXT: vmax.vv v16, v16, v24, v0.t403; CHECK-NEXT: ret404 %v = call <32 x i64> @llvm.vp.abs.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)405 ret <32 x i64> %v406}407 408define <32 x i64> @vp_abs_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {409; CHECK-LABEL: vp_abs_v32i64_unmasked:410; CHECK: # %bb.0:411; CHECK-NEXT: li a2, 16412; CHECK-NEXT: mv a1, a0413; CHECK-NEXT: bltu a0, a2, .LBB35_2414; CHECK-NEXT: # %bb.1:415; CHECK-NEXT: li a1, 16416; CHECK-NEXT: .LBB35_2:417; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma418; CHECK-NEXT: vrsub.vi v24, v8, 0419; CHECK-NEXT: vmax.vv v8, v8, v24420; CHECK-NEXT: addi a1, a0, -16421; CHECK-NEXT: sltu a0, a0, a1422; CHECK-NEXT: addi a0, a0, -1423; CHECK-NEXT: and a0, a0, a1424; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma425; CHECK-NEXT: vrsub.vi v24, v16, 0426; CHECK-NEXT: vmax.vv v16, v16, v24427; CHECK-NEXT: ret428 %v = call <32 x i64> @llvm.vp.abs.v32i64(<32 x i64> %va, i1 false, <32 x i1> splat (i1 true), i32 %evl)429 ret <32 x i64> %v430}431