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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define void @abs_v16i8(ptr %x) {6; CHECK-LABEL: abs_v16i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma9; CHECK-NEXT: vle8.v v8, (a0)10; CHECK-NEXT: vrsub.vi v9, v8, 011; CHECK-NEXT: vmax.vv v8, v8, v912; CHECK-NEXT: vse8.v v8, (a0)13; CHECK-NEXT: ret14 %a = load <16 x i8>, ptr %x15 %b = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %a, i1 false)16 store <16 x i8> %b, ptr %x17 ret void18}19 20define void @abs_v8i16(ptr %x) {21; CHECK-LABEL: abs_v8i16:22; CHECK: # %bb.0:23; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma24; CHECK-NEXT: vle16.v v8, (a0)25; CHECK-NEXT: vrsub.vi v9, v8, 026; CHECK-NEXT: vmax.vv v8, v8, v927; CHECK-NEXT: vse16.v v8, (a0)28; CHECK-NEXT: ret29 %a = load <8 x i16>, ptr %x30 %b = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a, i1 false)31 store <8 x i16> %b, ptr %x32 ret void33}34 35define void @abs_v6i16(ptr %x) {36; CHECK-LABEL: abs_v6i16:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma39; CHECK-NEXT: vle16.v v8, (a0)40; CHECK-NEXT: vrsub.vi v9, v8, 041; CHECK-NEXT: vmax.vv v8, v8, v942; CHECK-NEXT: vse16.v v8, (a0)43; CHECK-NEXT: ret44 %a = load <6 x i16>, ptr %x45 %b = call <6 x i16> @llvm.abs.v6i16(<6 x i16> %a, i1 false)46 store <6 x i16> %b, ptr %x47 ret void48}49 50define void @abs_v4i32(ptr %x) {51; CHECK-LABEL: abs_v4i32:52; CHECK: # %bb.0:53; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma54; CHECK-NEXT: vle32.v v8, (a0)55; CHECK-NEXT: vrsub.vi v9, v8, 056; CHECK-NEXT: vmax.vv v8, v8, v957; CHECK-NEXT: vse32.v v8, (a0)58; CHECK-NEXT: ret59 %a = load <4 x i32>, ptr %x60 %b = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a, i1 false)61 store <4 x i32> %b, ptr %x62 ret void63}64 65define void @abs_v2i64(ptr %x) {66; CHECK-LABEL: abs_v2i64:67; CHECK: # %bb.0:68; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma69; CHECK-NEXT: vle64.v v8, (a0)70; CHECK-NEXT: vrsub.vi v9, v8, 071; CHECK-NEXT: vmax.vv v8, v8, v972; CHECK-NEXT: vse64.v v8, (a0)73; CHECK-NEXT: ret74 %a = load <2 x i64>, ptr %x75 %b = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a, i1 false)76 store <2 x i64> %b, ptr %x77 ret void78}79 80define void @abs_v32i8(ptr %x) {81; CHECK-LABEL: abs_v32i8:82; CHECK: # %bb.0:83; CHECK-NEXT: li a1, 3284; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma85; CHECK-NEXT: vle8.v v8, (a0)86; CHECK-NEXT: vrsub.vi v10, v8, 087; CHECK-NEXT: vmax.vv v8, v8, v1088; CHECK-NEXT: vse8.v v8, (a0)89; CHECK-NEXT: ret90 %a = load <32 x i8>, ptr %x91 %b = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %a, i1 false)92 store <32 x i8> %b, ptr %x93 ret void94}95 96define void @abs_v16i16(ptr %x) {97; CHECK-LABEL: abs_v16i16:98; CHECK: # %bb.0:99; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma100; CHECK-NEXT: vle16.v v8, (a0)101; CHECK-NEXT: vrsub.vi v10, v8, 0102; CHECK-NEXT: vmax.vv v8, v8, v10103; CHECK-NEXT: vse16.v v8, (a0)104; CHECK-NEXT: ret105 %a = load <16 x i16>, ptr %x106 %b = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a, i1 false)107 store <16 x i16> %b, ptr %x108 ret void109}110 111define void @abs_v8i32(ptr %x) {112; CHECK-LABEL: abs_v8i32:113; CHECK: # %bb.0:114; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma115; CHECK-NEXT: vle32.v v8, (a0)116; CHECK-NEXT: vrsub.vi v10, v8, 0117; CHECK-NEXT: vmax.vv v8, v8, v10118; CHECK-NEXT: vse32.v v8, (a0)119; CHECK-NEXT: ret120 %a = load <8 x i32>, ptr %x121 %b = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a, i1 false)122 store <8 x i32> %b, ptr %x123 ret void124}125 126define void @abs_v4i64(ptr %x) {127; CHECK-LABEL: abs_v4i64:128; CHECK: # %bb.0:129; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma130; CHECK-NEXT: vle64.v v8, (a0)131; CHECK-NEXT: vrsub.vi v10, v8, 0132; CHECK-NEXT: vmax.vv v8, v8, v10133; CHECK-NEXT: vse64.v v8, (a0)134; CHECK-NEXT: ret135 %a = load <4 x i64>, ptr %x136 %b = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a, i1 false)137 store <4 x i64> %b, ptr %x138 ret void139}140 141define void @abs_v4i64_of_sext_v4i8(ptr %x) {142; CHECK-LABEL: abs_v4i64_of_sext_v4i8:143; CHECK: # %bb.0:144; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma145; CHECK-NEXT: vle8.v v8, (a0)146; CHECK-NEXT: vrsub.vi v9, v8, 0147; CHECK-NEXT: vmax.vv v10, v8, v9148; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma149; CHECK-NEXT: vzext.vf8 v8, v10150; CHECK-NEXT: vse64.v v8, (a0)151; CHECK-NEXT: ret152 %a = load <4 x i8>, ptr %x153 %a.ext = sext <4 x i8> %a to <4 x i64>154 %b = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a.ext, i1 false)155 store <4 x i64> %b, ptr %x156 ret void157}158 159define void @abs_v4i64_of_sext_v4i16(ptr %x) {160; CHECK-LABEL: abs_v4i64_of_sext_v4i16:161; CHECK: # %bb.0:162; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma163; CHECK-NEXT: vle16.v v8, (a0)164; CHECK-NEXT: vrsub.vi v9, v8, 0165; CHECK-NEXT: vmax.vv v10, v8, v9166; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma167; CHECK-NEXT: vzext.vf4 v8, v10168; CHECK-NEXT: vse64.v v8, (a0)169; CHECK-NEXT: ret170 %a = load <4 x i16>, ptr %x171 %a.ext = sext <4 x i16> %a to <4 x i64>172 %b = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a.ext, i1 false)173 store <4 x i64> %b, ptr %x174 ret void175}176 177define void @abs_v4i64_of_sext_v4i32(ptr %x) {178; CHECK-LABEL: abs_v4i64_of_sext_v4i32:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma181; CHECK-NEXT: vle32.v v8, (a0)182; CHECK-NEXT: vrsub.vi v9, v8, 0183; CHECK-NEXT: vmax.vv v10, v8, v9184; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma185; CHECK-NEXT: vzext.vf2 v8, v10186; CHECK-NEXT: vse64.v v8, (a0)187; CHECK-NEXT: ret188 %a = load <4 x i32>, ptr %x189 %a.ext = sext <4 x i32> %a to <4 x i64>190 %b = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a.ext, i1 false)191 store <4 x i64> %b, ptr %x192 ret void193}194