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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV646 7define <2 x i8> @vp_bitreverse_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vp_bitreverse_v2i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vand.vi v9, v8, 15, v0.t12; CHECK-NEXT: li a0, 5113; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t14; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t15; CHECK-NEXT: vand.vi v8, v8, 15, v0.t16; CHECK-NEXT: vor.vv v8, v8, v9, v0.t17; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t18; CHECK-NEXT: vand.vx v9, v9, a0, v0.t19; CHECK-NEXT: vand.vx v8, v8, a0, v0.t20; CHECK-NEXT: li a0, 8521; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t22; CHECK-NEXT: vor.vv v8, v9, v8, v0.t23; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t24; CHECK-NEXT: vand.vx v9, v9, a0, v0.t25; CHECK-NEXT: vand.vx v8, v8, a0, v0.t26; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t27; CHECK-NEXT: vor.vv v8, v9, v8, v0.t28; CHECK-NEXT: ret29 %v = call <2 x i8> @llvm.vp.bitreverse.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl)30 ret <2 x i8> %v31}32 33define <2 x i8> @vp_bitreverse_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {34; CHECK-LABEL: vp_bitreverse_v2i8_unmasked:35; CHECK: # %bb.0:36; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma37; CHECK-NEXT: vand.vi v9, v8, 1538; CHECK-NEXT: vsrl.vi v8, v8, 439; CHECK-NEXT: li a0, 5140; CHECK-NEXT: vsll.vi v9, v9, 441; CHECK-NEXT: vand.vi v8, v8, 1542; CHECK-NEXT: vor.vv v8, v8, v943; CHECK-NEXT: vsrl.vi v9, v8, 244; CHECK-NEXT: vand.vx v8, v8, a045; CHECK-NEXT: vand.vx v9, v9, a046; CHECK-NEXT: li a0, 8547; CHECK-NEXT: vsll.vi v8, v8, 248; CHECK-NEXT: vor.vv v8, v9, v849; CHECK-NEXT: vsrl.vi v9, v8, 150; CHECK-NEXT: vand.vx v8, v8, a051; CHECK-NEXT: vand.vx v9, v9, a052; CHECK-NEXT: vadd.vv v8, v8, v853; CHECK-NEXT: vor.vv v8, v9, v854; CHECK-NEXT: ret55 %v = call <2 x i8> @llvm.vp.bitreverse.v2i8(<2 x i8> %va, <2 x i1> splat (i1 true), i32 %evl)56 ret <2 x i8> %v57}58 59define <4 x i8> @vp_bitreverse_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {60; CHECK-LABEL: vp_bitreverse_v4i8:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma63; CHECK-NEXT: vand.vi v9, v8, 15, v0.t64; CHECK-NEXT: li a0, 5165; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t66; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t67; CHECK-NEXT: vand.vi v8, v8, 15, v0.t68; CHECK-NEXT: vor.vv v8, v8, v9, v0.t69; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t70; CHECK-NEXT: vand.vx v9, v9, a0, v0.t71; CHECK-NEXT: vand.vx v8, v8, a0, v0.t72; CHECK-NEXT: li a0, 8573; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t74; CHECK-NEXT: vor.vv v8, v9, v8, v0.t75; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t76; CHECK-NEXT: vand.vx v9, v9, a0, v0.t77; CHECK-NEXT: vand.vx v8, v8, a0, v0.t78; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t79; CHECK-NEXT: vor.vv v8, v9, v8, v0.t80; CHECK-NEXT: ret81 %v = call <4 x i8> @llvm.vp.bitreverse.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)82 ret <4 x i8> %v83}84 85define <4 x i8> @vp_bitreverse_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {86; CHECK-LABEL: vp_bitreverse_v4i8_unmasked:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma89; CHECK-NEXT: vand.vi v9, v8, 1590; CHECK-NEXT: vsrl.vi v8, v8, 491; CHECK-NEXT: li a0, 5192; CHECK-NEXT: vsll.vi v9, v9, 493; CHECK-NEXT: vand.vi v8, v8, 1594; CHECK-NEXT: vor.vv v8, v8, v995; CHECK-NEXT: vsrl.vi v9, v8, 296; CHECK-NEXT: vand.vx v8, v8, a097; CHECK-NEXT: vand.vx v9, v9, a098; CHECK-NEXT: li a0, 8599; CHECK-NEXT: vsll.vi v8, v8, 2100; CHECK-NEXT: vor.vv v8, v9, v8101; CHECK-NEXT: vsrl.vi v9, v8, 1102; CHECK-NEXT: vand.vx v8, v8, a0103; CHECK-NEXT: vand.vx v9, v9, a0104; CHECK-NEXT: vadd.vv v8, v8, v8105; CHECK-NEXT: vor.vv v8, v9, v8106; CHECK-NEXT: ret107 %v = call <4 x i8> @llvm.vp.bitreverse.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)108 ret <4 x i8> %v109}110 111define <8 x i8> @vp_bitreverse_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {112; CHECK-LABEL: vp_bitreverse_v8i8:113; CHECK: # %bb.0:114; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma115; CHECK-NEXT: vand.vi v9, v8, 15, v0.t116; CHECK-NEXT: li a0, 51117; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t118; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t119; CHECK-NEXT: vand.vi v8, v8, 15, v0.t120; CHECK-NEXT: vor.vv v8, v8, v9, v0.t121; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t122; CHECK-NEXT: vand.vx v9, v9, a0, v0.t123; CHECK-NEXT: vand.vx v8, v8, a0, v0.t124; CHECK-NEXT: li a0, 85125; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t126; CHECK-NEXT: vor.vv v8, v9, v8, v0.t127; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t128; CHECK-NEXT: vand.vx v9, v9, a0, v0.t129; CHECK-NEXT: vand.vx v8, v8, a0, v0.t130; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t131; CHECK-NEXT: vor.vv v8, v9, v8, v0.t132; CHECK-NEXT: ret133 %v = call <8 x i8> @llvm.vp.bitreverse.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl)134 ret <8 x i8> %v135}136 137define <8 x i8> @vp_bitreverse_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {138; CHECK-LABEL: vp_bitreverse_v8i8_unmasked:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma141; CHECK-NEXT: vand.vi v9, v8, 15142; CHECK-NEXT: vsrl.vi v8, v8, 4143; CHECK-NEXT: li a0, 51144; CHECK-NEXT: vsll.vi v9, v9, 4145; CHECK-NEXT: vand.vi v8, v8, 15146; CHECK-NEXT: vor.vv v8, v8, v9147; CHECK-NEXT: vsrl.vi v9, v8, 2148; CHECK-NEXT: vand.vx v8, v8, a0149; CHECK-NEXT: vand.vx v9, v9, a0150; CHECK-NEXT: li a0, 85151; CHECK-NEXT: vsll.vi v8, v8, 2152; CHECK-NEXT: vor.vv v8, v9, v8153; CHECK-NEXT: vsrl.vi v9, v8, 1154; CHECK-NEXT: vand.vx v8, v8, a0155; CHECK-NEXT: vand.vx v9, v9, a0156; CHECK-NEXT: vadd.vv v8, v8, v8157; CHECK-NEXT: vor.vv v8, v9, v8158; CHECK-NEXT: ret159 %v = call <8 x i8> @llvm.vp.bitreverse.v8i8(<8 x i8> %va, <8 x i1> splat (i1 true), i32 %evl)160 ret <8 x i8> %v161}162 163define <16 x i8> @vp_bitreverse_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {164; CHECK-LABEL: vp_bitreverse_v16i8:165; CHECK: # %bb.0:166; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma167; CHECK-NEXT: vand.vi v9, v8, 15, v0.t168; CHECK-NEXT: li a0, 51169; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t170; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t171; CHECK-NEXT: vand.vi v8, v8, 15, v0.t172; CHECK-NEXT: vor.vv v8, v8, v9, v0.t173; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t174; CHECK-NEXT: vand.vx v9, v9, a0, v0.t175; CHECK-NEXT: vand.vx v8, v8, a0, v0.t176; CHECK-NEXT: li a0, 85177; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t178; CHECK-NEXT: vor.vv v8, v9, v8, v0.t179; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t180; CHECK-NEXT: vand.vx v9, v9, a0, v0.t181; CHECK-NEXT: vand.vx v8, v8, a0, v0.t182; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t183; CHECK-NEXT: vor.vv v8, v9, v8, v0.t184; CHECK-NEXT: ret185 %v = call <16 x i8> @llvm.vp.bitreverse.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl)186 ret <16 x i8> %v187}188 189define <16 x i8> @vp_bitreverse_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {190; CHECK-LABEL: vp_bitreverse_v16i8_unmasked:191; CHECK: # %bb.0:192; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma193; CHECK-NEXT: vand.vi v9, v8, 15194; CHECK-NEXT: vsrl.vi v8, v8, 4195; CHECK-NEXT: li a0, 51196; CHECK-NEXT: vsll.vi v9, v9, 4197; CHECK-NEXT: vand.vi v8, v8, 15198; CHECK-NEXT: vor.vv v8, v8, v9199; CHECK-NEXT: vsrl.vi v9, v8, 2200; CHECK-NEXT: vand.vx v8, v8, a0201; CHECK-NEXT: vand.vx v9, v9, a0202; CHECK-NEXT: li a0, 85203; CHECK-NEXT: vsll.vi v8, v8, 2204; CHECK-NEXT: vor.vv v8, v9, v8205; CHECK-NEXT: vsrl.vi v9, v8, 1206; CHECK-NEXT: vand.vx v8, v8, a0207; CHECK-NEXT: vand.vx v9, v9, a0208; CHECK-NEXT: vadd.vv v8, v8, v8209; CHECK-NEXT: vor.vv v8, v9, v8210; CHECK-NEXT: ret211 %v = call <16 x i8> @llvm.vp.bitreverse.v16i8(<16 x i8> %va, <16 x i1> splat (i1 true), i32 %evl)212 ret <16 x i8> %v213}214 215define <2 x i16> @vp_bitreverse_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {216; CHECK-LABEL: vp_bitreverse_v2i16:217; CHECK: # %bb.0:218; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma219; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t220; CHECK-NEXT: lui a0, 1221; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t222; CHECK-NEXT: addi a0, a0, -241223; CHECK-NEXT: vor.vv v8, v8, v9, v0.t224; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t225; CHECK-NEXT: vand.vx v9, v9, a0, v0.t226; CHECK-NEXT: vand.vx v8, v8, a0, v0.t227; CHECK-NEXT: lui a0, 3228; CHECK-NEXT: addi a0, a0, 819229; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t230; CHECK-NEXT: vor.vv v8, v9, v8, v0.t231; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t232; CHECK-NEXT: vand.vx v9, v9, a0, v0.t233; CHECK-NEXT: vand.vx v8, v8, a0, v0.t234; CHECK-NEXT: lui a0, 5235; CHECK-NEXT: addi a0, a0, 1365236; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t237; CHECK-NEXT: vor.vv v8, v9, v8, v0.t238; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t239; CHECK-NEXT: vand.vx v9, v9, a0, v0.t240; CHECK-NEXT: vand.vx v8, v8, a0, v0.t241; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t242; CHECK-NEXT: vor.vv v8, v9, v8, v0.t243; CHECK-NEXT: ret244 %v = call <2 x i16> @llvm.vp.bitreverse.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl)245 ret <2 x i16> %v246}247 248define <2 x i16> @vp_bitreverse_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {249; CHECK-LABEL: vp_bitreverse_v2i16_unmasked:250; CHECK: # %bb.0:251; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma252; CHECK-NEXT: vsrl.vi v9, v8, 8253; CHECK-NEXT: vsll.vi v8, v8, 8254; CHECK-NEXT: lui a0, 1255; CHECK-NEXT: vor.vv v8, v8, v9256; CHECK-NEXT: addi a0, a0, -241257; CHECK-NEXT: vsrl.vi v9, v8, 4258; CHECK-NEXT: vand.vx v8, v8, a0259; CHECK-NEXT: vand.vx v9, v9, a0260; CHECK-NEXT: lui a0, 3261; CHECK-NEXT: addi a0, a0, 819262; CHECK-NEXT: vsll.vi v8, v8, 4263; CHECK-NEXT: vor.vv v8, v9, v8264; CHECK-NEXT: vsrl.vi v9, v8, 2265; CHECK-NEXT: vand.vx v8, v8, a0266; CHECK-NEXT: vand.vx v9, v9, a0267; CHECK-NEXT: lui a0, 5268; CHECK-NEXT: addi a0, a0, 1365269; CHECK-NEXT: vsll.vi v8, v8, 2270; CHECK-NEXT: vor.vv v8, v9, v8271; CHECK-NEXT: vsrl.vi v9, v8, 1272; CHECK-NEXT: vand.vx v8, v8, a0273; CHECK-NEXT: vand.vx v9, v9, a0274; CHECK-NEXT: vadd.vv v8, v8, v8275; CHECK-NEXT: vor.vv v8, v9, v8276; CHECK-NEXT: ret277 %v = call <2 x i16> @llvm.vp.bitreverse.v2i16(<2 x i16> %va, <2 x i1> splat (i1 true), i32 %evl)278 ret <2 x i16> %v279}280 281define <4 x i16> @vp_bitreverse_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {282; CHECK-LABEL: vp_bitreverse_v4i16:283; CHECK: # %bb.0:284; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma285; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t286; CHECK-NEXT: lui a0, 1287; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t288; CHECK-NEXT: addi a0, a0, -241289; CHECK-NEXT: vor.vv v8, v8, v9, v0.t290; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t291; CHECK-NEXT: vand.vx v9, v9, a0, v0.t292; CHECK-NEXT: vand.vx v8, v8, a0, v0.t293; CHECK-NEXT: lui a0, 3294; CHECK-NEXT: addi a0, a0, 819295; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t296; CHECK-NEXT: vor.vv v8, v9, v8, v0.t297; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t298; CHECK-NEXT: vand.vx v9, v9, a0, v0.t299; CHECK-NEXT: vand.vx v8, v8, a0, v0.t300; CHECK-NEXT: lui a0, 5301; CHECK-NEXT: addi a0, a0, 1365302; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t303; CHECK-NEXT: vor.vv v8, v9, v8, v0.t304; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t305; CHECK-NEXT: vand.vx v9, v9, a0, v0.t306; CHECK-NEXT: vand.vx v8, v8, a0, v0.t307; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t308; CHECK-NEXT: vor.vv v8, v9, v8, v0.t309; CHECK-NEXT: ret310 %v = call <4 x i16> @llvm.vp.bitreverse.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)311 ret <4 x i16> %v312}313 314define <4 x i16> @vp_bitreverse_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {315; CHECK-LABEL: vp_bitreverse_v4i16_unmasked:316; CHECK: # %bb.0:317; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma318; CHECK-NEXT: vsrl.vi v9, v8, 8319; CHECK-NEXT: vsll.vi v8, v8, 8320; CHECK-NEXT: lui a0, 1321; CHECK-NEXT: vor.vv v8, v8, v9322; CHECK-NEXT: addi a0, a0, -241323; CHECK-NEXT: vsrl.vi v9, v8, 4324; CHECK-NEXT: vand.vx v8, v8, a0325; CHECK-NEXT: vand.vx v9, v9, a0326; CHECK-NEXT: lui a0, 3327; CHECK-NEXT: addi a0, a0, 819328; CHECK-NEXT: vsll.vi v8, v8, 4329; CHECK-NEXT: vor.vv v8, v9, v8330; CHECK-NEXT: vsrl.vi v9, v8, 2331; CHECK-NEXT: vand.vx v8, v8, a0332; CHECK-NEXT: vand.vx v9, v9, a0333; CHECK-NEXT: lui a0, 5334; CHECK-NEXT: addi a0, a0, 1365335; CHECK-NEXT: vsll.vi v8, v8, 2336; CHECK-NEXT: vor.vv v8, v9, v8337; CHECK-NEXT: vsrl.vi v9, v8, 1338; CHECK-NEXT: vand.vx v8, v8, a0339; CHECK-NEXT: vand.vx v9, v9, a0340; CHECK-NEXT: vadd.vv v8, v8, v8341; CHECK-NEXT: vor.vv v8, v9, v8342; CHECK-NEXT: ret343 %v = call <4 x i16> @llvm.vp.bitreverse.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl)344 ret <4 x i16> %v345}346 347define <8 x i16> @vp_bitreverse_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {348; CHECK-LABEL: vp_bitreverse_v8i16:349; CHECK: # %bb.0:350; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma351; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t352; CHECK-NEXT: lui a0, 1353; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t354; CHECK-NEXT: addi a0, a0, -241355; CHECK-NEXT: vor.vv v8, v8, v9, v0.t356; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t357; CHECK-NEXT: vand.vx v9, v9, a0, v0.t358; CHECK-NEXT: vand.vx v8, v8, a0, v0.t359; CHECK-NEXT: lui a0, 3360; CHECK-NEXT: addi a0, a0, 819361; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t362; CHECK-NEXT: vor.vv v8, v9, v8, v0.t363; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t364; CHECK-NEXT: vand.vx v9, v9, a0, v0.t365; CHECK-NEXT: vand.vx v8, v8, a0, v0.t366; CHECK-NEXT: lui a0, 5367; CHECK-NEXT: addi a0, a0, 1365368; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t369; CHECK-NEXT: vor.vv v8, v9, v8, v0.t370; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t371; CHECK-NEXT: vand.vx v9, v9, a0, v0.t372; CHECK-NEXT: vand.vx v8, v8, a0, v0.t373; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t374; CHECK-NEXT: vor.vv v8, v9, v8, v0.t375; CHECK-NEXT: ret376 %v = call <8 x i16> @llvm.vp.bitreverse.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl)377 ret <8 x i16> %v378}379 380define <8 x i16> @vp_bitreverse_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {381; CHECK-LABEL: vp_bitreverse_v8i16_unmasked:382; CHECK: # %bb.0:383; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma384; CHECK-NEXT: vsrl.vi v9, v8, 8385; CHECK-NEXT: vsll.vi v8, v8, 8386; CHECK-NEXT: lui a0, 1387; CHECK-NEXT: vor.vv v8, v8, v9388; CHECK-NEXT: addi a0, a0, -241389; CHECK-NEXT: vsrl.vi v9, v8, 4390; CHECK-NEXT: vand.vx v8, v8, a0391; CHECK-NEXT: vand.vx v9, v9, a0392; CHECK-NEXT: lui a0, 3393; CHECK-NEXT: addi a0, a0, 819394; CHECK-NEXT: vsll.vi v8, v8, 4395; CHECK-NEXT: vor.vv v8, v9, v8396; CHECK-NEXT: vsrl.vi v9, v8, 2397; CHECK-NEXT: vand.vx v8, v8, a0398; CHECK-NEXT: vand.vx v9, v9, a0399; CHECK-NEXT: lui a0, 5400; CHECK-NEXT: addi a0, a0, 1365401; CHECK-NEXT: vsll.vi v8, v8, 2402; CHECK-NEXT: vor.vv v8, v9, v8403; CHECK-NEXT: vsrl.vi v9, v8, 1404; CHECK-NEXT: vand.vx v8, v8, a0405; CHECK-NEXT: vand.vx v9, v9, a0406; CHECK-NEXT: vadd.vv v8, v8, v8407; CHECK-NEXT: vor.vv v8, v9, v8408; CHECK-NEXT: ret409 %v = call <8 x i16> @llvm.vp.bitreverse.v8i16(<8 x i16> %va, <8 x i1> splat (i1 true), i32 %evl)410 ret <8 x i16> %v411}412 413define <16 x i16> @vp_bitreverse_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {414; CHECK-LABEL: vp_bitreverse_v16i16:415; CHECK: # %bb.0:416; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma417; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t418; CHECK-NEXT: lui a0, 1419; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t420; CHECK-NEXT: addi a0, a0, -241421; CHECK-NEXT: vor.vv v8, v8, v10, v0.t422; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t423; CHECK-NEXT: vand.vx v10, v10, a0, v0.t424; CHECK-NEXT: vand.vx v8, v8, a0, v0.t425; CHECK-NEXT: lui a0, 3426; CHECK-NEXT: addi a0, a0, 819427; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t428; CHECK-NEXT: vor.vv v8, v10, v8, v0.t429; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t430; CHECK-NEXT: vand.vx v10, v10, a0, v0.t431; CHECK-NEXT: vand.vx v8, v8, a0, v0.t432; CHECK-NEXT: lui a0, 5433; CHECK-NEXT: addi a0, a0, 1365434; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t435; CHECK-NEXT: vor.vv v8, v10, v8, v0.t436; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t437; CHECK-NEXT: vand.vx v10, v10, a0, v0.t438; CHECK-NEXT: vand.vx v8, v8, a0, v0.t439; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t440; CHECK-NEXT: vor.vv v8, v10, v8, v0.t441; CHECK-NEXT: ret442 %v = call <16 x i16> @llvm.vp.bitreverse.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl)443 ret <16 x i16> %v444}445 446define <16 x i16> @vp_bitreverse_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {447; CHECK-LABEL: vp_bitreverse_v16i16_unmasked:448; CHECK: # %bb.0:449; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma450; CHECK-NEXT: vsrl.vi v10, v8, 8451; CHECK-NEXT: vsll.vi v8, v8, 8452; CHECK-NEXT: lui a0, 1453; CHECK-NEXT: vor.vv v8, v8, v10454; CHECK-NEXT: addi a0, a0, -241455; CHECK-NEXT: vsrl.vi v10, v8, 4456; CHECK-NEXT: vand.vx v8, v8, a0457; CHECK-NEXT: vand.vx v10, v10, a0458; CHECK-NEXT: lui a0, 3459; CHECK-NEXT: addi a0, a0, 819460; CHECK-NEXT: vsll.vi v8, v8, 4461; CHECK-NEXT: vor.vv v8, v10, v8462; CHECK-NEXT: vsrl.vi v10, v8, 2463; CHECK-NEXT: vand.vx v8, v8, a0464; CHECK-NEXT: vand.vx v10, v10, a0465; CHECK-NEXT: lui a0, 5466; CHECK-NEXT: addi a0, a0, 1365467; CHECK-NEXT: vsll.vi v8, v8, 2468; CHECK-NEXT: vor.vv v8, v10, v8469; CHECK-NEXT: vsrl.vi v10, v8, 1470; CHECK-NEXT: vand.vx v8, v8, a0471; CHECK-NEXT: vand.vx v10, v10, a0472; CHECK-NEXT: vadd.vv v8, v8, v8473; CHECK-NEXT: vor.vv v8, v10, v8474; CHECK-NEXT: ret475 %v = call <16 x i16> @llvm.vp.bitreverse.v16i16(<16 x i16> %va, <16 x i1> splat (i1 true), i32 %evl)476 ret <16 x i16> %v477}478 479define <2 x i32> @vp_bitreverse_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {480; CHECK-LABEL: vp_bitreverse_v2i32:481; CHECK: # %bb.0:482; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma483; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t484; CHECK-NEXT: lui a0, 16485; CHECK-NEXT: addi a0, a0, -256486; CHECK-NEXT: vand.vx v9, v9, a0, v0.t487; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t488; CHECK-NEXT: vor.vv v9, v9, v10, v0.t489; CHECK-NEXT: vand.vx v10, v8, a0, v0.t490; CHECK-NEXT: lui a0, 61681491; CHECK-NEXT: addi a0, a0, -241492; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t493; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t494; CHECK-NEXT: vor.vv v8, v8, v10, v0.t495; CHECK-NEXT: vor.vv v8, v8, v9, v0.t496; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t497; CHECK-NEXT: vand.vx v9, v9, a0, v0.t498; CHECK-NEXT: vand.vx v8, v8, a0, v0.t499; CHECK-NEXT: lui a0, 209715500; CHECK-NEXT: addi a0, a0, 819501; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t502; CHECK-NEXT: vor.vv v8, v9, v8, v0.t503; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t504; CHECK-NEXT: vand.vx v9, v9, a0, v0.t505; CHECK-NEXT: vand.vx v8, v8, a0, v0.t506; CHECK-NEXT: lui a0, 349525507; CHECK-NEXT: addi a0, a0, 1365508; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t509; CHECK-NEXT: vor.vv v8, v9, v8, v0.t510; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t511; CHECK-NEXT: vand.vx v9, v9, a0, v0.t512; CHECK-NEXT: vand.vx v8, v8, a0, v0.t513; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t514; CHECK-NEXT: vor.vv v8, v9, v8, v0.t515; CHECK-NEXT: ret516 %v = call <2 x i32> @llvm.vp.bitreverse.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl)517 ret <2 x i32> %v518}519 520define <2 x i32> @vp_bitreverse_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {521; CHECK-LABEL: vp_bitreverse_v2i32_unmasked:522; CHECK: # %bb.0:523; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma524; CHECK-NEXT: vsrl.vi v9, v8, 8525; CHECK-NEXT: lui a0, 16526; CHECK-NEXT: vsrl.vi v10, v8, 24527; CHECK-NEXT: addi a0, a0, -256528; CHECK-NEXT: vand.vx v9, v9, a0529; CHECK-NEXT: vor.vv v9, v9, v10530; CHECK-NEXT: vsll.vi v10, v8, 24531; CHECK-NEXT: vand.vx v8, v8, a0532; CHECK-NEXT: lui a0, 61681533; CHECK-NEXT: addi a0, a0, -241534; CHECK-NEXT: vsll.vi v8, v8, 8535; CHECK-NEXT: vor.vv v8, v10, v8536; CHECK-NEXT: vor.vv v8, v8, v9537; CHECK-NEXT: vsrl.vi v9, v8, 4538; CHECK-NEXT: vand.vx v8, v8, a0539; CHECK-NEXT: vand.vx v9, v9, a0540; CHECK-NEXT: lui a0, 209715541; CHECK-NEXT: addi a0, a0, 819542; CHECK-NEXT: vsll.vi v8, v8, 4543; CHECK-NEXT: vor.vv v8, v9, v8544; CHECK-NEXT: vsrl.vi v9, v8, 2545; CHECK-NEXT: vand.vx v8, v8, a0546; CHECK-NEXT: vand.vx v9, v9, a0547; CHECK-NEXT: lui a0, 349525548; CHECK-NEXT: addi a0, a0, 1365549; CHECK-NEXT: vsll.vi v8, v8, 2550; CHECK-NEXT: vor.vv v8, v9, v8551; CHECK-NEXT: vsrl.vi v9, v8, 1552; CHECK-NEXT: vand.vx v8, v8, a0553; CHECK-NEXT: vand.vx v9, v9, a0554; CHECK-NEXT: vadd.vv v8, v8, v8555; CHECK-NEXT: vor.vv v8, v9, v8556; CHECK-NEXT: ret557 %v = call <2 x i32> @llvm.vp.bitreverse.v2i32(<2 x i32> %va, <2 x i1> splat (i1 true), i32 %evl)558 ret <2 x i32> %v559}560 561define <4 x i32> @vp_bitreverse_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {562; CHECK-LABEL: vp_bitreverse_v4i32:563; CHECK: # %bb.0:564; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma565; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t566; CHECK-NEXT: lui a0, 16567; CHECK-NEXT: addi a0, a0, -256568; CHECK-NEXT: vand.vx v9, v9, a0, v0.t569; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t570; CHECK-NEXT: vor.vv v9, v9, v10, v0.t571; CHECK-NEXT: vand.vx v10, v8, a0, v0.t572; CHECK-NEXT: lui a0, 61681573; CHECK-NEXT: addi a0, a0, -241574; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t575; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t576; CHECK-NEXT: vor.vv v8, v8, v10, v0.t577; CHECK-NEXT: vor.vv v8, v8, v9, v0.t578; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t579; CHECK-NEXT: vand.vx v9, v9, a0, v0.t580; CHECK-NEXT: vand.vx v8, v8, a0, v0.t581; CHECK-NEXT: lui a0, 209715582; CHECK-NEXT: addi a0, a0, 819583; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t584; CHECK-NEXT: vor.vv v8, v9, v8, v0.t585; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t586; CHECK-NEXT: vand.vx v9, v9, a0, v0.t587; CHECK-NEXT: vand.vx v8, v8, a0, v0.t588; CHECK-NEXT: lui a0, 349525589; CHECK-NEXT: addi a0, a0, 1365590; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t591; CHECK-NEXT: vor.vv v8, v9, v8, v0.t592; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t593; CHECK-NEXT: vand.vx v9, v9, a0, v0.t594; CHECK-NEXT: vand.vx v8, v8, a0, v0.t595; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t596; CHECK-NEXT: vor.vv v8, v9, v8, v0.t597; CHECK-NEXT: ret598 %v = call <4 x i32> @llvm.vp.bitreverse.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)599 ret <4 x i32> %v600}601 602define <4 x i32> @vp_bitreverse_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {603; CHECK-LABEL: vp_bitreverse_v4i32_unmasked:604; CHECK: # %bb.0:605; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma606; CHECK-NEXT: vsrl.vi v9, v8, 8607; CHECK-NEXT: lui a0, 16608; CHECK-NEXT: vsrl.vi v10, v8, 24609; CHECK-NEXT: addi a0, a0, -256610; CHECK-NEXT: vand.vx v9, v9, a0611; CHECK-NEXT: vor.vv v9, v9, v10612; CHECK-NEXT: vsll.vi v10, v8, 24613; CHECK-NEXT: vand.vx v8, v8, a0614; CHECK-NEXT: lui a0, 61681615; CHECK-NEXT: addi a0, a0, -241616; CHECK-NEXT: vsll.vi v8, v8, 8617; CHECK-NEXT: vor.vv v8, v10, v8618; CHECK-NEXT: vor.vv v8, v8, v9619; CHECK-NEXT: vsrl.vi v9, v8, 4620; CHECK-NEXT: vand.vx v8, v8, a0621; CHECK-NEXT: vand.vx v9, v9, a0622; CHECK-NEXT: lui a0, 209715623; CHECK-NEXT: addi a0, a0, 819624; CHECK-NEXT: vsll.vi v8, v8, 4625; CHECK-NEXT: vor.vv v8, v9, v8626; CHECK-NEXT: vsrl.vi v9, v8, 2627; CHECK-NEXT: vand.vx v8, v8, a0628; CHECK-NEXT: vand.vx v9, v9, a0629; CHECK-NEXT: lui a0, 349525630; CHECK-NEXT: addi a0, a0, 1365631; CHECK-NEXT: vsll.vi v8, v8, 2632; CHECK-NEXT: vor.vv v8, v9, v8633; CHECK-NEXT: vsrl.vi v9, v8, 1634; CHECK-NEXT: vand.vx v8, v8, a0635; CHECK-NEXT: vand.vx v9, v9, a0636; CHECK-NEXT: vadd.vv v8, v8, v8637; CHECK-NEXT: vor.vv v8, v9, v8638; CHECK-NEXT: ret639 %v = call <4 x i32> @llvm.vp.bitreverse.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl)640 ret <4 x i32> %v641}642 643define <8 x i32> @vp_bitreverse_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {644; CHECK-LABEL: vp_bitreverse_v8i32:645; CHECK: # %bb.0:646; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma647; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t648; CHECK-NEXT: lui a0, 16649; CHECK-NEXT: addi a0, a0, -256650; CHECK-NEXT: vand.vx v10, v10, a0, v0.t651; CHECK-NEXT: vsrl.vi v12, v8, 24, v0.t652; CHECK-NEXT: vor.vv v10, v10, v12, v0.t653; CHECK-NEXT: vand.vx v12, v8, a0, v0.t654; CHECK-NEXT: lui a0, 61681655; CHECK-NEXT: addi a0, a0, -241656; CHECK-NEXT: vsll.vi v12, v12, 8, v0.t657; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t658; CHECK-NEXT: vor.vv v8, v8, v12, v0.t659; CHECK-NEXT: vor.vv v8, v8, v10, v0.t660; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t661; CHECK-NEXT: vand.vx v10, v10, a0, v0.t662; CHECK-NEXT: vand.vx v8, v8, a0, v0.t663; CHECK-NEXT: lui a0, 209715664; CHECK-NEXT: addi a0, a0, 819665; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t666; CHECK-NEXT: vor.vv v8, v10, v8, v0.t667; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t668; CHECK-NEXT: vand.vx v10, v10, a0, v0.t669; CHECK-NEXT: vand.vx v8, v8, a0, v0.t670; CHECK-NEXT: lui a0, 349525671; CHECK-NEXT: addi a0, a0, 1365672; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t673; CHECK-NEXT: vor.vv v8, v10, v8, v0.t674; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t675; CHECK-NEXT: vand.vx v10, v10, a0, v0.t676; CHECK-NEXT: vand.vx v8, v8, a0, v0.t677; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t678; CHECK-NEXT: vor.vv v8, v10, v8, v0.t679; CHECK-NEXT: ret680 %v = call <8 x i32> @llvm.vp.bitreverse.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl)681 ret <8 x i32> %v682}683 684define <8 x i32> @vp_bitreverse_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {685; CHECK-LABEL: vp_bitreverse_v8i32_unmasked:686; CHECK: # %bb.0:687; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma688; CHECK-NEXT: vsrl.vi v10, v8, 8689; CHECK-NEXT: lui a0, 16690; CHECK-NEXT: vsrl.vi v12, v8, 24691; CHECK-NEXT: addi a0, a0, -256692; CHECK-NEXT: vand.vx v10, v10, a0693; CHECK-NEXT: vor.vv v10, v10, v12694; CHECK-NEXT: vsll.vi v12, v8, 24695; CHECK-NEXT: vand.vx v8, v8, a0696; CHECK-NEXT: lui a0, 61681697; CHECK-NEXT: addi a0, a0, -241698; CHECK-NEXT: vsll.vi v8, v8, 8699; CHECK-NEXT: vor.vv v8, v12, v8700; CHECK-NEXT: vor.vv v8, v8, v10701; CHECK-NEXT: vsrl.vi v10, v8, 4702; CHECK-NEXT: vand.vx v8, v8, a0703; CHECK-NEXT: vand.vx v10, v10, a0704; CHECK-NEXT: lui a0, 209715705; CHECK-NEXT: addi a0, a0, 819706; CHECK-NEXT: vsll.vi v8, v8, 4707; CHECK-NEXT: vor.vv v8, v10, v8708; CHECK-NEXT: vsrl.vi v10, v8, 2709; CHECK-NEXT: vand.vx v8, v8, a0710; CHECK-NEXT: vand.vx v10, v10, a0711; CHECK-NEXT: lui a0, 349525712; CHECK-NEXT: addi a0, a0, 1365713; CHECK-NEXT: vsll.vi v8, v8, 2714; CHECK-NEXT: vor.vv v8, v10, v8715; CHECK-NEXT: vsrl.vi v10, v8, 1716; CHECK-NEXT: vand.vx v8, v8, a0717; CHECK-NEXT: vand.vx v10, v10, a0718; CHECK-NEXT: vadd.vv v8, v8, v8719; CHECK-NEXT: vor.vv v8, v10, v8720; CHECK-NEXT: ret721 %v = call <8 x i32> @llvm.vp.bitreverse.v8i32(<8 x i32> %va, <8 x i1> splat (i1 true), i32 %evl)722 ret <8 x i32> %v723}724 725define <16 x i32> @vp_bitreverse_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {726; CHECK-LABEL: vp_bitreverse_v16i32:727; CHECK: # %bb.0:728; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma729; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t730; CHECK-NEXT: lui a0, 16731; CHECK-NEXT: addi a0, a0, -256732; CHECK-NEXT: vand.vx v12, v12, a0, v0.t733; CHECK-NEXT: vsrl.vi v16, v8, 24, v0.t734; CHECK-NEXT: vor.vv v12, v12, v16, v0.t735; CHECK-NEXT: vand.vx v16, v8, a0, v0.t736; CHECK-NEXT: lui a0, 61681737; CHECK-NEXT: addi a0, a0, -241738; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t739; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t740; CHECK-NEXT: vor.vv v8, v8, v16, v0.t741; CHECK-NEXT: vor.vv v8, v8, v12, v0.t742; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t743; CHECK-NEXT: vand.vx v12, v12, a0, v0.t744; CHECK-NEXT: vand.vx v8, v8, a0, v0.t745; CHECK-NEXT: lui a0, 209715746; CHECK-NEXT: addi a0, a0, 819747; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t748; CHECK-NEXT: vor.vv v8, v12, v8, v0.t749; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t750; CHECK-NEXT: vand.vx v12, v12, a0, v0.t751; CHECK-NEXT: vand.vx v8, v8, a0, v0.t752; CHECK-NEXT: lui a0, 349525753; CHECK-NEXT: addi a0, a0, 1365754; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t755; CHECK-NEXT: vor.vv v8, v12, v8, v0.t756; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t757; CHECK-NEXT: vand.vx v12, v12, a0, v0.t758; CHECK-NEXT: vand.vx v8, v8, a0, v0.t759; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t760; CHECK-NEXT: vor.vv v8, v12, v8, v0.t761; CHECK-NEXT: ret762 %v = call <16 x i32> @llvm.vp.bitreverse.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl)763 ret <16 x i32> %v764}765 766define <16 x i32> @vp_bitreverse_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {767; CHECK-LABEL: vp_bitreverse_v16i32_unmasked:768; CHECK: # %bb.0:769; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma770; CHECK-NEXT: vsrl.vi v12, v8, 8771; CHECK-NEXT: lui a0, 16772; CHECK-NEXT: vsrl.vi v16, v8, 24773; CHECK-NEXT: addi a0, a0, -256774; CHECK-NEXT: vand.vx v12, v12, a0775; CHECK-NEXT: vor.vv v12, v12, v16776; CHECK-NEXT: vsll.vi v16, v8, 24777; CHECK-NEXT: vand.vx v8, v8, a0778; CHECK-NEXT: lui a0, 61681779; CHECK-NEXT: addi a0, a0, -241780; CHECK-NEXT: vsll.vi v8, v8, 8781; CHECK-NEXT: vor.vv v8, v16, v8782; CHECK-NEXT: vor.vv v8, v8, v12783; CHECK-NEXT: vsrl.vi v12, v8, 4784; CHECK-NEXT: vand.vx v8, v8, a0785; CHECK-NEXT: vand.vx v12, v12, a0786; CHECK-NEXT: lui a0, 209715787; CHECK-NEXT: addi a0, a0, 819788; CHECK-NEXT: vsll.vi v8, v8, 4789; CHECK-NEXT: vor.vv v8, v12, v8790; CHECK-NEXT: vsrl.vi v12, v8, 2791; CHECK-NEXT: vand.vx v8, v8, a0792; CHECK-NEXT: vand.vx v12, v12, a0793; CHECK-NEXT: lui a0, 349525794; CHECK-NEXT: addi a0, a0, 1365795; CHECK-NEXT: vsll.vi v8, v8, 2796; CHECK-NEXT: vor.vv v8, v12, v8797; CHECK-NEXT: vsrl.vi v12, v8, 1798; CHECK-NEXT: vand.vx v8, v8, a0799; CHECK-NEXT: vand.vx v12, v12, a0800; CHECK-NEXT: vadd.vv v8, v8, v8801; CHECK-NEXT: vor.vv v8, v12, v8802; CHECK-NEXT: ret803 %v = call <16 x i32> @llvm.vp.bitreverse.v16i32(<16 x i32> %va, <16 x i1> splat (i1 true), i32 %evl)804 ret <16 x i32> %v805}806 807define <2 x i64> @vp_bitreverse_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {808; RV32-LABEL: vp_bitreverse_v2i64:809; RV32: # %bb.0:810; RV32-NEXT: addi sp, sp, -16811; RV32-NEXT: .cfi_def_cfa_offset 16812; RV32-NEXT: lui a4, 1044480813; RV32-NEXT: li a3, 56814; RV32-NEXT: lui a5, 16815; RV32-NEXT: li a2, 40816; RV32-NEXT: lui a1, 4080817; RV32-NEXT: addi a6, sp, 8818; RV32-NEXT: sw a4, 8(sp)819; RV32-NEXT: sw zero, 12(sp)820; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma821; RV32-NEXT: vlse64.v v9, (a6), zero822; RV32-NEXT: lui a4, 61681823; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma824; RV32-NEXT: vsll.vx v10, v8, a3, v0.t825; RV32-NEXT: addi a5, a5, -256826; RV32-NEXT: vand.vx v11, v8, a5, v0.t827; RV32-NEXT: vsll.vx v11, v11, a2, v0.t828; RV32-NEXT: vor.vv v10, v10, v11, v0.t829; RV32-NEXT: vand.vx v11, v8, a1, v0.t830; RV32-NEXT: vsll.vi v11, v11, 24, v0.t831; RV32-NEXT: vand.vv v12, v8, v9, v0.t832; RV32-NEXT: vsll.vi v12, v12, 8, v0.t833; RV32-NEXT: vor.vv v11, v11, v12, v0.t834; RV32-NEXT: vor.vv v10, v10, v11, v0.t835; RV32-NEXT: vsrl.vx v11, v8, a3, v0.t836; RV32-NEXT: lui a3, 209715837; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t838; RV32-NEXT: lui a2, 349525839; RV32-NEXT: addi a4, a4, -241840; RV32-NEXT: addi a3, a3, 819841; RV32-NEXT: addi a2, a2, 1365842; RV32-NEXT: vand.vx v12, v12, a5, v0.t843; RV32-NEXT: vor.vv v11, v12, v11, v0.t844; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t845; RV32-NEXT: vand.vx v12, v12, a1, v0.t846; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t847; RV32-NEXT: vand.vv v8, v8, v9, v0.t848; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma849; RV32-NEXT: vmv.v.x v9, a4850; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma851; RV32-NEXT: vor.vv v8, v8, v12, v0.t852; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma853; RV32-NEXT: vmv.v.x v12, a3854; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma855; RV32-NEXT: vor.vv v8, v8, v11, v0.t856; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma857; RV32-NEXT: vmv.v.x v11, a2858; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma859; RV32-NEXT: vor.vv v8, v10, v8, v0.t860; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t861; RV32-NEXT: vand.vv v10, v10, v9, v0.t862; RV32-NEXT: vand.vv v8, v8, v9, v0.t863; RV32-NEXT: vsll.vi v8, v8, 4, v0.t864; RV32-NEXT: vor.vv v8, v10, v8, v0.t865; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t866; RV32-NEXT: vand.vv v9, v9, v12, v0.t867; RV32-NEXT: vand.vv v8, v8, v12, v0.t868; RV32-NEXT: vsll.vi v8, v8, 2, v0.t869; RV32-NEXT: vor.vv v8, v9, v8, v0.t870; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t871; RV32-NEXT: vand.vv v9, v9, v11, v0.t872; RV32-NEXT: vand.vv v8, v8, v11, v0.t873; RV32-NEXT: vsll.vi v8, v8, 1, v0.t874; RV32-NEXT: vor.vv v8, v9, v8, v0.t875; RV32-NEXT: addi sp, sp, 16876; RV32-NEXT: .cfi_def_cfa_offset 0877; RV32-NEXT: ret878;879; RV64-LABEL: vp_bitreverse_v2i64:880; RV64: # %bb.0:881; RV64-NEXT: lui a1, 4080882; RV64-NEXT: li a3, 255883; RV64-NEXT: li a2, 56884; RV64-NEXT: lui a4, 16885; RV64-NEXT: lui a5, 61681886; RV64-NEXT: lui a6, 209715887; RV64-NEXT: lui a7, 349525888; RV64-NEXT: addi a5, a5, -241889; RV64-NEXT: addi a6, a6, 819890; RV64-NEXT: addi a7, a7, 1365891; RV64-NEXT: slli t0, a5, 32892; RV64-NEXT: add t0, a5, t0893; RV64-NEXT: slli a5, a6, 32894; RV64-NEXT: add a6, a6, a5895; RV64-NEXT: slli a5, a7, 32896; RV64-NEXT: add a5, a7, a5897; RV64-NEXT: li a7, 40898; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma899; RV64-NEXT: vand.vx v9, v8, a1, v0.t900; RV64-NEXT: slli a3, a3, 24901; RV64-NEXT: addi a0, a4, -256902; RV64-NEXT: vsll.vi v9, v9, 24, v0.t903; RV64-NEXT: vand.vx v10, v8, a3, v0.t904; RV64-NEXT: vsll.vi v10, v10, 8, v0.t905; RV64-NEXT: vor.vv v9, v9, v10, v0.t906; RV64-NEXT: vsll.vx v10, v8, a2, v0.t907; RV64-NEXT: vand.vx v11, v8, a0, v0.t908; RV64-NEXT: vsll.vx v11, v11, a7, v0.t909; RV64-NEXT: vor.vv v10, v10, v11, v0.t910; RV64-NEXT: vor.vv v9, v10, v9, v0.t911; RV64-NEXT: vsrl.vx v10, v8, a2, v0.t912; RV64-NEXT: vsrl.vx v11, v8, a7, v0.t913; RV64-NEXT: vand.vx v11, v11, a0, v0.t914; RV64-NEXT: vor.vv v10, v11, v10, v0.t915; RV64-NEXT: vsrl.vi v11, v8, 24, v0.t916; RV64-NEXT: vand.vx v11, v11, a1, v0.t917; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t918; RV64-NEXT: vand.vx v8, v8, a3, v0.t919; RV64-NEXT: vor.vv v8, v8, v11, v0.t920; RV64-NEXT: vor.vv v8, v8, v10, v0.t921; RV64-NEXT: vor.vv v8, v9, v8, v0.t922; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t923; RV64-NEXT: vand.vx v9, v9, t0, v0.t924; RV64-NEXT: vand.vx v8, v8, t0, v0.t925; RV64-NEXT: vsll.vi v8, v8, 4, v0.t926; RV64-NEXT: vor.vv v8, v9, v8, v0.t927; RV64-NEXT: vsrl.vi v9, v8, 2, v0.t928; RV64-NEXT: vand.vx v9, v9, a6, v0.t929; RV64-NEXT: vand.vx v8, v8, a6, v0.t930; RV64-NEXT: vsll.vi v8, v8, 2, v0.t931; RV64-NEXT: vor.vv v8, v9, v8, v0.t932; RV64-NEXT: vsrl.vi v9, v8, 1, v0.t933; RV64-NEXT: vand.vx v9, v9, a5, v0.t934; RV64-NEXT: vand.vx v8, v8, a5, v0.t935; RV64-NEXT: vsll.vi v8, v8, 1, v0.t936; RV64-NEXT: vor.vv v8, v9, v8, v0.t937; RV64-NEXT: ret938 %v = call <2 x i64> @llvm.vp.bitreverse.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl)939 ret <2 x i64> %v940}941 942define <2 x i64> @vp_bitreverse_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {943; RV32-LABEL: vp_bitreverse_v2i64_unmasked:944; RV32: # %bb.0:945; RV32-NEXT: addi sp, sp, -16946; RV32-NEXT: .cfi_def_cfa_offset 16947; RV32-NEXT: lui a1, 1044480948; RV32-NEXT: li a2, 56949; RV32-NEXT: lui a3, 16950; RV32-NEXT: li a4, 40951; RV32-NEXT: lui a5, 4080952; RV32-NEXT: addi a6, sp, 8953; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma954; RV32-NEXT: vsrl.vi v9, v8, 24955; RV32-NEXT: sw a1, 8(sp)956; RV32-NEXT: sw zero, 12(sp)957; RV32-NEXT: vsll.vx v10, v8, a2958; RV32-NEXT: addi a1, a3, -256959; RV32-NEXT: vsrl.vx v11, v8, a2960; RV32-NEXT: vsrl.vx v12, v8, a4961; RV32-NEXT: vand.vx v13, v8, a1962; RV32-NEXT: vand.vx v12, v12, a1963; RV32-NEXT: vor.vv v11, v12, v11964; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma965; RV32-NEXT: vlse64.v v12, (a6), zero966; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma967; RV32-NEXT: vsll.vx v13, v13, a4968; RV32-NEXT: vor.vv v10, v10, v13969; RV32-NEXT: vsrl.vi v13, v8, 8970; RV32-NEXT: vand.vx v9, v9, a5971; RV32-NEXT: vand.vv v13, v13, v12972; RV32-NEXT: vor.vv v9, v13, v9973; RV32-NEXT: lui a1, 61681974; RV32-NEXT: lui a2, 209715975; RV32-NEXT: lui a3, 349525976; RV32-NEXT: vand.vv v12, v8, v12977; RV32-NEXT: vand.vx v8, v8, a5978; RV32-NEXT: addi a1, a1, -241979; RV32-NEXT: addi a2, a2, 819980; RV32-NEXT: addi a3, a3, 1365981; RV32-NEXT: vsll.vi v8, v8, 24982; RV32-NEXT: vsll.vi v12, v12, 8983; RV32-NEXT: vor.vv v8, v8, v12984; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma985; RV32-NEXT: vmv.v.x v12, a1986; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma987; RV32-NEXT: vor.vv v9, v9, v11988; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma989; RV32-NEXT: vmv.v.x v11, a2990; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma991; RV32-NEXT: vor.vv v8, v10, v8992; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma993; RV32-NEXT: vmv.v.x v10, a3994; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma995; RV32-NEXT: vor.vv v8, v8, v9996; RV32-NEXT: vsrl.vi v9, v8, 4997; RV32-NEXT: vand.vv v8, v8, v12998; RV32-NEXT: vand.vv v9, v9, v12999; RV32-NEXT: vsll.vi v8, v8, 41000; RV32-NEXT: vor.vv v8, v9, v81001; RV32-NEXT: vsrl.vi v9, v8, 21002; RV32-NEXT: vand.vv v8, v8, v111003; RV32-NEXT: vand.vv v9, v9, v111004; RV32-NEXT: vsll.vi v8, v8, 21005; RV32-NEXT: vor.vv v8, v9, v81006; RV32-NEXT: vsrl.vi v9, v8, 11007; RV32-NEXT: vand.vv v8, v8, v101008; RV32-NEXT: vand.vv v9, v9, v101009; RV32-NEXT: vadd.vv v8, v8, v81010; RV32-NEXT: vor.vv v8, v9, v81011; RV32-NEXT: addi sp, sp, 161012; RV32-NEXT: .cfi_def_cfa_offset 01013; RV32-NEXT: ret1014;1015; RV64-LABEL: vp_bitreverse_v2i64_unmasked:1016; RV64: # %bb.0:1017; RV64-NEXT: lui a1, 40801018; RV64-NEXT: li a2, 2551019; RV64-NEXT: li a3, 561020; RV64-NEXT: lui a4, 161021; RV64-NEXT: li a5, 401022; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma1023; RV64-NEXT: vsrl.vi v9, v8, 241024; RV64-NEXT: vsrl.vi v10, v8, 81025; RV64-NEXT: addi a0, a4, -2561026; RV64-NEXT: vsrl.vx v11, v8, a31027; RV64-NEXT: vsrl.vx v12, v8, a51028; RV64-NEXT: vand.vx v12, v12, a01029; RV64-NEXT: vor.vv v11, v12, v111030; RV64-NEXT: vand.vx v12, v8, a11031; RV64-NEXT: slli a2, a2, 241032; RV64-NEXT: vand.vx v9, v9, a11033; RV64-NEXT: vsll.vi v12, v12, 241034; RV64-NEXT: vand.vx v10, v10, a21035; RV64-NEXT: vor.vv v9, v10, v91036; RV64-NEXT: vand.vx v10, v8, a21037; RV64-NEXT: vsll.vi v10, v10, 81038; RV64-NEXT: vor.vv v10, v12, v101039; RV64-NEXT: vsll.vx v12, v8, a31040; RV64-NEXT: vand.vx v8, v8, a01041; RV64-NEXT: vsll.vx v8, v8, a51042; RV64-NEXT: vor.vv v8, v12, v81043; RV64-NEXT: lui a0, 616811044; RV64-NEXT: lui a1, 2097151045; RV64-NEXT: lui a2, 3495251046; RV64-NEXT: addi a0, a0, -2411047; RV64-NEXT: addi a1, a1, 8191048; RV64-NEXT: addi a2, a2, 13651049; RV64-NEXT: slli a3, a0, 321050; RV64-NEXT: slli a4, a1, 321051; RV64-NEXT: add a0, a0, a31052; RV64-NEXT: slli a3, a2, 321053; RV64-NEXT: add a1, a1, a41054; RV64-NEXT: add a2, a2, a31055; RV64-NEXT: vor.vv v9, v9, v111056; RV64-NEXT: vor.vv v8, v8, v101057; RV64-NEXT: vor.vv v8, v8, v91058; RV64-NEXT: vsrl.vi v9, v8, 41059; RV64-NEXT: vand.vx v8, v8, a01060; RV64-NEXT: vand.vx v9, v9, a01061; RV64-NEXT: vsll.vi v8, v8, 41062; RV64-NEXT: vor.vv v8, v9, v81063; RV64-NEXT: vsrl.vi v9, v8, 21064; RV64-NEXT: vand.vx v8, v8, a11065; RV64-NEXT: vand.vx v9, v9, a11066; RV64-NEXT: vsll.vi v8, v8, 21067; RV64-NEXT: vor.vv v8, v9, v81068; RV64-NEXT: vsrl.vi v9, v8, 11069; RV64-NEXT: vand.vx v8, v8, a21070; RV64-NEXT: vand.vx v9, v9, a21071; RV64-NEXT: vadd.vv v8, v8, v81072; RV64-NEXT: vor.vv v8, v9, v81073; RV64-NEXT: ret1074 %v = call <2 x i64> @llvm.vp.bitreverse.v2i64(<2 x i64> %va, <2 x i1> splat (i1 true), i32 %evl)1075 ret <2 x i64> %v1076}1077 1078define <4 x i64> @vp_bitreverse_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {1079; RV32-LABEL: vp_bitreverse_v4i64:1080; RV32: # %bb.0:1081; RV32-NEXT: addi sp, sp, -161082; RV32-NEXT: .cfi_def_cfa_offset 161083; RV32-NEXT: lui a4, 10444801084; RV32-NEXT: li a3, 561085; RV32-NEXT: lui a5, 161086; RV32-NEXT: li a2, 401087; RV32-NEXT: lui a1, 40801088; RV32-NEXT: addi a6, sp, 81089; RV32-NEXT: sw a4, 8(sp)1090; RV32-NEXT: sw zero, 12(sp)1091; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1092; RV32-NEXT: vlse64.v v10, (a6), zero1093; RV32-NEXT: lui a4, 616811094; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1095; RV32-NEXT: vsll.vx v12, v8, a3, v0.t1096; RV32-NEXT: addi a5, a5, -2561097; RV32-NEXT: vand.vx v14, v8, a5, v0.t1098; RV32-NEXT: vsll.vx v14, v14, a2, v0.t1099; RV32-NEXT: vor.vv v12, v12, v14, v0.t1100; RV32-NEXT: vand.vx v14, v8, a1, v0.t1101; RV32-NEXT: vsll.vi v14, v14, 24, v0.t1102; RV32-NEXT: vand.vv v16, v8, v10, v0.t1103; RV32-NEXT: vsll.vi v16, v16, 8, v0.t1104; RV32-NEXT: vor.vv v14, v14, v16, v0.t1105; RV32-NEXT: vor.vv v12, v12, v14, v0.t1106; RV32-NEXT: vsrl.vx v14, v8, a3, v0.t1107; RV32-NEXT: lui a3, 2097151108; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t1109; RV32-NEXT: lui a2, 3495251110; RV32-NEXT: addi a4, a4, -2411111; RV32-NEXT: addi a3, a3, 8191112; RV32-NEXT: addi a2, a2, 13651113; RV32-NEXT: vand.vx v16, v16, a5, v0.t1114; RV32-NEXT: vor.vv v14, v16, v14, v0.t1115; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t1116; RV32-NEXT: vand.vx v16, v16, a1, v0.t1117; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t1118; RV32-NEXT: vand.vv v8, v8, v10, v0.t1119; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1120; RV32-NEXT: vmv.v.x v10, a41121; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1122; RV32-NEXT: vor.vv v8, v8, v16, v0.t1123; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1124; RV32-NEXT: vmv.v.x v16, a31125; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1126; RV32-NEXT: vor.vv v8, v8, v14, v0.t1127; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1128; RV32-NEXT: vmv.v.x v14, a21129; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1130; RV32-NEXT: vor.vv v8, v12, v8, v0.t1131; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t1132; RV32-NEXT: vand.vv v12, v12, v10, v0.t1133; RV32-NEXT: vand.vv v8, v8, v10, v0.t1134; RV32-NEXT: vsll.vi v8, v8, 4, v0.t1135; RV32-NEXT: vor.vv v8, v12, v8, v0.t1136; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t1137; RV32-NEXT: vand.vv v10, v10, v16, v0.t1138; RV32-NEXT: vand.vv v8, v8, v16, v0.t1139; RV32-NEXT: vsll.vi v8, v8, 2, v0.t1140; RV32-NEXT: vor.vv v8, v10, v8, v0.t1141; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t1142; RV32-NEXT: vand.vv v10, v10, v14, v0.t1143; RV32-NEXT: vand.vv v8, v8, v14, v0.t1144; RV32-NEXT: vsll.vi v8, v8, 1, v0.t1145; RV32-NEXT: vor.vv v8, v10, v8, v0.t1146; RV32-NEXT: addi sp, sp, 161147; RV32-NEXT: .cfi_def_cfa_offset 01148; RV32-NEXT: ret1149;1150; RV64-LABEL: vp_bitreverse_v4i64:1151; RV64: # %bb.0:1152; RV64-NEXT: lui a1, 40801153; RV64-NEXT: li a3, 2551154; RV64-NEXT: li a2, 561155; RV64-NEXT: lui a4, 161156; RV64-NEXT: lui a5, 616811157; RV64-NEXT: lui a6, 2097151158; RV64-NEXT: lui a7, 3495251159; RV64-NEXT: addi a5, a5, -2411160; RV64-NEXT: addi a6, a6, 8191161; RV64-NEXT: addi a7, a7, 13651162; RV64-NEXT: slli t0, a5, 321163; RV64-NEXT: add t0, a5, t01164; RV64-NEXT: slli a5, a6, 321165; RV64-NEXT: add a6, a6, a51166; RV64-NEXT: slli a5, a7, 321167; RV64-NEXT: add a5, a7, a51168; RV64-NEXT: li a7, 401169; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma1170; RV64-NEXT: vand.vx v10, v8, a1, v0.t1171; RV64-NEXT: slli a3, a3, 241172; RV64-NEXT: addi a0, a4, -2561173; RV64-NEXT: vsll.vi v10, v10, 24, v0.t1174; RV64-NEXT: vand.vx v12, v8, a3, v0.t1175; RV64-NEXT: vsll.vi v12, v12, 8, v0.t1176; RV64-NEXT: vor.vv v10, v10, v12, v0.t1177; RV64-NEXT: vsll.vx v12, v8, a2, v0.t1178; RV64-NEXT: vand.vx v14, v8, a0, v0.t1179; RV64-NEXT: vsll.vx v14, v14, a7, v0.t1180; RV64-NEXT: vor.vv v12, v12, v14, v0.t1181; RV64-NEXT: vor.vv v10, v12, v10, v0.t1182; RV64-NEXT: vsrl.vx v12, v8, a2, v0.t1183; RV64-NEXT: vsrl.vx v14, v8, a7, v0.t1184; RV64-NEXT: vand.vx v14, v14, a0, v0.t1185; RV64-NEXT: vor.vv v12, v14, v12, v0.t1186; RV64-NEXT: vsrl.vi v14, v8, 24, v0.t1187; RV64-NEXT: vand.vx v14, v14, a1, v0.t1188; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t1189; RV64-NEXT: vand.vx v8, v8, a3, v0.t1190; RV64-NEXT: vor.vv v8, v8, v14, v0.t1191; RV64-NEXT: vor.vv v8, v8, v12, v0.t1192; RV64-NEXT: vor.vv v8, v10, v8, v0.t1193; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t1194; RV64-NEXT: vand.vx v10, v10, t0, v0.t1195; RV64-NEXT: vand.vx v8, v8, t0, v0.t1196; RV64-NEXT: vsll.vi v8, v8, 4, v0.t1197; RV64-NEXT: vor.vv v8, v10, v8, v0.t1198; RV64-NEXT: vsrl.vi v10, v8, 2, v0.t1199; RV64-NEXT: vand.vx v10, v10, a6, v0.t1200; RV64-NEXT: vand.vx v8, v8, a6, v0.t1201; RV64-NEXT: vsll.vi v8, v8, 2, v0.t1202; RV64-NEXT: vor.vv v8, v10, v8, v0.t1203; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t1204; RV64-NEXT: vand.vx v10, v10, a5, v0.t1205; RV64-NEXT: vand.vx v8, v8, a5, v0.t1206; RV64-NEXT: vsll.vi v8, v8, 1, v0.t1207; RV64-NEXT: vor.vv v8, v10, v8, v0.t1208; RV64-NEXT: ret1209 %v = call <4 x i64> @llvm.vp.bitreverse.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)1210 ret <4 x i64> %v1211}1212 1213define <4 x i64> @vp_bitreverse_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {1214; RV32-LABEL: vp_bitreverse_v4i64_unmasked:1215; RV32: # %bb.0:1216; RV32-NEXT: addi sp, sp, -161217; RV32-NEXT: .cfi_def_cfa_offset 161218; RV32-NEXT: lui a1, 10444801219; RV32-NEXT: li a2, 561220; RV32-NEXT: lui a3, 161221; RV32-NEXT: li a4, 401222; RV32-NEXT: lui a5, 40801223; RV32-NEXT: addi a6, sp, 81224; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1225; RV32-NEXT: vsrl.vi v14, v8, 241226; RV32-NEXT: sw a1, 8(sp)1227; RV32-NEXT: sw zero, 12(sp)1228; RV32-NEXT: vsll.vx v12, v8, a21229; RV32-NEXT: addi a1, a3, -2561230; RV32-NEXT: vsrl.vx v10, v8, a21231; RV32-NEXT: vsrl.vx v16, v8, a41232; RV32-NEXT: vand.vx v18, v8, a11233; RV32-NEXT: vand.vx v16, v16, a11234; RV32-NEXT: vor.vv v10, v16, v101235; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1236; RV32-NEXT: vlse64.v v16, (a6), zero1237; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1238; RV32-NEXT: vsll.vx v18, v18, a41239; RV32-NEXT: vor.vv v12, v12, v181240; RV32-NEXT: vsrl.vi v18, v8, 81241; RV32-NEXT: vand.vx v14, v14, a51242; RV32-NEXT: vand.vv v18, v18, v161243; RV32-NEXT: vor.vv v14, v18, v141244; RV32-NEXT: lui a1, 616811245; RV32-NEXT: lui a2, 2097151246; RV32-NEXT: lui a3, 3495251247; RV32-NEXT: vand.vv v16, v8, v161248; RV32-NEXT: vand.vx v8, v8, a51249; RV32-NEXT: addi a1, a1, -2411250; RV32-NEXT: addi a2, a2, 8191251; RV32-NEXT: addi a3, a3, 13651252; RV32-NEXT: vsll.vi v8, v8, 241253; RV32-NEXT: vsll.vi v16, v16, 81254; RV32-NEXT: vor.vv v8, v8, v161255; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1256; RV32-NEXT: vmv.v.x v16, a11257; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1258; RV32-NEXT: vor.vv v10, v14, v101259; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1260; RV32-NEXT: vmv.v.x v14, a21261; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1262; RV32-NEXT: vor.vv v8, v12, v81263; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1264; RV32-NEXT: vmv.v.x v12, a31265; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1266; RV32-NEXT: vor.vv v8, v8, v101267; RV32-NEXT: vsrl.vi v10, v8, 41268; RV32-NEXT: vand.vv v8, v8, v161269; RV32-NEXT: vand.vv v10, v10, v161270; RV32-NEXT: vsll.vi v8, v8, 41271; RV32-NEXT: vor.vv v8, v10, v81272; RV32-NEXT: vsrl.vi v10, v8, 21273; RV32-NEXT: vand.vv v8, v8, v141274; RV32-NEXT: vand.vv v10, v10, v141275; RV32-NEXT: vsll.vi v8, v8, 21276; RV32-NEXT: vor.vv v8, v10, v81277; RV32-NEXT: vsrl.vi v10, v8, 11278; RV32-NEXT: vand.vv v8, v8, v121279; RV32-NEXT: vand.vv v10, v10, v121280; RV32-NEXT: vadd.vv v8, v8, v81281; RV32-NEXT: vor.vv v8, v10, v81282; RV32-NEXT: addi sp, sp, 161283; RV32-NEXT: .cfi_def_cfa_offset 01284; RV32-NEXT: ret1285;1286; RV64-LABEL: vp_bitreverse_v4i64_unmasked:1287; RV64: # %bb.0:1288; RV64-NEXT: lui a1, 40801289; RV64-NEXT: li a2, 2551290; RV64-NEXT: li a3, 561291; RV64-NEXT: lui a4, 161292; RV64-NEXT: li a5, 401293; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma1294; RV64-NEXT: vsrl.vi v12, v8, 241295; RV64-NEXT: vsrl.vi v14, v8, 81296; RV64-NEXT: addi a0, a4, -2561297; RV64-NEXT: vsrl.vx v10, v8, a31298; RV64-NEXT: vsrl.vx v16, v8, a51299; RV64-NEXT: vand.vx v16, v16, a01300; RV64-NEXT: vor.vv v10, v16, v101301; RV64-NEXT: vand.vx v16, v8, a11302; RV64-NEXT: slli a2, a2, 241303; RV64-NEXT: vand.vx v12, v12, a11304; RV64-NEXT: vsll.vi v16, v16, 241305; RV64-NEXT: vand.vx v14, v14, a21306; RV64-NEXT: vor.vv v12, v14, v121307; RV64-NEXT: vand.vx v14, v8, a21308; RV64-NEXT: vsll.vi v14, v14, 81309; RV64-NEXT: vor.vv v14, v16, v141310; RV64-NEXT: vsll.vx v16, v8, a31311; RV64-NEXT: vand.vx v8, v8, a01312; RV64-NEXT: vsll.vx v8, v8, a51313; RV64-NEXT: vor.vv v8, v16, v81314; RV64-NEXT: lui a0, 616811315; RV64-NEXT: lui a1, 2097151316; RV64-NEXT: lui a2, 3495251317; RV64-NEXT: addi a0, a0, -2411318; RV64-NEXT: addi a1, a1, 8191319; RV64-NEXT: addi a2, a2, 13651320; RV64-NEXT: slli a3, a0, 321321; RV64-NEXT: slli a4, a1, 321322; RV64-NEXT: add a0, a0, a31323; RV64-NEXT: slli a3, a2, 321324; RV64-NEXT: add a1, a1, a41325; RV64-NEXT: add a2, a2, a31326; RV64-NEXT: vor.vv v10, v12, v101327; RV64-NEXT: vor.vv v8, v8, v141328; RV64-NEXT: vor.vv v8, v8, v101329; RV64-NEXT: vsrl.vi v10, v8, 41330; RV64-NEXT: vand.vx v8, v8, a01331; RV64-NEXT: vand.vx v10, v10, a01332; RV64-NEXT: vsll.vi v8, v8, 41333; RV64-NEXT: vor.vv v8, v10, v81334; RV64-NEXT: vsrl.vi v10, v8, 21335; RV64-NEXT: vand.vx v8, v8, a11336; RV64-NEXT: vand.vx v10, v10, a11337; RV64-NEXT: vsll.vi v8, v8, 21338; RV64-NEXT: vor.vv v8, v10, v81339; RV64-NEXT: vsrl.vi v10, v8, 11340; RV64-NEXT: vand.vx v8, v8, a21341; RV64-NEXT: vand.vx v10, v10, a21342; RV64-NEXT: vadd.vv v8, v8, v81343; RV64-NEXT: vor.vv v8, v10, v81344; RV64-NEXT: ret1345 %v = call <4 x i64> @llvm.vp.bitreverse.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl)1346 ret <4 x i64> %v1347}1348 1349define <8 x i64> @vp_bitreverse_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {1350; RV32-LABEL: vp_bitreverse_v8i64:1351; RV32: # %bb.0:1352; RV32-NEXT: addi sp, sp, -161353; RV32-NEXT: .cfi_def_cfa_offset 161354; RV32-NEXT: lui a4, 10444801355; RV32-NEXT: li a3, 561356; RV32-NEXT: lui a5, 161357; RV32-NEXT: li a2, 401358; RV32-NEXT: lui a1, 40801359; RV32-NEXT: addi a6, sp, 81360; RV32-NEXT: sw a4, 8(sp)1361; RV32-NEXT: sw zero, 12(sp)1362; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1363; RV32-NEXT: vlse64.v v12, (a6), zero1364; RV32-NEXT: lui a4, 616811365; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1366; RV32-NEXT: vsll.vx v16, v8, a3, v0.t1367; RV32-NEXT: addi a5, a5, -2561368; RV32-NEXT: vand.vx v20, v8, a5, v0.t1369; RV32-NEXT: vsll.vx v20, v20, a2, v0.t1370; RV32-NEXT: vor.vv v16, v16, v20, v0.t1371; RV32-NEXT: vand.vx v20, v8, a1, v0.t1372; RV32-NEXT: vsll.vi v20, v20, 24, v0.t1373; RV32-NEXT: vand.vv v24, v8, v12, v0.t1374; RV32-NEXT: vsll.vi v24, v24, 8, v0.t1375; RV32-NEXT: vor.vv v20, v20, v24, v0.t1376; RV32-NEXT: vor.vv v16, v16, v20, v0.t1377; RV32-NEXT: vsrl.vx v20, v8, a3, v0.t1378; RV32-NEXT: lui a3, 2097151379; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t1380; RV32-NEXT: lui a2, 3495251381; RV32-NEXT: addi a4, a4, -2411382; RV32-NEXT: addi a3, a3, 8191383; RV32-NEXT: addi a2, a2, 13651384; RV32-NEXT: vand.vx v24, v24, a5, v0.t1385; RV32-NEXT: vor.vv v20, v24, v20, v0.t1386; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t1387; RV32-NEXT: vand.vx v24, v24, a1, v0.t1388; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t1389; RV32-NEXT: vand.vv v8, v8, v12, v0.t1390; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1391; RV32-NEXT: vmv.v.x v28, a41392; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1393; RV32-NEXT: vor.vv v8, v8, v24, v0.t1394; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1395; RV32-NEXT: vmv.v.x v12, a31396; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1397; RV32-NEXT: vor.vv v20, v8, v20, v0.t1398; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1399; RV32-NEXT: vmv.v.x v8, a21400; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1401; RV32-NEXT: vor.vv v16, v16, v20, v0.t1402; RV32-NEXT: vsrl.vi v20, v16, 4, v0.t1403; RV32-NEXT: vand.vv v20, v20, v28, v0.t1404; RV32-NEXT: vand.vv v16, v16, v28, v0.t1405; RV32-NEXT: vsll.vi v16, v16, 4, v0.t1406; RV32-NEXT: vor.vv v16, v20, v16, v0.t1407; RV32-NEXT: vsrl.vi v20, v16, 2, v0.t1408; RV32-NEXT: vand.vv v20, v20, v12, v0.t1409; RV32-NEXT: vand.vv v12, v16, v12, v0.t1410; RV32-NEXT: vsll.vi v12, v12, 2, v0.t1411; RV32-NEXT: vor.vv v12, v20, v12, v0.t1412; RV32-NEXT: vsrl.vi v16, v12, 1, v0.t1413; RV32-NEXT: vand.vv v16, v16, v8, v0.t1414; RV32-NEXT: vand.vv v8, v12, v8, v0.t1415; RV32-NEXT: vsll.vi v8, v8, 1, v0.t1416; RV32-NEXT: vor.vv v8, v16, v8, v0.t1417; RV32-NEXT: addi sp, sp, 161418; RV32-NEXT: .cfi_def_cfa_offset 01419; RV32-NEXT: ret1420;1421; RV64-LABEL: vp_bitreverse_v8i64:1422; RV64: # %bb.0:1423; RV64-NEXT: lui a1, 40801424; RV64-NEXT: li a3, 2551425; RV64-NEXT: li a2, 561426; RV64-NEXT: lui a4, 161427; RV64-NEXT: lui a5, 616811428; RV64-NEXT: lui a6, 2097151429; RV64-NEXT: lui a7, 3495251430; RV64-NEXT: addi a5, a5, -2411431; RV64-NEXT: addi a6, a6, 8191432; RV64-NEXT: addi a7, a7, 13651433; RV64-NEXT: slli t0, a5, 321434; RV64-NEXT: add t0, a5, t01435; RV64-NEXT: slli a5, a6, 321436; RV64-NEXT: add a6, a6, a51437; RV64-NEXT: slli a5, a7, 321438; RV64-NEXT: add a5, a7, a51439; RV64-NEXT: li a7, 401440; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma1441; RV64-NEXT: vand.vx v12, v8, a1, v0.t1442; RV64-NEXT: slli a3, a3, 241443; RV64-NEXT: addi a0, a4, -2561444; RV64-NEXT: vsll.vi v12, v12, 24, v0.t1445; RV64-NEXT: vand.vx v16, v8, a3, v0.t1446; RV64-NEXT: vsll.vi v16, v16, 8, v0.t1447; RV64-NEXT: vor.vv v12, v12, v16, v0.t1448; RV64-NEXT: vsll.vx v16, v8, a2, v0.t1449; RV64-NEXT: vand.vx v20, v8, a0, v0.t1450; RV64-NEXT: vsll.vx v20, v20, a7, v0.t1451; RV64-NEXT: vor.vv v16, v16, v20, v0.t1452; RV64-NEXT: vor.vv v12, v16, v12, v0.t1453; RV64-NEXT: vsrl.vx v16, v8, a2, v0.t1454; RV64-NEXT: vsrl.vx v20, v8, a7, v0.t1455; RV64-NEXT: vand.vx v20, v20, a0, v0.t1456; RV64-NEXT: vor.vv v16, v20, v16, v0.t1457; RV64-NEXT: vsrl.vi v20, v8, 24, v0.t1458; RV64-NEXT: vand.vx v20, v20, a1, v0.t1459; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t1460; RV64-NEXT: vand.vx v8, v8, a3, v0.t1461; RV64-NEXT: vor.vv v8, v8, v20, v0.t1462; RV64-NEXT: vor.vv v8, v8, v16, v0.t1463; RV64-NEXT: vor.vv v8, v12, v8, v0.t1464; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t1465; RV64-NEXT: vand.vx v12, v12, t0, v0.t1466; RV64-NEXT: vand.vx v8, v8, t0, v0.t1467; RV64-NEXT: vsll.vi v8, v8, 4, v0.t1468; RV64-NEXT: vor.vv v8, v12, v8, v0.t1469; RV64-NEXT: vsrl.vi v12, v8, 2, v0.t1470; RV64-NEXT: vand.vx v12, v12, a6, v0.t1471; RV64-NEXT: vand.vx v8, v8, a6, v0.t1472; RV64-NEXT: vsll.vi v8, v8, 2, v0.t1473; RV64-NEXT: vor.vv v8, v12, v8, v0.t1474; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t1475; RV64-NEXT: vand.vx v12, v12, a5, v0.t1476; RV64-NEXT: vand.vx v8, v8, a5, v0.t1477; RV64-NEXT: vsll.vi v8, v8, 1, v0.t1478; RV64-NEXT: vor.vv v8, v12, v8, v0.t1479; RV64-NEXT: ret1480 %v = call <8 x i64> @llvm.vp.bitreverse.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl)1481 ret <8 x i64> %v1482}1483 1484define <8 x i64> @vp_bitreverse_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {1485; RV32-LABEL: vp_bitreverse_v8i64_unmasked:1486; RV32: # %bb.0:1487; RV32-NEXT: addi sp, sp, -161488; RV32-NEXT: .cfi_def_cfa_offset 161489; RV32-NEXT: lui a1, 10444801490; RV32-NEXT: li a2, 561491; RV32-NEXT: lui a3, 161492; RV32-NEXT: li a4, 401493; RV32-NEXT: lui a5, 40801494; RV32-NEXT: addi a6, sp, 81495; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1496; RV32-NEXT: vsrl.vi v20, v8, 241497; RV32-NEXT: sw a1, 8(sp)1498; RV32-NEXT: sw zero, 12(sp)1499; RV32-NEXT: vsll.vx v16, v8, a21500; RV32-NEXT: addi a1, a3, -2561501; RV32-NEXT: vsrl.vx v12, v8, a21502; RV32-NEXT: vsrl.vx v24, v8, a41503; RV32-NEXT: vand.vx v28, v8, a11504; RV32-NEXT: vand.vx v24, v24, a11505; RV32-NEXT: vor.vv v12, v24, v121506; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1507; RV32-NEXT: vlse64.v v24, (a6), zero1508; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1509; RV32-NEXT: vsll.vx v28, v28, a41510; RV32-NEXT: vor.vv v16, v16, v281511; RV32-NEXT: vsrl.vi v28, v8, 81512; RV32-NEXT: vand.vx v20, v20, a51513; RV32-NEXT: vand.vv v28, v28, v241514; RV32-NEXT: vor.vv v20, v28, v201515; RV32-NEXT: lui a1, 616811516; RV32-NEXT: lui a2, 2097151517; RV32-NEXT: lui a3, 3495251518; RV32-NEXT: vand.vv v24, v8, v241519; RV32-NEXT: vand.vx v8, v8, a51520; RV32-NEXT: addi a1, a1, -2411521; RV32-NEXT: addi a2, a2, 8191522; RV32-NEXT: addi a3, a3, 13651523; RV32-NEXT: vsll.vi v8, v8, 241524; RV32-NEXT: vsll.vi v24, v24, 81525; RV32-NEXT: vor.vv v8, v8, v241526; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1527; RV32-NEXT: vmv.v.x v24, a11528; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1529; RV32-NEXT: vor.vv v12, v20, v121530; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1531; RV32-NEXT: vmv.v.x v20, a21532; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1533; RV32-NEXT: vor.vv v8, v16, v81534; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1535; RV32-NEXT: vmv.v.x v16, a31536; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1537; RV32-NEXT: vor.vv v8, v8, v121538; RV32-NEXT: vsrl.vi v12, v8, 41539; RV32-NEXT: vand.vv v8, v8, v241540; RV32-NEXT: vand.vv v12, v12, v241541; RV32-NEXT: vsll.vi v8, v8, 41542; RV32-NEXT: vor.vv v8, v12, v81543; RV32-NEXT: vsrl.vi v12, v8, 21544; RV32-NEXT: vand.vv v8, v8, v201545; RV32-NEXT: vand.vv v12, v12, v201546; RV32-NEXT: vsll.vi v8, v8, 21547; RV32-NEXT: vor.vv v8, v12, v81548; RV32-NEXT: vsrl.vi v12, v8, 11549; RV32-NEXT: vand.vv v8, v8, v161550; RV32-NEXT: vand.vv v12, v12, v161551; RV32-NEXT: vadd.vv v8, v8, v81552; RV32-NEXT: vor.vv v8, v12, v81553; RV32-NEXT: addi sp, sp, 161554; RV32-NEXT: .cfi_def_cfa_offset 01555; RV32-NEXT: ret1556;1557; RV64-LABEL: vp_bitreverse_v8i64_unmasked:1558; RV64: # %bb.0:1559; RV64-NEXT: lui a1, 40801560; RV64-NEXT: li a2, 2551561; RV64-NEXT: li a3, 561562; RV64-NEXT: lui a4, 161563; RV64-NEXT: li a5, 401564; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma1565; RV64-NEXT: vsrl.vi v16, v8, 241566; RV64-NEXT: vsrl.vi v20, v8, 81567; RV64-NEXT: addi a0, a4, -2561568; RV64-NEXT: vsrl.vx v12, v8, a31569; RV64-NEXT: vsrl.vx v24, v8, a51570; RV64-NEXT: vand.vx v24, v24, a01571; RV64-NEXT: vor.vv v12, v24, v121572; RV64-NEXT: vand.vx v24, v8, a11573; RV64-NEXT: slli a2, a2, 241574; RV64-NEXT: vand.vx v16, v16, a11575; RV64-NEXT: vsll.vi v24, v24, 241576; RV64-NEXT: vand.vx v20, v20, a21577; RV64-NEXT: vor.vv v16, v20, v161578; RV64-NEXT: vand.vx v20, v8, a21579; RV64-NEXT: vsll.vi v20, v20, 81580; RV64-NEXT: vor.vv v20, v24, v201581; RV64-NEXT: vsll.vx v24, v8, a31582; RV64-NEXT: vand.vx v8, v8, a01583; RV64-NEXT: vsll.vx v8, v8, a51584; RV64-NEXT: vor.vv v8, v24, v81585; RV64-NEXT: lui a0, 616811586; RV64-NEXT: lui a1, 2097151587; RV64-NEXT: lui a2, 3495251588; RV64-NEXT: addi a0, a0, -2411589; RV64-NEXT: addi a1, a1, 8191590; RV64-NEXT: addi a2, a2, 13651591; RV64-NEXT: slli a3, a0, 321592; RV64-NEXT: slli a4, a1, 321593; RV64-NEXT: add a0, a0, a31594; RV64-NEXT: slli a3, a2, 321595; RV64-NEXT: add a1, a1, a41596; RV64-NEXT: add a2, a2, a31597; RV64-NEXT: vor.vv v12, v16, v121598; RV64-NEXT: vor.vv v8, v8, v201599; RV64-NEXT: vor.vv v8, v8, v121600; RV64-NEXT: vsrl.vi v12, v8, 41601; RV64-NEXT: vand.vx v8, v8, a01602; RV64-NEXT: vand.vx v12, v12, a01603; RV64-NEXT: vsll.vi v8, v8, 41604; RV64-NEXT: vor.vv v8, v12, v81605; RV64-NEXT: vsrl.vi v12, v8, 21606; RV64-NEXT: vand.vx v8, v8, a11607; RV64-NEXT: vand.vx v12, v12, a11608; RV64-NEXT: vsll.vi v8, v8, 21609; RV64-NEXT: vor.vv v8, v12, v81610; RV64-NEXT: vsrl.vi v12, v8, 11611; RV64-NEXT: vand.vx v8, v8, a21612; RV64-NEXT: vand.vx v12, v12, a21613; RV64-NEXT: vadd.vv v8, v8, v81614; RV64-NEXT: vor.vv v8, v12, v81615; RV64-NEXT: ret1616 %v = call <8 x i64> @llvm.vp.bitreverse.v8i64(<8 x i64> %va, <8 x i1> splat (i1 true), i32 %evl)1617 ret <8 x i64> %v1618}1619 1620define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {1621; RV32-LABEL: vp_bitreverse_v15i64:1622; RV32: # %bb.0:1623; RV32-NEXT: addi sp, sp, -161624; RV32-NEXT: .cfi_def_cfa_offset 161625; RV32-NEXT: csrr a1, vlenb1626; RV32-NEXT: li a2, 241627; RV32-NEXT: mul a1, a1, a21628; RV32-NEXT: sub sp, sp, a11629; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb1630; RV32-NEXT: lui a1, 10444801631; RV32-NEXT: li a2, 561632; RV32-NEXT: lui a3, 161633; RV32-NEXT: li a4, 401634; RV32-NEXT: addi a5, sp, 81635; RV32-NEXT: sw a1, 8(sp)1636; RV32-NEXT: sw zero, 12(sp)1637; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1638; RV32-NEXT: vsll.vx v16, v8, a2, v0.t1639; RV32-NEXT: addi a1, a3, -2561640; RV32-NEXT: vand.vx v24, v8, a1, v0.t1641; RV32-NEXT: vsll.vx v24, v24, a4, v0.t1642; RV32-NEXT: vor.vv v16, v16, v24, v0.t1643; RV32-NEXT: csrr a3, vlenb1644; RV32-NEXT: slli a3, a3, 31645; RV32-NEXT: add a3, sp, a31646; RV32-NEXT: addi a3, a3, 161647; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill1648; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1649; RV32-NEXT: vlse64.v v16, (a5), zero1650; RV32-NEXT: csrr a3, vlenb1651; RV32-NEXT: slli a3, a3, 41652; RV32-NEXT: add a3, sp, a31653; RV32-NEXT: addi a3, a3, 161654; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill1655; RV32-NEXT: lui a3, 40801656; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1657; RV32-NEXT: vand.vx v16, v8, a3, v0.t1658; RV32-NEXT: vsll.vi v24, v16, 24, v0.t1659; RV32-NEXT: csrr a5, vlenb1660; RV32-NEXT: slli a5, a5, 41661; RV32-NEXT: add a5, sp, a51662; RV32-NEXT: addi a5, a5, 161663; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload1664; RV32-NEXT: vand.vv v16, v8, v16, v0.t1665; RV32-NEXT: vsll.vi v16, v16, 8, v0.t1666; RV32-NEXT: vor.vv v16, v24, v16, v0.t1667; RV32-NEXT: csrr a5, vlenb1668; RV32-NEXT: slli a5, a5, 31669; RV32-NEXT: add a5, sp, a51670; RV32-NEXT: addi a5, a5, 161671; RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload1672; RV32-NEXT: vor.vv v16, v24, v16, v0.t1673; RV32-NEXT: csrr a5, vlenb1674; RV32-NEXT: slli a5, a5, 31675; RV32-NEXT: add a5, sp, a51676; RV32-NEXT: addi a5, a5, 161677; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill1678; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t1679; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t1680; RV32-NEXT: vand.vx v24, v24, a1, v0.t1681; RV32-NEXT: vor.vv v16, v24, v16, v0.t1682; RV32-NEXT: addi a1, sp, 161683; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1684; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t1685; RV32-NEXT: vand.vx v24, v24, a3, v0.t1686; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t1687; RV32-NEXT: csrr a1, vlenb1688; RV32-NEXT: slli a1, a1, 41689; RV32-NEXT: add a1, sp, a11690; RV32-NEXT: addi a1, a1, 161691; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1692; RV32-NEXT: vand.vv v8, v8, v16, v0.t1693; RV32-NEXT: vor.vv v8, v8, v24, v0.t1694; RV32-NEXT: addi a1, sp, 161695; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1696; RV32-NEXT: vor.vv v8, v8, v16, v0.t1697; RV32-NEXT: lui a1, 616811698; RV32-NEXT: lui a2, 2097151699; RV32-NEXT: lui a3, 3495251700; RV32-NEXT: addi a1, a1, -2411701; RV32-NEXT: addi a2, a2, 8191702; RV32-NEXT: addi a3, a3, 13651703; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma1704; RV32-NEXT: vmv.v.x v24, a11705; RV32-NEXT: csrr a1, vlenb1706; RV32-NEXT: slli a1, a1, 31707; RV32-NEXT: add a1, sp, a11708; RV32-NEXT: addi a1, a1, 161709; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1710; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1711; RV32-NEXT: vor.vv v8, v16, v8, v0.t1712; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t1713; RV32-NEXT: vand.vv v16, v16, v24, v0.t1714; RV32-NEXT: vand.vv v24, v8, v24, v0.t1715; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma1716; RV32-NEXT: vmv.v.x v8, a21717; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1718; RV32-NEXT: vsll.vi v24, v24, 4, v0.t1719; RV32-NEXT: vor.vv v24, v16, v24, v0.t1720; RV32-NEXT: vsrl.vi v16, v24, 2, v0.t1721; RV32-NEXT: vand.vv v16, v16, v8, v0.t1722; RV32-NEXT: vand.vv v24, v24, v8, v0.t1723; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma1724; RV32-NEXT: vmv.v.x v8, a31725; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1726; RV32-NEXT: vsll.vi v24, v24, 2, v0.t1727; RV32-NEXT: vor.vv v16, v16, v24, v0.t1728; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t1729; RV32-NEXT: vand.vv v24, v24, v8, v0.t1730; RV32-NEXT: vand.vv v8, v16, v8, v0.t1731; RV32-NEXT: vsll.vi v8, v8, 1, v0.t1732; RV32-NEXT: vor.vv v8, v24, v8, v0.t1733; RV32-NEXT: csrr a0, vlenb1734; RV32-NEXT: li a1, 241735; RV32-NEXT: mul a0, a0, a11736; RV32-NEXT: add sp, sp, a01737; RV32-NEXT: .cfi_def_cfa sp, 161738; RV32-NEXT: addi sp, sp, 161739; RV32-NEXT: .cfi_def_cfa_offset 01740; RV32-NEXT: ret1741;1742; RV64-LABEL: vp_bitreverse_v15i64:1743; RV64: # %bb.0:1744; RV64-NEXT: addi sp, sp, -161745; RV64-NEXT: .cfi_def_cfa_offset 161746; RV64-NEXT: csrr a1, vlenb1747; RV64-NEXT: slli a1, a1, 31748; RV64-NEXT: sub sp, sp, a11749; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb1750; RV64-NEXT: lui a1, 40801751; RV64-NEXT: li a2, 2551752; RV64-NEXT: li a3, 561753; RV64-NEXT: lui a4, 161754; RV64-NEXT: li a5, 401755; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1756; RV64-NEXT: vand.vx v16, v8, a1, v0.t1757; RV64-NEXT: slli a2, a2, 241758; RV64-NEXT: addi a0, a4, -2561759; RV64-NEXT: vsll.vi v16, v16, 24, v0.t1760; RV64-NEXT: vand.vx v24, v8, a2, v0.t1761; RV64-NEXT: vsll.vi v24, v24, 8, v0.t1762; RV64-NEXT: vor.vv v16, v16, v24, v0.t1763; RV64-NEXT: addi a4, sp, 161764; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill1765; RV64-NEXT: vsll.vx v24, v8, a3, v0.t1766; RV64-NEXT: vand.vx v16, v8, a0, v0.t1767; RV64-NEXT: vsll.vx v16, v16, a5, v0.t1768; RV64-NEXT: vor.vv v16, v24, v16, v0.t1769; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload1770; RV64-NEXT: vor.vv v16, v16, v24, v0.t1771; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill1772; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t1773; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t1774; RV64-NEXT: vand.vx v16, v16, a0, v0.t1775; RV64-NEXT: vor.vv v24, v16, v24, v0.t1776; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t1777; RV64-NEXT: vand.vx v16, v16, a1, v0.t1778; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t1779; RV64-NEXT: vand.vx v8, v8, a2, v0.t1780; RV64-NEXT: vor.vv v8, v8, v16, v0.t1781; RV64-NEXT: vor.vv v8, v8, v24, v0.t1782; RV64-NEXT: lui a0, 616811783; RV64-NEXT: lui a1, 2097151784; RV64-NEXT: lui a2, 3495251785; RV64-NEXT: addi a0, a0, -2411786; RV64-NEXT: addi a1, a1, 8191787; RV64-NEXT: addi a2, a2, 13651788; RV64-NEXT: slli a3, a0, 321789; RV64-NEXT: slli a4, a1, 321790; RV64-NEXT: add a0, a0, a31791; RV64-NEXT: slli a3, a2, 321792; RV64-NEXT: add a1, a1, a41793; RV64-NEXT: add a2, a2, a31794; RV64-NEXT: addi a3, sp, 161795; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload1796; RV64-NEXT: vor.vv v8, v16, v8, v0.t1797; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t1798; RV64-NEXT: vand.vx v16, v16, a0, v0.t1799; RV64-NEXT: vand.vx v8, v8, a0, v0.t1800; RV64-NEXT: vsll.vi v8, v8, 4, v0.t1801; RV64-NEXT: vor.vv v8, v16, v8, v0.t1802; RV64-NEXT: vsrl.vi v16, v8, 2, v0.t1803; RV64-NEXT: vand.vx v16, v16, a1, v0.t1804; RV64-NEXT: vand.vx v8, v8, a1, v0.t1805; RV64-NEXT: vsll.vi v8, v8, 2, v0.t1806; RV64-NEXT: vor.vv v8, v16, v8, v0.t1807; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t1808; RV64-NEXT: vand.vx v16, v16, a2, v0.t1809; RV64-NEXT: vand.vx v8, v8, a2, v0.t1810; RV64-NEXT: vsll.vi v8, v8, 1, v0.t1811; RV64-NEXT: vor.vv v8, v16, v8, v0.t1812; RV64-NEXT: csrr a0, vlenb1813; RV64-NEXT: slli a0, a0, 31814; RV64-NEXT: add sp, sp, a01815; RV64-NEXT: .cfi_def_cfa sp, 161816; RV64-NEXT: addi sp, sp, 161817; RV64-NEXT: .cfi_def_cfa_offset 01818; RV64-NEXT: ret1819 %v = call <15 x i64> @llvm.vp.bitreverse.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl)1820 ret <15 x i64> %v1821}1822 1823define <15 x i64> @vp_bitreverse_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {1824; RV32-LABEL: vp_bitreverse_v15i64_unmasked:1825; RV32: # %bb.0:1826; RV32-NEXT: addi sp, sp, -161827; RV32-NEXT: .cfi_def_cfa_offset 161828; RV32-NEXT: csrr a1, vlenb1829; RV32-NEXT: slli a1, a1, 41830; RV32-NEXT: sub sp, sp, a11831; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb1832; RV32-NEXT: lui a1, 10444801833; RV32-NEXT: li a2, 561834; RV32-NEXT: lui a3, 161835; RV32-NEXT: li a4, 401836; RV32-NEXT: lui a5, 40801837; RV32-NEXT: addi a6, sp, 81838; RV32-NEXT: sw a1, 8(sp)1839; RV32-NEXT: sw zero, 12(sp)1840; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1841; RV32-NEXT: vsll.vx v16, v8, a21842; RV32-NEXT: addi a1, a3, -2561843; RV32-NEXT: vsrl.vx v24, v8, a21844; RV32-NEXT: vsrl.vx v0, v8, a41845; RV32-NEXT: vand.vx v0, v0, a11846; RV32-NEXT: vor.vv v24, v0, v241847; RV32-NEXT: addi a2, sp, 161848; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill1849; RV32-NEXT: vand.vx v24, v8, a11850; RV32-NEXT: vsll.vx v24, v24, a41851; RV32-NEXT: vor.vv v16, v16, v241852; RV32-NEXT: csrr a1, vlenb1853; RV32-NEXT: slli a1, a1, 31854; RV32-NEXT: add a1, sp, a11855; RV32-NEXT: addi a1, a1, 161856; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1857; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1858; RV32-NEXT: vlse64.v v24, (a6), zero1859; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1860; RV32-NEXT: vsrl.vi v16, v8, 241861; RV32-NEXT: vand.vx v16, v16, a51862; RV32-NEXT: vsrl.vi v0, v8, 81863; RV32-NEXT: vand.vv v0, v0, v241864; RV32-NEXT: vor.vv v16, v0, v161865; RV32-NEXT: vand.vv v24, v8, v241866; RV32-NEXT: vand.vx v8, v8, a51867; RV32-NEXT: vsll.vi v8, v8, 241868; RV32-NEXT: vsll.vi v24, v24, 81869; RV32-NEXT: vor.vv v24, v8, v241870; RV32-NEXT: addi a1, sp, 161871; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1872; RV32-NEXT: vor.vv v8, v16, v81873; RV32-NEXT: lui a1, 616811874; RV32-NEXT: lui a2, 2097151875; RV32-NEXT: lui a3, 3495251876; RV32-NEXT: addi a1, a1, -2411877; RV32-NEXT: addi a2, a2, 8191878; RV32-NEXT: addi a3, a3, 13651879; RV32-NEXT: csrr a4, vlenb1880; RV32-NEXT: slli a4, a4, 31881; RV32-NEXT: add a4, sp, a41882; RV32-NEXT: addi a4, a4, 161883; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload1884; RV32-NEXT: vor.vv v16, v16, v241885; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma1886; RV32-NEXT: vmv.v.x v24, a11887; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1888; RV32-NEXT: vor.vv v8, v16, v81889; RV32-NEXT: vsrl.vi v16, v8, 41890; RV32-NEXT: vand.vv v8, v8, v241891; RV32-NEXT: vand.vv v16, v16, v241892; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma1893; RV32-NEXT: vmv.v.x v24, a21894; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1895; RV32-NEXT: vsll.vi v8, v8, 41896; RV32-NEXT: vor.vv v8, v16, v81897; RV32-NEXT: vsrl.vi v16, v8, 21898; RV32-NEXT: vand.vv v8, v8, v241899; RV32-NEXT: vand.vv v16, v16, v241900; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma1901; RV32-NEXT: vmv.v.x v24, a31902; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1903; RV32-NEXT: vsll.vi v8, v8, 21904; RV32-NEXT: vor.vv v8, v16, v81905; RV32-NEXT: vsrl.vi v16, v8, 11906; RV32-NEXT: vand.vv v8, v8, v241907; RV32-NEXT: vand.vv v16, v16, v241908; RV32-NEXT: vadd.vv v8, v8, v81909; RV32-NEXT: vor.vv v8, v16, v81910; RV32-NEXT: csrr a0, vlenb1911; RV32-NEXT: slli a0, a0, 41912; RV32-NEXT: add sp, sp, a01913; RV32-NEXT: .cfi_def_cfa sp, 161914; RV32-NEXT: addi sp, sp, 161915; RV32-NEXT: .cfi_def_cfa_offset 01916; RV32-NEXT: ret1917;1918; RV64-LABEL: vp_bitreverse_v15i64_unmasked:1919; RV64: # %bb.0:1920; RV64-NEXT: addi sp, sp, -161921; RV64-NEXT: .cfi_def_cfa_offset 161922; RV64-NEXT: csrr a1, vlenb1923; RV64-NEXT: slli a1, a1, 31924; RV64-NEXT: sub sp, sp, a11925; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb1926; RV64-NEXT: lui a1, 40801927; RV64-NEXT: li a2, 2551928; RV64-NEXT: li a3, 561929; RV64-NEXT: lui a4, 161930; RV64-NEXT: li a5, 401931; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1932; RV64-NEXT: vsrl.vi v24, v8, 241933; RV64-NEXT: addi a0, a4, -2561934; RV64-NEXT: vsrl.vx v16, v8, a31935; RV64-NEXT: vsrl.vx v0, v8, a51936; RV64-NEXT: vand.vx v0, v0, a01937; RV64-NEXT: vor.vv v16, v0, v161938; RV64-NEXT: addi a4, sp, 161939; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill1940; RV64-NEXT: vsrl.vi v0, v8, 81941; RV64-NEXT: slli a2, a2, 241942; RV64-NEXT: vand.vx v24, v24, a11943; RV64-NEXT: vand.vx v0, v0, a21944; RV64-NEXT: vor.vv v24, v0, v241945; RV64-NEXT: vand.vx v0, v8, a11946; RV64-NEXT: vsll.vi v0, v0, 241947; RV64-NEXT: vand.vx v16, v8, a21948; RV64-NEXT: vsll.vi v16, v16, 81949; RV64-NEXT: vor.vv v0, v0, v161950; RV64-NEXT: vsll.vx v16, v8, a31951; RV64-NEXT: vand.vx v8, v8, a01952; RV64-NEXT: vsll.vx v8, v8, a51953; RV64-NEXT: vor.vv v8, v16, v81954; RV64-NEXT: lui a0, 616811955; RV64-NEXT: lui a1, 2097151956; RV64-NEXT: lui a2, 3495251957; RV64-NEXT: addi a0, a0, -2411958; RV64-NEXT: addi a1, a1, 8191959; RV64-NEXT: addi a2, a2, 13651960; RV64-NEXT: slli a3, a0, 321961; RV64-NEXT: slli a4, a1, 321962; RV64-NEXT: add a0, a0, a31963; RV64-NEXT: slli a3, a2, 321964; RV64-NEXT: add a1, a1, a41965; RV64-NEXT: add a2, a2, a31966; RV64-NEXT: addi a3, sp, 161967; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload1968; RV64-NEXT: vor.vv v16, v24, v161969; RV64-NEXT: vor.vv v8, v8, v01970; RV64-NEXT: vor.vv v8, v8, v161971; RV64-NEXT: vsrl.vi v16, v8, 41972; RV64-NEXT: vand.vx v8, v8, a01973; RV64-NEXT: vand.vx v16, v16, a01974; RV64-NEXT: vsll.vi v8, v8, 41975; RV64-NEXT: vor.vv v8, v16, v81976; RV64-NEXT: vsrl.vi v16, v8, 21977; RV64-NEXT: vand.vx v8, v8, a11978; RV64-NEXT: vand.vx v16, v16, a11979; RV64-NEXT: vsll.vi v8, v8, 21980; RV64-NEXT: vor.vv v8, v16, v81981; RV64-NEXT: vsrl.vi v16, v8, 11982; RV64-NEXT: vand.vx v8, v8, a21983; RV64-NEXT: vand.vx v16, v16, a21984; RV64-NEXT: vadd.vv v8, v8, v81985; RV64-NEXT: vor.vv v8, v16, v81986; RV64-NEXT: csrr a0, vlenb1987; RV64-NEXT: slli a0, a0, 31988; RV64-NEXT: add sp, sp, a01989; RV64-NEXT: .cfi_def_cfa sp, 161990; RV64-NEXT: addi sp, sp, 161991; RV64-NEXT: .cfi_def_cfa_offset 01992; RV64-NEXT: ret1993 %v = call <15 x i64> @llvm.vp.bitreverse.v15i64(<15 x i64> %va, <15 x i1> splat (i1 true), i32 %evl)1994 ret <15 x i64> %v1995}1996 1997define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {1998; RV32-LABEL: vp_bitreverse_v16i64:1999; RV32: # %bb.0:2000; RV32-NEXT: addi sp, sp, -162001; RV32-NEXT: .cfi_def_cfa_offset 162002; RV32-NEXT: csrr a1, vlenb2003; RV32-NEXT: li a2, 242004; RV32-NEXT: mul a1, a1, a22005; RV32-NEXT: sub sp, sp, a12006; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb2007; RV32-NEXT: lui a1, 10444802008; RV32-NEXT: li a2, 562009; RV32-NEXT: lui a3, 162010; RV32-NEXT: li a4, 402011; RV32-NEXT: addi a5, sp, 82012; RV32-NEXT: sw a1, 8(sp)2013; RV32-NEXT: sw zero, 12(sp)2014; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2015; RV32-NEXT: vsll.vx v16, v8, a2, v0.t2016; RV32-NEXT: addi a1, a3, -2562017; RV32-NEXT: vand.vx v24, v8, a1, v0.t2018; RV32-NEXT: vsll.vx v24, v24, a4, v0.t2019; RV32-NEXT: vor.vv v16, v16, v24, v0.t2020; RV32-NEXT: csrr a3, vlenb2021; RV32-NEXT: slli a3, a3, 32022; RV32-NEXT: add a3, sp, a32023; RV32-NEXT: addi a3, a3, 162024; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill2025; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma2026; RV32-NEXT: vlse64.v v16, (a5), zero2027; RV32-NEXT: csrr a3, vlenb2028; RV32-NEXT: slli a3, a3, 42029; RV32-NEXT: add a3, sp, a32030; RV32-NEXT: addi a3, a3, 162031; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill2032; RV32-NEXT: lui a3, 40802033; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2034; RV32-NEXT: vand.vx v16, v8, a3, v0.t2035; RV32-NEXT: vsll.vi v24, v16, 24, v0.t2036; RV32-NEXT: csrr a5, vlenb2037; RV32-NEXT: slli a5, a5, 42038; RV32-NEXT: add a5, sp, a52039; RV32-NEXT: addi a5, a5, 162040; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload2041; RV32-NEXT: vand.vv v16, v8, v16, v0.t2042; RV32-NEXT: vsll.vi v16, v16, 8, v0.t2043; RV32-NEXT: vor.vv v16, v24, v16, v0.t2044; RV32-NEXT: csrr a5, vlenb2045; RV32-NEXT: slli a5, a5, 32046; RV32-NEXT: add a5, sp, a52047; RV32-NEXT: addi a5, a5, 162048; RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload2049; RV32-NEXT: vor.vv v16, v24, v16, v0.t2050; RV32-NEXT: csrr a5, vlenb2051; RV32-NEXT: slli a5, a5, 32052; RV32-NEXT: add a5, sp, a52053; RV32-NEXT: addi a5, a5, 162054; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill2055; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t2056; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t2057; RV32-NEXT: vand.vx v24, v24, a1, v0.t2058; RV32-NEXT: vor.vv v16, v24, v16, v0.t2059; RV32-NEXT: addi a1, sp, 162060; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill2061; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t2062; RV32-NEXT: vand.vx v24, v24, a3, v0.t2063; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t2064; RV32-NEXT: csrr a1, vlenb2065; RV32-NEXT: slli a1, a1, 42066; RV32-NEXT: add a1, sp, a12067; RV32-NEXT: addi a1, a1, 162068; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload2069; RV32-NEXT: vand.vv v8, v8, v16, v0.t2070; RV32-NEXT: vor.vv v8, v8, v24, v0.t2071; RV32-NEXT: addi a1, sp, 162072; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload2073; RV32-NEXT: vor.vv v8, v8, v16, v0.t2074; RV32-NEXT: lui a1, 616812075; RV32-NEXT: lui a2, 2097152076; RV32-NEXT: lui a3, 3495252077; RV32-NEXT: addi a1, a1, -2412078; RV32-NEXT: addi a2, a2, 8192079; RV32-NEXT: addi a3, a3, 13652080; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2081; RV32-NEXT: vmv.v.x v24, a12082; RV32-NEXT: csrr a1, vlenb2083; RV32-NEXT: slli a1, a1, 32084; RV32-NEXT: add a1, sp, a12085; RV32-NEXT: addi a1, a1, 162086; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload2087; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2088; RV32-NEXT: vor.vv v8, v16, v8, v0.t2089; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t2090; RV32-NEXT: vand.vv v16, v16, v24, v0.t2091; RV32-NEXT: vand.vv v24, v8, v24, v0.t2092; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma2093; RV32-NEXT: vmv.v.x v8, a22094; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2095; RV32-NEXT: vsll.vi v24, v24, 4, v0.t2096; RV32-NEXT: vor.vv v24, v16, v24, v0.t2097; RV32-NEXT: vsrl.vi v16, v24, 2, v0.t2098; RV32-NEXT: vand.vv v16, v16, v8, v0.t2099; RV32-NEXT: vand.vv v24, v24, v8, v0.t2100; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma2101; RV32-NEXT: vmv.v.x v8, a32102; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2103; RV32-NEXT: vsll.vi v24, v24, 2, v0.t2104; RV32-NEXT: vor.vv v16, v16, v24, v0.t2105; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t2106; RV32-NEXT: vand.vv v24, v24, v8, v0.t2107; RV32-NEXT: vand.vv v8, v16, v8, v0.t2108; RV32-NEXT: vsll.vi v8, v8, 1, v0.t2109; RV32-NEXT: vor.vv v8, v24, v8, v0.t2110; RV32-NEXT: csrr a0, vlenb2111; RV32-NEXT: li a1, 242112; RV32-NEXT: mul a0, a0, a12113; RV32-NEXT: add sp, sp, a02114; RV32-NEXT: .cfi_def_cfa sp, 162115; RV32-NEXT: addi sp, sp, 162116; RV32-NEXT: .cfi_def_cfa_offset 02117; RV32-NEXT: ret2118;2119; RV64-LABEL: vp_bitreverse_v16i64:2120; RV64: # %bb.0:2121; RV64-NEXT: addi sp, sp, -162122; RV64-NEXT: .cfi_def_cfa_offset 162123; RV64-NEXT: csrr a1, vlenb2124; RV64-NEXT: slli a1, a1, 32125; RV64-NEXT: sub sp, sp, a12126; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb2127; RV64-NEXT: lui a1, 40802128; RV64-NEXT: li a2, 2552129; RV64-NEXT: li a3, 562130; RV64-NEXT: lui a4, 162131; RV64-NEXT: li a5, 402132; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2133; RV64-NEXT: vand.vx v16, v8, a1, v0.t2134; RV64-NEXT: slli a2, a2, 242135; RV64-NEXT: addi a0, a4, -2562136; RV64-NEXT: vsll.vi v16, v16, 24, v0.t2137; RV64-NEXT: vand.vx v24, v8, a2, v0.t2138; RV64-NEXT: vsll.vi v24, v24, 8, v0.t2139; RV64-NEXT: vor.vv v16, v16, v24, v0.t2140; RV64-NEXT: addi a4, sp, 162141; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill2142; RV64-NEXT: vsll.vx v24, v8, a3, v0.t2143; RV64-NEXT: vand.vx v16, v8, a0, v0.t2144; RV64-NEXT: vsll.vx v16, v16, a5, v0.t2145; RV64-NEXT: vor.vv v16, v24, v16, v0.t2146; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload2147; RV64-NEXT: vor.vv v16, v16, v24, v0.t2148; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill2149; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t2150; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t2151; RV64-NEXT: vand.vx v16, v16, a0, v0.t2152; RV64-NEXT: vor.vv v24, v16, v24, v0.t2153; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t2154; RV64-NEXT: vand.vx v16, v16, a1, v0.t2155; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t2156; RV64-NEXT: vand.vx v8, v8, a2, v0.t2157; RV64-NEXT: vor.vv v8, v8, v16, v0.t2158; RV64-NEXT: vor.vv v8, v8, v24, v0.t2159; RV64-NEXT: lui a0, 616812160; RV64-NEXT: lui a1, 2097152161; RV64-NEXT: lui a2, 3495252162; RV64-NEXT: addi a0, a0, -2412163; RV64-NEXT: addi a1, a1, 8192164; RV64-NEXT: addi a2, a2, 13652165; RV64-NEXT: slli a3, a0, 322166; RV64-NEXT: slli a4, a1, 322167; RV64-NEXT: add a0, a0, a32168; RV64-NEXT: slli a3, a2, 322169; RV64-NEXT: add a1, a1, a42170; RV64-NEXT: add a2, a2, a32171; RV64-NEXT: addi a3, sp, 162172; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload2173; RV64-NEXT: vor.vv v8, v16, v8, v0.t2174; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t2175; RV64-NEXT: vand.vx v16, v16, a0, v0.t2176; RV64-NEXT: vand.vx v8, v8, a0, v0.t2177; RV64-NEXT: vsll.vi v8, v8, 4, v0.t2178; RV64-NEXT: vor.vv v8, v16, v8, v0.t2179; RV64-NEXT: vsrl.vi v16, v8, 2, v0.t2180; RV64-NEXT: vand.vx v16, v16, a1, v0.t2181; RV64-NEXT: vand.vx v8, v8, a1, v0.t2182; RV64-NEXT: vsll.vi v8, v8, 2, v0.t2183; RV64-NEXT: vor.vv v8, v16, v8, v0.t2184; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t2185; RV64-NEXT: vand.vx v16, v16, a2, v0.t2186; RV64-NEXT: vand.vx v8, v8, a2, v0.t2187; RV64-NEXT: vsll.vi v8, v8, 1, v0.t2188; RV64-NEXT: vor.vv v8, v16, v8, v0.t2189; RV64-NEXT: csrr a0, vlenb2190; RV64-NEXT: slli a0, a0, 32191; RV64-NEXT: add sp, sp, a02192; RV64-NEXT: .cfi_def_cfa sp, 162193; RV64-NEXT: addi sp, sp, 162194; RV64-NEXT: .cfi_def_cfa_offset 02195; RV64-NEXT: ret2196 %v = call <16 x i64> @llvm.vp.bitreverse.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl)2197 ret <16 x i64> %v2198}2199 2200define <16 x i64> @vp_bitreverse_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {2201; RV32-LABEL: vp_bitreverse_v16i64_unmasked:2202; RV32: # %bb.0:2203; RV32-NEXT: addi sp, sp, -162204; RV32-NEXT: .cfi_def_cfa_offset 162205; RV32-NEXT: csrr a1, vlenb2206; RV32-NEXT: slli a1, a1, 42207; RV32-NEXT: sub sp, sp, a12208; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb2209; RV32-NEXT: lui a1, 10444802210; RV32-NEXT: li a2, 562211; RV32-NEXT: lui a3, 162212; RV32-NEXT: li a4, 402213; RV32-NEXT: lui a5, 40802214; RV32-NEXT: addi a6, sp, 82215; RV32-NEXT: sw a1, 8(sp)2216; RV32-NEXT: sw zero, 12(sp)2217; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2218; RV32-NEXT: vsll.vx v16, v8, a22219; RV32-NEXT: addi a1, a3, -2562220; RV32-NEXT: vsrl.vx v24, v8, a22221; RV32-NEXT: vsrl.vx v0, v8, a42222; RV32-NEXT: vand.vx v0, v0, a12223; RV32-NEXT: vor.vv v24, v0, v242224; RV32-NEXT: addi a2, sp, 162225; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill2226; RV32-NEXT: vand.vx v24, v8, a12227; RV32-NEXT: vsll.vx v24, v24, a42228; RV32-NEXT: vor.vv v16, v16, v242229; RV32-NEXT: csrr a1, vlenb2230; RV32-NEXT: slli a1, a1, 32231; RV32-NEXT: add a1, sp, a12232; RV32-NEXT: addi a1, a1, 162233; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill2234; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma2235; RV32-NEXT: vlse64.v v24, (a6), zero2236; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2237; RV32-NEXT: vsrl.vi v16, v8, 242238; RV32-NEXT: vand.vx v16, v16, a52239; RV32-NEXT: vsrl.vi v0, v8, 82240; RV32-NEXT: vand.vv v0, v0, v242241; RV32-NEXT: vor.vv v16, v0, v162242; RV32-NEXT: vand.vv v24, v8, v242243; RV32-NEXT: vand.vx v8, v8, a52244; RV32-NEXT: vsll.vi v8, v8, 242245; RV32-NEXT: vsll.vi v24, v24, 82246; RV32-NEXT: vor.vv v24, v8, v242247; RV32-NEXT: addi a1, sp, 162248; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload2249; RV32-NEXT: vor.vv v8, v16, v82250; RV32-NEXT: lui a1, 616812251; RV32-NEXT: lui a2, 2097152252; RV32-NEXT: lui a3, 3495252253; RV32-NEXT: addi a1, a1, -2412254; RV32-NEXT: addi a2, a2, 8192255; RV32-NEXT: addi a3, a3, 13652256; RV32-NEXT: csrr a4, vlenb2257; RV32-NEXT: slli a4, a4, 32258; RV32-NEXT: add a4, sp, a42259; RV32-NEXT: addi a4, a4, 162260; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload2261; RV32-NEXT: vor.vv v16, v16, v242262; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2263; RV32-NEXT: vmv.v.x v24, a12264; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2265; RV32-NEXT: vor.vv v8, v16, v82266; RV32-NEXT: vsrl.vi v16, v8, 42267; RV32-NEXT: vand.vv v8, v8, v242268; RV32-NEXT: vand.vv v16, v16, v242269; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma2270; RV32-NEXT: vmv.v.x v24, a22271; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2272; RV32-NEXT: vsll.vi v8, v8, 42273; RV32-NEXT: vor.vv v8, v16, v82274; RV32-NEXT: vsrl.vi v16, v8, 22275; RV32-NEXT: vand.vv v8, v8, v242276; RV32-NEXT: vand.vv v16, v16, v242277; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma2278; RV32-NEXT: vmv.v.x v24, a32279; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2280; RV32-NEXT: vsll.vi v8, v8, 22281; RV32-NEXT: vor.vv v8, v16, v82282; RV32-NEXT: vsrl.vi v16, v8, 12283; RV32-NEXT: vand.vv v8, v8, v242284; RV32-NEXT: vand.vv v16, v16, v242285; RV32-NEXT: vadd.vv v8, v8, v82286; RV32-NEXT: vor.vv v8, v16, v82287; RV32-NEXT: csrr a0, vlenb2288; RV32-NEXT: slli a0, a0, 42289; RV32-NEXT: add sp, sp, a02290; RV32-NEXT: .cfi_def_cfa sp, 162291; RV32-NEXT: addi sp, sp, 162292; RV32-NEXT: .cfi_def_cfa_offset 02293; RV32-NEXT: ret2294;2295; RV64-LABEL: vp_bitreverse_v16i64_unmasked:2296; RV64: # %bb.0:2297; RV64-NEXT: addi sp, sp, -162298; RV64-NEXT: .cfi_def_cfa_offset 162299; RV64-NEXT: csrr a1, vlenb2300; RV64-NEXT: slli a1, a1, 32301; RV64-NEXT: sub sp, sp, a12302; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb2303; RV64-NEXT: lui a1, 40802304; RV64-NEXT: li a2, 2552305; RV64-NEXT: li a3, 562306; RV64-NEXT: lui a4, 162307; RV64-NEXT: li a5, 402308; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2309; RV64-NEXT: vsrl.vi v24, v8, 242310; RV64-NEXT: addi a0, a4, -2562311; RV64-NEXT: vsrl.vx v16, v8, a32312; RV64-NEXT: vsrl.vx v0, v8, a52313; RV64-NEXT: vand.vx v0, v0, a02314; RV64-NEXT: vor.vv v16, v0, v162315; RV64-NEXT: addi a4, sp, 162316; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill2317; RV64-NEXT: vsrl.vi v0, v8, 82318; RV64-NEXT: slli a2, a2, 242319; RV64-NEXT: vand.vx v24, v24, a12320; RV64-NEXT: vand.vx v0, v0, a22321; RV64-NEXT: vor.vv v24, v0, v242322; RV64-NEXT: vand.vx v0, v8, a12323; RV64-NEXT: vsll.vi v0, v0, 242324; RV64-NEXT: vand.vx v16, v8, a22325; RV64-NEXT: vsll.vi v16, v16, 82326; RV64-NEXT: vor.vv v0, v0, v162327; RV64-NEXT: vsll.vx v16, v8, a32328; RV64-NEXT: vand.vx v8, v8, a02329; RV64-NEXT: vsll.vx v8, v8, a52330; RV64-NEXT: vor.vv v8, v16, v82331; RV64-NEXT: lui a0, 616812332; RV64-NEXT: lui a1, 2097152333; RV64-NEXT: lui a2, 3495252334; RV64-NEXT: addi a0, a0, -2412335; RV64-NEXT: addi a1, a1, 8192336; RV64-NEXT: addi a2, a2, 13652337; RV64-NEXT: slli a3, a0, 322338; RV64-NEXT: slli a4, a1, 322339; RV64-NEXT: add a0, a0, a32340; RV64-NEXT: slli a3, a2, 322341; RV64-NEXT: add a1, a1, a42342; RV64-NEXT: add a2, a2, a32343; RV64-NEXT: addi a3, sp, 162344; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload2345; RV64-NEXT: vor.vv v16, v24, v162346; RV64-NEXT: vor.vv v8, v8, v02347; RV64-NEXT: vor.vv v8, v8, v162348; RV64-NEXT: vsrl.vi v16, v8, 42349; RV64-NEXT: vand.vx v8, v8, a02350; RV64-NEXT: vand.vx v16, v16, a02351; RV64-NEXT: vsll.vi v8, v8, 42352; RV64-NEXT: vor.vv v8, v16, v82353; RV64-NEXT: vsrl.vi v16, v8, 22354; RV64-NEXT: vand.vx v8, v8, a12355; RV64-NEXT: vand.vx v16, v16, a12356; RV64-NEXT: vsll.vi v8, v8, 22357; RV64-NEXT: vor.vv v8, v16, v82358; RV64-NEXT: vsrl.vi v16, v8, 12359; RV64-NEXT: vand.vx v8, v8, a22360; RV64-NEXT: vand.vx v16, v16, a22361; RV64-NEXT: vadd.vv v8, v8, v82362; RV64-NEXT: vor.vv v8, v16, v82363; RV64-NEXT: csrr a0, vlenb2364; RV64-NEXT: slli a0, a0, 32365; RV64-NEXT: add sp, sp, a02366; RV64-NEXT: .cfi_def_cfa sp, 162367; RV64-NEXT: addi sp, sp, 162368; RV64-NEXT: .cfi_def_cfa_offset 02369; RV64-NEXT: ret2370 %v = call <16 x i64> @llvm.vp.bitreverse.v16i64(<16 x i64> %va, <16 x i1> splat (i1 true), i32 %evl)2371 ret <16 x i64> %v2372}2373 2374define <128 x i16> @vp_bitreverse_v128i16(<128 x i16> %va, <128 x i1> %m, i32 zeroext %evl) {2375; CHECK-LABEL: vp_bitreverse_v128i16:2376; CHECK: # %bb.0:2377; CHECK-NEXT: li a2, 642378; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma2379; CHECK-NEXT: vslidedown.vi v7, v0, 82380; CHECK-NEXT: mv a1, a02381; CHECK-NEXT: bltu a0, a2, .LBB34_22382; CHECK-NEXT: # %bb.1:2383; CHECK-NEXT: li a1, 642384; CHECK-NEXT: .LBB34_2:2385; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma2386; CHECK-NEXT: vsrl.vi v24, v8, 8, v0.t2387; CHECK-NEXT: lui a1, 12388; CHECK-NEXT: lui a2, 32389; CHECK-NEXT: addi a3, a0, -642390; CHECK-NEXT: sltu a0, a0, a32391; CHECK-NEXT: addi a0, a0, -12392; CHECK-NEXT: and a3, a0, a32393; CHECK-NEXT: lui a0, 52394; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t2395; CHECK-NEXT: addi a1, a1, -2412396; CHECK-NEXT: addi a2, a2, 8192397; CHECK-NEXT: addi a0, a0, 13652398; CHECK-NEXT: vor.vv v8, v8, v24, v0.t2399; CHECK-NEXT: vsrl.vi v24, v8, 4, v0.t2400; CHECK-NEXT: vand.vx v24, v24, a1, v0.t2401; CHECK-NEXT: vand.vx v8, v8, a1, v0.t2402; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t2403; CHECK-NEXT: vor.vv v8, v24, v8, v0.t2404; CHECK-NEXT: vsrl.vi v24, v8, 2, v0.t2405; CHECK-NEXT: vand.vx v24, v24, a2, v0.t2406; CHECK-NEXT: vand.vx v8, v8, a2, v0.t2407; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t2408; CHECK-NEXT: vor.vv v8, v24, v8, v0.t2409; CHECK-NEXT: vsrl.vi v24, v8, 1, v0.t2410; CHECK-NEXT: vand.vx v24, v24, a0, v0.t2411; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2412; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t2413; CHECK-NEXT: vor.vv v8, v24, v8, v0.t2414; CHECK-NEXT: vmv1r.v v0, v72415; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma2416; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t2417; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t2418; CHECK-NEXT: vor.vv v16, v16, v24, v0.t2419; CHECK-NEXT: vsrl.vi v24, v16, 4, v0.t2420; CHECK-NEXT: vand.vx v24, v24, a1, v0.t2421; CHECK-NEXT: vand.vx v16, v16, a1, v0.t2422; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t2423; CHECK-NEXT: vor.vv v16, v24, v16, v0.t2424; CHECK-NEXT: vsrl.vi v24, v16, 2, v0.t2425; CHECK-NEXT: vand.vx v24, v24, a2, v0.t2426; CHECK-NEXT: vand.vx v16, v16, a2, v0.t2427; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t2428; CHECK-NEXT: vor.vv v16, v24, v16, v0.t2429; CHECK-NEXT: vsrl.vi v24, v16, 1, v0.t2430; CHECK-NEXT: vand.vx v24, v24, a0, v0.t2431; CHECK-NEXT: vand.vx v16, v16, a0, v0.t2432; CHECK-NEXT: vsll.vi v16, v16, 1, v0.t2433; CHECK-NEXT: vor.vv v16, v24, v16, v0.t2434; CHECK-NEXT: ret2435 %v = call <128 x i16> @llvm.vp.bitreverse.v128i16(<128 x i16> %va, <128 x i1> %m, i32 %evl)2436 ret <128 x i16> %v2437}2438 2439define <128 x i16> @vp_bitreverse_v128i16_unmasked(<128 x i16> %va, i32 zeroext %evl) {2440; CHECK-LABEL: vp_bitreverse_v128i16_unmasked:2441; CHECK: # %bb.0:2442; CHECK-NEXT: li a2, 642443; CHECK-NEXT: mv a1, a02444; CHECK-NEXT: bltu a0, a2, .LBB35_22445; CHECK-NEXT: # %bb.1:2446; CHECK-NEXT: li a1, 642447; CHECK-NEXT: .LBB35_2:2448; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma2449; CHECK-NEXT: vsrl.vi v24, v8, 82450; CHECK-NEXT: vsll.vi v8, v8, 82451; CHECK-NEXT: lui a2, 12452; CHECK-NEXT: lui a3, 32453; CHECK-NEXT: addi a4, a0, -642454; CHECK-NEXT: sltu a0, a0, a42455; CHECK-NEXT: addi a0, a0, -12456; CHECK-NEXT: and a0, a0, a42457; CHECK-NEXT: lui a4, 52458; CHECK-NEXT: vor.vv v8, v8, v242459; CHECK-NEXT: addi a2, a2, -2412460; CHECK-NEXT: addi a3, a3, 8192461; CHECK-NEXT: addi a4, a4, 13652462; CHECK-NEXT: vsrl.vi v24, v8, 42463; CHECK-NEXT: vand.vx v8, v8, a22464; CHECK-NEXT: vand.vx v24, v24, a22465; CHECK-NEXT: vsll.vi v8, v8, 42466; CHECK-NEXT: vor.vv v8, v24, v82467; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma2468; CHECK-NEXT: vsrl.vi v24, v16, 82469; CHECK-NEXT: vsll.vi v16, v16, 82470; CHECK-NEXT: vor.vv v16, v16, v242471; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma2472; CHECK-NEXT: vsrl.vi v24, v8, 22473; CHECK-NEXT: vand.vx v8, v8, a32474; CHECK-NEXT: vand.vx v24, v24, a32475; CHECK-NEXT: vsll.vi v8, v8, 22476; CHECK-NEXT: vor.vv v8, v24, v82477; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma2478; CHECK-NEXT: vsrl.vi v24, v16, 42479; CHECK-NEXT: vand.vx v16, v16, a22480; CHECK-NEXT: vand.vx v24, v24, a22481; CHECK-NEXT: vsll.vi v16, v16, 42482; CHECK-NEXT: vor.vv v16, v24, v162483; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma2484; CHECK-NEXT: vsrl.vi v24, v8, 12485; CHECK-NEXT: vand.vx v8, v8, a42486; CHECK-NEXT: vand.vx v24, v24, a42487; CHECK-NEXT: vadd.vv v8, v8, v82488; CHECK-NEXT: vor.vv v8, v24, v82489; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma2490; CHECK-NEXT: vsrl.vi v24, v16, 22491; CHECK-NEXT: vand.vx v16, v16, a32492; CHECK-NEXT: vand.vx v24, v24, a32493; CHECK-NEXT: vsll.vi v16, v16, 22494; CHECK-NEXT: vor.vv v16, v24, v162495; CHECK-NEXT: vsrl.vi v24, v16, 12496; CHECK-NEXT: vand.vx v16, v16, a42497; CHECK-NEXT: vand.vx v24, v24, a42498; CHECK-NEXT: vadd.vv v16, v16, v162499; CHECK-NEXT: vor.vv v16, v24, v162500; CHECK-NEXT: ret2501 %v = call <128 x i16> @llvm.vp.bitreverse.v128i16(<128 x i16> %va, <128 x i1> splat (i1 true), i32 %evl)2502 ret <128 x i16> %v2503}2504