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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB6 7define void @bitreverse_v8i16(ptr %x, ptr %y) {8; CHECK-LABEL: bitreverse_v8i16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma11; CHECK-NEXT: vle16.v v8, (a0)12; CHECK-NEXT: lui a1, 113; CHECK-NEXT: addi a1, a1, -24114; CHECK-NEXT: vsrl.vi v9, v8, 815; CHECK-NEXT: vsll.vi v8, v8, 816; CHECK-NEXT: vor.vv v8, v8, v917; CHECK-NEXT: vsrl.vi v9, v8, 418; CHECK-NEXT: vand.vx v8, v8, a119; CHECK-NEXT: vand.vx v9, v9, a120; CHECK-NEXT: lui a1, 321; CHECK-NEXT: addi a1, a1, 81922; CHECK-NEXT: vsll.vi v8, v8, 423; CHECK-NEXT: vor.vv v8, v9, v824; CHECK-NEXT: vsrl.vi v9, v8, 225; CHECK-NEXT: vand.vx v8, v8, a126; CHECK-NEXT: vand.vx v9, v9, a127; CHECK-NEXT: lui a1, 528; CHECK-NEXT: addi a1, a1, 136529; CHECK-NEXT: vsll.vi v8, v8, 230; CHECK-NEXT: vor.vv v8, v9, v831; CHECK-NEXT: vsrl.vi v9, v8, 132; CHECK-NEXT: vand.vx v8, v8, a133; CHECK-NEXT: vand.vx v9, v9, a134; CHECK-NEXT: vadd.vv v8, v8, v835; CHECK-NEXT: vor.vv v8, v9, v836; CHECK-NEXT: vse16.v v8, (a0)37; CHECK-NEXT: ret38;39; ZVBB-LABEL: bitreverse_v8i16:40; ZVBB: # %bb.0:41; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma42; ZVBB-NEXT: vle16.v v8, (a0)43; ZVBB-NEXT: vbrev.v v8, v844; ZVBB-NEXT: vse16.v v8, (a0)45; ZVBB-NEXT: ret46 %a = load <8 x i16>, ptr %x47 %b = load <8 x i16>, ptr %y48 %c = call <8 x i16> @llvm.bitreverse.v8i16(<8 x i16> %a)49 store <8 x i16> %c, ptr %x50 ret void51}52 53define void @bitreverse_v4i32(ptr %x, ptr %y) {54; CHECK-LABEL: bitreverse_v4i32:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma57; CHECK-NEXT: vle32.v v8, (a0)58; CHECK-NEXT: lui a1, 1659; CHECK-NEXT: addi a1, a1, -25660; CHECK-NEXT: vsrl.vi v9, v8, 861; CHECK-NEXT: vsrl.vi v10, v8, 2462; CHECK-NEXT: vand.vx v9, v9, a163; CHECK-NEXT: vor.vv v9, v9, v1064; CHECK-NEXT: vand.vx v10, v8, a165; CHECK-NEXT: lui a1, 6168166; CHECK-NEXT: addi a1, a1, -24167; CHECK-NEXT: vsll.vi v8, v8, 2468; CHECK-NEXT: vsll.vi v10, v10, 869; CHECK-NEXT: vor.vv v8, v8, v1070; CHECK-NEXT: vor.vv v8, v8, v971; CHECK-NEXT: vsrl.vi v9, v8, 472; CHECK-NEXT: vand.vx v8, v8, a173; CHECK-NEXT: vand.vx v9, v9, a174; CHECK-NEXT: lui a1, 20971575; CHECK-NEXT: addi a1, a1, 81976; CHECK-NEXT: vsll.vi v8, v8, 477; CHECK-NEXT: vor.vv v8, v9, v878; CHECK-NEXT: vsrl.vi v9, v8, 279; CHECK-NEXT: vand.vx v8, v8, a180; CHECK-NEXT: vand.vx v9, v9, a181; CHECK-NEXT: lui a1, 34952582; CHECK-NEXT: addi a1, a1, 136583; CHECK-NEXT: vsll.vi v8, v8, 284; CHECK-NEXT: vor.vv v8, v9, v885; CHECK-NEXT: vsrl.vi v9, v8, 186; CHECK-NEXT: vand.vx v8, v8, a187; CHECK-NEXT: vand.vx v9, v9, a188; CHECK-NEXT: vadd.vv v8, v8, v889; CHECK-NEXT: vor.vv v8, v9, v890; CHECK-NEXT: vse32.v v8, (a0)91; CHECK-NEXT: ret92;93; ZVBB-LABEL: bitreverse_v4i32:94; ZVBB: # %bb.0:95; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma96; ZVBB-NEXT: vle32.v v8, (a0)97; ZVBB-NEXT: vbrev.v v8, v898; ZVBB-NEXT: vse32.v v8, (a0)99; ZVBB-NEXT: ret100 %a = load <4 x i32>, ptr %x101 %b = load <4 x i32>, ptr %y102 %c = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> %a)103 store <4 x i32> %c, ptr %x104 ret void105}106 107define void @bitreverse_v2i64(ptr %x, ptr %y) {108; RV32-LABEL: bitreverse_v2i64:109; RV32: # %bb.0:110; RV32-NEXT: addi sp, sp, -16111; RV32-NEXT: .cfi_def_cfa_offset 16112; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma113; RV32-NEXT: vle64.v v8, (a0)114; RV32-NEXT: lui a2, 1044480115; RV32-NEXT: li a3, 56116; RV32-NEXT: li a4, 40117; RV32-NEXT: lui a5, 16118; RV32-NEXT: lui a1, 4080119; RV32-NEXT: addi a6, sp, 8120; RV32-NEXT: sw a2, 8(sp)121; RV32-NEXT: sw zero, 12(sp)122; RV32-NEXT: addi a2, a5, -256123; RV32-NEXT: vlse64.v v9, (a6), zero124; RV32-NEXT: vsrl.vx v10, v8, a3125; RV32-NEXT: vsrl.vx v11, v8, a4126; RV32-NEXT: vsrl.vi v12, v8, 24127; RV32-NEXT: vsll.vx v13, v8, a3128; RV32-NEXT: vand.vx v11, v11, a2129; RV32-NEXT: vor.vv v10, v11, v10130; RV32-NEXT: vand.vx v11, v8, a2131; RV32-NEXT: vsll.vx v11, v11, a4132; RV32-NEXT: vor.vv v11, v13, v11133; RV32-NEXT: vsrl.vi v13, v8, 8134; RV32-NEXT: vand.vx v12, v12, a1135; RV32-NEXT: vand.vv v13, v13, v9136; RV32-NEXT: vor.vv v12, v13, v12137; RV32-NEXT: lui a2, 61681138; RV32-NEXT: lui a3, 209715139; RV32-NEXT: lui a4, 349525140; RV32-NEXT: addi a2, a2, -241141; RV32-NEXT: addi a3, a3, 819142; RV32-NEXT: addi a4, a4, 1365143; RV32-NEXT: vor.vv v10, v12, v10144; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma145; RV32-NEXT: vmv.v.x v12, a2146; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma147; RV32-NEXT: vand.vv v9, v8, v9148; RV32-NEXT: vand.vx v8, v8, a1149; RV32-NEXT: vsll.vi v8, v8, 24150; RV32-NEXT: vsll.vi v9, v9, 8151; RV32-NEXT: vor.vv v8, v8, v9152; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma153; RV32-NEXT: vmv.v.x v9, a3154; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma155; RV32-NEXT: vor.vv v8, v11, v8156; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma157; RV32-NEXT: vmv.v.x v11, a4158; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma159; RV32-NEXT: vor.vv v8, v8, v10160; RV32-NEXT: vsrl.vi v10, v8, 4161; RV32-NEXT: vand.vv v8, v8, v12162; RV32-NEXT: vand.vv v10, v10, v12163; RV32-NEXT: vsll.vi v8, v8, 4164; RV32-NEXT: vor.vv v8, v10, v8165; RV32-NEXT: vsrl.vi v10, v8, 2166; RV32-NEXT: vand.vv v8, v8, v9167; RV32-NEXT: vand.vv v9, v10, v9168; RV32-NEXT: vsll.vi v8, v8, 2169; RV32-NEXT: vor.vv v8, v9, v8170; RV32-NEXT: vsrl.vi v9, v8, 1171; RV32-NEXT: vand.vv v8, v8, v11172; RV32-NEXT: vand.vv v9, v9, v11173; RV32-NEXT: vadd.vv v8, v8, v8174; RV32-NEXT: vor.vv v8, v9, v8175; RV32-NEXT: vse64.v v8, (a0)176; RV32-NEXT: addi sp, sp, 16177; RV32-NEXT: .cfi_def_cfa_offset 0178; RV32-NEXT: ret179;180; RV64-LABEL: bitreverse_v2i64:181; RV64: # %bb.0:182; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma183; RV64-NEXT: vle64.v v8, (a0)184; RV64-NEXT: li a1, 56185; RV64-NEXT: li a2, 40186; RV64-NEXT: lui a3, 16187; RV64-NEXT: lui a4, 4080188; RV64-NEXT: li a5, 255189; RV64-NEXT: addi a3, a3, -256190; RV64-NEXT: slli a5, a5, 24191; RV64-NEXT: vsrl.vx v9, v8, a1192; RV64-NEXT: vsrl.vx v10, v8, a2193; RV64-NEXT: vsrl.vi v11, v8, 24194; RV64-NEXT: vsrl.vi v12, v8, 8195; RV64-NEXT: vand.vx v10, v10, a3196; RV64-NEXT: vor.vv v9, v10, v9197; RV64-NEXT: vand.vx v10, v8, a5198; RV64-NEXT: vand.vx v11, v11, a4199; RV64-NEXT: vand.vx v12, v12, a5200; RV64-NEXT: vor.vv v11, v12, v11201; RV64-NEXT: vand.vx v12, v8, a4202; RV64-NEXT: vsll.vi v10, v10, 8203; RV64-NEXT: vsll.vi v12, v12, 24204; RV64-NEXT: vor.vv v10, v12, v10205; RV64-NEXT: vsll.vx v12, v8, a1206; RV64-NEXT: vand.vx v8, v8, a3207; RV64-NEXT: vsll.vx v8, v8, a2208; RV64-NEXT: vor.vv v8, v12, v8209; RV64-NEXT: lui a1, 61681210; RV64-NEXT: lui a2, 209715211; RV64-NEXT: lui a3, 349525212; RV64-NEXT: addi a1, a1, -241213; RV64-NEXT: addi a2, a2, 819214; RV64-NEXT: addi a3, a3, 1365215; RV64-NEXT: slli a4, a1, 32216; RV64-NEXT: slli a5, a2, 32217; RV64-NEXT: add a1, a1, a4218; RV64-NEXT: slli a4, a3, 32219; RV64-NEXT: add a2, a2, a5220; RV64-NEXT: add a3, a3, a4221; RV64-NEXT: vor.vv v9, v11, v9222; RV64-NEXT: vor.vv v8, v8, v10223; RV64-NEXT: vor.vv v8, v8, v9224; RV64-NEXT: vsrl.vi v9, v8, 4225; RV64-NEXT: vand.vx v8, v8, a1226; RV64-NEXT: vand.vx v9, v9, a1227; RV64-NEXT: vsll.vi v8, v8, 4228; RV64-NEXT: vor.vv v8, v9, v8229; RV64-NEXT: vsrl.vi v9, v8, 2230; RV64-NEXT: vand.vx v8, v8, a2231; RV64-NEXT: vand.vx v9, v9, a2232; RV64-NEXT: vsll.vi v8, v8, 2233; RV64-NEXT: vor.vv v8, v9, v8234; RV64-NEXT: vsrl.vi v9, v8, 1235; RV64-NEXT: vand.vx v8, v8, a3236; RV64-NEXT: vand.vx v9, v9, a3237; RV64-NEXT: vadd.vv v8, v8, v8238; RV64-NEXT: vor.vv v8, v9, v8239; RV64-NEXT: vse64.v v8, (a0)240; RV64-NEXT: ret241;242; ZVBB-LABEL: bitreverse_v2i64:243; ZVBB: # %bb.0:244; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma245; ZVBB-NEXT: vle64.v v8, (a0)246; ZVBB-NEXT: vbrev.v v8, v8247; ZVBB-NEXT: vse64.v v8, (a0)248; ZVBB-NEXT: ret249 %a = load <2 x i64>, ptr %x250 %b = load <2 x i64>, ptr %y251 %c = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %a)252 store <2 x i64> %c, ptr %x253 ret void254}255 256define void @bitreverse_v16i16(ptr %x, ptr %y) {257; CHECK-LABEL: bitreverse_v16i16:258; CHECK: # %bb.0:259; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma260; CHECK-NEXT: vle16.v v8, (a0)261; CHECK-NEXT: lui a1, 1262; CHECK-NEXT: addi a1, a1, -241263; CHECK-NEXT: vsrl.vi v10, v8, 8264; CHECK-NEXT: vsll.vi v8, v8, 8265; CHECK-NEXT: vor.vv v8, v8, v10266; CHECK-NEXT: vsrl.vi v10, v8, 4267; CHECK-NEXT: vand.vx v8, v8, a1268; CHECK-NEXT: vand.vx v10, v10, a1269; CHECK-NEXT: lui a1, 3270; CHECK-NEXT: addi a1, a1, 819271; CHECK-NEXT: vsll.vi v8, v8, 4272; CHECK-NEXT: vor.vv v8, v10, v8273; CHECK-NEXT: vsrl.vi v10, v8, 2274; CHECK-NEXT: vand.vx v8, v8, a1275; CHECK-NEXT: vand.vx v10, v10, a1276; CHECK-NEXT: lui a1, 5277; CHECK-NEXT: addi a1, a1, 1365278; CHECK-NEXT: vsll.vi v8, v8, 2279; CHECK-NEXT: vor.vv v8, v10, v8280; CHECK-NEXT: vsrl.vi v10, v8, 1281; CHECK-NEXT: vand.vx v8, v8, a1282; CHECK-NEXT: vand.vx v10, v10, a1283; CHECK-NEXT: vadd.vv v8, v8, v8284; CHECK-NEXT: vor.vv v8, v10, v8285; CHECK-NEXT: vse16.v v8, (a0)286; CHECK-NEXT: ret287;288; ZVBB-LABEL: bitreverse_v16i16:289; ZVBB: # %bb.0:290; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma291; ZVBB-NEXT: vle16.v v8, (a0)292; ZVBB-NEXT: vbrev.v v8, v8293; ZVBB-NEXT: vse16.v v8, (a0)294; ZVBB-NEXT: ret295 %a = load <16 x i16>, ptr %x296 %b = load <16 x i16>, ptr %y297 %c = call <16 x i16> @llvm.bitreverse.v16i16(<16 x i16> %a)298 store <16 x i16> %c, ptr %x299 ret void300}301 302define void @bitreverse_v8i32(ptr %x, ptr %y) {303; CHECK-LABEL: bitreverse_v8i32:304; CHECK: # %bb.0:305; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma306; CHECK-NEXT: vle32.v v8, (a0)307; CHECK-NEXT: lui a1, 16308; CHECK-NEXT: addi a1, a1, -256309; CHECK-NEXT: vsrl.vi v10, v8, 8310; CHECK-NEXT: vsrl.vi v12, v8, 24311; CHECK-NEXT: vand.vx v10, v10, a1312; CHECK-NEXT: vor.vv v10, v10, v12313; CHECK-NEXT: vand.vx v12, v8, a1314; CHECK-NEXT: lui a1, 61681315; CHECK-NEXT: addi a1, a1, -241316; CHECK-NEXT: vsll.vi v8, v8, 24317; CHECK-NEXT: vsll.vi v12, v12, 8318; CHECK-NEXT: vor.vv v8, v8, v12319; CHECK-NEXT: vor.vv v8, v8, v10320; CHECK-NEXT: vsrl.vi v10, v8, 4321; CHECK-NEXT: vand.vx v8, v8, a1322; CHECK-NEXT: vand.vx v10, v10, a1323; CHECK-NEXT: lui a1, 209715324; CHECK-NEXT: addi a1, a1, 819325; CHECK-NEXT: vsll.vi v8, v8, 4326; CHECK-NEXT: vor.vv v8, v10, v8327; CHECK-NEXT: vsrl.vi v10, v8, 2328; CHECK-NEXT: vand.vx v8, v8, a1329; CHECK-NEXT: vand.vx v10, v10, a1330; CHECK-NEXT: lui a1, 349525331; CHECK-NEXT: addi a1, a1, 1365332; CHECK-NEXT: vsll.vi v8, v8, 2333; CHECK-NEXT: vor.vv v8, v10, v8334; CHECK-NEXT: vsrl.vi v10, v8, 1335; CHECK-NEXT: vand.vx v8, v8, a1336; CHECK-NEXT: vand.vx v10, v10, a1337; CHECK-NEXT: vadd.vv v8, v8, v8338; CHECK-NEXT: vor.vv v8, v10, v8339; CHECK-NEXT: vse32.v v8, (a0)340; CHECK-NEXT: ret341;342; ZVBB-LABEL: bitreverse_v8i32:343; ZVBB: # %bb.0:344; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma345; ZVBB-NEXT: vle32.v v8, (a0)346; ZVBB-NEXT: vbrev.v v8, v8347; ZVBB-NEXT: vse32.v v8, (a0)348; ZVBB-NEXT: ret349 %a = load <8 x i32>, ptr %x350 %b = load <8 x i32>, ptr %y351 %c = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %a)352 store <8 x i32> %c, ptr %x353 ret void354}355 356define void @bitreverse_v4i64(ptr %x, ptr %y) {357; RV32-LABEL: bitreverse_v4i64:358; RV32: # %bb.0:359; RV32-NEXT: addi sp, sp, -16360; RV32-NEXT: .cfi_def_cfa_offset 16361; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma362; RV32-NEXT: vle64.v v8, (a0)363; RV32-NEXT: lui a2, 1044480364; RV32-NEXT: li a3, 56365; RV32-NEXT: li a4, 40366; RV32-NEXT: lui a5, 16367; RV32-NEXT: lui a1, 4080368; RV32-NEXT: addi a6, sp, 8369; RV32-NEXT: sw a2, 8(sp)370; RV32-NEXT: sw zero, 12(sp)371; RV32-NEXT: addi a2, a5, -256372; RV32-NEXT: vlse64.v v10, (a6), zero373; RV32-NEXT: vsrl.vx v12, v8, a3374; RV32-NEXT: vsrl.vx v14, v8, a4375; RV32-NEXT: vsrl.vi v16, v8, 24376; RV32-NEXT: vsll.vx v18, v8, a3377; RV32-NEXT: vand.vx v14, v14, a2378; RV32-NEXT: vor.vv v14, v14, v12379; RV32-NEXT: vand.vx v12, v8, a2380; RV32-NEXT: vsll.vx v12, v12, a4381; RV32-NEXT: vor.vv v12, v18, v12382; RV32-NEXT: vsrl.vi v18, v8, 8383; RV32-NEXT: vand.vx v16, v16, a1384; RV32-NEXT: vand.vv v18, v18, v10385; RV32-NEXT: vor.vv v16, v18, v16386; RV32-NEXT: lui a2, 61681387; RV32-NEXT: lui a3, 209715388; RV32-NEXT: lui a4, 349525389; RV32-NEXT: addi a2, a2, -241390; RV32-NEXT: addi a3, a3, 819391; RV32-NEXT: addi a4, a4, 1365392; RV32-NEXT: vor.vv v14, v16, v14393; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma394; RV32-NEXT: vmv.v.x v16, a2395; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma396; RV32-NEXT: vand.vv v10, v8, v10397; RV32-NEXT: vand.vx v8, v8, a1398; RV32-NEXT: vsll.vi v8, v8, 24399; RV32-NEXT: vsll.vi v10, v10, 8400; RV32-NEXT: vor.vv v8, v8, v10401; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma402; RV32-NEXT: vmv.v.x v10, a3403; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma404; RV32-NEXT: vor.vv v8, v12, v8405; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma406; RV32-NEXT: vmv.v.x v12, a4407; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma408; RV32-NEXT: vor.vv v8, v8, v14409; RV32-NEXT: vsrl.vi v14, v8, 4410; RV32-NEXT: vand.vv v8, v8, v16411; RV32-NEXT: vand.vv v14, v14, v16412; RV32-NEXT: vsll.vi v8, v8, 4413; RV32-NEXT: vor.vv v8, v14, v8414; RV32-NEXT: vsrl.vi v14, v8, 2415; RV32-NEXT: vand.vv v8, v8, v10416; RV32-NEXT: vand.vv v10, v14, v10417; RV32-NEXT: vsll.vi v8, v8, 2418; RV32-NEXT: vor.vv v8, v10, v8419; RV32-NEXT: vsrl.vi v10, v8, 1420; RV32-NEXT: vand.vv v8, v8, v12421; RV32-NEXT: vand.vv v10, v10, v12422; RV32-NEXT: vadd.vv v8, v8, v8423; RV32-NEXT: vor.vv v8, v10, v8424; RV32-NEXT: vse64.v v8, (a0)425; RV32-NEXT: addi sp, sp, 16426; RV32-NEXT: .cfi_def_cfa_offset 0427; RV32-NEXT: ret428;429; RV64-LABEL: bitreverse_v4i64:430; RV64: # %bb.0:431; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma432; RV64-NEXT: vle64.v v14, (a0)433; RV64-NEXT: li a1, 56434; RV64-NEXT: li a2, 40435; RV64-NEXT: lui a3, 16436; RV64-NEXT: lui a4, 4080437; RV64-NEXT: li a5, 255438; RV64-NEXT: addi a3, a3, -256439; RV64-NEXT: slli a5, a5, 24440; RV64-NEXT: vsrl.vx v8, v14, a1441; RV64-NEXT: vsrl.vx v10, v14, a2442; RV64-NEXT: vsrl.vi v12, v14, 24443; RV64-NEXT: vsrl.vi v16, v14, 8444; RV64-NEXT: vand.vx v10, v10, a3445; RV64-NEXT: vor.vv v8, v10, v8446; RV64-NEXT: vand.vx v18, v14, a5447; RV64-NEXT: vand.vx v10, v12, a4448; RV64-NEXT: vand.vx v12, v16, a5449; RV64-NEXT: vor.vv v10, v12, v10450; RV64-NEXT: vand.vx v12, v14, a4451; RV64-NEXT: vsll.vi v16, v18, 8452; RV64-NEXT: vsll.vi v12, v12, 24453; RV64-NEXT: vor.vv v12, v12, v16454; RV64-NEXT: vsll.vx v16, v14, a1455; RV64-NEXT: vand.vx v14, v14, a3456; RV64-NEXT: vsll.vx v14, v14, a2457; RV64-NEXT: vor.vv v14, v16, v14458; RV64-NEXT: lui a1, 61681459; RV64-NEXT: lui a2, 209715460; RV64-NEXT: lui a3, 349525461; RV64-NEXT: addi a1, a1, -241462; RV64-NEXT: addi a2, a2, 819463; RV64-NEXT: addi a3, a3, 1365464; RV64-NEXT: slli a4, a1, 32465; RV64-NEXT: slli a5, a2, 32466; RV64-NEXT: add a1, a1, a4467; RV64-NEXT: slli a4, a3, 32468; RV64-NEXT: add a2, a2, a5469; RV64-NEXT: add a3, a3, a4470; RV64-NEXT: vor.vv v8, v10, v8471; RV64-NEXT: vor.vv v10, v14, v12472; RV64-NEXT: vor.vv v8, v10, v8473; RV64-NEXT: vsrl.vi v10, v8, 4474; RV64-NEXT: vand.vx v8, v8, a1475; RV64-NEXT: vand.vx v10, v10, a1476; RV64-NEXT: vsll.vi v8, v8, 4477; RV64-NEXT: vor.vv v8, v10, v8478; RV64-NEXT: vsrl.vi v10, v8, 2479; RV64-NEXT: vand.vx v8, v8, a2480; RV64-NEXT: vand.vx v10, v10, a2481; RV64-NEXT: vsll.vi v8, v8, 2482; RV64-NEXT: vor.vv v8, v10, v8483; RV64-NEXT: vsrl.vi v10, v8, 1484; RV64-NEXT: vand.vx v8, v8, a3485; RV64-NEXT: vand.vx v10, v10, a3486; RV64-NEXT: vadd.vv v8, v8, v8487; RV64-NEXT: vor.vv v8, v10, v8488; RV64-NEXT: vse64.v v8, (a0)489; RV64-NEXT: ret490;491; ZVBB-LABEL: bitreverse_v4i64:492; ZVBB: # %bb.0:493; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma494; ZVBB-NEXT: vle64.v v8, (a0)495; ZVBB-NEXT: vbrev.v v8, v8496; ZVBB-NEXT: vse64.v v8, (a0)497; ZVBB-NEXT: ret498 %a = load <4 x i64>, ptr %x499 %b = load <4 x i64>, ptr %y500 %c = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %a)501 store <4 x i64> %c, ptr %x502 ret void503}504