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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV646 7define <2 x i16> @vp_bswap_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vp_bswap_v2i16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma11; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t12; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t13; CHECK-NEXT: vor.vv v8, v8, v9, v0.t14; CHECK-NEXT: ret15 %v = call <2 x i16> @llvm.vp.bswap.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl)16 ret <2 x i16> %v17}18 19define <2 x i16> @vp_bswap_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {20; CHECK-LABEL: vp_bswap_v2i16_unmasked:21; CHECK: # %bb.0:22; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma23; CHECK-NEXT: vsrl.vi v9, v8, 824; CHECK-NEXT: vsll.vi v8, v8, 825; CHECK-NEXT: vor.vv v8, v8, v926; CHECK-NEXT: ret27 %v = call <2 x i16> @llvm.vp.bswap.v2i16(<2 x i16> %va, <2 x i1> splat (i1 true), i32 %evl)28 ret <2 x i16> %v29}30 31define <4 x i16> @vp_bswap_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {32; CHECK-LABEL: vp_bswap_v4i16:33; CHECK: # %bb.0:34; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma35; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t36; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t37; CHECK-NEXT: vor.vv v8, v8, v9, v0.t38; CHECK-NEXT: ret39 %v = call <4 x i16> @llvm.vp.bswap.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)40 ret <4 x i16> %v41}42 43define <4 x i16> @vp_bswap_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {44; CHECK-LABEL: vp_bswap_v4i16_unmasked:45; CHECK: # %bb.0:46; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma47; CHECK-NEXT: vsrl.vi v9, v8, 848; CHECK-NEXT: vsll.vi v8, v8, 849; CHECK-NEXT: vor.vv v8, v8, v950; CHECK-NEXT: ret51 %v = call <4 x i16> @llvm.vp.bswap.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl)52 ret <4 x i16> %v53}54 55define <8 x i16> @vp_bswap_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {56; CHECK-LABEL: vp_bswap_v8i16:57; CHECK: # %bb.0:58; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma59; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t60; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t61; CHECK-NEXT: vor.vv v8, v8, v9, v0.t62; CHECK-NEXT: ret63 %v = call <8 x i16> @llvm.vp.bswap.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl)64 ret <8 x i16> %v65}66 67define <8 x i16> @vp_bswap_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {68; CHECK-LABEL: vp_bswap_v8i16_unmasked:69; CHECK: # %bb.0:70; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma71; CHECK-NEXT: vsrl.vi v9, v8, 872; CHECK-NEXT: vsll.vi v8, v8, 873; CHECK-NEXT: vor.vv v8, v8, v974; CHECK-NEXT: ret75 %v = call <8 x i16> @llvm.vp.bswap.v8i16(<8 x i16> %va, <8 x i1> splat (i1 true), i32 %evl)76 ret <8 x i16> %v77}78 79define <16 x i16> @vp_bswap_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {80; CHECK-LABEL: vp_bswap_v16i16:81; CHECK: # %bb.0:82; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma83; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t84; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t85; CHECK-NEXT: vor.vv v8, v8, v10, v0.t86; CHECK-NEXT: ret87 %v = call <16 x i16> @llvm.vp.bswap.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl)88 ret <16 x i16> %v89}90 91define <16 x i16> @vp_bswap_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {92; CHECK-LABEL: vp_bswap_v16i16_unmasked:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma95; CHECK-NEXT: vsrl.vi v10, v8, 896; CHECK-NEXT: vsll.vi v8, v8, 897; CHECK-NEXT: vor.vv v8, v8, v1098; CHECK-NEXT: ret99 %v = call <16 x i16> @llvm.vp.bswap.v16i16(<16 x i16> %va, <16 x i1> splat (i1 true), i32 %evl)100 ret <16 x i16> %v101}102 103define <2 x i32> @vp_bswap_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {104; CHECK-LABEL: vp_bswap_v2i32:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma107; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t108; CHECK-NEXT: lui a0, 16109; CHECK-NEXT: addi a0, a0, -256110; CHECK-NEXT: vand.vx v9, v9, a0, v0.t111; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t112; CHECK-NEXT: vor.vv v9, v9, v10, v0.t113; CHECK-NEXT: vand.vx v10, v8, a0, v0.t114; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t115; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t116; CHECK-NEXT: vor.vv v8, v8, v10, v0.t117; CHECK-NEXT: vor.vv v8, v8, v9, v0.t118; CHECK-NEXT: ret119 %v = call <2 x i32> @llvm.vp.bswap.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl)120 ret <2 x i32> %v121}122 123define <2 x i32> @vp_bswap_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {124; CHECK-LABEL: vp_bswap_v2i32_unmasked:125; CHECK: # %bb.0:126; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma127; CHECK-NEXT: vsrl.vi v9, v8, 8128; CHECK-NEXT: lui a0, 16129; CHECK-NEXT: vsrl.vi v10, v8, 24130; CHECK-NEXT: addi a0, a0, -256131; CHECK-NEXT: vand.vx v9, v9, a0132; CHECK-NEXT: vor.vv v9, v9, v10133; CHECK-NEXT: vand.vx v10, v8, a0134; CHECK-NEXT: vsll.vi v10, v10, 8135; CHECK-NEXT: vsll.vi v8, v8, 24136; CHECK-NEXT: vor.vv v8, v8, v10137; CHECK-NEXT: vor.vv v8, v8, v9138; CHECK-NEXT: ret139 %v = call <2 x i32> @llvm.vp.bswap.v2i32(<2 x i32> %va, <2 x i1> splat (i1 true), i32 %evl)140 ret <2 x i32> %v141}142 143define <4 x i32> @vp_bswap_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {144; CHECK-LABEL: vp_bswap_v4i32:145; CHECK: # %bb.0:146; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma147; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t148; CHECK-NEXT: lui a0, 16149; CHECK-NEXT: addi a0, a0, -256150; CHECK-NEXT: vand.vx v9, v9, a0, v0.t151; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t152; CHECK-NEXT: vor.vv v9, v9, v10, v0.t153; CHECK-NEXT: vand.vx v10, v8, a0, v0.t154; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t155; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t156; CHECK-NEXT: vor.vv v8, v8, v10, v0.t157; CHECK-NEXT: vor.vv v8, v8, v9, v0.t158; CHECK-NEXT: ret159 %v = call <4 x i32> @llvm.vp.bswap.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)160 ret <4 x i32> %v161}162 163define <4 x i32> @vp_bswap_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {164; CHECK-LABEL: vp_bswap_v4i32_unmasked:165; CHECK: # %bb.0:166; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma167; CHECK-NEXT: vsrl.vi v9, v8, 8168; CHECK-NEXT: lui a0, 16169; CHECK-NEXT: vsrl.vi v10, v8, 24170; CHECK-NEXT: addi a0, a0, -256171; CHECK-NEXT: vand.vx v9, v9, a0172; CHECK-NEXT: vor.vv v9, v9, v10173; CHECK-NEXT: vand.vx v10, v8, a0174; CHECK-NEXT: vsll.vi v10, v10, 8175; CHECK-NEXT: vsll.vi v8, v8, 24176; CHECK-NEXT: vor.vv v8, v8, v10177; CHECK-NEXT: vor.vv v8, v8, v9178; CHECK-NEXT: ret179 %v = call <4 x i32> @llvm.vp.bswap.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl)180 ret <4 x i32> %v181}182 183define <8 x i32> @vp_bswap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {184; CHECK-LABEL: vp_bswap_v8i32:185; CHECK: # %bb.0:186; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma187; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t188; CHECK-NEXT: lui a0, 16189; CHECK-NEXT: addi a0, a0, -256190; CHECK-NEXT: vand.vx v10, v10, a0, v0.t191; CHECK-NEXT: vsrl.vi v12, v8, 24, v0.t192; CHECK-NEXT: vor.vv v10, v10, v12, v0.t193; CHECK-NEXT: vand.vx v12, v8, a0, v0.t194; CHECK-NEXT: vsll.vi v12, v12, 8, v0.t195; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t196; CHECK-NEXT: vor.vv v8, v8, v12, v0.t197; CHECK-NEXT: vor.vv v8, v8, v10, v0.t198; CHECK-NEXT: ret199 %v = call <8 x i32> @llvm.vp.bswap.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl)200 ret <8 x i32> %v201}202 203define <8 x i32> @vp_bswap_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {204; CHECK-LABEL: vp_bswap_v8i32_unmasked:205; CHECK: # %bb.0:206; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma207; CHECK-NEXT: vsrl.vi v10, v8, 8208; CHECK-NEXT: lui a0, 16209; CHECK-NEXT: vsrl.vi v12, v8, 24210; CHECK-NEXT: addi a0, a0, -256211; CHECK-NEXT: vand.vx v10, v10, a0212; CHECK-NEXT: vor.vv v10, v10, v12213; CHECK-NEXT: vand.vx v12, v8, a0214; CHECK-NEXT: vsll.vi v12, v12, 8215; CHECK-NEXT: vsll.vi v8, v8, 24216; CHECK-NEXT: vor.vv v8, v8, v12217; CHECK-NEXT: vor.vv v8, v8, v10218; CHECK-NEXT: ret219 %v = call <8 x i32> @llvm.vp.bswap.v8i32(<8 x i32> %va, <8 x i1> splat (i1 true), i32 %evl)220 ret <8 x i32> %v221}222 223define <16 x i32> @vp_bswap_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {224; CHECK-LABEL: vp_bswap_v16i32:225; CHECK: # %bb.0:226; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma227; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t228; CHECK-NEXT: lui a0, 16229; CHECK-NEXT: addi a0, a0, -256230; CHECK-NEXT: vand.vx v12, v12, a0, v0.t231; CHECK-NEXT: vsrl.vi v16, v8, 24, v0.t232; CHECK-NEXT: vor.vv v12, v12, v16, v0.t233; CHECK-NEXT: vand.vx v16, v8, a0, v0.t234; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t235; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t236; CHECK-NEXT: vor.vv v8, v8, v16, v0.t237; CHECK-NEXT: vor.vv v8, v8, v12, v0.t238; CHECK-NEXT: ret239 %v = call <16 x i32> @llvm.vp.bswap.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl)240 ret <16 x i32> %v241}242 243define <16 x i32> @vp_bswap_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {244; CHECK-LABEL: vp_bswap_v16i32_unmasked:245; CHECK: # %bb.0:246; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma247; CHECK-NEXT: vsrl.vi v12, v8, 8248; CHECK-NEXT: lui a0, 16249; CHECK-NEXT: vsrl.vi v16, v8, 24250; CHECK-NEXT: addi a0, a0, -256251; CHECK-NEXT: vand.vx v12, v12, a0252; CHECK-NEXT: vor.vv v12, v12, v16253; CHECK-NEXT: vand.vx v16, v8, a0254; CHECK-NEXT: vsll.vi v16, v16, 8255; CHECK-NEXT: vsll.vi v8, v8, 24256; CHECK-NEXT: vor.vv v8, v8, v16257; CHECK-NEXT: vor.vv v8, v8, v12258; CHECK-NEXT: ret259 %v = call <16 x i32> @llvm.vp.bswap.v16i32(<16 x i32> %va, <16 x i1> splat (i1 true), i32 %evl)260 ret <16 x i32> %v261}262 263define <2 x i64> @vp_bswap_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {264; RV32-LABEL: vp_bswap_v2i64:265; RV32: # %bb.0:266; RV32-NEXT: addi sp, sp, -16267; RV32-NEXT: .cfi_def_cfa_offset 16268; RV32-NEXT: lui a1, 1044480269; RV32-NEXT: li a2, 56270; RV32-NEXT: lui a3, 16271; RV32-NEXT: li a4, 40272; RV32-NEXT: lui a5, 4080273; RV32-NEXT: addi a6, sp, 8274; RV32-NEXT: sw a1, 8(sp)275; RV32-NEXT: sw zero, 12(sp)276; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma277; RV32-NEXT: vsll.vx v9, v8, a2, v0.t278; RV32-NEXT: addi a1, a3, -256279; RV32-NEXT: vand.vx v10, v8, a1, v0.t280; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma281; RV32-NEXT: vlse64.v v11, (a6), zero282; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma283; RV32-NEXT: vsll.vx v10, v10, a4, v0.t284; RV32-NEXT: vor.vv v9, v9, v10, v0.t285; RV32-NEXT: vand.vx v10, v8, a5, v0.t286; RV32-NEXT: vsll.vi v10, v10, 24, v0.t287; RV32-NEXT: vand.vv v12, v8, v11, v0.t288; RV32-NEXT: vsll.vi v12, v12, 8, v0.t289; RV32-NEXT: vor.vv v10, v10, v12, v0.t290; RV32-NEXT: vor.vv v9, v9, v10, v0.t291; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t292; RV32-NEXT: vsrl.vx v12, v8, a4, v0.t293; RV32-NEXT: vand.vx v12, v12, a1, v0.t294; RV32-NEXT: vor.vv v10, v12, v10, v0.t295; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t296; RV32-NEXT: vand.vx v12, v12, a5, v0.t297; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t298; RV32-NEXT: vand.vv v8, v8, v11, v0.t299; RV32-NEXT: vor.vv v8, v8, v12, v0.t300; RV32-NEXT: vor.vv v8, v8, v10, v0.t301; RV32-NEXT: vor.vv v8, v9, v8, v0.t302; RV32-NEXT: addi sp, sp, 16303; RV32-NEXT: .cfi_def_cfa_offset 0304; RV32-NEXT: ret305;306; RV64-LABEL: vp_bswap_v2i64:307; RV64: # %bb.0:308; RV64-NEXT: lui a1, 4080309; RV64-NEXT: li a2, 255310; RV64-NEXT: li a3, 56311; RV64-NEXT: lui a4, 16312; RV64-NEXT: li a5, 40313; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma314; RV64-NEXT: vand.vx v9, v8, a1, v0.t315; RV64-NEXT: slli a2, a2, 24316; RV64-NEXT: addi a0, a4, -256317; RV64-NEXT: vsll.vi v9, v9, 24, v0.t318; RV64-NEXT: vand.vx v10, v8, a2, v0.t319; RV64-NEXT: vsll.vi v10, v10, 8, v0.t320; RV64-NEXT: vor.vv v9, v9, v10, v0.t321; RV64-NEXT: vsll.vx v10, v8, a3, v0.t322; RV64-NEXT: vand.vx v11, v8, a0, v0.t323; RV64-NEXT: vsll.vx v11, v11, a5, v0.t324; RV64-NEXT: vor.vv v10, v10, v11, v0.t325; RV64-NEXT: vor.vv v9, v10, v9, v0.t326; RV64-NEXT: vsrl.vx v10, v8, a3, v0.t327; RV64-NEXT: vsrl.vx v11, v8, a5, v0.t328; RV64-NEXT: vand.vx v11, v11, a0, v0.t329; RV64-NEXT: vor.vv v10, v11, v10, v0.t330; RV64-NEXT: vsrl.vi v11, v8, 24, v0.t331; RV64-NEXT: vand.vx v11, v11, a1, v0.t332; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t333; RV64-NEXT: vand.vx v8, v8, a2, v0.t334; RV64-NEXT: vor.vv v8, v8, v11, v0.t335; RV64-NEXT: vor.vv v8, v8, v10, v0.t336; RV64-NEXT: vor.vv v8, v9, v8, v0.t337; RV64-NEXT: ret338 %v = call <2 x i64> @llvm.vp.bswap.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl)339 ret <2 x i64> %v340}341 342define <2 x i64> @vp_bswap_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {343; RV32-LABEL: vp_bswap_v2i64_unmasked:344; RV32: # %bb.0:345; RV32-NEXT: addi sp, sp, -16346; RV32-NEXT: .cfi_def_cfa_offset 16347; RV32-NEXT: lui a1, 1044480348; RV32-NEXT: li a2, 56349; RV32-NEXT: lui a3, 16350; RV32-NEXT: li a4, 40351; RV32-NEXT: lui a5, 4080352; RV32-NEXT: addi a6, sp, 8353; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma354; RV32-NEXT: vsrl.vi v9, v8, 24355; RV32-NEXT: sw a1, 8(sp)356; RV32-NEXT: sw zero, 12(sp)357; RV32-NEXT: vsll.vx v10, v8, a2358; RV32-NEXT: addi a1, a3, -256359; RV32-NEXT: vsrl.vx v11, v8, a2360; RV32-NEXT: vsrl.vx v12, v8, a4361; RV32-NEXT: vand.vx v13, v8, a1362; RV32-NEXT: vand.vx v12, v12, a1363; RV32-NEXT: vor.vv v11, v12, v11364; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma365; RV32-NEXT: vlse64.v v12, (a6), zero366; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma367; RV32-NEXT: vsll.vx v13, v13, a4368; RV32-NEXT: vor.vv v10, v10, v13369; RV32-NEXT: vsrl.vi v13, v8, 8370; RV32-NEXT: vand.vx v9, v9, a5371; RV32-NEXT: vand.vv v13, v13, v12372; RV32-NEXT: vor.vv v9, v13, v9373; RV32-NEXT: vand.vv v12, v8, v12374; RV32-NEXT: vand.vx v8, v8, a5375; RV32-NEXT: vsll.vi v8, v8, 24376; RV32-NEXT: vsll.vi v12, v12, 8377; RV32-NEXT: vor.vv v8, v8, v12378; RV32-NEXT: vor.vv v8, v10, v8379; RV32-NEXT: vor.vv v9, v9, v11380; RV32-NEXT: vor.vv v8, v8, v9381; RV32-NEXT: addi sp, sp, 16382; RV32-NEXT: .cfi_def_cfa_offset 0383; RV32-NEXT: ret384;385; RV64-LABEL: vp_bswap_v2i64_unmasked:386; RV64: # %bb.0:387; RV64-NEXT: lui a1, 4080388; RV64-NEXT: li a2, 255389; RV64-NEXT: li a3, 56390; RV64-NEXT: lui a4, 16391; RV64-NEXT: li a5, 40392; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma393; RV64-NEXT: vsrl.vi v9, v8, 24394; RV64-NEXT: vsrl.vi v10, v8, 8395; RV64-NEXT: addi a0, a4, -256396; RV64-NEXT: vsrl.vx v11, v8, a3397; RV64-NEXT: vsrl.vx v12, v8, a5398; RV64-NEXT: vand.vx v12, v12, a0399; RV64-NEXT: vor.vv v11, v12, v11400; RV64-NEXT: vand.vx v12, v8, a1401; RV64-NEXT: slli a2, a2, 24402; RV64-NEXT: vand.vx v9, v9, a1403; RV64-NEXT: vsll.vi v12, v12, 24404; RV64-NEXT: vand.vx v10, v10, a2405; RV64-NEXT: vor.vv v9, v10, v9406; RV64-NEXT: vand.vx v10, v8, a2407; RV64-NEXT: vsll.vi v10, v10, 8408; RV64-NEXT: vor.vv v10, v12, v10409; RV64-NEXT: vsll.vx v12, v8, a3410; RV64-NEXT: vand.vx v8, v8, a0411; RV64-NEXT: vsll.vx v8, v8, a5412; RV64-NEXT: vor.vv v8, v12, v8413; RV64-NEXT: vor.vv v8, v8, v10414; RV64-NEXT: vor.vv v9, v9, v11415; RV64-NEXT: vor.vv v8, v8, v9416; RV64-NEXT: ret417 %v = call <2 x i64> @llvm.vp.bswap.v2i64(<2 x i64> %va, <2 x i1> splat (i1 true), i32 %evl)418 ret <2 x i64> %v419}420 421define <4 x i64> @vp_bswap_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {422; RV32-LABEL: vp_bswap_v4i64:423; RV32: # %bb.0:424; RV32-NEXT: addi sp, sp, -16425; RV32-NEXT: .cfi_def_cfa_offset 16426; RV32-NEXT: lui a1, 1044480427; RV32-NEXT: li a2, 56428; RV32-NEXT: lui a3, 16429; RV32-NEXT: li a4, 40430; RV32-NEXT: lui a5, 4080431; RV32-NEXT: addi a6, sp, 8432; RV32-NEXT: sw a1, 8(sp)433; RV32-NEXT: sw zero, 12(sp)434; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma435; RV32-NEXT: vsll.vx v10, v8, a2, v0.t436; RV32-NEXT: addi a1, a3, -256437; RV32-NEXT: vand.vx v12, v8, a1, v0.t438; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma439; RV32-NEXT: vlse64.v v14, (a6), zero440; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma441; RV32-NEXT: vsll.vx v12, v12, a4, v0.t442; RV32-NEXT: vor.vv v10, v10, v12, v0.t443; RV32-NEXT: vand.vx v12, v8, a5, v0.t444; RV32-NEXT: vsll.vi v12, v12, 24, v0.t445; RV32-NEXT: vand.vv v16, v8, v14, v0.t446; RV32-NEXT: vsll.vi v16, v16, 8, v0.t447; RV32-NEXT: vor.vv v12, v12, v16, v0.t448; RV32-NEXT: vor.vv v10, v10, v12, v0.t449; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t450; RV32-NEXT: vsrl.vx v16, v8, a4, v0.t451; RV32-NEXT: vand.vx v16, v16, a1, v0.t452; RV32-NEXT: vor.vv v12, v16, v12, v0.t453; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t454; RV32-NEXT: vand.vx v16, v16, a5, v0.t455; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t456; RV32-NEXT: vand.vv v8, v8, v14, v0.t457; RV32-NEXT: vor.vv v8, v8, v16, v0.t458; RV32-NEXT: vor.vv v8, v8, v12, v0.t459; RV32-NEXT: vor.vv v8, v10, v8, v0.t460; RV32-NEXT: addi sp, sp, 16461; RV32-NEXT: .cfi_def_cfa_offset 0462; RV32-NEXT: ret463;464; RV64-LABEL: vp_bswap_v4i64:465; RV64: # %bb.0:466; RV64-NEXT: lui a1, 4080467; RV64-NEXT: li a2, 255468; RV64-NEXT: li a3, 56469; RV64-NEXT: lui a4, 16470; RV64-NEXT: li a5, 40471; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma472; RV64-NEXT: vand.vx v10, v8, a1, v0.t473; RV64-NEXT: slli a2, a2, 24474; RV64-NEXT: addi a0, a4, -256475; RV64-NEXT: vsll.vi v10, v10, 24, v0.t476; RV64-NEXT: vand.vx v12, v8, a2, v0.t477; RV64-NEXT: vsll.vi v12, v12, 8, v0.t478; RV64-NEXT: vor.vv v10, v10, v12, v0.t479; RV64-NEXT: vsll.vx v12, v8, a3, v0.t480; RV64-NEXT: vand.vx v14, v8, a0, v0.t481; RV64-NEXT: vsll.vx v14, v14, a5, v0.t482; RV64-NEXT: vor.vv v12, v12, v14, v0.t483; RV64-NEXT: vor.vv v10, v12, v10, v0.t484; RV64-NEXT: vsrl.vx v12, v8, a3, v0.t485; RV64-NEXT: vsrl.vx v14, v8, a5, v0.t486; RV64-NEXT: vand.vx v14, v14, a0, v0.t487; RV64-NEXT: vor.vv v12, v14, v12, v0.t488; RV64-NEXT: vsrl.vi v14, v8, 24, v0.t489; RV64-NEXT: vand.vx v14, v14, a1, v0.t490; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t491; RV64-NEXT: vand.vx v8, v8, a2, v0.t492; RV64-NEXT: vor.vv v8, v8, v14, v0.t493; RV64-NEXT: vor.vv v8, v8, v12, v0.t494; RV64-NEXT: vor.vv v8, v10, v8, v0.t495; RV64-NEXT: ret496 %v = call <4 x i64> @llvm.vp.bswap.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)497 ret <4 x i64> %v498}499 500define <4 x i64> @vp_bswap_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {501; RV32-LABEL: vp_bswap_v4i64_unmasked:502; RV32: # %bb.0:503; RV32-NEXT: addi sp, sp, -16504; RV32-NEXT: .cfi_def_cfa_offset 16505; RV32-NEXT: lui a1, 1044480506; RV32-NEXT: li a2, 56507; RV32-NEXT: lui a3, 16508; RV32-NEXT: li a4, 40509; RV32-NEXT: lui a5, 4080510; RV32-NEXT: addi a6, sp, 8511; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma512; RV32-NEXT: vsrl.vi v10, v8, 24513; RV32-NEXT: sw a1, 8(sp)514; RV32-NEXT: sw zero, 12(sp)515; RV32-NEXT: vsll.vx v12, v8, a2516; RV32-NEXT: addi a1, a3, -256517; RV32-NEXT: vsrl.vx v14, v8, a2518; RV32-NEXT: vsrl.vx v16, v8, a4519; RV32-NEXT: vand.vx v18, v8, a1520; RV32-NEXT: vand.vx v16, v16, a1521; RV32-NEXT: vor.vv v14, v16, v14522; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma523; RV32-NEXT: vlse64.v v16, (a6), zero524; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma525; RV32-NEXT: vsll.vx v18, v18, a4526; RV32-NEXT: vor.vv v12, v12, v18527; RV32-NEXT: vsrl.vi v18, v8, 8528; RV32-NEXT: vand.vx v10, v10, a5529; RV32-NEXT: vand.vv v18, v18, v16530; RV32-NEXT: vor.vv v10, v18, v10531; RV32-NEXT: vand.vv v16, v8, v16532; RV32-NEXT: vand.vx v8, v8, a5533; RV32-NEXT: vsll.vi v8, v8, 24534; RV32-NEXT: vsll.vi v16, v16, 8535; RV32-NEXT: vor.vv v8, v8, v16536; RV32-NEXT: vor.vv v8, v12, v8537; RV32-NEXT: vor.vv v10, v10, v14538; RV32-NEXT: vor.vv v8, v8, v10539; RV32-NEXT: addi sp, sp, 16540; RV32-NEXT: .cfi_def_cfa_offset 0541; RV32-NEXT: ret542;543; RV64-LABEL: vp_bswap_v4i64_unmasked:544; RV64: # %bb.0:545; RV64-NEXT: lui a1, 4080546; RV64-NEXT: li a2, 255547; RV64-NEXT: li a3, 56548; RV64-NEXT: lui a4, 16549; RV64-NEXT: li a5, 40550; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma551; RV64-NEXT: vsrl.vi v10, v8, 24552; RV64-NEXT: vsrl.vi v12, v8, 8553; RV64-NEXT: addi a0, a4, -256554; RV64-NEXT: vsrl.vx v14, v8, a3555; RV64-NEXT: vsrl.vx v16, v8, a5556; RV64-NEXT: vand.vx v16, v16, a0557; RV64-NEXT: vor.vv v14, v16, v14558; RV64-NEXT: vand.vx v16, v8, a1559; RV64-NEXT: slli a2, a2, 24560; RV64-NEXT: vand.vx v10, v10, a1561; RV64-NEXT: vsll.vi v16, v16, 24562; RV64-NEXT: vand.vx v12, v12, a2563; RV64-NEXT: vor.vv v10, v12, v10564; RV64-NEXT: vand.vx v12, v8, a2565; RV64-NEXT: vsll.vi v12, v12, 8566; RV64-NEXT: vor.vv v12, v16, v12567; RV64-NEXT: vsll.vx v16, v8, a3568; RV64-NEXT: vand.vx v8, v8, a0569; RV64-NEXT: vsll.vx v8, v8, a5570; RV64-NEXT: vor.vv v8, v16, v8571; RV64-NEXT: vor.vv v8, v8, v12572; RV64-NEXT: vor.vv v10, v10, v14573; RV64-NEXT: vor.vv v8, v8, v10574; RV64-NEXT: ret575 %v = call <4 x i64> @llvm.vp.bswap.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl)576 ret <4 x i64> %v577}578 579define <8 x i64> @vp_bswap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {580; RV32-LABEL: vp_bswap_v8i64:581; RV32: # %bb.0:582; RV32-NEXT: addi sp, sp, -16583; RV32-NEXT: .cfi_def_cfa_offset 16584; RV32-NEXT: lui a1, 1044480585; RV32-NEXT: li a2, 56586; RV32-NEXT: lui a3, 16587; RV32-NEXT: li a4, 40588; RV32-NEXT: lui a5, 4080589; RV32-NEXT: addi a6, sp, 8590; RV32-NEXT: sw a1, 8(sp)591; RV32-NEXT: sw zero, 12(sp)592; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma593; RV32-NEXT: vsll.vx v16, v8, a2, v0.t594; RV32-NEXT: addi a1, a3, -256595; RV32-NEXT: vand.vx v20, v8, a1, v0.t596; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma597; RV32-NEXT: vlse64.v v12, (a6), zero598; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma599; RV32-NEXT: vsll.vx v20, v20, a4, v0.t600; RV32-NEXT: vor.vv v16, v16, v20, v0.t601; RV32-NEXT: vand.vx v20, v8, a5, v0.t602; RV32-NEXT: vsll.vi v20, v20, 24, v0.t603; RV32-NEXT: vand.vv v24, v8, v12, v0.t604; RV32-NEXT: vsll.vi v24, v24, 8, v0.t605; RV32-NEXT: vor.vv v20, v20, v24, v0.t606; RV32-NEXT: vor.vv v16, v16, v20, v0.t607; RV32-NEXT: vsrl.vx v20, v8, a2, v0.t608; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t609; RV32-NEXT: vand.vx v24, v24, a1, v0.t610; RV32-NEXT: vor.vv v20, v24, v20, v0.t611; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t612; RV32-NEXT: vand.vx v24, v24, a5, v0.t613; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t614; RV32-NEXT: vand.vv v8, v8, v12, v0.t615; RV32-NEXT: vor.vv v8, v8, v24, v0.t616; RV32-NEXT: vor.vv v8, v8, v20, v0.t617; RV32-NEXT: vor.vv v8, v16, v8, v0.t618; RV32-NEXT: addi sp, sp, 16619; RV32-NEXT: .cfi_def_cfa_offset 0620; RV32-NEXT: ret621;622; RV64-LABEL: vp_bswap_v8i64:623; RV64: # %bb.0:624; RV64-NEXT: lui a1, 4080625; RV64-NEXT: li a2, 255626; RV64-NEXT: li a3, 56627; RV64-NEXT: lui a4, 16628; RV64-NEXT: li a5, 40629; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma630; RV64-NEXT: vand.vx v12, v8, a1, v0.t631; RV64-NEXT: slli a2, a2, 24632; RV64-NEXT: addi a0, a4, -256633; RV64-NEXT: vsll.vi v12, v12, 24, v0.t634; RV64-NEXT: vand.vx v16, v8, a2, v0.t635; RV64-NEXT: vsll.vi v16, v16, 8, v0.t636; RV64-NEXT: vor.vv v12, v12, v16, v0.t637; RV64-NEXT: vsll.vx v16, v8, a3, v0.t638; RV64-NEXT: vand.vx v20, v8, a0, v0.t639; RV64-NEXT: vsll.vx v20, v20, a5, v0.t640; RV64-NEXT: vor.vv v16, v16, v20, v0.t641; RV64-NEXT: vor.vv v12, v16, v12, v0.t642; RV64-NEXT: vsrl.vx v16, v8, a3, v0.t643; RV64-NEXT: vsrl.vx v20, v8, a5, v0.t644; RV64-NEXT: vand.vx v20, v20, a0, v0.t645; RV64-NEXT: vor.vv v16, v20, v16, v0.t646; RV64-NEXT: vsrl.vi v20, v8, 24, v0.t647; RV64-NEXT: vand.vx v20, v20, a1, v0.t648; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t649; RV64-NEXT: vand.vx v8, v8, a2, v0.t650; RV64-NEXT: vor.vv v8, v8, v20, v0.t651; RV64-NEXT: vor.vv v8, v8, v16, v0.t652; RV64-NEXT: vor.vv v8, v12, v8, v0.t653; RV64-NEXT: ret654 %v = call <8 x i64> @llvm.vp.bswap.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl)655 ret <8 x i64> %v656}657 658define <8 x i64> @vp_bswap_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {659; RV32-LABEL: vp_bswap_v8i64_unmasked:660; RV32: # %bb.0:661; RV32-NEXT: addi sp, sp, -16662; RV32-NEXT: .cfi_def_cfa_offset 16663; RV32-NEXT: lui a1, 1044480664; RV32-NEXT: li a2, 56665; RV32-NEXT: lui a3, 16666; RV32-NEXT: li a4, 40667; RV32-NEXT: lui a5, 4080668; RV32-NEXT: addi a6, sp, 8669; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma670; RV32-NEXT: vsrl.vi v12, v8, 24671; RV32-NEXT: sw a1, 8(sp)672; RV32-NEXT: sw zero, 12(sp)673; RV32-NEXT: vsll.vx v16, v8, a2674; RV32-NEXT: addi a1, a3, -256675; RV32-NEXT: vsrl.vx v20, v8, a2676; RV32-NEXT: vsrl.vx v24, v8, a4677; RV32-NEXT: vand.vx v28, v8, a1678; RV32-NEXT: vand.vx v24, v24, a1679; RV32-NEXT: vor.vv v20, v24, v20680; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma681; RV32-NEXT: vlse64.v v24, (a6), zero682; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma683; RV32-NEXT: vsll.vx v28, v28, a4684; RV32-NEXT: vor.vv v16, v16, v28685; RV32-NEXT: vsrl.vi v28, v8, 8686; RV32-NEXT: vand.vx v12, v12, a5687; RV32-NEXT: vand.vv v28, v28, v24688; RV32-NEXT: vor.vv v12, v28, v12689; RV32-NEXT: vand.vv v24, v8, v24690; RV32-NEXT: vand.vx v8, v8, a5691; RV32-NEXT: vsll.vi v8, v8, 24692; RV32-NEXT: vsll.vi v24, v24, 8693; RV32-NEXT: vor.vv v8, v8, v24694; RV32-NEXT: vor.vv v8, v16, v8695; RV32-NEXT: vor.vv v12, v12, v20696; RV32-NEXT: vor.vv v8, v8, v12697; RV32-NEXT: addi sp, sp, 16698; RV32-NEXT: .cfi_def_cfa_offset 0699; RV32-NEXT: ret700;701; RV64-LABEL: vp_bswap_v8i64_unmasked:702; RV64: # %bb.0:703; RV64-NEXT: lui a1, 4080704; RV64-NEXT: li a2, 255705; RV64-NEXT: li a3, 56706; RV64-NEXT: lui a4, 16707; RV64-NEXT: li a5, 40708; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma709; RV64-NEXT: vsrl.vi v12, v8, 24710; RV64-NEXT: vsrl.vi v16, v8, 8711; RV64-NEXT: addi a0, a4, -256712; RV64-NEXT: vsrl.vx v20, v8, a3713; RV64-NEXT: vsrl.vx v24, v8, a5714; RV64-NEXT: vand.vx v24, v24, a0715; RV64-NEXT: vor.vv v20, v24, v20716; RV64-NEXT: vand.vx v24, v8, a1717; RV64-NEXT: slli a2, a2, 24718; RV64-NEXT: vand.vx v12, v12, a1719; RV64-NEXT: vsll.vi v24, v24, 24720; RV64-NEXT: vand.vx v16, v16, a2721; RV64-NEXT: vor.vv v12, v16, v12722; RV64-NEXT: vand.vx v16, v8, a2723; RV64-NEXT: vsll.vi v16, v16, 8724; RV64-NEXT: vor.vv v16, v24, v16725; RV64-NEXT: vsll.vx v24, v8, a3726; RV64-NEXT: vand.vx v8, v8, a0727; RV64-NEXT: vsll.vx v8, v8, a5728; RV64-NEXT: vor.vv v8, v24, v8729; RV64-NEXT: vor.vv v8, v8, v16730; RV64-NEXT: vor.vv v12, v12, v20731; RV64-NEXT: vor.vv v8, v8, v12732; RV64-NEXT: ret733 %v = call <8 x i64> @llvm.vp.bswap.v8i64(<8 x i64> %va, <8 x i1> splat (i1 true), i32 %evl)734 ret <8 x i64> %v735}736 737define <15 x i64> @vp_bswap_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {738; RV32-LABEL: vp_bswap_v15i64:739; RV32: # %bb.0:740; RV32-NEXT: addi sp, sp, -16741; RV32-NEXT: .cfi_def_cfa_offset 16742; RV32-NEXT: csrr a1, vlenb743; RV32-NEXT: li a2, 24744; RV32-NEXT: mul a1, a1, a2745; RV32-NEXT: sub sp, sp, a1746; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb747; RV32-NEXT: lui a1, 1044480748; RV32-NEXT: li a2, 56749; RV32-NEXT: lui a3, 16750; RV32-NEXT: li a4, 40751; RV32-NEXT: addi a5, sp, 8752; RV32-NEXT: sw a1, 8(sp)753; RV32-NEXT: sw zero, 12(sp)754; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma755; RV32-NEXT: vsll.vx v16, v8, a2, v0.t756; RV32-NEXT: addi a1, a3, -256757; RV32-NEXT: vand.vx v24, v8, a1, v0.t758; RV32-NEXT: vsll.vx v24, v24, a4, v0.t759; RV32-NEXT: vor.vv v16, v16, v24, v0.t760; RV32-NEXT: csrr a3, vlenb761; RV32-NEXT: slli a3, a3, 3762; RV32-NEXT: add a3, sp, a3763; RV32-NEXT: addi a3, a3, 16764; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill765; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma766; RV32-NEXT: vlse64.v v16, (a5), zero767; RV32-NEXT: csrr a3, vlenb768; RV32-NEXT: slli a3, a3, 4769; RV32-NEXT: add a3, sp, a3770; RV32-NEXT: addi a3, a3, 16771; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill772; RV32-NEXT: lui a3, 4080773; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma774; RV32-NEXT: vand.vx v16, v8, a3, v0.t775; RV32-NEXT: vsll.vi v24, v16, 24, v0.t776; RV32-NEXT: csrr a0, vlenb777; RV32-NEXT: slli a0, a0, 4778; RV32-NEXT: add a0, sp, a0779; RV32-NEXT: addi a0, a0, 16780; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload781; RV32-NEXT: vand.vv v16, v8, v16, v0.t782; RV32-NEXT: vsll.vi v16, v16, 8, v0.t783; RV32-NEXT: vor.vv v16, v24, v16, v0.t784; RV32-NEXT: csrr a0, vlenb785; RV32-NEXT: slli a0, a0, 3786; RV32-NEXT: add a0, sp, a0787; RV32-NEXT: addi a0, a0, 16788; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload789; RV32-NEXT: vor.vv v16, v24, v16, v0.t790; RV32-NEXT: csrr a0, vlenb791; RV32-NEXT: slli a0, a0, 3792; RV32-NEXT: add a0, sp, a0793; RV32-NEXT: addi a0, a0, 16794; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill795; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t796; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t797; RV32-NEXT: vand.vx v24, v24, a1, v0.t798; RV32-NEXT: vor.vv v16, v24, v16, v0.t799; RV32-NEXT: addi a0, sp, 16800; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill801; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t802; RV32-NEXT: vand.vx v24, v24, a3, v0.t803; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t804; RV32-NEXT: csrr a0, vlenb805; RV32-NEXT: slli a0, a0, 4806; RV32-NEXT: add a0, sp, a0807; RV32-NEXT: addi a0, a0, 16808; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload809; RV32-NEXT: vand.vv v8, v8, v16, v0.t810; RV32-NEXT: vor.vv v8, v8, v24, v0.t811; RV32-NEXT: addi a0, sp, 16812; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload813; RV32-NEXT: vor.vv v8, v8, v16, v0.t814; RV32-NEXT: csrr a0, vlenb815; RV32-NEXT: slli a0, a0, 3816; RV32-NEXT: add a0, sp, a0817; RV32-NEXT: addi a0, a0, 16818; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload819; RV32-NEXT: vor.vv v8, v16, v8, v0.t820; RV32-NEXT: csrr a0, vlenb821; RV32-NEXT: li a1, 24822; RV32-NEXT: mul a0, a0, a1823; RV32-NEXT: add sp, sp, a0824; RV32-NEXT: .cfi_def_cfa sp, 16825; RV32-NEXT: addi sp, sp, 16826; RV32-NEXT: .cfi_def_cfa_offset 0827; RV32-NEXT: ret828;829; RV64-LABEL: vp_bswap_v15i64:830; RV64: # %bb.0:831; RV64-NEXT: addi sp, sp, -16832; RV64-NEXT: .cfi_def_cfa_offset 16833; RV64-NEXT: csrr a1, vlenb834; RV64-NEXT: slli a1, a1, 3835; RV64-NEXT: sub sp, sp, a1836; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb837; RV64-NEXT: lui a1, 4080838; RV64-NEXT: li a2, 255839; RV64-NEXT: li a3, 56840; RV64-NEXT: lui a4, 16841; RV64-NEXT: li a5, 40842; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma843; RV64-NEXT: vand.vx v16, v8, a1, v0.t844; RV64-NEXT: slli a2, a2, 24845; RV64-NEXT: addi a0, a4, -256846; RV64-NEXT: vsll.vi v16, v16, 24, v0.t847; RV64-NEXT: vand.vx v24, v8, a2, v0.t848; RV64-NEXT: vsll.vi v24, v24, 8, v0.t849; RV64-NEXT: vor.vv v16, v16, v24, v0.t850; RV64-NEXT: addi a4, sp, 16851; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill852; RV64-NEXT: vsll.vx v24, v8, a3, v0.t853; RV64-NEXT: vand.vx v16, v8, a0, v0.t854; RV64-NEXT: vsll.vx v16, v16, a5, v0.t855; RV64-NEXT: vor.vv v16, v24, v16, v0.t856; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload857; RV64-NEXT: vor.vv v16, v16, v24, v0.t858; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill859; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t860; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t861; RV64-NEXT: vand.vx v16, v16, a0, v0.t862; RV64-NEXT: vor.vv v24, v16, v24, v0.t863; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t864; RV64-NEXT: vand.vx v16, v16, a1, v0.t865; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t866; RV64-NEXT: vand.vx v8, v8, a2, v0.t867; RV64-NEXT: vor.vv v8, v8, v16, v0.t868; RV64-NEXT: vor.vv v8, v8, v24, v0.t869; RV64-NEXT: addi a0, sp, 16870; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload871; RV64-NEXT: vor.vv v8, v16, v8, v0.t872; RV64-NEXT: csrr a0, vlenb873; RV64-NEXT: slli a0, a0, 3874; RV64-NEXT: add sp, sp, a0875; RV64-NEXT: .cfi_def_cfa sp, 16876; RV64-NEXT: addi sp, sp, 16877; RV64-NEXT: .cfi_def_cfa_offset 0878; RV64-NEXT: ret879 %v = call <15 x i64> @llvm.vp.bswap.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl)880 ret <15 x i64> %v881}882 883define <15 x i64> @vp_bswap_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {884; RV32-LABEL: vp_bswap_v15i64_unmasked:885; RV32: # %bb.0:886; RV32-NEXT: addi sp, sp, -16887; RV32-NEXT: .cfi_def_cfa_offset 16888; RV32-NEXT: csrr a1, vlenb889; RV32-NEXT: slli a1, a1, 4890; RV32-NEXT: sub sp, sp, a1891; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb892; RV32-NEXT: lui a1, 1044480893; RV32-NEXT: li a2, 56894; RV32-NEXT: lui a3, 16895; RV32-NEXT: li a4, 40896; RV32-NEXT: lui a5, 4080897; RV32-NEXT: addi a6, sp, 8898; RV32-NEXT: sw a1, 8(sp)899; RV32-NEXT: sw zero, 12(sp)900; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma901; RV32-NEXT: vsll.vx v24, v8, a2902; RV32-NEXT: addi a1, a3, -256903; RV32-NEXT: vsrl.vx v16, v8, a2904; RV32-NEXT: vsrl.vx v0, v8, a4905; RV32-NEXT: vand.vx v0, v0, a1906; RV32-NEXT: vor.vv v16, v0, v16907; RV32-NEXT: csrr a2, vlenb908; RV32-NEXT: slli a2, a2, 3909; RV32-NEXT: add a2, sp, a2910; RV32-NEXT: addi a2, a2, 16911; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill912; RV32-NEXT: vand.vx v0, v8, a1913; RV32-NEXT: vsll.vx v0, v0, a4914; RV32-NEXT: vor.vv v16, v24, v0915; RV32-NEXT: addi a1, sp, 16916; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill917; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma918; RV32-NEXT: vlse64.v v0, (a6), zero919; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma920; RV32-NEXT: vsrl.vi v16, v8, 24921; RV32-NEXT: vand.vx v16, v16, a5922; RV32-NEXT: vsrl.vi v24, v8, 8923; RV32-NEXT: vand.vv v24, v24, v0924; RV32-NEXT: vor.vv v16, v24, v16925; RV32-NEXT: vand.vv v24, v8, v0926; RV32-NEXT: vand.vx v8, v8, a5927; RV32-NEXT: vsll.vi v8, v8, 24928; RV32-NEXT: vsll.vi v24, v24, 8929; RV32-NEXT: vor.vv v8, v8, v24930; RV32-NEXT: addi a0, sp, 16931; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload932; RV32-NEXT: vor.vv v8, v24, v8933; RV32-NEXT: csrr a0, vlenb934; RV32-NEXT: slli a0, a0, 3935; RV32-NEXT: add a0, sp, a0936; RV32-NEXT: addi a0, a0, 16937; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload938; RV32-NEXT: vor.vv v16, v16, v24939; RV32-NEXT: vor.vv v8, v8, v16940; RV32-NEXT: csrr a0, vlenb941; RV32-NEXT: slli a0, a0, 4942; RV32-NEXT: add sp, sp, a0943; RV32-NEXT: .cfi_def_cfa sp, 16944; RV32-NEXT: addi sp, sp, 16945; RV32-NEXT: .cfi_def_cfa_offset 0946; RV32-NEXT: ret947;948; RV64-LABEL: vp_bswap_v15i64_unmasked:949; RV64: # %bb.0:950; RV64-NEXT: addi sp, sp, -16951; RV64-NEXT: .cfi_def_cfa_offset 16952; RV64-NEXT: csrr a1, vlenb953; RV64-NEXT: slli a1, a1, 3954; RV64-NEXT: sub sp, sp, a1955; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb956; RV64-NEXT: lui a1, 4080957; RV64-NEXT: li a2, 255958; RV64-NEXT: li a3, 56959; RV64-NEXT: lui a4, 16960; RV64-NEXT: li a5, 40961; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma962; RV64-NEXT: vsrl.vi v24, v8, 24963; RV64-NEXT: addi a0, a4, -256964; RV64-NEXT: vsrl.vx v16, v8, a3965; RV64-NEXT: vsrl.vx v0, v8, a5966; RV64-NEXT: vand.vx v0, v0, a0967; RV64-NEXT: vor.vv v16, v0, v16968; RV64-NEXT: addi a4, sp, 16969; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill970; RV64-NEXT: vsrl.vi v0, v8, 8971; RV64-NEXT: slli a2, a2, 24972; RV64-NEXT: vand.vx v24, v24, a1973; RV64-NEXT: vand.vx v0, v0, a2974; RV64-NEXT: vor.vv v24, v0, v24975; RV64-NEXT: vand.vx v0, v8, a1976; RV64-NEXT: vsll.vi v0, v0, 24977; RV64-NEXT: vand.vx v16, v8, a2978; RV64-NEXT: vsll.vi v16, v16, 8979; RV64-NEXT: vor.vv v16, v0, v16980; RV64-NEXT: vsll.vx v0, v8, a3981; RV64-NEXT: vand.vx v8, v8, a0982; RV64-NEXT: vsll.vx v8, v8, a5983; RV64-NEXT: vor.vv v8, v0, v8984; RV64-NEXT: vor.vv v8, v8, v16985; RV64-NEXT: addi a0, sp, 16986; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload987; RV64-NEXT: vor.vv v16, v24, v16988; RV64-NEXT: vor.vv v8, v8, v16989; RV64-NEXT: csrr a0, vlenb990; RV64-NEXT: slli a0, a0, 3991; RV64-NEXT: add sp, sp, a0992; RV64-NEXT: .cfi_def_cfa sp, 16993; RV64-NEXT: addi sp, sp, 16994; RV64-NEXT: .cfi_def_cfa_offset 0995; RV64-NEXT: ret996 %v = call <15 x i64> @llvm.vp.bswap.v15i64(<15 x i64> %va, <15 x i1> splat (i1 true), i32 %evl)997 ret <15 x i64> %v998}999 1000define <16 x i64> @vp_bswap_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {1001; RV32-LABEL: vp_bswap_v16i64:1002; RV32: # %bb.0:1003; RV32-NEXT: addi sp, sp, -161004; RV32-NEXT: .cfi_def_cfa_offset 161005; RV32-NEXT: csrr a1, vlenb1006; RV32-NEXT: li a2, 241007; RV32-NEXT: mul a1, a1, a21008; RV32-NEXT: sub sp, sp, a11009; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb1010; RV32-NEXT: lui a1, 10444801011; RV32-NEXT: li a2, 561012; RV32-NEXT: lui a3, 161013; RV32-NEXT: li a4, 401014; RV32-NEXT: addi a5, sp, 81015; RV32-NEXT: sw a1, 8(sp)1016; RV32-NEXT: sw zero, 12(sp)1017; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1018; RV32-NEXT: vsll.vx v16, v8, a2, v0.t1019; RV32-NEXT: addi a1, a3, -2561020; RV32-NEXT: vand.vx v24, v8, a1, v0.t1021; RV32-NEXT: vsll.vx v24, v24, a4, v0.t1022; RV32-NEXT: vor.vv v16, v16, v24, v0.t1023; RV32-NEXT: csrr a3, vlenb1024; RV32-NEXT: slli a3, a3, 31025; RV32-NEXT: add a3, sp, a31026; RV32-NEXT: addi a3, a3, 161027; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill1028; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1029; RV32-NEXT: vlse64.v v16, (a5), zero1030; RV32-NEXT: csrr a3, vlenb1031; RV32-NEXT: slli a3, a3, 41032; RV32-NEXT: add a3, sp, a31033; RV32-NEXT: addi a3, a3, 161034; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill1035; RV32-NEXT: lui a3, 40801036; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1037; RV32-NEXT: vand.vx v16, v8, a3, v0.t1038; RV32-NEXT: vsll.vi v24, v16, 24, v0.t1039; RV32-NEXT: csrr a0, vlenb1040; RV32-NEXT: slli a0, a0, 41041; RV32-NEXT: add a0, sp, a01042; RV32-NEXT: addi a0, a0, 161043; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1044; RV32-NEXT: vand.vv v16, v8, v16, v0.t1045; RV32-NEXT: vsll.vi v16, v16, 8, v0.t1046; RV32-NEXT: vor.vv v16, v24, v16, v0.t1047; RV32-NEXT: csrr a0, vlenb1048; RV32-NEXT: slli a0, a0, 31049; RV32-NEXT: add a0, sp, a01050; RV32-NEXT: addi a0, a0, 161051; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload1052; RV32-NEXT: vor.vv v16, v24, v16, v0.t1053; RV32-NEXT: csrr a0, vlenb1054; RV32-NEXT: slli a0, a0, 31055; RV32-NEXT: add a0, sp, a01056; RV32-NEXT: addi a0, a0, 161057; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill1058; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t1059; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t1060; RV32-NEXT: vand.vx v24, v24, a1, v0.t1061; RV32-NEXT: vor.vv v16, v24, v16, v0.t1062; RV32-NEXT: addi a0, sp, 161063; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill1064; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t1065; RV32-NEXT: vand.vx v24, v24, a3, v0.t1066; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t1067; RV32-NEXT: csrr a0, vlenb1068; RV32-NEXT: slli a0, a0, 41069; RV32-NEXT: add a0, sp, a01070; RV32-NEXT: addi a0, a0, 161071; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1072; RV32-NEXT: vand.vv v8, v8, v16, v0.t1073; RV32-NEXT: vor.vv v8, v8, v24, v0.t1074; RV32-NEXT: addi a0, sp, 161075; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1076; RV32-NEXT: vor.vv v8, v8, v16, v0.t1077; RV32-NEXT: csrr a0, vlenb1078; RV32-NEXT: slli a0, a0, 31079; RV32-NEXT: add a0, sp, a01080; RV32-NEXT: addi a0, a0, 161081; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1082; RV32-NEXT: vor.vv v8, v16, v8, v0.t1083; RV32-NEXT: csrr a0, vlenb1084; RV32-NEXT: li a1, 241085; RV32-NEXT: mul a0, a0, a11086; RV32-NEXT: add sp, sp, a01087; RV32-NEXT: .cfi_def_cfa sp, 161088; RV32-NEXT: addi sp, sp, 161089; RV32-NEXT: .cfi_def_cfa_offset 01090; RV32-NEXT: ret1091;1092; RV64-LABEL: vp_bswap_v16i64:1093; RV64: # %bb.0:1094; RV64-NEXT: addi sp, sp, -161095; RV64-NEXT: .cfi_def_cfa_offset 161096; RV64-NEXT: csrr a1, vlenb1097; RV64-NEXT: slli a1, a1, 31098; RV64-NEXT: sub sp, sp, a11099; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb1100; RV64-NEXT: lui a1, 40801101; RV64-NEXT: li a2, 2551102; RV64-NEXT: li a3, 561103; RV64-NEXT: lui a4, 161104; RV64-NEXT: li a5, 401105; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1106; RV64-NEXT: vand.vx v16, v8, a1, v0.t1107; RV64-NEXT: slli a2, a2, 241108; RV64-NEXT: addi a0, a4, -2561109; RV64-NEXT: vsll.vi v16, v16, 24, v0.t1110; RV64-NEXT: vand.vx v24, v8, a2, v0.t1111; RV64-NEXT: vsll.vi v24, v24, 8, v0.t1112; RV64-NEXT: vor.vv v16, v16, v24, v0.t1113; RV64-NEXT: addi a4, sp, 161114; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill1115; RV64-NEXT: vsll.vx v24, v8, a3, v0.t1116; RV64-NEXT: vand.vx v16, v8, a0, v0.t1117; RV64-NEXT: vsll.vx v16, v16, a5, v0.t1118; RV64-NEXT: vor.vv v16, v24, v16, v0.t1119; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload1120; RV64-NEXT: vor.vv v16, v16, v24, v0.t1121; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill1122; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t1123; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t1124; RV64-NEXT: vand.vx v16, v16, a0, v0.t1125; RV64-NEXT: vor.vv v24, v16, v24, v0.t1126; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t1127; RV64-NEXT: vand.vx v16, v16, a1, v0.t1128; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t1129; RV64-NEXT: vand.vx v8, v8, a2, v0.t1130; RV64-NEXT: vor.vv v8, v8, v16, v0.t1131; RV64-NEXT: vor.vv v8, v8, v24, v0.t1132; RV64-NEXT: addi a0, sp, 161133; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1134; RV64-NEXT: vor.vv v8, v16, v8, v0.t1135; RV64-NEXT: csrr a0, vlenb1136; RV64-NEXT: slli a0, a0, 31137; RV64-NEXT: add sp, sp, a01138; RV64-NEXT: .cfi_def_cfa sp, 161139; RV64-NEXT: addi sp, sp, 161140; RV64-NEXT: .cfi_def_cfa_offset 01141; RV64-NEXT: ret1142 %v = call <16 x i64> @llvm.vp.bswap.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl)1143 ret <16 x i64> %v1144}1145 1146define <16 x i64> @vp_bswap_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {1147; RV32-LABEL: vp_bswap_v16i64_unmasked:1148; RV32: # %bb.0:1149; RV32-NEXT: addi sp, sp, -161150; RV32-NEXT: .cfi_def_cfa_offset 161151; RV32-NEXT: csrr a1, vlenb1152; RV32-NEXT: slli a1, a1, 41153; RV32-NEXT: sub sp, sp, a11154; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb1155; RV32-NEXT: lui a1, 10444801156; RV32-NEXT: li a2, 561157; RV32-NEXT: lui a3, 161158; RV32-NEXT: li a4, 401159; RV32-NEXT: lui a5, 40801160; RV32-NEXT: addi a6, sp, 81161; RV32-NEXT: sw a1, 8(sp)1162; RV32-NEXT: sw zero, 12(sp)1163; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1164; RV32-NEXT: vsll.vx v24, v8, a21165; RV32-NEXT: addi a1, a3, -2561166; RV32-NEXT: vsrl.vx v16, v8, a21167; RV32-NEXT: vsrl.vx v0, v8, a41168; RV32-NEXT: vand.vx v0, v0, a11169; RV32-NEXT: vor.vv v16, v0, v161170; RV32-NEXT: csrr a2, vlenb1171; RV32-NEXT: slli a2, a2, 31172; RV32-NEXT: add a2, sp, a21173; RV32-NEXT: addi a2, a2, 161174; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill1175; RV32-NEXT: vand.vx v0, v8, a11176; RV32-NEXT: vsll.vx v0, v0, a41177; RV32-NEXT: vor.vv v16, v24, v01178; RV32-NEXT: addi a1, sp, 161179; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1180; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1181; RV32-NEXT: vlse64.v v0, (a6), zero1182; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1183; RV32-NEXT: vsrl.vi v16, v8, 241184; RV32-NEXT: vand.vx v16, v16, a51185; RV32-NEXT: vsrl.vi v24, v8, 81186; RV32-NEXT: vand.vv v24, v24, v01187; RV32-NEXT: vor.vv v16, v24, v161188; RV32-NEXT: vand.vv v24, v8, v01189; RV32-NEXT: vand.vx v8, v8, a51190; RV32-NEXT: vsll.vi v8, v8, 241191; RV32-NEXT: vsll.vi v24, v24, 81192; RV32-NEXT: vor.vv v8, v8, v241193; RV32-NEXT: addi a0, sp, 161194; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload1195; RV32-NEXT: vor.vv v8, v24, v81196; RV32-NEXT: csrr a0, vlenb1197; RV32-NEXT: slli a0, a0, 31198; RV32-NEXT: add a0, sp, a01199; RV32-NEXT: addi a0, a0, 161200; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload1201; RV32-NEXT: vor.vv v16, v16, v241202; RV32-NEXT: vor.vv v8, v8, v161203; RV32-NEXT: csrr a0, vlenb1204; RV32-NEXT: slli a0, a0, 41205; RV32-NEXT: add sp, sp, a01206; RV32-NEXT: .cfi_def_cfa sp, 161207; RV32-NEXT: addi sp, sp, 161208; RV32-NEXT: .cfi_def_cfa_offset 01209; RV32-NEXT: ret1210;1211; RV64-LABEL: vp_bswap_v16i64_unmasked:1212; RV64: # %bb.0:1213; RV64-NEXT: addi sp, sp, -161214; RV64-NEXT: .cfi_def_cfa_offset 161215; RV64-NEXT: csrr a1, vlenb1216; RV64-NEXT: slli a1, a1, 31217; RV64-NEXT: sub sp, sp, a11218; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb1219; RV64-NEXT: lui a1, 40801220; RV64-NEXT: li a2, 2551221; RV64-NEXT: li a3, 561222; RV64-NEXT: lui a4, 161223; RV64-NEXT: li a5, 401224; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1225; RV64-NEXT: vsrl.vi v24, v8, 241226; RV64-NEXT: addi a0, a4, -2561227; RV64-NEXT: vsrl.vx v16, v8, a31228; RV64-NEXT: vsrl.vx v0, v8, a51229; RV64-NEXT: vand.vx v0, v0, a01230; RV64-NEXT: vor.vv v16, v0, v161231; RV64-NEXT: addi a4, sp, 161232; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill1233; RV64-NEXT: vsrl.vi v0, v8, 81234; RV64-NEXT: slli a2, a2, 241235; RV64-NEXT: vand.vx v24, v24, a11236; RV64-NEXT: vand.vx v0, v0, a21237; RV64-NEXT: vor.vv v24, v0, v241238; RV64-NEXT: vand.vx v0, v8, a11239; RV64-NEXT: vsll.vi v0, v0, 241240; RV64-NEXT: vand.vx v16, v8, a21241; RV64-NEXT: vsll.vi v16, v16, 81242; RV64-NEXT: vor.vv v16, v0, v161243; RV64-NEXT: vsll.vx v0, v8, a31244; RV64-NEXT: vand.vx v8, v8, a01245; RV64-NEXT: vsll.vx v8, v8, a51246; RV64-NEXT: vor.vv v8, v0, v81247; RV64-NEXT: vor.vv v8, v8, v161248; RV64-NEXT: addi a0, sp, 161249; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1250; RV64-NEXT: vor.vv v16, v24, v161251; RV64-NEXT: vor.vv v8, v8, v161252; RV64-NEXT: csrr a0, vlenb1253; RV64-NEXT: slli a0, a0, 31254; RV64-NEXT: add sp, sp, a01255; RV64-NEXT: .cfi_def_cfa sp, 161256; RV64-NEXT: addi sp, sp, 161257; RV64-NEXT: .cfi_def_cfa_offset 01258; RV64-NEXT: ret1259 %v = call <16 x i64> @llvm.vp.bswap.v16i64(<16 x i64> %va, <16 x i1> splat (i1 true), i32 %evl)1260 ret <16 x i64> %v1261}1262 1263define <128 x i16> @vp_bswap_v128i16(<128 x i16> %va, <128 x i1> %m, i32 zeroext %evl) {1264; CHECK-LABEL: vp_bswap_v128i16:1265; CHECK: # %bb.0:1266; CHECK-NEXT: li a2, 641267; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma1268; CHECK-NEXT: vslidedown.vi v7, v0, 81269; CHECK-NEXT: mv a1, a01270; CHECK-NEXT: bltu a0, a2, .LBB26_21271; CHECK-NEXT: # %bb.1:1272; CHECK-NEXT: li a1, 641273; CHECK-NEXT: .LBB26_2:1274; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1275; CHECK-NEXT: vsrl.vi v24, v8, 8, v0.t1276; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t1277; CHECK-NEXT: vor.vv v8, v8, v24, v0.t1278; CHECK-NEXT: addi a1, a0, -641279; CHECK-NEXT: sltu a0, a0, a11280; CHECK-NEXT: addi a0, a0, -11281; CHECK-NEXT: and a0, a0, a11282; CHECK-NEXT: vmv1r.v v0, v71283; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma1284; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t1285; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t1286; CHECK-NEXT: vor.vv v16, v16, v24, v0.t1287; CHECK-NEXT: ret1288 %v = call <128 x i16> @llvm.vp.bswap.v128i16(<128 x i16> %va, <128 x i1> %m, i32 %evl)1289 ret <128 x i16> %v1290}1291 1292define <128 x i16> @vp_bswap_v128i16_unmasked(<128 x i16> %va, i32 zeroext %evl) {1293; CHECK-LABEL: vp_bswap_v128i16_unmasked:1294; CHECK: # %bb.0:1295; CHECK-NEXT: li a2, 641296; CHECK-NEXT: mv a1, a01297; CHECK-NEXT: bltu a0, a2, .LBB27_21298; CHECK-NEXT: # %bb.1:1299; CHECK-NEXT: li a1, 641300; CHECK-NEXT: .LBB27_2:1301; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1302; CHECK-NEXT: vsrl.vi v24, v8, 81303; CHECK-NEXT: vsll.vi v8, v8, 81304; CHECK-NEXT: vor.vv v8, v8, v241305; CHECK-NEXT: addi a1, a0, -641306; CHECK-NEXT: sltu a0, a0, a11307; CHECK-NEXT: addi a0, a0, -11308; CHECK-NEXT: and a0, a0, a11309; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma1310; CHECK-NEXT: vsrl.vi v24, v16, 81311; CHECK-NEXT: vsll.vi v16, v16, 81312; CHECK-NEXT: vor.vv v16, v16, v241313; CHECK-NEXT: ret1314 %v = call <128 x i16> @llvm.vp.bswap.v128i16(<128 x i16> %va, <128 x i1> splat (i1 true), i32 %evl)1315 ret <128 x i16> %v1316}1317