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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVKB5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVKB6 7define void @bswap_v8i16(ptr %x, ptr %y) {8; CHECK-LABEL: bswap_v8i16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma11; CHECK-NEXT: vle16.v v8, (a0)12; CHECK-NEXT: vsrl.vi v9, v8, 813; CHECK-NEXT: vsll.vi v8, v8, 814; CHECK-NEXT: vor.vv v8, v8, v915; CHECK-NEXT: vse16.v v8, (a0)16; CHECK-NEXT: ret17;18; ZVKB-LABEL: bswap_v8i16:19; ZVKB: # %bb.0:20; ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma21; ZVKB-NEXT: vle16.v v8, (a0)22; ZVKB-NEXT: vrev8.v v8, v823; ZVKB-NEXT: vse16.v v8, (a0)24; ZVKB-NEXT: ret25 %a = load <8 x i16>, ptr %x26 %b = load <8 x i16>, ptr %y27 %c = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %a)28 store <8 x i16> %c, ptr %x29 ret void30}31 32define void @bswap_v4i32(ptr %x, ptr %y) {33; CHECK-LABEL: bswap_v4i32:34; CHECK: # %bb.0:35; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma36; CHECK-NEXT: vle32.v v8, (a0)37; CHECK-NEXT: lui a1, 1638; CHECK-NEXT: addi a1, a1, -25639; CHECK-NEXT: vsrl.vi v9, v8, 840; CHECK-NEXT: vsrl.vi v10, v8, 2441; CHECK-NEXT: vand.vx v9, v9, a142; CHECK-NEXT: vor.vv v9, v9, v1043; CHECK-NEXT: vand.vx v10, v8, a144; CHECK-NEXT: vsll.vi v8, v8, 2445; CHECK-NEXT: vsll.vi v10, v10, 846; CHECK-NEXT: vor.vv v8, v8, v1047; CHECK-NEXT: vor.vv v8, v8, v948; CHECK-NEXT: vse32.v v8, (a0)49; CHECK-NEXT: ret50;51; ZVKB-LABEL: bswap_v4i32:52; ZVKB: # %bb.0:53; ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma54; ZVKB-NEXT: vle32.v v8, (a0)55; ZVKB-NEXT: vrev8.v v8, v856; ZVKB-NEXT: vse32.v v8, (a0)57; ZVKB-NEXT: ret58 %a = load <4 x i32>, ptr %x59 %b = load <4 x i32>, ptr %y60 %c = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %a)61 store <4 x i32> %c, ptr %x62 ret void63}64 65define void @bswap_v2i64(ptr %x, ptr %y) {66; RV32-LABEL: bswap_v2i64:67; RV32: # %bb.0:68; RV32-NEXT: addi sp, sp, -1669; RV32-NEXT: .cfi_def_cfa_offset 1670; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma71; RV32-NEXT: vle64.v v8, (a0)72; RV32-NEXT: lui a1, 104448073; RV32-NEXT: li a2, 5674; RV32-NEXT: li a3, 4075; RV32-NEXT: lui a4, 1676; RV32-NEXT: lui a5, 408077; RV32-NEXT: addi a6, sp, 878; RV32-NEXT: sw a1, 8(sp)79; RV32-NEXT: sw zero, 12(sp)80; RV32-NEXT: addi a1, a4, -25681; RV32-NEXT: vlse64.v v9, (a6), zero82; RV32-NEXT: vsrl.vx v10, v8, a283; RV32-NEXT: vsrl.vx v11, v8, a384; RV32-NEXT: vsrl.vi v12, v8, 2485; RV32-NEXT: vsll.vx v13, v8, a286; RV32-NEXT: vand.vx v11, v11, a187; RV32-NEXT: vor.vv v10, v11, v1088; RV32-NEXT: vand.vx v11, v8, a189; RV32-NEXT: vsll.vx v11, v11, a390; RV32-NEXT: vor.vv v11, v13, v1191; RV32-NEXT: vsrl.vi v13, v8, 892; RV32-NEXT: vand.vx v12, v12, a593; RV32-NEXT: vand.vv v13, v13, v994; RV32-NEXT: vor.vv v12, v13, v1295; RV32-NEXT: vand.vv v9, v8, v996; RV32-NEXT: vand.vx v8, v8, a597; RV32-NEXT: vsll.vi v8, v8, 2498; RV32-NEXT: vsll.vi v9, v9, 899; RV32-NEXT: vor.vv v10, v12, v10100; RV32-NEXT: vor.vv v8, v8, v9101; RV32-NEXT: vor.vv v8, v11, v8102; RV32-NEXT: vor.vv v8, v8, v10103; RV32-NEXT: vse64.v v8, (a0)104; RV32-NEXT: addi sp, sp, 16105; RV32-NEXT: .cfi_def_cfa_offset 0106; RV32-NEXT: ret107;108; RV64-LABEL: bswap_v2i64:109; RV64: # %bb.0:110; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma111; RV64-NEXT: vle64.v v8, (a0)112; RV64-NEXT: li a1, 56113; RV64-NEXT: li a2, 40114; RV64-NEXT: lui a3, 16115; RV64-NEXT: lui a4, 4080116; RV64-NEXT: li a5, 255117; RV64-NEXT: addi a3, a3, -256118; RV64-NEXT: slli a5, a5, 24119; RV64-NEXT: vsrl.vx v9, v8, a1120; RV64-NEXT: vsrl.vx v10, v8, a2121; RV64-NEXT: vsrl.vi v11, v8, 24122; RV64-NEXT: vsrl.vi v12, v8, 8123; RV64-NEXT: vand.vx v10, v10, a3124; RV64-NEXT: vor.vv v9, v10, v9125; RV64-NEXT: vand.vx v10, v8, a5126; RV64-NEXT: vand.vx v11, v11, a4127; RV64-NEXT: vand.vx v12, v12, a5128; RV64-NEXT: vor.vv v11, v12, v11129; RV64-NEXT: vand.vx v12, v8, a4130; RV64-NEXT: vsll.vi v10, v10, 8131; RV64-NEXT: vsll.vi v12, v12, 24132; RV64-NEXT: vor.vv v10, v12, v10133; RV64-NEXT: vsll.vx v12, v8, a1134; RV64-NEXT: vand.vx v8, v8, a3135; RV64-NEXT: vsll.vx v8, v8, a2136; RV64-NEXT: vor.vv v8, v12, v8137; RV64-NEXT: vor.vv v9, v11, v9138; RV64-NEXT: vor.vv v8, v8, v10139; RV64-NEXT: vor.vv v8, v8, v9140; RV64-NEXT: vse64.v v8, (a0)141; RV64-NEXT: ret142;143; ZVKB-LABEL: bswap_v2i64:144; ZVKB: # %bb.0:145; ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma146; ZVKB-NEXT: vle64.v v8, (a0)147; ZVKB-NEXT: vrev8.v v8, v8148; ZVKB-NEXT: vse64.v v8, (a0)149; ZVKB-NEXT: ret150 %a = load <2 x i64>, ptr %x151 %b = load <2 x i64>, ptr %y152 %c = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %a)153 store <2 x i64> %c, ptr %x154 ret void155}156 157define void @bswap_v16i16(ptr %x, ptr %y) {158; CHECK-LABEL: bswap_v16i16:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma161; CHECK-NEXT: vle16.v v8, (a0)162; CHECK-NEXT: vsrl.vi v10, v8, 8163; CHECK-NEXT: vsll.vi v8, v8, 8164; CHECK-NEXT: vor.vv v8, v8, v10165; CHECK-NEXT: vse16.v v8, (a0)166; CHECK-NEXT: ret167;168; ZVKB-LABEL: bswap_v16i16:169; ZVKB: # %bb.0:170; ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma171; ZVKB-NEXT: vle16.v v8, (a0)172; ZVKB-NEXT: vrev8.v v8, v8173; ZVKB-NEXT: vse16.v v8, (a0)174; ZVKB-NEXT: ret175 %a = load <16 x i16>, ptr %x176 %b = load <16 x i16>, ptr %y177 %c = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %a)178 store <16 x i16> %c, ptr %x179 ret void180}181 182define void @bswap_v8i32(ptr %x, ptr %y) {183; CHECK-LABEL: bswap_v8i32:184; CHECK: # %bb.0:185; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma186; CHECK-NEXT: vle32.v v8, (a0)187; CHECK-NEXT: lui a1, 16188; CHECK-NEXT: addi a1, a1, -256189; CHECK-NEXT: vsrl.vi v10, v8, 8190; CHECK-NEXT: vsrl.vi v12, v8, 24191; CHECK-NEXT: vand.vx v10, v10, a1192; CHECK-NEXT: vor.vv v10, v10, v12193; CHECK-NEXT: vand.vx v12, v8, a1194; CHECK-NEXT: vsll.vi v8, v8, 24195; CHECK-NEXT: vsll.vi v12, v12, 8196; CHECK-NEXT: vor.vv v8, v8, v12197; CHECK-NEXT: vor.vv v8, v8, v10198; CHECK-NEXT: vse32.v v8, (a0)199; CHECK-NEXT: ret200;201; ZVKB-LABEL: bswap_v8i32:202; ZVKB: # %bb.0:203; ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma204; ZVKB-NEXT: vle32.v v8, (a0)205; ZVKB-NEXT: vrev8.v v8, v8206; ZVKB-NEXT: vse32.v v8, (a0)207; ZVKB-NEXT: ret208 %a = load <8 x i32>, ptr %x209 %b = load <8 x i32>, ptr %y210 %c = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %a)211 store <8 x i32> %c, ptr %x212 ret void213}214 215define void @bswap_v4i64(ptr %x, ptr %y) {216; RV32-LABEL: bswap_v4i64:217; RV32: # %bb.0:218; RV32-NEXT: addi sp, sp, -16219; RV32-NEXT: .cfi_def_cfa_offset 16220; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma221; RV32-NEXT: vle64.v v8, (a0)222; RV32-NEXT: lui a1, 1044480223; RV32-NEXT: li a2, 56224; RV32-NEXT: li a3, 40225; RV32-NEXT: lui a4, 16226; RV32-NEXT: lui a5, 4080227; RV32-NEXT: addi a6, sp, 8228; RV32-NEXT: sw a1, 8(sp)229; RV32-NEXT: sw zero, 12(sp)230; RV32-NEXT: addi a1, a4, -256231; RV32-NEXT: vlse64.v v10, (a6), zero232; RV32-NEXT: vsrl.vx v12, v8, a2233; RV32-NEXT: vsrl.vx v14, v8, a3234; RV32-NEXT: vsrl.vi v16, v8, 24235; RV32-NEXT: vsll.vx v18, v8, a2236; RV32-NEXT: vand.vx v14, v14, a1237; RV32-NEXT: vor.vv v12, v14, v12238; RV32-NEXT: vand.vx v14, v8, a1239; RV32-NEXT: vsll.vx v14, v14, a3240; RV32-NEXT: vor.vv v14, v18, v14241; RV32-NEXT: vsrl.vi v18, v8, 8242; RV32-NEXT: vand.vx v16, v16, a5243; RV32-NEXT: vand.vv v18, v18, v10244; RV32-NEXT: vor.vv v16, v18, v16245; RV32-NEXT: vand.vv v10, v8, v10246; RV32-NEXT: vand.vx v8, v8, a5247; RV32-NEXT: vsll.vi v8, v8, 24248; RV32-NEXT: vsll.vi v10, v10, 8249; RV32-NEXT: vor.vv v12, v16, v12250; RV32-NEXT: vor.vv v8, v8, v10251; RV32-NEXT: vor.vv v8, v14, v8252; RV32-NEXT: vor.vv v8, v8, v12253; RV32-NEXT: vse64.v v8, (a0)254; RV32-NEXT: addi sp, sp, 16255; RV32-NEXT: .cfi_def_cfa_offset 0256; RV32-NEXT: ret257;258; RV64-LABEL: bswap_v4i64:259; RV64: # %bb.0:260; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma261; RV64-NEXT: vle64.v v8, (a0)262; RV64-NEXT: li a1, 56263; RV64-NEXT: li a2, 40264; RV64-NEXT: lui a3, 16265; RV64-NEXT: lui a4, 4080266; RV64-NEXT: li a5, 255267; RV64-NEXT: addi a3, a3, -256268; RV64-NEXT: slli a5, a5, 24269; RV64-NEXT: vsrl.vx v10, v8, a1270; RV64-NEXT: vsrl.vx v12, v8, a2271; RV64-NEXT: vsrl.vi v14, v8, 24272; RV64-NEXT: vsrl.vi v16, v8, 8273; RV64-NEXT: vand.vx v12, v12, a3274; RV64-NEXT: vor.vv v10, v12, v10275; RV64-NEXT: vand.vx v12, v8, a5276; RV64-NEXT: vand.vx v14, v14, a4277; RV64-NEXT: vand.vx v16, v16, a5278; RV64-NEXT: vor.vv v14, v16, v14279; RV64-NEXT: vand.vx v16, v8, a4280; RV64-NEXT: vsll.vi v12, v12, 8281; RV64-NEXT: vsll.vi v16, v16, 24282; RV64-NEXT: vor.vv v12, v16, v12283; RV64-NEXT: vsll.vx v16, v8, a1284; RV64-NEXT: vand.vx v8, v8, a3285; RV64-NEXT: vsll.vx v8, v8, a2286; RV64-NEXT: vor.vv v8, v16, v8287; RV64-NEXT: vor.vv v10, v14, v10288; RV64-NEXT: vor.vv v8, v8, v12289; RV64-NEXT: vor.vv v8, v8, v10290; RV64-NEXT: vse64.v v8, (a0)291; RV64-NEXT: ret292;293; ZVKB-LABEL: bswap_v4i64:294; ZVKB: # %bb.0:295; ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma296; ZVKB-NEXT: vle64.v v8, (a0)297; ZVKB-NEXT: vrev8.v v8, v8298; ZVKB-NEXT: vse64.v v8, (a0)299; ZVKB-NEXT: ret300 %a = load <4 x i64>, ptr %x301 %b = load <4 x i64>, ptr %y302 %c = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)303 store <4 x i64> %c, ptr %x304 ret void305}306