628 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define <4 x i32> @add_constant_rhs(i32 %a, i32 %b, i32 %c, i32 %d) {6; CHECK-LABEL: add_constant_rhs:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma9; CHECK-NEXT: vmv.v.x v8, a010; CHECK-NEXT: lui a0, %hi(.LCPI0_0)11; CHECK-NEXT: addi a0, a0, %lo(.LCPI0_0)12; CHECK-NEXT: vle32.v v9, (a0)13; CHECK-NEXT: vslide1down.vx v8, v8, a114; CHECK-NEXT: vslide1down.vx v8, v8, a215; CHECK-NEXT: vslide1down.vx v8, v8, a316; CHECK-NEXT: vadd.vv v8, v8, v917; CHECK-NEXT: ret18 %e0 = add i32 %a, 2319 %e1 = add i32 %b, 2520 %e2 = add i32 %c, 121 %e3 = add i32 %d, 235522 %v0 = insertelement <4 x i32> poison, i32 %e0, i32 023 %v1 = insertelement <4 x i32> %v0, i32 %e1, i32 124 %v2 = insertelement <4 x i32> %v1, i32 %e2, i32 225 %v3 = insertelement <4 x i32> %v2, i32 %e3, i32 326 ret <4 x i32> %v327}28 29define <8 x i32> @add_constant_rhs_8xi32(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) {30; CHECK-LABEL: add_constant_rhs_8xi32:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma33; CHECK-NEXT: vmv.v.x v8, a034; CHECK-NEXT: lui a0, %hi(.LCPI1_0)35; CHECK-NEXT: addi a0, a0, %lo(.LCPI1_0)36; CHECK-NEXT: vslide1down.vx v8, v8, a137; CHECK-NEXT: vslide1down.vx v8, v8, a238; CHECK-NEXT: vslide1down.vx v8, v8, a339; CHECK-NEXT: vslide1down.vx v8, v8, a440; CHECK-NEXT: vle32.v v10, (a0)41; CHECK-NEXT: vslide1down.vx v8, v8, a542; CHECK-NEXT: vslide1down.vx v8, v8, a643; CHECK-NEXT: vslide1down.vx v8, v8, a744; CHECK-NEXT: vadd.vv v8, v8, v1045; CHECK-NEXT: ret46 %e0 = add i32 %a, 2347 %e1 = add i32 %b, 2548 %e2 = add i32 %c, 149 %e3 = add i32 %d, 235550 %e4 = add i32 %e, 2351 %e5 = add i32 %f, 2352 %e6 = add i32 %g, 2253 %e7 = add i32 %h, 2354 %v0 = insertelement <8 x i32> poison, i32 %e0, i32 055 %v1 = insertelement <8 x i32> %v0, i32 %e1, i32 156 %v2 = insertelement <8 x i32> %v1, i32 %e2, i32 257 %v3 = insertelement <8 x i32> %v2, i32 %e3, i32 358 %v4 = insertelement <8 x i32> %v3, i32 %e4, i32 459 %v5 = insertelement <8 x i32> %v4, i32 %e5, i32 560 %v6 = insertelement <8 x i32> %v5, i32 %e6, i32 661 %v7 = insertelement <8 x i32> %v6, i32 %e7, i32 762 ret <8 x i32> %v763}64 65 66define <4 x i32> @sub_constant_rhs(i32 %a, i32 %b, i32 %c, i32 %d) {67; CHECK-LABEL: sub_constant_rhs:68; CHECK: # %bb.0:69; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma70; CHECK-NEXT: vmv.v.x v8, a071; CHECK-NEXT: lui a0, %hi(.LCPI2_0)72; CHECK-NEXT: addi a0, a0, %lo(.LCPI2_0)73; CHECK-NEXT: vle32.v v9, (a0)74; CHECK-NEXT: vslide1down.vx v8, v8, a175; CHECK-NEXT: vslide1down.vx v8, v8, a276; CHECK-NEXT: vslide1down.vx v8, v8, a377; CHECK-NEXT: vsub.vv v8, v8, v978; CHECK-NEXT: ret79 %e0 = sub i32 %a, 2380 %e1 = sub i32 %b, 2581 %e2 = sub i32 %c, 182 %e3 = sub i32 %d, 235583 %v0 = insertelement <4 x i32> poison, i32 %e0, i32 084 %v1 = insertelement <4 x i32> %v0, i32 %e1, i32 185 %v2 = insertelement <4 x i32> %v1, i32 %e2, i32 286 %v3 = insertelement <4 x i32> %v2, i32 %e3, i32 387 ret <4 x i32> %v388}89 90define <4 x i32> @mul_constant_rhs(i32 %a, i32 %b, i32 %c, i32 %d) {91; CHECK-LABEL: mul_constant_rhs:92; CHECK: # %bb.0:93; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma94; CHECK-NEXT: vmv.v.x v8, a095; CHECK-NEXT: lui a0, %hi(.LCPI3_0)96; CHECK-NEXT: addi a0, a0, %lo(.LCPI3_0)97; CHECK-NEXT: vle32.v v9, (a0)98; CHECK-NEXT: vslide1down.vx v8, v8, a199; CHECK-NEXT: vslide1down.vx v8, v8, a2100; CHECK-NEXT: vslide1down.vx v8, v8, a3101; CHECK-NEXT: vmul.vv v8, v8, v9102; CHECK-NEXT: ret103 %e0 = mul i32 %a, 23104 %e1 = mul i32 %b, 25105 %e2 = mul i32 %c, 27106 %e3 = mul i32 %d, 2355107 %v0 = insertelement <4 x i32> poison, i32 %e0, i32 0108 %v1 = insertelement <4 x i32> %v0, i32 %e1, i32 1109 %v2 = insertelement <4 x i32> %v1, i32 %e2, i32 2110 %v3 = insertelement <4 x i32> %v2, i32 %e3, i32 3111 ret <4 x i32> %v3112}113 114define <4 x i32> @udiv_constant_rhs(i32 %a, i32 %b, i32 %c, i32 %d) {115; CHECK-LABEL: udiv_constant_rhs:116; CHECK: # %bb.0:117; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma118; CHECK-NEXT: vmv.v.x v8, a0119; CHECK-NEXT: lui a0, %hi(.LCPI4_0)120; CHECK-NEXT: addi a0, a0, %lo(.LCPI4_0)121; CHECK-NEXT: vmv.v.i v9, 0122; CHECK-NEXT: vslide1down.vx v8, v8, a1123; CHECK-NEXT: lui a1, 524288124; CHECK-NEXT: vle32.v v10, (a0)125; CHECK-NEXT: lui a0, %hi(.LCPI4_1)126; CHECK-NEXT: addi a0, a0, %lo(.LCPI4_1)127; CHECK-NEXT: vslide1down.vx v9, v9, a1128; CHECK-NEXT: vle32.v v11, (a0)129; CHECK-NEXT: vslide1down.vx v8, v8, a2130; CHECK-NEXT: vslide1down.vx v8, v8, a3131; CHECK-NEXT: vmulhu.vv v10, v8, v10132; CHECK-NEXT: vsub.vv v12, v8, v10133; CHECK-NEXT: vmulhu.vv v9, v12, v9134; CHECK-NEXT: vadd.vv v9, v9, v10135; CHECK-NEXT: vmv.v.i v0, 4136; CHECK-NEXT: vsrl.vv v9, v9, v11137; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0138; CHECK-NEXT: ret139 %e0 = udiv i32 %a, 23140 %e1 = udiv i32 %b, 25141 %e2 = udiv i32 %c, 1142 %e3 = udiv i32 %d, 235143 %v0 = insertelement <4 x i32> poison, i32 %e0, i32 0144 %v1 = insertelement <4 x i32> %v0, i32 %e1, i32 1145 %v2 = insertelement <4 x i32> %v1, i32 %e2, i32 2146 %v3 = insertelement <4 x i32> %v2, i32 %e3, i32 3147 ret <4 x i32> %v3148}149 150 151define <4 x float> @fadd_constant_rhs(float %a, float %b, float %c, float %d) {152; CHECK-LABEL: fadd_constant_rhs:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma155; CHECK-NEXT: vfmv.v.f v8, fa0156; CHECK-NEXT: lui a0, %hi(.LCPI5_0)157; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_0)158; CHECK-NEXT: vle32.v v9, (a0)159; CHECK-NEXT: vfslide1down.vf v8, v8, fa1160; CHECK-NEXT: vfslide1down.vf v8, v8, fa2161; CHECK-NEXT: vfslide1down.vf v8, v8, fa3162; CHECK-NEXT: vfadd.vv v8, v8, v9163; CHECK-NEXT: ret164 %e0 = fadd float %a, 23.0165 %e1 = fadd float %b, 25.0166 %e2 = fadd float %c, 2.0167 %e3 = fadd float %d, 23.0168 %v0 = insertelement <4 x float> poison, float %e0, i32 0169 %v1 = insertelement <4 x float> %v0, float %e1, i32 1170 %v2 = insertelement <4 x float> %v1, float %e2, i32 2171 %v3 = insertelement <4 x float> %v2, float %e3, i32 3172 ret <4 x float> %v3173}174 175define <4 x float> @fdiv_constant_rhs(float %a, float %b, float %c, float %d) {176; CHECK-LABEL: fdiv_constant_rhs:177; CHECK: # %bb.0:178; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma179; CHECK-NEXT: vfmv.v.f v8, fa0180; CHECK-NEXT: lui a0, %hi(.LCPI6_0)181; CHECK-NEXT: addi a0, a0, %lo(.LCPI6_0)182; CHECK-NEXT: vle32.v v9, (a0)183; CHECK-NEXT: vfslide1down.vf v8, v8, fa1184; CHECK-NEXT: vfslide1down.vf v8, v8, fa2185; CHECK-NEXT: vfslide1down.vf v8, v8, fa3186; CHECK-NEXT: vfdiv.vv v8, v8, v9187; CHECK-NEXT: ret188 %e0 = fdiv float %a, 23.0189 %e1 = fdiv float %b, 25.0190 %e2 = fdiv float %c, 10.0191 %e3 = fdiv float %d, 23.0192 %v0 = insertelement <4 x float> poison, float %e0, i32 0193 %v1 = insertelement <4 x float> %v0, float %e1, i32 1194 %v2 = insertelement <4 x float> %v1, float %e2, i32 2195 %v3 = insertelement <4 x float> %v2, float %e3, i32 3196 ret <4 x float> %v3197}198 199define <4 x i32> @add_constant_rhs_splat(i32 %a, i32 %b, i32 %c, i32 %d) {200; CHECK-LABEL: add_constant_rhs_splat:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma203; CHECK-NEXT: vmv.v.x v8, a0204; CHECK-NEXT: vslide1down.vx v8, v8, a1205; CHECK-NEXT: vslide1down.vx v8, v8, a2206; CHECK-NEXT: vslide1down.vx v8, v8, a3207; CHECK-NEXT: li a0, 23208; CHECK-NEXT: vadd.vx v8, v8, a0209; CHECK-NEXT: ret210 %e0 = add i32 %a, 23211 %e1 = add i32 %b, 23212 %e2 = add i32 %c, 23213 %e3 = add i32 %d, 23214 %v0 = insertelement <4 x i32> poison, i32 %e0, i32 0215 %v1 = insertelement <4 x i32> %v0, i32 %e1, i32 1216 %v2 = insertelement <4 x i32> %v1, i32 %e2, i32 2217 %v3 = insertelement <4 x i32> %v2, i32 %e3, i32 3218 ret <4 x i32> %v3219}220 221define <4 x i32> @add_constant_rhs_with_identity(i32 %a, i32 %b, i32 %c, i32 %d) {222; RV32-LABEL: add_constant_rhs_with_identity:223; RV32: # %bb.0:224; RV32-NEXT: addi a1, a1, 25225; RV32-NEXT: addi a2, a2, 1226; RV32-NEXT: addi a3, a3, 2047227; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma228; RV32-NEXT: vmv.v.x v8, a0229; RV32-NEXT: addi a0, a3, 308230; RV32-NEXT: vslide1down.vx v8, v8, a1231; RV32-NEXT: vslide1down.vx v8, v8, a2232; RV32-NEXT: vslide1down.vx v8, v8, a0233; RV32-NEXT: ret234;235; RV64-LABEL: add_constant_rhs_with_identity:236; RV64: # %bb.0:237; RV64-NEXT: addiw a1, a1, 25238; RV64-NEXT: addiw a2, a2, 1239; RV64-NEXT: addi a3, a3, 2047240; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma241; RV64-NEXT: vmv.v.x v8, a0242; RV64-NEXT: addiw a0, a3, 308243; RV64-NEXT: vslide1down.vx v8, v8, a1244; RV64-NEXT: vslide1down.vx v8, v8, a2245; RV64-NEXT: vslide1down.vx v8, v8, a0246; RV64-NEXT: ret247 %e0 = add i32 %a, 0248 %e1 = add i32 %b, 25249 %e2 = add i32 %c, 1250 %e3 = add i32 %d, 2355251 %v0 = insertelement <4 x i32> poison, i32 %e0, i32 0252 %v1 = insertelement <4 x i32> %v0, i32 %e1, i32 1253 %v2 = insertelement <4 x i32> %v1, i32 %e2, i32 2254 %v3 = insertelement <4 x i32> %v2, i32 %e3, i32 3255 ret <4 x i32> %v3256}257 258define <4 x i32> @add_constant_rhs_identity(i32 %a, i32 %b, i32 %c, i32 %d) {259; RV32-LABEL: add_constant_rhs_identity:260; RV32: # %bb.0:261; RV32-NEXT: addi a1, a1, 25262; RV32-NEXT: addi a2, a2, 1263; RV32-NEXT: addi a3, a3, 2047264; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma265; RV32-NEXT: vmv.v.x v8, a0266; RV32-NEXT: addi a0, a3, 308267; RV32-NEXT: vslide1down.vx v8, v8, a1268; RV32-NEXT: vslide1down.vx v8, v8, a2269; RV32-NEXT: vslide1down.vx v8, v8, a0270; RV32-NEXT: ret271;272; RV64-LABEL: add_constant_rhs_identity:273; RV64: # %bb.0:274; RV64-NEXT: addiw a1, a1, 25275; RV64-NEXT: addiw a2, a2, 1276; RV64-NEXT: addi a3, a3, 2047277; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma278; RV64-NEXT: vmv.v.x v8, a0279; RV64-NEXT: addiw a0, a3, 308280; RV64-NEXT: vslide1down.vx v8, v8, a1281; RV64-NEXT: vslide1down.vx v8, v8, a2282; RV64-NEXT: vslide1down.vx v8, v8, a0283; RV64-NEXT: ret284 %e0 = add i32 %a, 0285 %e1 = add i32 %b, 25286 %e2 = add i32 %c, 1287 %e3 = add i32 %d, 2355288 %v0 = insertelement <4 x i32> poison, i32 %e0, i32 0289 %v1 = insertelement <4 x i32> %v0, i32 %e1, i32 1290 %v2 = insertelement <4 x i32> %v1, i32 %e2, i32 2291 %v3 = insertelement <4 x i32> %v2, i32 %e3, i32 3292 ret <4 x i32> %v3293}294 295define <4 x i32> @add_constant_rhs_identity2(i32 %a, i32 %b, i32 %c, i32 %d) {296; CHECK-LABEL: add_constant_rhs_identity2:297; CHECK: # %bb.0:298; CHECK-NEXT: addi a0, a0, 23299; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma300; CHECK-NEXT: vmv.v.x v8, a0301; CHECK-NEXT: vslide1down.vx v8, v8, a1302; CHECK-NEXT: vslide1down.vx v8, v8, a2303; CHECK-NEXT: vslide1down.vx v8, v8, a3304; CHECK-NEXT: ret305 %e0 = add i32 %a, 23306 %v0 = insertelement <4 x i32> poison, i32 %e0, i32 0307 %v1 = insertelement <4 x i32> %v0, i32 %b, i32 1308 %v2 = insertelement <4 x i32> %v1, i32 %c, i32 2309 %v3 = insertelement <4 x i32> %v2, i32 %d, i32 3310 ret <4 x i32> %v3311}312 313define <4 x i32> @add_constant_rhs_inverse(i32 %a, i32 %b, i32 %c, i32 %d) {314; CHECK-LABEL: add_constant_rhs_inverse:315; CHECK: # %bb.0:316; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma317; CHECK-NEXT: vmv.v.x v8, a0318; CHECK-NEXT: lui a0, %hi(.LCPI11_0)319; CHECK-NEXT: addi a0, a0, %lo(.LCPI11_0)320; CHECK-NEXT: vle32.v v9, (a0)321; CHECK-NEXT: vslide1down.vx v8, v8, a1322; CHECK-NEXT: vslide1down.vx v8, v8, a2323; CHECK-NEXT: vslide1down.vx v8, v8, a3324; CHECK-NEXT: vadd.vv v8, v8, v9325; CHECK-NEXT: ret326 %e0 = sub i32 %a, 1327 %e1 = add i32 %b, 25328 %e2 = add i32 %c, 1329 %e3 = add i32 %d, 2355330 %v0 = insertelement <4 x i32> poison, i32 %e0, i32 0331 %v1 = insertelement <4 x i32> %v0, i32 %e1, i32 1332 %v2 = insertelement <4 x i32> %v1, i32 %e2, i32 2333 %v3 = insertelement <4 x i32> %v2, i32 %e3, i32 3334 ret <4 x i32> %v3335}336 337define <4 x i32> @add_constant_rhs_commute(i32 %a, i32 %b, i32 %c, i32 %d) {338; CHECK-LABEL: add_constant_rhs_commute:339; CHECK: # %bb.0:340; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma341; CHECK-NEXT: vmv.v.x v8, a0342; CHECK-NEXT: lui a0, %hi(.LCPI12_0)343; CHECK-NEXT: addi a0, a0, %lo(.LCPI12_0)344; CHECK-NEXT: vle32.v v9, (a0)345; CHECK-NEXT: vslide1down.vx v8, v8, a1346; CHECK-NEXT: vslide1down.vx v8, v8, a2347; CHECK-NEXT: vslide1down.vx v8, v8, a3348; CHECK-NEXT: vadd.vv v8, v8, v9349; CHECK-NEXT: ret350 %e0 = add i32 %a, 23351 %e1 = add i32 %b, 25352 %e2 = add i32 1, %c353 %e3 = add i32 %d, 2355354 %v0 = insertelement <4 x i32> poison, i32 %e0, i32 0355 %v1 = insertelement <4 x i32> %v0, i32 %e1, i32 1356 %v2 = insertelement <4 x i32> %v1, i32 %e2, i32 2357 %v3 = insertelement <4 x i32> %v2, i32 %e3, i32 3358 ret <4 x i32> %v3359}360 361 362define <4 x i32> @add_general_rhs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) {363; RV32-LABEL: add_general_rhs:364; RV32: # %bb.0:365; RV32-NEXT: add a0, a0, a4366; RV32-NEXT: add a1, a1, a5367; RV32-NEXT: add a2, a2, a6368; RV32-NEXT: add a3, a3, a7369; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma370; RV32-NEXT: vmv.v.x v8, a0371; RV32-NEXT: vslide1down.vx v8, v8, a1372; RV32-NEXT: vslide1down.vx v8, v8, a2373; RV32-NEXT: vslide1down.vx v8, v8, a3374; RV32-NEXT: ret375;376; RV64-LABEL: add_general_rhs:377; RV64: # %bb.0:378; RV64-NEXT: add a0, a0, a4379; RV64-NEXT: addw a1, a1, a5380; RV64-NEXT: addw a2, a2, a6381; RV64-NEXT: addw a3, a3, a7382; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma383; RV64-NEXT: vmv.v.x v8, a0384; RV64-NEXT: vslide1down.vx v8, v8, a1385; RV64-NEXT: vslide1down.vx v8, v8, a2386; RV64-NEXT: vslide1down.vx v8, v8, a3387; RV64-NEXT: ret388 %e0 = add i32 %a, %e389 %e1 = add i32 %b, %f390 %e2 = add i32 %c, %g391 %e3 = add i32 %d, %h392 %v0 = insertelement <4 x i32> poison, i32 %e0, i32 0393 %v1 = insertelement <4 x i32> %v0, i32 %e1, i32 1394 %v2 = insertelement <4 x i32> %v1, i32 %e2, i32 2395 %v3 = insertelement <4 x i32> %v2, i32 %e3, i32 3396 ret <4 x i32> %v3397}398 399define <4 x i32> @add_general_splat(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {400; RV32-LABEL: add_general_splat:401; RV32: # %bb.0:402; RV32-NEXT: add a0, a0, a4403; RV32-NEXT: add a1, a1, a4404; RV32-NEXT: add a2, a2, a4405; RV32-NEXT: add a3, a3, a4406; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma407; RV32-NEXT: vmv.v.x v8, a0408; RV32-NEXT: vslide1down.vx v8, v8, a1409; RV32-NEXT: vslide1down.vx v8, v8, a2410; RV32-NEXT: vslide1down.vx v8, v8, a3411; RV32-NEXT: ret412;413; RV64-LABEL: add_general_splat:414; RV64: # %bb.0:415; RV64-NEXT: add a0, a0, a4416; RV64-NEXT: addw a1, a1, a4417; RV64-NEXT: addw a2, a2, a4418; RV64-NEXT: addw a3, a3, a4419; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma420; RV64-NEXT: vmv.v.x v8, a0421; RV64-NEXT: vslide1down.vx v8, v8, a1422; RV64-NEXT: vslide1down.vx v8, v8, a2423; RV64-NEXT: vslide1down.vx v8, v8, a3424; RV64-NEXT: ret425 %e0 = add i32 %a, %e426 %e1 = add i32 %b, %e427 %e2 = add i32 %c, %e428 %e3 = add i32 %d, %e429 %v0 = insertelement <4 x i32> poison, i32 %e0, i32 0430 %v1 = insertelement <4 x i32> %v0, i32 %e1, i32 1431 %v2 = insertelement <4 x i32> %v1, i32 %e2, i32 2432 %v3 = insertelement <4 x i32> %v2, i32 %e3, i32 3433 ret <4 x i32> %v3434}435 436; This test previously failed with an assertion failure because constant shift437; amounts are type legalized early.438define void @buggy(i32 %0) #0 {439; RV32-LABEL: buggy:440; RV32: # %bb.0: # %entry441; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma442; RV32-NEXT: vmv.s.x v8, a0443; RV32-NEXT: vadd.vv v8, v8, v8444; RV32-NEXT: vor.vi v8, v8, 1445; RV32-NEXT: vrgather.vi v9, v8, 0446; RV32-NEXT: vse32.v v9, (zero)447; RV32-NEXT: ret448;449; RV64-LABEL: buggy:450; RV64: # %bb.0: # %entry451; RV64-NEXT: slli a0, a0, 1452; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma453; RV64-NEXT: vmv.s.x v8, a0454; RV64-NEXT: vor.vi v8, v8, 1455; RV64-NEXT: vrgather.vi v9, v8, 0456; RV64-NEXT: vse32.v v9, (zero)457; RV64-NEXT: ret458entry:459 %mul.us.us.i.3 = shl i32 %0, 1460 %1 = insertelement <4 x i32> zeroinitializer, i32 %mul.us.us.i.3, i64 0461 %2 = or <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>462 %3 = shufflevector <4 x i32> %2, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer463 store <4 x i32> %3, ptr null, align 16464 ret void465}466 467 468define <8 x i32> @add_constant_rhs_8xi32_vector_in(<8 x i32> %vin, i32 %a, i32 %b, i32 %c, i32 %d) {469; CHECK-LABEL: add_constant_rhs_8xi32_vector_in:470; CHECK: # %bb.0:471; CHECK-NEXT: addi a0, a0, 23472; CHECK-NEXT: addi a1, a1, 25473; CHECK-NEXT: addi a2, a2, 1474; CHECK-NEXT: addi a3, a3, 2047475; CHECK-NEXT: addi a3, a3, 308476; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma477; CHECK-NEXT: vmv.s.x v8, a0478; CHECK-NEXT: vmv.s.x v10, a1479; CHECK-NEXT: vslideup.vi v8, v10, 1480; CHECK-NEXT: vmv.s.x v10, a2481; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma482; CHECK-NEXT: vslideup.vi v8, v10, 2483; CHECK-NEXT: vmv.s.x v10, a3484; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma485; CHECK-NEXT: vslideup.vi v8, v10, 3486; CHECK-NEXT: ret487 %e0 = add i32 %a, 23488 %e1 = add i32 %b, 25489 %e2 = add i32 %c, 1490 %e3 = add i32 %d, 2355491 %v0 = insertelement <8 x i32> %vin, i32 %e0, i32 0492 %v1 = insertelement <8 x i32> %v0, i32 %e1, i32 1493 %v2 = insertelement <8 x i32> %v1, i32 %e2, i32 2494 %v3 = insertelement <8 x i32> %v2, i32 %e3, i32 3495 ret <8 x i32> %v3496}497 498define <8 x i32> @add_constant_rhs_8xi32_vector_in2(<8 x i32> %vin, i32 %a, i32 %b, i32 %c, i32 %d) {499; CHECK-LABEL: add_constant_rhs_8xi32_vector_in2:500; CHECK: # %bb.0:501; CHECK-NEXT: addi a0, a0, 23502; CHECK-NEXT: addi a1, a1, 25503; CHECK-NEXT: addi a2, a2, 1504; CHECK-NEXT: addi a3, a3, 2047505; CHECK-NEXT: addi a3, a3, 308506; CHECK-NEXT: vsetivli zero, 5, e32, m2, tu, ma507; CHECK-NEXT: vmv.s.x v10, a0508; CHECK-NEXT: vslideup.vi v8, v10, 4509; CHECK-NEXT: vmv.s.x v10, a1510; CHECK-NEXT: vsetivli zero, 6, e32, m2, tu, ma511; CHECK-NEXT: vslideup.vi v8, v10, 5512; CHECK-NEXT: vmv.s.x v10, a2513; CHECK-NEXT: vsetivli zero, 7, e32, m2, tu, ma514; CHECK-NEXT: vslideup.vi v8, v10, 6515; CHECK-NEXT: vmv.s.x v10, a3516; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma517; CHECK-NEXT: vslideup.vi v8, v10, 7518; CHECK-NEXT: ret519 %e0 = add i32 %a, 23520 %e1 = add i32 %b, 25521 %e2 = add i32 %c, 1522 %e3 = add i32 %d, 2355523 %v0 = insertelement <8 x i32> %vin, i32 %e0, i32 4524 %v1 = insertelement <8 x i32> %v0, i32 %e1, i32 5525 %v2 = insertelement <8 x i32> %v1, i32 %e2, i32 6526 %v3 = insertelement <8 x i32> %v2, i32 %e3, i32 7527 ret <8 x i32> %v3528}529 530define <8 x i32> @add_constant_rhs_8xi32_vector_in3(<8 x i32> %vin, i32 %a, i32 %b, i32 %c, i32 %d) {531; CHECK-LABEL: add_constant_rhs_8xi32_vector_in3:532; CHECK: # %bb.0:533; CHECK-NEXT: addi a0, a0, 23534; CHECK-NEXT: addi a1, a1, 25535; CHECK-NEXT: addi a2, a2, 1536; CHECK-NEXT: addi a3, a3, 2047537; CHECK-NEXT: addi a3, a3, 308538; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma539; CHECK-NEXT: vmv.s.x v8, a0540; CHECK-NEXT: vmv.s.x v10, a1541; CHECK-NEXT: vslideup.vi v8, v10, 2542; CHECK-NEXT: vmv.s.x v10, a2543; CHECK-NEXT: vsetivli zero, 5, e32, m2, tu, ma544; CHECK-NEXT: vslideup.vi v8, v10, 4545; CHECK-NEXT: vmv.s.x v10, a3546; CHECK-NEXT: vsetivli zero, 7, e32, m2, tu, ma547; CHECK-NEXT: vslideup.vi v8, v10, 6548; CHECK-NEXT: ret549 %e0 = add i32 %a, 23550 %e1 = add i32 %b, 25551 %e2 = add i32 %c, 1552 %e3 = add i32 %d, 2355553 %v0 = insertelement <8 x i32> %vin, i32 %e0, i32 0554 %v1 = insertelement <8 x i32> %v0, i32 %e1, i32 2555 %v2 = insertelement <8 x i32> %v1, i32 %e2, i32 4556 %v3 = insertelement <8 x i32> %v2, i32 %e3, i32 6557 ret <8 x i32> %v3558}559 560define <8 x i32> @add_constant_rhs_8xi32_partial(<8 x i32> %vin, i32 %a, i32 %b, i32 %c, i32 %d) {561; CHECK-LABEL: add_constant_rhs_8xi32_partial:562; CHECK: # %bb.0:563; CHECK-NEXT: vsetivli zero, 5, e32, m2, tu, ma564; CHECK-NEXT: vmv.s.x v10, a0565; CHECK-NEXT: vmv.s.x v12, a1566; CHECK-NEXT: vslideup.vi v8, v10, 4567; CHECK-NEXT: vmv.s.x v10, a2568; CHECK-NEXT: lui a0, %hi(.LCPI19_0)569; CHECK-NEXT: addi a0, a0, %lo(.LCPI19_0)570; CHECK-NEXT: vsetivli zero, 6, e32, m2, tu, ma571; CHECK-NEXT: vslideup.vi v8, v12, 5572; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma573; CHECK-NEXT: vle32.v v12, (a0)574; CHECK-NEXT: vsetivli zero, 7, e32, m2, tu, ma575; CHECK-NEXT: vslideup.vi v8, v10, 6576; CHECK-NEXT: vmv.s.x v10, a3577; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma578; CHECK-NEXT: vslideup.vi v8, v10, 7579; CHECK-NEXT: vadd.vv v8, v8, v12580; CHECK-NEXT: ret581 %vadd = add <8 x i32> %vin, <i32 1, i32 2, i32 3, i32 5, i32 poison, i32 poison, i32 poison, i32 poison>582 %e0 = add i32 %a, 23583 %e1 = add i32 %b, 25584 %e2 = add i32 %c, 1585 %e3 = add i32 %d, 2355586 %v0 = insertelement <8 x i32> %vadd, i32 %e0, i32 4587 %v1 = insertelement <8 x i32> %v0, i32 %e1, i32 5588 %v2 = insertelement <8 x i32> %v1, i32 %e2, i32 6589 %v3 = insertelement <8 x i32> %v2, i32 %e3, i32 7590 ret <8 x i32> %v3591}592 593; Here we can not pull the ashr through into the vector domain due to594; the truncate semantics of the build_vector. Doing so would595; truncate before the ashr instead of after it, so if %a or %b596; is e.g. UINT32_MAX+1 we get different result.597define <2 x i32> @build_vec_of_trunc_op(i64 %a, i64 %b) {598; RV32-LABEL: build_vec_of_trunc_op:599; RV32: # %bb.0: # %entry600; RV32-NEXT: slli a1, a1, 31601; RV32-NEXT: srli a0, a0, 1602; RV32-NEXT: slli a3, a3, 31603; RV32-NEXT: srli a2, a2, 1604; RV32-NEXT: or a0, a0, a1605; RV32-NEXT: or a2, a2, a3606; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma607; RV32-NEXT: vmv.v.x v8, a0608; RV32-NEXT: vslide1down.vx v8, v8, a2609; RV32-NEXT: ret610;611; RV64-LABEL: build_vec_of_trunc_op:612; RV64: # %bb.0: # %entry613; RV64-NEXT: srli a0, a0, 1614; RV64-NEXT: srli a1, a1, 1615; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma616; RV64-NEXT: vmv.v.x v8, a0617; RV64-NEXT: vslide1down.vx v8, v8, a1618; RV64-NEXT: ret619entry:620 %conv11.i = ashr i64 %a, 1621 %conv11.2 = ashr i64 %b, 1622 %0 = trunc i64 %conv11.i to i32623 %1 = trunc i64 %conv11.2 to i32624 %2 = insertelement <2 x i32> zeroinitializer, i32 %0, i64 0625 %3 = insertelement <2 x i32> %2, i32 %1, i64 1626 ret <2 x i32> %3627}628