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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s4 5define <1 x i8> @vector_compress_v1i8(<1 x i8> %v, <1 x i1> %mask) {6; CHECK-LABEL: vector_compress_v1i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma9; CHECK-NEXT: vcompress.vm v9, v8, v010; CHECK-NEXT: vmv1r.v v8, v911; CHECK-NEXT: ret12 %ret = call <1 x i8> @llvm.experimental.vector.compress.v1i8(<1 x i8> %v, <1 x i1> %mask, <1 x i8> poison)13 ret <1 x i8> %ret14}15 16define <1 x i8> @vector_compress_v1i8_passthru(<1 x i8> %passthru, <1 x i8> %v, <1 x i1> %mask) {17; CHECK-LABEL: vector_compress_v1i8_passthru:18; CHECK: # %bb.0:19; CHECK-NEXT: vsetivli zero, 1, e8, mf8, tu, ma20; CHECK-NEXT: vcompress.vm v8, v9, v021; CHECK-NEXT: ret22 %ret = call <1 x i8> @llvm.experimental.vector.compress.v1i8(<1 x i8> %v, <1 x i1> %mask, <1 x i8> %passthru)23 ret <1 x i8> %ret24}25 26define <2 x i8> @vector_compress_v2i8(<2 x i8> %v, <2 x i1> %mask) {27; CHECK-LABEL: vector_compress_v2i8:28; CHECK: # %bb.0:29; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma30; CHECK-NEXT: vcompress.vm v9, v8, v031; CHECK-NEXT: vmv1r.v v8, v932; CHECK-NEXT: ret33 %ret = call <2 x i8> @llvm.experimental.vector.compress.v2i8(<2 x i8> %v, <2 x i1> %mask, <2 x i8> poison)34 ret <2 x i8> %ret35}36 37define <2 x i8> @vector_compress_v2i8_passthru(<2 x i8> %passthru, <2 x i8> %v, <2 x i1> %mask) {38; CHECK-LABEL: vector_compress_v2i8_passthru:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetivli zero, 2, e8, mf8, tu, ma41; CHECK-NEXT: vcompress.vm v8, v9, v042; CHECK-NEXT: ret43 %ret = call <2 x i8> @llvm.experimental.vector.compress.v2i8(<2 x i8> %v, <2 x i1> %mask, <2 x i8> %passthru)44 ret <2 x i8> %ret45}46 47define <4 x i8> @vector_compress_v4i8(<4 x i8> %v, <4 x i1> %mask) {48; CHECK-LABEL: vector_compress_v4i8:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma51; CHECK-NEXT: vcompress.vm v9, v8, v052; CHECK-NEXT: vmv1r.v v8, v953; CHECK-NEXT: ret54 %ret = call <4 x i8> @llvm.experimental.vector.compress.v4i8(<4 x i8> %v, <4 x i1> %mask, <4 x i8> poison)55 ret <4 x i8> %ret56}57 58define <4 x i8> @vector_compress_v4i8_passthru(<4 x i8> %passthru, <4 x i8> %v, <4 x i1> %mask) {59; CHECK-LABEL: vector_compress_v4i8_passthru:60; CHECK: # %bb.0:61; CHECK-NEXT: vsetivli zero, 4, e8, mf4, tu, ma62; CHECK-NEXT: vcompress.vm v8, v9, v063; CHECK-NEXT: ret64 %ret = call <4 x i8> @llvm.experimental.vector.compress.v4i8(<4 x i8> %v, <4 x i1> %mask, <4 x i8> %passthru)65 ret <4 x i8> %ret66}67 68define <8 x i8> @vector_compress_v8i8(<8 x i8> %v, <8 x i1> %mask) {69; CHECK-LABEL: vector_compress_v8i8:70; CHECK: # %bb.0:71; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma72; CHECK-NEXT: vcompress.vm v9, v8, v073; CHECK-NEXT: vmv1r.v v8, v974; CHECK-NEXT: ret75 %ret = call <8 x i8> @llvm.experimental.vector.compress.v8i8(<8 x i8> %v, <8 x i1> %mask, <8 x i8> poison)76 ret <8 x i8> %ret77}78 79define <8 x i8> @vector_compress_v8i8_passthru(<8 x i8> %passthru, <8 x i8> %v, <8 x i1> %mask) {80; CHECK-LABEL: vector_compress_v8i8_passthru:81; CHECK: # %bb.0:82; CHECK-NEXT: vsetivli zero, 8, e8, mf2, tu, ma83; CHECK-NEXT: vcompress.vm v8, v9, v084; CHECK-NEXT: ret85 %ret = call <8 x i8> @llvm.experimental.vector.compress.v8i8(<8 x i8> %v, <8 x i1> %mask, <8 x i8> %passthru)86 ret <8 x i8> %ret87}88 89define <1 x i16> @vector_compress_v1i16(<1 x i16> %v, <1 x i1> %mask) {90; CHECK-LABEL: vector_compress_v1i16:91; CHECK: # %bb.0:92; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma93; CHECK-NEXT: vcompress.vm v9, v8, v094; CHECK-NEXT: vmv1r.v v8, v995; CHECK-NEXT: ret96 %ret = call <1 x i16> @llvm.experimental.vector.compress.v1i16(<1 x i16> %v, <1 x i1> %mask, <1 x i16> poison)97 ret <1 x i16> %ret98}99 100define <1 x i16> @vector_compress_v1i16_passthru(<1 x i16> %passthru, <1 x i16> %v, <1 x i1> %mask) {101; CHECK-LABEL: vector_compress_v1i16_passthru:102; CHECK: # %bb.0:103; CHECK-NEXT: vsetivli zero, 1, e16, mf4, tu, ma104; CHECK-NEXT: vcompress.vm v8, v9, v0105; CHECK-NEXT: ret106 %ret = call <1 x i16> @llvm.experimental.vector.compress.v1i16(<1 x i16> %v, <1 x i1> %mask, <1 x i16> %passthru)107 ret <1 x i16> %ret108}109 110define <2 x i16> @vector_compress_v2i16(<2 x i16> %v, <2 x i1> %mask) {111; CHECK-LABEL: vector_compress_v2i16:112; CHECK: # %bb.0:113; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma114; CHECK-NEXT: vcompress.vm v9, v8, v0115; CHECK-NEXT: vmv1r.v v8, v9116; CHECK-NEXT: ret117 %ret = call <2 x i16> @llvm.experimental.vector.compress.v2i16(<2 x i16> %v, <2 x i1> %mask, <2 x i16> poison)118 ret <2 x i16> %ret119}120 121define <2 x i16> @vector_compress_v2i16_passthru(<2 x i16> %passthru, <2 x i16> %v, <2 x i1> %mask) {122; CHECK-LABEL: vector_compress_v2i16_passthru:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetivli zero, 2, e16, mf4, tu, ma125; CHECK-NEXT: vcompress.vm v8, v9, v0126; CHECK-NEXT: ret127 %ret = call <2 x i16> @llvm.experimental.vector.compress.v2i16(<2 x i16> %v, <2 x i1> %mask, <2 x i16> %passthru)128 ret <2 x i16> %ret129}130 131define <4 x i16> @vector_compress_v4i16(<4 x i16> %v, <4 x i1> %mask) {132; CHECK-LABEL: vector_compress_v4i16:133; CHECK: # %bb.0:134; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma135; CHECK-NEXT: vcompress.vm v9, v8, v0136; CHECK-NEXT: vmv1r.v v8, v9137; CHECK-NEXT: ret138 %ret = call <4 x i16> @llvm.experimental.vector.compress.v4i16(<4 x i16> %v, <4 x i1> %mask, <4 x i16> poison)139 ret <4 x i16> %ret140}141 142define <4 x i16> @vector_compress_v4i16_passthru(<4 x i16> %passthru, <4 x i16> %v, <4 x i1> %mask) {143; CHECK-LABEL: vector_compress_v4i16_passthru:144; CHECK: # %bb.0:145; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, ma146; CHECK-NEXT: vcompress.vm v8, v9, v0147; CHECK-NEXT: ret148 %ret = call <4 x i16> @llvm.experimental.vector.compress.v4i16(<4 x i16> %v, <4 x i1> %mask, <4 x i16> %passthru)149 ret <4 x i16> %ret150}151 152define <8 x i16> @vector_compress_v8i16(<8 x i16> %v, <8 x i1> %mask) {153; CHECK-LABEL: vector_compress_v8i16:154; CHECK: # %bb.0:155; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma156; CHECK-NEXT: vcompress.vm v9, v8, v0157; CHECK-NEXT: vmv.v.v v8, v9158; CHECK-NEXT: ret159 %ret = call <8 x i16> @llvm.experimental.vector.compress.v8i16(<8 x i16> %v, <8 x i1> %mask, <8 x i16> poison)160 ret <8 x i16> %ret161}162 163define <8 x i16> @vector_compress_v8i16_passthru(<8 x i16> %passthru, <8 x i16> %v, <8 x i1> %mask) {164; CHECK-LABEL: vector_compress_v8i16_passthru:165; CHECK: # %bb.0:166; CHECK-NEXT: vsetivli zero, 8, e16, m1, tu, ma167; CHECK-NEXT: vcompress.vm v8, v9, v0168; CHECK-NEXT: ret169 %ret = call <8 x i16> @llvm.experimental.vector.compress.v8i16(<8 x i16> %v, <8 x i1> %mask, <8 x i16> %passthru)170 ret <8 x i16> %ret171}172 173define <1 x i32> @vector_compress_v1i32(<1 x i32> %v, <1 x i1> %mask) {174; CHECK-LABEL: vector_compress_v1i32:175; CHECK: # %bb.0:176; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma177; CHECK-NEXT: vcompress.vm v9, v8, v0178; CHECK-NEXT: vmv1r.v v8, v9179; CHECK-NEXT: ret180 %ret = call <1 x i32> @llvm.experimental.vector.compress.v1i32(<1 x i32> %v, <1 x i1> %mask, <1 x i32> poison)181 ret <1 x i32> %ret182}183 184define <1 x i32> @vector_compress_v1i32_passthru(<1 x i32> %passthru, <1 x i32> %v, <1 x i1> %mask) {185; CHECK-LABEL: vector_compress_v1i32_passthru:186; CHECK: # %bb.0:187; CHECK-NEXT: vsetivli zero, 1, e32, mf2, tu, ma188; CHECK-NEXT: vcompress.vm v8, v9, v0189; CHECK-NEXT: ret190 %ret = call <1 x i32> @llvm.experimental.vector.compress.v1i32(<1 x i32> %v, <1 x i1> %mask, <1 x i32> %passthru)191 ret <1 x i32> %ret192}193 194define <2 x i32> @vector_compress_v2i32(<2 x i32> %v, <2 x i1> %mask) {195; CHECK-LABEL: vector_compress_v2i32:196; CHECK: # %bb.0:197; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma198; CHECK-NEXT: vcompress.vm v9, v8, v0199; CHECK-NEXT: vmv1r.v v8, v9200; CHECK-NEXT: ret201 %ret = call <2 x i32> @llvm.experimental.vector.compress.v2i32(<2 x i32> %v, <2 x i1> %mask, <2 x i32> poison)202 ret <2 x i32> %ret203}204 205define <2 x i32> @vector_compress_v2i32_passthru(<2 x i32> %passthru, <2 x i32> %v, <2 x i1> %mask) {206; CHECK-LABEL: vector_compress_v2i32_passthru:207; CHECK: # %bb.0:208; CHECK-NEXT: vsetivli zero, 2, e32, mf2, tu, ma209; CHECK-NEXT: vcompress.vm v8, v9, v0210; CHECK-NEXT: ret211 %ret = call <2 x i32> @llvm.experimental.vector.compress.v2i32(<2 x i32> %v, <2 x i1> %mask, <2 x i32> %passthru)212 ret <2 x i32> %ret213}214 215define <4 x i32> @vector_compress_v4i32(<4 x i32> %v, <4 x i1> %mask) {216; CHECK-LABEL: vector_compress_v4i32:217; CHECK: # %bb.0:218; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma219; CHECK-NEXT: vcompress.vm v9, v8, v0220; CHECK-NEXT: vmv.v.v v8, v9221; CHECK-NEXT: ret222 %ret = call <4 x i32> @llvm.experimental.vector.compress.v4i32(<4 x i32> %v, <4 x i1> %mask, <4 x i32> poison)223 ret <4 x i32> %ret224}225 226define <4 x i32> @vector_compress_v4i32_passthru(<4 x i32> %passthru, <4 x i32> %v, <4 x i1> %mask) {227; CHECK-LABEL: vector_compress_v4i32_passthru:228; CHECK: # %bb.0:229; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma230; CHECK-NEXT: vcompress.vm v8, v9, v0231; CHECK-NEXT: ret232 %ret = call <4 x i32> @llvm.experimental.vector.compress.v4i32(<4 x i32> %v, <4 x i1> %mask, <4 x i32> %passthru)233 ret <4 x i32> %ret234}235 236define <8 x i32> @vector_compress_v8i32(<8 x i32> %v, <8 x i1> %mask) {237; CHECK-LABEL: vector_compress_v8i32:238; CHECK: # %bb.0:239; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma240; CHECK-NEXT: vcompress.vm v10, v8, v0241; CHECK-NEXT: vmv.v.v v8, v10242; CHECK-NEXT: ret243 %ret = call <8 x i32> @llvm.experimental.vector.compress.v8i32(<8 x i32> %v, <8 x i1> %mask, <8 x i32> poison)244 ret <8 x i32> %ret245}246 247define <8 x i32> @vector_compress_v8i32_passthru(<8 x i32> %passthru, <8 x i32> %v, <8 x i1> %mask) {248; CHECK-LABEL: vector_compress_v8i32_passthru:249; CHECK: # %bb.0:250; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, ma251; CHECK-NEXT: vcompress.vm v8, v10, v0252; CHECK-NEXT: ret253 %ret = call <8 x i32> @llvm.experimental.vector.compress.v8i32(<8 x i32> %v, <8 x i1> %mask, <8 x i32> %passthru)254 ret <8 x i32> %ret255}256 257define <1 x i64> @vector_compress_v1i64(<1 x i64> %v, <1 x i1> %mask) {258; CHECK-LABEL: vector_compress_v1i64:259; CHECK: # %bb.0:260; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma261; CHECK-NEXT: vcompress.vm v9, v8, v0262; CHECK-NEXT: vmv.v.v v8, v9263; CHECK-NEXT: ret264 %ret = call <1 x i64> @llvm.experimental.vector.compress.v1i64(<1 x i64> %v, <1 x i1> %mask, <1 x i64> poison)265 ret <1 x i64> %ret266}267 268define <1 x i64> @vector_compress_v1i64_passthru(<1 x i64> %passthru, <1 x i64> %v, <1 x i1> %mask) {269; CHECK-LABEL: vector_compress_v1i64_passthru:270; CHECK: # %bb.0:271; CHECK-NEXT: vsetivli zero, 1, e64, m1, tu, ma272; CHECK-NEXT: vcompress.vm v8, v9, v0273; CHECK-NEXT: ret274 %ret = call <1 x i64> @llvm.experimental.vector.compress.v1i64(<1 x i64> %v, <1 x i1> %mask, <1 x i64> %passthru)275 ret <1 x i64> %ret276}277 278define <2 x i64> @vector_compress_v2i64(<2 x i64> %v, <2 x i1> %mask) {279; CHECK-LABEL: vector_compress_v2i64:280; CHECK: # %bb.0:281; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma282; CHECK-NEXT: vcompress.vm v9, v8, v0283; CHECK-NEXT: vmv.v.v v8, v9284; CHECK-NEXT: ret285 %ret = call <2 x i64> @llvm.experimental.vector.compress.v2i64(<2 x i64> %v, <2 x i1> %mask, <2 x i64> poison)286 ret <2 x i64> %ret287}288 289define <2 x i64> @vector_compress_v2i64_passthru(<2 x i64> %passthru, <2 x i64> %v, <2 x i1> %mask) {290; CHECK-LABEL: vector_compress_v2i64_passthru:291; CHECK: # %bb.0:292; CHECK-NEXT: vsetivli zero, 2, e64, m1, tu, ma293; CHECK-NEXT: vcompress.vm v8, v9, v0294; CHECK-NEXT: ret295 %ret = call <2 x i64> @llvm.experimental.vector.compress.v2i64(<2 x i64> %v, <2 x i1> %mask, <2 x i64> %passthru)296 ret <2 x i64> %ret297}298 299define <4 x i64> @vector_compress_v4i64(<4 x i64> %v, <4 x i1> %mask) {300; CHECK-LABEL: vector_compress_v4i64:301; CHECK: # %bb.0:302; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma303; CHECK-NEXT: vcompress.vm v10, v8, v0304; CHECK-NEXT: vmv.v.v v8, v10305; CHECK-NEXT: ret306 %ret = call <4 x i64> @llvm.experimental.vector.compress.v4i64(<4 x i64> %v, <4 x i1> %mask, <4 x i64> poison)307 ret <4 x i64> %ret308}309 310define <4 x i64> @vector_compress_v4i64_passthru(<4 x i64> %passthru, <4 x i64> %v, <4 x i1> %mask) {311; CHECK-LABEL: vector_compress_v4i64_passthru:312; CHECK: # %bb.0:313; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma314; CHECK-NEXT: vcompress.vm v8, v10, v0315; CHECK-NEXT: ret316 %ret = call <4 x i64> @llvm.experimental.vector.compress.v4i64(<4 x i64> %v, <4 x i1> %mask, <4 x i64> %passthru)317 ret <4 x i64> %ret318}319 320define <8 x i64> @vector_compress_v8i64(<8 x i64> %v, <8 x i1> %mask) {321; CHECK-LABEL: vector_compress_v8i64:322; CHECK: # %bb.0:323; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma324; CHECK-NEXT: vcompress.vm v12, v8, v0325; CHECK-NEXT: vmv.v.v v8, v12326; CHECK-NEXT: ret327 %ret = call <8 x i64> @llvm.experimental.vector.compress.v8i64(<8 x i64> %v, <8 x i1> %mask, <8 x i64> poison)328 ret <8 x i64> %ret329}330 331define <8 x i64> @vector_compress_v8i64_passthru(<8 x i64> %passthru, <8 x i64> %v, <8 x i1> %mask) {332; CHECK-LABEL: vector_compress_v8i64_passthru:333; CHECK: # %bb.0:334; CHECK-NEXT: vsetivli zero, 8, e64, m4, tu, ma335; CHECK-NEXT: vcompress.vm v8, v12, v0336; CHECK-NEXT: ret337 %ret = call <8 x i64> @llvm.experimental.vector.compress.v8i64(<8 x i64> %v, <8 x i1> %mask, <8 x i64> %passthru)338 ret <8 x i64> %ret339}340