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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV323; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV644 5define void @compressstore_v1f16(ptr %base, <1 x half> %v, <1 x i1> %mask) {6; RV32-LABEL: compressstore_v1f16:7; RV32: # %bb.0:8; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma9; RV32-NEXT: vcompress.vm v9, v8, v010; RV32-NEXT: vcpop.m a1, v011; RV32-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12; RV32-NEXT: vse16.v v9, (a0)13; RV32-NEXT: ret14;15; RV64-LABEL: compressstore_v1f16:16; RV64: # %bb.0:17; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma18; RV64-NEXT: vcompress.vm v9, v8, v019; RV64-NEXT: vcpop.m a1, v020; RV64-NEXT: vsetvli zero, a1, e16, mf4, ta, ma21; RV64-NEXT: vse16.v v9, (a0)22; RV64-NEXT: ret23 call void @llvm.masked.compressstore.v1f16(<1 x half> %v, ptr align 2 %base, <1 x i1> %mask)24 ret void25}26 27define void @compressstore_v2f16(ptr %base, <2 x half> %v, <2 x i1> %mask) {28; RV32-LABEL: compressstore_v2f16:29; RV32: # %bb.0:30; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma31; RV32-NEXT: vcompress.vm v9, v8, v032; RV32-NEXT: vcpop.m a1, v033; RV32-NEXT: vsetvli zero, a1, e16, mf4, ta, ma34; RV32-NEXT: vse16.v v9, (a0)35; RV32-NEXT: ret36;37; RV64-LABEL: compressstore_v2f16:38; RV64: # %bb.0:39; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma40; RV64-NEXT: vcompress.vm v9, v8, v041; RV64-NEXT: vcpop.m a1, v042; RV64-NEXT: vsetvli zero, a1, e16, mf4, ta, ma43; RV64-NEXT: vse16.v v9, (a0)44; RV64-NEXT: ret45 call void @llvm.masked.compressstore.v2f16(<2 x half> %v, ptr align 2 %base, <2 x i1> %mask)46 ret void47}48 49define void @compressstore_v4f16(ptr %base, <4 x half> %v, <4 x i1> %mask) {50; RV32-LABEL: compressstore_v4f16:51; RV32: # %bb.0:52; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma53; RV32-NEXT: vcompress.vm v9, v8, v054; RV32-NEXT: vcpop.m a1, v055; RV32-NEXT: vsetvli zero, a1, e16, mf2, ta, ma56; RV32-NEXT: vse16.v v9, (a0)57; RV32-NEXT: ret58;59; RV64-LABEL: compressstore_v4f16:60; RV64: # %bb.0:61; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma62; RV64-NEXT: vcompress.vm v9, v8, v063; RV64-NEXT: vcpop.m a1, v064; RV64-NEXT: vsetvli zero, a1, e16, mf2, ta, ma65; RV64-NEXT: vse16.v v9, (a0)66; RV64-NEXT: ret67 call void @llvm.masked.compressstore.v4f16(<4 x half> %v, ptr align 2 %base, <4 x i1> %mask)68 ret void69}70 71define void @compressstore_v8f16(ptr %base, <8 x half> %v, <8 x i1> %mask) {72; RV32-LABEL: compressstore_v8f16:73; RV32: # %bb.0:74; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma75; RV32-NEXT: vcompress.vm v9, v8, v076; RV32-NEXT: vcpop.m a1, v077; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma78; RV32-NEXT: vse16.v v9, (a0)79; RV32-NEXT: ret80;81; RV64-LABEL: compressstore_v8f16:82; RV64: # %bb.0:83; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, ma84; RV64-NEXT: vcompress.vm v9, v8, v085; RV64-NEXT: vcpop.m a1, v086; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, ma87; RV64-NEXT: vse16.v v9, (a0)88; RV64-NEXT: ret89 call void @llvm.masked.compressstore.v8f16(<8 x half> %v, ptr align 2 %base, <8 x i1> %mask)90 ret void91}92 93define void @compressstore_v1f32(ptr %base, <1 x float> %v, <1 x i1> %mask) {94; RV32-LABEL: compressstore_v1f32:95; RV32: # %bb.0:96; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma97; RV32-NEXT: vcompress.vm v9, v8, v098; RV32-NEXT: vcpop.m a1, v099; RV32-NEXT: vsetvli zero, a1, e32, mf2, ta, ma100; RV32-NEXT: vse32.v v9, (a0)101; RV32-NEXT: ret102;103; RV64-LABEL: compressstore_v1f32:104; RV64: # %bb.0:105; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma106; RV64-NEXT: vcompress.vm v9, v8, v0107; RV64-NEXT: vcpop.m a1, v0108; RV64-NEXT: vsetvli zero, a1, e32, mf2, ta, ma109; RV64-NEXT: vse32.v v9, (a0)110; RV64-NEXT: ret111 call void @llvm.masked.compressstore.v1f32(<1 x float> %v, ptr align 4 %base, <1 x i1> %mask)112 ret void113}114 115define void @compressstore_v2f32(ptr %base, <2 x float> %v, <2 x i1> %mask) {116; RV32-LABEL: compressstore_v2f32:117; RV32: # %bb.0:118; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma119; RV32-NEXT: vcompress.vm v9, v8, v0120; RV32-NEXT: vcpop.m a1, v0121; RV32-NEXT: vsetvli zero, a1, e32, mf2, ta, ma122; RV32-NEXT: vse32.v v9, (a0)123; RV32-NEXT: ret124;125; RV64-LABEL: compressstore_v2f32:126; RV64: # %bb.0:127; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma128; RV64-NEXT: vcompress.vm v9, v8, v0129; RV64-NEXT: vcpop.m a1, v0130; RV64-NEXT: vsetvli zero, a1, e32, mf2, ta, ma131; RV64-NEXT: vse32.v v9, (a0)132; RV64-NEXT: ret133 call void @llvm.masked.compressstore.v2f32(<2 x float> %v, ptr align 4 %base, <2 x i1> %mask)134 ret void135}136 137define void @compressstore_v4f32(ptr %base, <4 x float> %v, <4 x i1> %mask) {138; RV32-LABEL: compressstore_v4f32:139; RV32: # %bb.0:140; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma141; RV32-NEXT: vcompress.vm v9, v8, v0142; RV32-NEXT: vcpop.m a1, v0143; RV32-NEXT: vsetvli zero, a1, e32, m1, ta, ma144; RV32-NEXT: vse32.v v9, (a0)145; RV32-NEXT: ret146;147; RV64-LABEL: compressstore_v4f32:148; RV64: # %bb.0:149; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma150; RV64-NEXT: vcompress.vm v9, v8, v0151; RV64-NEXT: vcpop.m a1, v0152; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma153; RV64-NEXT: vse32.v v9, (a0)154; RV64-NEXT: ret155 call void @llvm.masked.compressstore.v4f32(<4 x float> %v, ptr align 4 %base, <4 x i1> %mask)156 ret void157}158 159define void @compressstore_v8f32(ptr %base, <8 x float> %v, <8 x i1> %mask) {160; RV32-LABEL: compressstore_v8f32:161; RV32: # %bb.0:162; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma163; RV32-NEXT: vcompress.vm v10, v8, v0164; RV32-NEXT: vcpop.m a1, v0165; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma166; RV32-NEXT: vse32.v v10, (a0)167; RV32-NEXT: ret168;169; RV64-LABEL: compressstore_v8f32:170; RV64: # %bb.0:171; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma172; RV64-NEXT: vcompress.vm v10, v8, v0173; RV64-NEXT: vcpop.m a1, v0174; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma175; RV64-NEXT: vse32.v v10, (a0)176; RV64-NEXT: ret177 call void @llvm.masked.compressstore.v8f32(<8 x float> %v, ptr align 4 %base, <8 x i1> %mask)178 ret void179}180 181define void @compressstore_v1f64(ptr %base, <1 x double> %v, <1 x i1> %mask) {182; RV32-LABEL: compressstore_v1f64:183; RV32: # %bb.0:184; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma185; RV32-NEXT: vcompress.vm v9, v8, v0186; RV32-NEXT: vcpop.m a1, v0187; RV32-NEXT: vsetvli zero, a1, e64, m1, ta, ma188; RV32-NEXT: vse64.v v9, (a0)189; RV32-NEXT: ret190;191; RV64-LABEL: compressstore_v1f64:192; RV64: # %bb.0:193; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma194; RV64-NEXT: vcompress.vm v9, v8, v0195; RV64-NEXT: vcpop.m a1, v0196; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma197; RV64-NEXT: vse64.v v9, (a0)198; RV64-NEXT: ret199 call void @llvm.masked.compressstore.v1f64(<1 x double> %v, ptr align 8 %base, <1 x i1> %mask)200 ret void201}202 203define void @compressstore_v2f64(ptr %base, <2 x double> %v, <2 x i1> %mask) {204; RV32-LABEL: compressstore_v2f64:205; RV32: # %bb.0:206; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma207; RV32-NEXT: vcompress.vm v9, v8, v0208; RV32-NEXT: vcpop.m a1, v0209; RV32-NEXT: vsetvli zero, a1, e64, m1, ta, ma210; RV32-NEXT: vse64.v v9, (a0)211; RV32-NEXT: ret212;213; RV64-LABEL: compressstore_v2f64:214; RV64: # %bb.0:215; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma216; RV64-NEXT: vcompress.vm v9, v8, v0217; RV64-NEXT: vcpop.m a1, v0218; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma219; RV64-NEXT: vse64.v v9, (a0)220; RV64-NEXT: ret221 call void @llvm.masked.compressstore.v2f64(<2 x double> %v, ptr align 8 %base, <2 x i1> %mask)222 ret void223}224 225define void @compressstore_v4f64(ptr %base, <4 x double> %v, <4 x i1> %mask) {226; RV32-LABEL: compressstore_v4f64:227; RV32: # %bb.0:228; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma229; RV32-NEXT: vcompress.vm v10, v8, v0230; RV32-NEXT: vcpop.m a1, v0231; RV32-NEXT: vsetvli zero, a1, e64, m2, ta, ma232; RV32-NEXT: vse64.v v10, (a0)233; RV32-NEXT: ret234;235; RV64-LABEL: compressstore_v4f64:236; RV64: # %bb.0:237; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma238; RV64-NEXT: vcompress.vm v10, v8, v0239; RV64-NEXT: vcpop.m a1, v0240; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma241; RV64-NEXT: vse64.v v10, (a0)242; RV64-NEXT: ret243 call void @llvm.masked.compressstore.v4f64(<4 x double> %v, ptr align 8 %base, <4 x i1> %mask)244 ret void245}246 247define void @compressstore_v8f64(ptr %base, <8 x double> %v, <8 x i1> %mask) {248; RV32-LABEL: compressstore_v8f64:249; RV32: # %bb.0:250; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma251; RV32-NEXT: vcompress.vm v12, v8, v0252; RV32-NEXT: vcpop.m a1, v0253; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma254; RV32-NEXT: vse64.v v12, (a0)255; RV32-NEXT: ret256;257; RV64-LABEL: compressstore_v8f64:258; RV64: # %bb.0:259; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma260; RV64-NEXT: vcompress.vm v12, v8, v0261; RV64-NEXT: vcpop.m a1, v0262; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma263; RV64-NEXT: vse64.v v12, (a0)264; RV64-NEXT: ret265 call void @llvm.masked.compressstore.v8f64(<8 x double> %v, ptr align 8 %base, <8 x i1> %mask)266 ret void267}268