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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV646 7define <2 x i8> @vp_ctlz_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vp_ctlz_v2i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t12; CHECK-NEXT: li a0, 8513; CHECK-NEXT: vor.vv v8, v8, v9, v0.t14; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t15; CHECK-NEXT: vor.vv v8, v8, v9, v0.t16; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t17; CHECK-NEXT: vor.vv v8, v8, v9, v0.t18; CHECK-NEXT: vnot.v v8, v8, v0.t19; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t20; CHECK-NEXT: vand.vx v9, v9, a0, v0.t21; CHECK-NEXT: li a0, 5122; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t23; CHECK-NEXT: vand.vx v9, v8, a0, v0.t24; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t25; CHECK-NEXT: vand.vx v8, v8, a0, v0.t26; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t27; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t28; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t29; CHECK-NEXT: vand.vi v8, v8, 15, v0.t30; CHECK-NEXT: ret31 %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl)32 ret <2 x i8> %v33}34 35define <2 x i8> @vp_ctlz_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {36; CHECK-LABEL: vp_ctlz_v2i8_unmasked:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma39; CHECK-NEXT: vsrl.vi v9, v8, 140; CHECK-NEXT: li a0, 8541; CHECK-NEXT: vor.vv v8, v8, v942; CHECK-NEXT: vsrl.vi v9, v8, 243; CHECK-NEXT: vor.vv v8, v8, v944; CHECK-NEXT: vsrl.vi v9, v8, 445; CHECK-NEXT: vor.vv v8, v8, v946; CHECK-NEXT: vnot.v v8, v847; CHECK-NEXT: vsrl.vi v9, v8, 148; CHECK-NEXT: vand.vx v9, v9, a049; CHECK-NEXT: li a0, 5150; CHECK-NEXT: vsub.vv v8, v8, v951; CHECK-NEXT: vand.vx v9, v8, a052; CHECK-NEXT: vsrl.vi v8, v8, 253; CHECK-NEXT: vand.vx v8, v8, a054; CHECK-NEXT: vadd.vv v8, v9, v855; CHECK-NEXT: vsrl.vi v9, v8, 456; CHECK-NEXT: vadd.vv v8, v8, v957; CHECK-NEXT: vand.vi v8, v8, 1558; CHECK-NEXT: ret59 %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl)60 ret <2 x i8> %v61}62 63define <4 x i8> @vp_ctlz_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {64; CHECK-LABEL: vp_ctlz_v4i8:65; CHECK: # %bb.0:66; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma67; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t68; CHECK-NEXT: li a0, 8569; CHECK-NEXT: vor.vv v8, v8, v9, v0.t70; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t71; CHECK-NEXT: vor.vv v8, v8, v9, v0.t72; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t73; CHECK-NEXT: vor.vv v8, v8, v9, v0.t74; CHECK-NEXT: vnot.v v8, v8, v0.t75; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t76; CHECK-NEXT: vand.vx v9, v9, a0, v0.t77; CHECK-NEXT: li a0, 5178; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t79; CHECK-NEXT: vand.vx v9, v8, a0, v0.t80; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t81; CHECK-NEXT: vand.vx v8, v8, a0, v0.t82; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t83; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t84; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t85; CHECK-NEXT: vand.vi v8, v8, 15, v0.t86; CHECK-NEXT: ret87 %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl)88 ret <4 x i8> %v89}90 91define <4 x i8> @vp_ctlz_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {92; CHECK-LABEL: vp_ctlz_v4i8_unmasked:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma95; CHECK-NEXT: vsrl.vi v9, v8, 196; CHECK-NEXT: li a0, 8597; CHECK-NEXT: vor.vv v8, v8, v998; CHECK-NEXT: vsrl.vi v9, v8, 299; CHECK-NEXT: vor.vv v8, v8, v9100; CHECK-NEXT: vsrl.vi v9, v8, 4101; CHECK-NEXT: vor.vv v8, v8, v9102; CHECK-NEXT: vnot.v v8, v8103; CHECK-NEXT: vsrl.vi v9, v8, 1104; CHECK-NEXT: vand.vx v9, v9, a0105; CHECK-NEXT: li a0, 51106; CHECK-NEXT: vsub.vv v8, v8, v9107; CHECK-NEXT: vand.vx v9, v8, a0108; CHECK-NEXT: vsrl.vi v8, v8, 2109; CHECK-NEXT: vand.vx v8, v8, a0110; CHECK-NEXT: vadd.vv v8, v9, v8111; CHECK-NEXT: vsrl.vi v9, v8, 4112; CHECK-NEXT: vadd.vv v8, v8, v9113; CHECK-NEXT: vand.vi v8, v8, 15114; CHECK-NEXT: ret115 %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl)116 ret <4 x i8> %v117}118 119define <8 x i8> @vp_ctlz_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {120; CHECK-LABEL: vp_ctlz_v8i8:121; CHECK: # %bb.0:122; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma123; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t124; CHECK-NEXT: li a0, 85125; CHECK-NEXT: vor.vv v8, v8, v9, v0.t126; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t127; CHECK-NEXT: vor.vv v8, v8, v9, v0.t128; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t129; CHECK-NEXT: vor.vv v8, v8, v9, v0.t130; CHECK-NEXT: vnot.v v8, v8, v0.t131; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t132; CHECK-NEXT: vand.vx v9, v9, a0, v0.t133; CHECK-NEXT: li a0, 51134; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t135; CHECK-NEXT: vand.vx v9, v8, a0, v0.t136; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t137; CHECK-NEXT: vand.vx v8, v8, a0, v0.t138; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t139; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t140; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t141; CHECK-NEXT: vand.vi v8, v8, 15, v0.t142; CHECK-NEXT: ret143 %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl)144 ret <8 x i8> %v145}146 147define <8 x i8> @vp_ctlz_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {148; CHECK-LABEL: vp_ctlz_v8i8_unmasked:149; CHECK: # %bb.0:150; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma151; CHECK-NEXT: vsrl.vi v9, v8, 1152; CHECK-NEXT: li a0, 85153; CHECK-NEXT: vor.vv v8, v8, v9154; CHECK-NEXT: vsrl.vi v9, v8, 2155; CHECK-NEXT: vor.vv v8, v8, v9156; CHECK-NEXT: vsrl.vi v9, v8, 4157; CHECK-NEXT: vor.vv v8, v8, v9158; CHECK-NEXT: vnot.v v8, v8159; CHECK-NEXT: vsrl.vi v9, v8, 1160; CHECK-NEXT: vand.vx v9, v9, a0161; CHECK-NEXT: li a0, 51162; CHECK-NEXT: vsub.vv v8, v8, v9163; CHECK-NEXT: vand.vx v9, v8, a0164; CHECK-NEXT: vsrl.vi v8, v8, 2165; CHECK-NEXT: vand.vx v8, v8, a0166; CHECK-NEXT: vadd.vv v8, v9, v8167; CHECK-NEXT: vsrl.vi v9, v8, 4168; CHECK-NEXT: vadd.vv v8, v8, v9169; CHECK-NEXT: vand.vi v8, v8, 15170; CHECK-NEXT: ret171 %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl)172 ret <8 x i8> %v173}174 175define <16 x i8> @vp_ctlz_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {176; CHECK-LABEL: vp_ctlz_v16i8:177; CHECK: # %bb.0:178; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma179; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t180; CHECK-NEXT: li a0, 85181; CHECK-NEXT: vor.vv v8, v8, v9, v0.t182; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t183; CHECK-NEXT: vor.vv v8, v8, v9, v0.t184; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t185; CHECK-NEXT: vor.vv v8, v8, v9, v0.t186; CHECK-NEXT: vnot.v v8, v8, v0.t187; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t188; CHECK-NEXT: vand.vx v9, v9, a0, v0.t189; CHECK-NEXT: li a0, 51190; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t191; CHECK-NEXT: vand.vx v9, v8, a0, v0.t192; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t193; CHECK-NEXT: vand.vx v8, v8, a0, v0.t194; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t195; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t196; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t197; CHECK-NEXT: vand.vi v8, v8, 15, v0.t198; CHECK-NEXT: ret199 %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl)200 ret <16 x i8> %v201}202 203define <16 x i8> @vp_ctlz_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {204; CHECK-LABEL: vp_ctlz_v16i8_unmasked:205; CHECK: # %bb.0:206; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma207; CHECK-NEXT: vsrl.vi v9, v8, 1208; CHECK-NEXT: li a0, 85209; CHECK-NEXT: vor.vv v8, v8, v9210; CHECK-NEXT: vsrl.vi v9, v8, 2211; CHECK-NEXT: vor.vv v8, v8, v9212; CHECK-NEXT: vsrl.vi v9, v8, 4213; CHECK-NEXT: vor.vv v8, v8, v9214; CHECK-NEXT: vnot.v v8, v8215; CHECK-NEXT: vsrl.vi v9, v8, 1216; CHECK-NEXT: vand.vx v9, v9, a0217; CHECK-NEXT: li a0, 51218; CHECK-NEXT: vsub.vv v8, v8, v9219; CHECK-NEXT: vand.vx v9, v8, a0220; CHECK-NEXT: vsrl.vi v8, v8, 2221; CHECK-NEXT: vand.vx v8, v8, a0222; CHECK-NEXT: vadd.vv v8, v9, v8223; CHECK-NEXT: vsrl.vi v9, v8, 4224; CHECK-NEXT: vadd.vv v8, v8, v9225; CHECK-NEXT: vand.vi v8, v8, 15226; CHECK-NEXT: ret227 %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl)228 ret <16 x i8> %v229}230 231define <2 x i16> @vp_ctlz_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {232; CHECK-LABEL: vp_ctlz_v2i16:233; CHECK: # %bb.0:234; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma235; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t236; CHECK-NEXT: lui a0, 5237; CHECK-NEXT: vor.vv v8, v8, v9, v0.t238; CHECK-NEXT: addi a0, a0, 1365239; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t240; CHECK-NEXT: vor.vv v8, v8, v9, v0.t241; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t242; CHECK-NEXT: vor.vv v8, v8, v9, v0.t243; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t244; CHECK-NEXT: vor.vv v8, v8, v9, v0.t245; CHECK-NEXT: vnot.v v8, v8, v0.t246; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t247; CHECK-NEXT: vand.vx v9, v9, a0, v0.t248; CHECK-NEXT: lui a0, 3249; CHECK-NEXT: addi a0, a0, 819250; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t251; CHECK-NEXT: vand.vx v9, v8, a0, v0.t252; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t253; CHECK-NEXT: vand.vx v8, v8, a0, v0.t254; CHECK-NEXT: lui a0, 1255; CHECK-NEXT: addi a0, a0, -241256; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t257; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t258; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t259; CHECK-NEXT: vand.vx v8, v8, a0, v0.t260; CHECK-NEXT: li a0, 257261; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t262; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t263; CHECK-NEXT: ret264 %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl)265 ret <2 x i16> %v266}267 268define <2 x i16> @vp_ctlz_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {269; CHECK-LABEL: vp_ctlz_v2i16_unmasked:270; CHECK: # %bb.0:271; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma272; CHECK-NEXT: vsrl.vi v9, v8, 1273; CHECK-NEXT: lui a0, 5274; CHECK-NEXT: vor.vv v8, v8, v9275; CHECK-NEXT: addi a0, a0, 1365276; CHECK-NEXT: vsrl.vi v9, v8, 2277; CHECK-NEXT: vor.vv v8, v8, v9278; CHECK-NEXT: vsrl.vi v9, v8, 4279; CHECK-NEXT: vor.vv v8, v8, v9280; CHECK-NEXT: vsrl.vi v9, v8, 8281; CHECK-NEXT: vor.vv v8, v8, v9282; CHECK-NEXT: vnot.v v8, v8283; CHECK-NEXT: vsrl.vi v9, v8, 1284; CHECK-NEXT: vand.vx v9, v9, a0285; CHECK-NEXT: lui a0, 3286; CHECK-NEXT: addi a0, a0, 819287; CHECK-NEXT: vsub.vv v8, v8, v9288; CHECK-NEXT: vand.vx v9, v8, a0289; CHECK-NEXT: vsrl.vi v8, v8, 2290; CHECK-NEXT: vand.vx v8, v8, a0291; CHECK-NEXT: lui a0, 1292; CHECK-NEXT: addi a0, a0, -241293; CHECK-NEXT: vadd.vv v8, v9, v8294; CHECK-NEXT: vsrl.vi v9, v8, 4295; CHECK-NEXT: vadd.vv v8, v8, v9296; CHECK-NEXT: vand.vx v8, v8, a0297; CHECK-NEXT: li a0, 257298; CHECK-NEXT: vmul.vx v8, v8, a0299; CHECK-NEXT: vsrl.vi v8, v8, 8300; CHECK-NEXT: ret301 %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl)302 ret <2 x i16> %v303}304 305define <4 x i16> @vp_ctlz_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {306; CHECK-LABEL: vp_ctlz_v4i16:307; CHECK: # %bb.0:308; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma309; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t310; CHECK-NEXT: lui a0, 5311; CHECK-NEXT: vor.vv v8, v8, v9, v0.t312; CHECK-NEXT: addi a0, a0, 1365313; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t314; CHECK-NEXT: vor.vv v8, v8, v9, v0.t315; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t316; CHECK-NEXT: vor.vv v8, v8, v9, v0.t317; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t318; CHECK-NEXT: vor.vv v8, v8, v9, v0.t319; CHECK-NEXT: vnot.v v8, v8, v0.t320; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t321; CHECK-NEXT: vand.vx v9, v9, a0, v0.t322; CHECK-NEXT: lui a0, 3323; CHECK-NEXT: addi a0, a0, 819324; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t325; CHECK-NEXT: vand.vx v9, v8, a0, v0.t326; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t327; CHECK-NEXT: vand.vx v8, v8, a0, v0.t328; CHECK-NEXT: lui a0, 1329; CHECK-NEXT: addi a0, a0, -241330; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t331; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t332; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t333; CHECK-NEXT: vand.vx v8, v8, a0, v0.t334; CHECK-NEXT: li a0, 257335; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t336; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t337; CHECK-NEXT: ret338 %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl)339 ret <4 x i16> %v340}341 342define <4 x i16> @vp_ctlz_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {343; CHECK-LABEL: vp_ctlz_v4i16_unmasked:344; CHECK: # %bb.0:345; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma346; CHECK-NEXT: vsrl.vi v9, v8, 1347; CHECK-NEXT: lui a0, 5348; CHECK-NEXT: vor.vv v8, v8, v9349; CHECK-NEXT: addi a0, a0, 1365350; CHECK-NEXT: vsrl.vi v9, v8, 2351; CHECK-NEXT: vor.vv v8, v8, v9352; CHECK-NEXT: vsrl.vi v9, v8, 4353; CHECK-NEXT: vor.vv v8, v8, v9354; CHECK-NEXT: vsrl.vi v9, v8, 8355; CHECK-NEXT: vor.vv v8, v8, v9356; CHECK-NEXT: vnot.v v8, v8357; CHECK-NEXT: vsrl.vi v9, v8, 1358; CHECK-NEXT: vand.vx v9, v9, a0359; CHECK-NEXT: lui a0, 3360; CHECK-NEXT: addi a0, a0, 819361; CHECK-NEXT: vsub.vv v8, v8, v9362; CHECK-NEXT: vand.vx v9, v8, a0363; CHECK-NEXT: vsrl.vi v8, v8, 2364; CHECK-NEXT: vand.vx v8, v8, a0365; CHECK-NEXT: lui a0, 1366; CHECK-NEXT: addi a0, a0, -241367; CHECK-NEXT: vadd.vv v8, v9, v8368; CHECK-NEXT: vsrl.vi v9, v8, 4369; CHECK-NEXT: vadd.vv v8, v8, v9370; CHECK-NEXT: vand.vx v8, v8, a0371; CHECK-NEXT: li a0, 257372; CHECK-NEXT: vmul.vx v8, v8, a0373; CHECK-NEXT: vsrl.vi v8, v8, 8374; CHECK-NEXT: ret375 %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl)376 ret <4 x i16> %v377}378 379define <8 x i16> @vp_ctlz_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {380; CHECK-LABEL: vp_ctlz_v8i16:381; CHECK: # %bb.0:382; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma383; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t384; CHECK-NEXT: lui a0, 5385; CHECK-NEXT: vor.vv v8, v8, v9, v0.t386; CHECK-NEXT: addi a0, a0, 1365387; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t388; CHECK-NEXT: vor.vv v8, v8, v9, v0.t389; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t390; CHECK-NEXT: vor.vv v8, v8, v9, v0.t391; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t392; CHECK-NEXT: vor.vv v8, v8, v9, v0.t393; CHECK-NEXT: vnot.v v8, v8, v0.t394; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t395; CHECK-NEXT: vand.vx v9, v9, a0, v0.t396; CHECK-NEXT: lui a0, 3397; CHECK-NEXT: addi a0, a0, 819398; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t399; CHECK-NEXT: vand.vx v9, v8, a0, v0.t400; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t401; CHECK-NEXT: vand.vx v8, v8, a0, v0.t402; CHECK-NEXT: lui a0, 1403; CHECK-NEXT: addi a0, a0, -241404; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t405; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t406; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t407; CHECK-NEXT: vand.vx v8, v8, a0, v0.t408; CHECK-NEXT: li a0, 257409; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t410; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t411; CHECK-NEXT: ret412 %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl)413 ret <8 x i16> %v414}415 416define <8 x i16> @vp_ctlz_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {417; CHECK-LABEL: vp_ctlz_v8i16_unmasked:418; CHECK: # %bb.0:419; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma420; CHECK-NEXT: vsrl.vi v9, v8, 1421; CHECK-NEXT: lui a0, 5422; CHECK-NEXT: vor.vv v8, v8, v9423; CHECK-NEXT: addi a0, a0, 1365424; CHECK-NEXT: vsrl.vi v9, v8, 2425; CHECK-NEXT: vor.vv v8, v8, v9426; CHECK-NEXT: vsrl.vi v9, v8, 4427; CHECK-NEXT: vor.vv v8, v8, v9428; CHECK-NEXT: vsrl.vi v9, v8, 8429; CHECK-NEXT: vor.vv v8, v8, v9430; CHECK-NEXT: vnot.v v8, v8431; CHECK-NEXT: vsrl.vi v9, v8, 1432; CHECK-NEXT: vand.vx v9, v9, a0433; CHECK-NEXT: lui a0, 3434; CHECK-NEXT: addi a0, a0, 819435; CHECK-NEXT: vsub.vv v8, v8, v9436; CHECK-NEXT: vand.vx v9, v8, a0437; CHECK-NEXT: vsrl.vi v8, v8, 2438; CHECK-NEXT: vand.vx v8, v8, a0439; CHECK-NEXT: lui a0, 1440; CHECK-NEXT: addi a0, a0, -241441; CHECK-NEXT: vadd.vv v8, v9, v8442; CHECK-NEXT: vsrl.vi v9, v8, 4443; CHECK-NEXT: vadd.vv v8, v8, v9444; CHECK-NEXT: vand.vx v8, v8, a0445; CHECK-NEXT: li a0, 257446; CHECK-NEXT: vmul.vx v8, v8, a0447; CHECK-NEXT: vsrl.vi v8, v8, 8448; CHECK-NEXT: ret449 %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl)450 ret <8 x i16> %v451}452 453define <16 x i16> @vp_ctlz_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {454; CHECK-LABEL: vp_ctlz_v16i16:455; CHECK: # %bb.0:456; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma457; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t458; CHECK-NEXT: lui a0, 5459; CHECK-NEXT: vor.vv v8, v8, v10, v0.t460; CHECK-NEXT: addi a0, a0, 1365461; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t462; CHECK-NEXT: vor.vv v8, v8, v10, v0.t463; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t464; CHECK-NEXT: vor.vv v8, v8, v10, v0.t465; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t466; CHECK-NEXT: vor.vv v8, v8, v10, v0.t467; CHECK-NEXT: vnot.v v8, v8, v0.t468; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t469; CHECK-NEXT: vand.vx v10, v10, a0, v0.t470; CHECK-NEXT: lui a0, 3471; CHECK-NEXT: addi a0, a0, 819472; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t473; CHECK-NEXT: vand.vx v10, v8, a0, v0.t474; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t475; CHECK-NEXT: vand.vx v8, v8, a0, v0.t476; CHECK-NEXT: lui a0, 1477; CHECK-NEXT: addi a0, a0, -241478; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t479; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t480; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t481; CHECK-NEXT: vand.vx v8, v8, a0, v0.t482; CHECK-NEXT: li a0, 257483; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t484; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t485; CHECK-NEXT: ret486 %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl)487 ret <16 x i16> %v488}489 490define <16 x i16> @vp_ctlz_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {491; CHECK-LABEL: vp_ctlz_v16i16_unmasked:492; CHECK: # %bb.0:493; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma494; CHECK-NEXT: vsrl.vi v10, v8, 1495; CHECK-NEXT: lui a0, 5496; CHECK-NEXT: vor.vv v8, v8, v10497; CHECK-NEXT: addi a0, a0, 1365498; CHECK-NEXT: vsrl.vi v10, v8, 2499; CHECK-NEXT: vor.vv v8, v8, v10500; CHECK-NEXT: vsrl.vi v10, v8, 4501; CHECK-NEXT: vor.vv v8, v8, v10502; CHECK-NEXT: vsrl.vi v10, v8, 8503; CHECK-NEXT: vor.vv v8, v8, v10504; CHECK-NEXT: vnot.v v8, v8505; CHECK-NEXT: vsrl.vi v10, v8, 1506; CHECK-NEXT: vand.vx v10, v10, a0507; CHECK-NEXT: lui a0, 3508; CHECK-NEXT: addi a0, a0, 819509; CHECK-NEXT: vsub.vv v8, v8, v10510; CHECK-NEXT: vand.vx v10, v8, a0511; CHECK-NEXT: vsrl.vi v8, v8, 2512; CHECK-NEXT: vand.vx v8, v8, a0513; CHECK-NEXT: lui a0, 1514; CHECK-NEXT: addi a0, a0, -241515; CHECK-NEXT: vadd.vv v8, v10, v8516; CHECK-NEXT: vsrl.vi v10, v8, 4517; CHECK-NEXT: vadd.vv v8, v8, v10518; CHECK-NEXT: vand.vx v8, v8, a0519; CHECK-NEXT: li a0, 257520; CHECK-NEXT: vmul.vx v8, v8, a0521; CHECK-NEXT: vsrl.vi v8, v8, 8522; CHECK-NEXT: ret523 %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl)524 ret <16 x i16> %v525}526 527define <2 x i32> @vp_ctlz_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {528; CHECK-LABEL: vp_ctlz_v2i32:529; CHECK: # %bb.0:530; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma531; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t532; CHECK-NEXT: lui a0, 349525533; CHECK-NEXT: vor.vv v8, v8, v9, v0.t534; CHECK-NEXT: addi a0, a0, 1365535; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t536; CHECK-NEXT: vor.vv v8, v8, v9, v0.t537; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t538; CHECK-NEXT: vor.vv v8, v8, v9, v0.t539; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t540; CHECK-NEXT: vor.vv v8, v8, v9, v0.t541; CHECK-NEXT: vsrl.vi v9, v8, 16, v0.t542; CHECK-NEXT: vor.vv v8, v8, v9, v0.t543; CHECK-NEXT: vnot.v v8, v8, v0.t544; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t545; CHECK-NEXT: vand.vx v9, v9, a0, v0.t546; CHECK-NEXT: lui a0, 209715547; CHECK-NEXT: addi a0, a0, 819548; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t549; CHECK-NEXT: vand.vx v9, v8, a0, v0.t550; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t551; CHECK-NEXT: vand.vx v8, v8, a0, v0.t552; CHECK-NEXT: lui a0, 61681553; CHECK-NEXT: addi a0, a0, -241554; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t555; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t556; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t557; CHECK-NEXT: vand.vx v8, v8, a0, v0.t558; CHECK-NEXT: lui a0, 4112559; CHECK-NEXT: addi a0, a0, 257560; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t561; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t562; CHECK-NEXT: ret563 %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl)564 ret <2 x i32> %v565}566 567define <2 x i32> @vp_ctlz_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {568; CHECK-LABEL: vp_ctlz_v2i32_unmasked:569; CHECK: # %bb.0:570; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma571; CHECK-NEXT: vsrl.vi v9, v8, 1572; CHECK-NEXT: lui a0, 349525573; CHECK-NEXT: vor.vv v8, v8, v9574; CHECK-NEXT: addi a0, a0, 1365575; CHECK-NEXT: vsrl.vi v9, v8, 2576; CHECK-NEXT: vor.vv v8, v8, v9577; CHECK-NEXT: vsrl.vi v9, v8, 4578; CHECK-NEXT: vor.vv v8, v8, v9579; CHECK-NEXT: vsrl.vi v9, v8, 8580; CHECK-NEXT: vor.vv v8, v8, v9581; CHECK-NEXT: vsrl.vi v9, v8, 16582; CHECK-NEXT: vor.vv v8, v8, v9583; CHECK-NEXT: vnot.v v8, v8584; CHECK-NEXT: vsrl.vi v9, v8, 1585; CHECK-NEXT: vand.vx v9, v9, a0586; CHECK-NEXT: lui a0, 209715587; CHECK-NEXT: addi a0, a0, 819588; CHECK-NEXT: vsub.vv v8, v8, v9589; CHECK-NEXT: vand.vx v9, v8, a0590; CHECK-NEXT: vsrl.vi v8, v8, 2591; CHECK-NEXT: vand.vx v8, v8, a0592; CHECK-NEXT: lui a0, 61681593; CHECK-NEXT: addi a0, a0, -241594; CHECK-NEXT: vadd.vv v8, v9, v8595; CHECK-NEXT: vsrl.vi v9, v8, 4596; CHECK-NEXT: vadd.vv v8, v8, v9597; CHECK-NEXT: vand.vx v8, v8, a0598; CHECK-NEXT: lui a0, 4112599; CHECK-NEXT: addi a0, a0, 257600; CHECK-NEXT: vmul.vx v8, v8, a0601; CHECK-NEXT: vsrl.vi v8, v8, 24602; CHECK-NEXT: ret603 %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl)604 ret <2 x i32> %v605}606 607define <4 x i32> @vp_ctlz_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {608; CHECK-LABEL: vp_ctlz_v4i32:609; CHECK: # %bb.0:610; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma611; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t612; CHECK-NEXT: lui a0, 349525613; CHECK-NEXT: vor.vv v8, v8, v9, v0.t614; CHECK-NEXT: addi a0, a0, 1365615; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t616; CHECK-NEXT: vor.vv v8, v8, v9, v0.t617; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t618; CHECK-NEXT: vor.vv v8, v8, v9, v0.t619; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t620; CHECK-NEXT: vor.vv v8, v8, v9, v0.t621; CHECK-NEXT: vsrl.vi v9, v8, 16, v0.t622; CHECK-NEXT: vor.vv v8, v8, v9, v0.t623; CHECK-NEXT: vnot.v v8, v8, v0.t624; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t625; CHECK-NEXT: vand.vx v9, v9, a0, v0.t626; CHECK-NEXT: lui a0, 209715627; CHECK-NEXT: addi a0, a0, 819628; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t629; CHECK-NEXT: vand.vx v9, v8, a0, v0.t630; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t631; CHECK-NEXT: vand.vx v8, v8, a0, v0.t632; CHECK-NEXT: lui a0, 61681633; CHECK-NEXT: addi a0, a0, -241634; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t635; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t636; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t637; CHECK-NEXT: vand.vx v8, v8, a0, v0.t638; CHECK-NEXT: lui a0, 4112639; CHECK-NEXT: addi a0, a0, 257640; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t641; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t642; CHECK-NEXT: ret643 %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl)644 ret <4 x i32> %v645}646 647define <4 x i32> @vp_ctlz_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {648; CHECK-LABEL: vp_ctlz_v4i32_unmasked:649; CHECK: # %bb.0:650; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma651; CHECK-NEXT: vsrl.vi v9, v8, 1652; CHECK-NEXT: lui a0, 349525653; CHECK-NEXT: vor.vv v8, v8, v9654; CHECK-NEXT: addi a0, a0, 1365655; CHECK-NEXT: vsrl.vi v9, v8, 2656; CHECK-NEXT: vor.vv v8, v8, v9657; CHECK-NEXT: vsrl.vi v9, v8, 4658; CHECK-NEXT: vor.vv v8, v8, v9659; CHECK-NEXT: vsrl.vi v9, v8, 8660; CHECK-NEXT: vor.vv v8, v8, v9661; CHECK-NEXT: vsrl.vi v9, v8, 16662; CHECK-NEXT: vor.vv v8, v8, v9663; CHECK-NEXT: vnot.v v8, v8664; CHECK-NEXT: vsrl.vi v9, v8, 1665; CHECK-NEXT: vand.vx v9, v9, a0666; CHECK-NEXT: lui a0, 209715667; CHECK-NEXT: addi a0, a0, 819668; CHECK-NEXT: vsub.vv v8, v8, v9669; CHECK-NEXT: vand.vx v9, v8, a0670; CHECK-NEXT: vsrl.vi v8, v8, 2671; CHECK-NEXT: vand.vx v8, v8, a0672; CHECK-NEXT: lui a0, 61681673; CHECK-NEXT: addi a0, a0, -241674; CHECK-NEXT: vadd.vv v8, v9, v8675; CHECK-NEXT: vsrl.vi v9, v8, 4676; CHECK-NEXT: vadd.vv v8, v8, v9677; CHECK-NEXT: vand.vx v8, v8, a0678; CHECK-NEXT: lui a0, 4112679; CHECK-NEXT: addi a0, a0, 257680; CHECK-NEXT: vmul.vx v8, v8, a0681; CHECK-NEXT: vsrl.vi v8, v8, 24682; CHECK-NEXT: ret683 %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl)684 ret <4 x i32> %v685}686 687define <8 x i32> @vp_ctlz_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {688; CHECK-LABEL: vp_ctlz_v8i32:689; CHECK: # %bb.0:690; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma691; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t692; CHECK-NEXT: lui a0, 349525693; CHECK-NEXT: vor.vv v8, v8, v10, v0.t694; CHECK-NEXT: addi a0, a0, 1365695; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t696; CHECK-NEXT: vor.vv v8, v8, v10, v0.t697; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t698; CHECK-NEXT: vor.vv v8, v8, v10, v0.t699; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t700; CHECK-NEXT: vor.vv v8, v8, v10, v0.t701; CHECK-NEXT: vsrl.vi v10, v8, 16, v0.t702; CHECK-NEXT: vor.vv v8, v8, v10, v0.t703; CHECK-NEXT: vnot.v v8, v8, v0.t704; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t705; CHECK-NEXT: vand.vx v10, v10, a0, v0.t706; CHECK-NEXT: lui a0, 209715707; CHECK-NEXT: addi a0, a0, 819708; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t709; CHECK-NEXT: vand.vx v10, v8, a0, v0.t710; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t711; CHECK-NEXT: vand.vx v8, v8, a0, v0.t712; CHECK-NEXT: lui a0, 61681713; CHECK-NEXT: addi a0, a0, -241714; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t715; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t716; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t717; CHECK-NEXT: vand.vx v8, v8, a0, v0.t718; CHECK-NEXT: lui a0, 4112719; CHECK-NEXT: addi a0, a0, 257720; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t721; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t722; CHECK-NEXT: ret723 %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl)724 ret <8 x i32> %v725}726 727define <8 x i32> @vp_ctlz_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {728; CHECK-LABEL: vp_ctlz_v8i32_unmasked:729; CHECK: # %bb.0:730; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma731; CHECK-NEXT: vsrl.vi v10, v8, 1732; CHECK-NEXT: lui a0, 349525733; CHECK-NEXT: vor.vv v8, v8, v10734; CHECK-NEXT: addi a0, a0, 1365735; CHECK-NEXT: vsrl.vi v10, v8, 2736; CHECK-NEXT: vor.vv v8, v8, v10737; CHECK-NEXT: vsrl.vi v10, v8, 4738; CHECK-NEXT: vor.vv v8, v8, v10739; CHECK-NEXT: vsrl.vi v10, v8, 8740; CHECK-NEXT: vor.vv v8, v8, v10741; CHECK-NEXT: vsrl.vi v10, v8, 16742; CHECK-NEXT: vor.vv v8, v8, v10743; CHECK-NEXT: vnot.v v8, v8744; CHECK-NEXT: vsrl.vi v10, v8, 1745; CHECK-NEXT: vand.vx v10, v10, a0746; CHECK-NEXT: lui a0, 209715747; CHECK-NEXT: addi a0, a0, 819748; CHECK-NEXT: vsub.vv v8, v8, v10749; CHECK-NEXT: vand.vx v10, v8, a0750; CHECK-NEXT: vsrl.vi v8, v8, 2751; CHECK-NEXT: vand.vx v8, v8, a0752; CHECK-NEXT: lui a0, 61681753; CHECK-NEXT: addi a0, a0, -241754; CHECK-NEXT: vadd.vv v8, v10, v8755; CHECK-NEXT: vsrl.vi v10, v8, 4756; CHECK-NEXT: vadd.vv v8, v8, v10757; CHECK-NEXT: vand.vx v8, v8, a0758; CHECK-NEXT: lui a0, 4112759; CHECK-NEXT: addi a0, a0, 257760; CHECK-NEXT: vmul.vx v8, v8, a0761; CHECK-NEXT: vsrl.vi v8, v8, 24762; CHECK-NEXT: ret763 %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl)764 ret <8 x i32> %v765}766 767define <16 x i32> @vp_ctlz_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {768; CHECK-LABEL: vp_ctlz_v16i32:769; CHECK: # %bb.0:770; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma771; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t772; CHECK-NEXT: lui a0, 349525773; CHECK-NEXT: vor.vv v8, v8, v12, v0.t774; CHECK-NEXT: addi a0, a0, 1365775; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t776; CHECK-NEXT: vor.vv v8, v8, v12, v0.t777; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t778; CHECK-NEXT: vor.vv v8, v8, v12, v0.t779; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t780; CHECK-NEXT: vor.vv v8, v8, v12, v0.t781; CHECK-NEXT: vsrl.vi v12, v8, 16, v0.t782; CHECK-NEXT: vor.vv v8, v8, v12, v0.t783; CHECK-NEXT: vnot.v v8, v8, v0.t784; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t785; CHECK-NEXT: vand.vx v12, v12, a0, v0.t786; CHECK-NEXT: lui a0, 209715787; CHECK-NEXT: addi a0, a0, 819788; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t789; CHECK-NEXT: vand.vx v12, v8, a0, v0.t790; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t791; CHECK-NEXT: vand.vx v8, v8, a0, v0.t792; CHECK-NEXT: lui a0, 61681793; CHECK-NEXT: addi a0, a0, -241794; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t795; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t796; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t797; CHECK-NEXT: vand.vx v8, v8, a0, v0.t798; CHECK-NEXT: lui a0, 4112799; CHECK-NEXT: addi a0, a0, 257800; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t801; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t802; CHECK-NEXT: ret803 %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl)804 ret <16 x i32> %v805}806 807define <16 x i32> @vp_ctlz_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {808; CHECK-LABEL: vp_ctlz_v16i32_unmasked:809; CHECK: # %bb.0:810; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma811; CHECK-NEXT: vsrl.vi v12, v8, 1812; CHECK-NEXT: lui a0, 349525813; CHECK-NEXT: vor.vv v8, v8, v12814; CHECK-NEXT: addi a0, a0, 1365815; CHECK-NEXT: vsrl.vi v12, v8, 2816; CHECK-NEXT: vor.vv v8, v8, v12817; CHECK-NEXT: vsrl.vi v12, v8, 4818; CHECK-NEXT: vor.vv v8, v8, v12819; CHECK-NEXT: vsrl.vi v12, v8, 8820; CHECK-NEXT: vor.vv v8, v8, v12821; CHECK-NEXT: vsrl.vi v12, v8, 16822; CHECK-NEXT: vor.vv v8, v8, v12823; CHECK-NEXT: vnot.v v8, v8824; CHECK-NEXT: vsrl.vi v12, v8, 1825; CHECK-NEXT: vand.vx v12, v12, a0826; CHECK-NEXT: lui a0, 209715827; CHECK-NEXT: addi a0, a0, 819828; CHECK-NEXT: vsub.vv v8, v8, v12829; CHECK-NEXT: vand.vx v12, v8, a0830; CHECK-NEXT: vsrl.vi v8, v8, 2831; CHECK-NEXT: vand.vx v8, v8, a0832; CHECK-NEXT: lui a0, 61681833; CHECK-NEXT: addi a0, a0, -241834; CHECK-NEXT: vadd.vv v8, v12, v8835; CHECK-NEXT: vsrl.vi v12, v8, 4836; CHECK-NEXT: vadd.vv v8, v8, v12837; CHECK-NEXT: vand.vx v8, v8, a0838; CHECK-NEXT: lui a0, 4112839; CHECK-NEXT: addi a0, a0, 257840; CHECK-NEXT: vmul.vx v8, v8, a0841; CHECK-NEXT: vsrl.vi v8, v8, 24842; CHECK-NEXT: ret843 %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl)844 ret <16 x i32> %v845}846 847define <2 x i64> @vp_ctlz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {848; RV32-LABEL: vp_ctlz_v2i64:849; RV32: # %bb.0:850; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma851; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t852; RV32-NEXT: lui a1, 349525853; RV32-NEXT: addi a1, a1, 1365854; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma855; RV32-NEXT: vmv.v.x v10, a1856; RV32-NEXT: li a1, 32857; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma858; RV32-NEXT: vor.vv v8, v8, v9, v0.t859; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t860; RV32-NEXT: vor.vv v8, v8, v9, v0.t861; RV32-NEXT: vsrl.vi v9, v8, 4, v0.t862; RV32-NEXT: vor.vv v8, v8, v9, v0.t863; RV32-NEXT: vsrl.vi v9, v8, 8, v0.t864; RV32-NEXT: vor.vv v8, v8, v9, v0.t865; RV32-NEXT: vsrl.vi v9, v8, 16, v0.t866; RV32-NEXT: vor.vv v8, v8, v9, v0.t867; RV32-NEXT: vsrl.vx v9, v8, a1, v0.t868; RV32-NEXT: lui a1, 209715869; RV32-NEXT: addi a1, a1, 819870; RV32-NEXT: vor.vv v8, v8, v9, v0.t871; RV32-NEXT: vnot.v v8, v8, v0.t872; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t873; RV32-NEXT: vand.vv v9, v9, v10, v0.t874; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma875; RV32-NEXT: vmv.v.x v10, a1876; RV32-NEXT: lui a1, 61681877; RV32-NEXT: addi a1, a1, -241878; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma879; RV32-NEXT: vsub.vv v8, v8, v9, v0.t880; RV32-NEXT: vand.vv v9, v8, v10, v0.t881; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t882; RV32-NEXT: vand.vv v8, v8, v10, v0.t883; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma884; RV32-NEXT: vmv.v.x v10, a1885; RV32-NEXT: lui a1, 4112886; RV32-NEXT: addi a1, a1, 257887; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma888; RV32-NEXT: vadd.vv v8, v9, v8, v0.t889; RV32-NEXT: vsrl.vi v9, v8, 4, v0.t890; RV32-NEXT: vadd.vv v8, v8, v9, v0.t891; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma892; RV32-NEXT: vmv.v.x v9, a1893; RV32-NEXT: li a1, 56894; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma895; RV32-NEXT: vand.vv v8, v8, v10, v0.t896; RV32-NEXT: vmul.vv v8, v8, v9, v0.t897; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t898; RV32-NEXT: ret899;900; RV64-LABEL: vp_ctlz_v2i64:901; RV64: # %bb.0:902; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma903; RV64-NEXT: vsrl.vi v9, v8, 1, v0.t904; RV64-NEXT: lui a0, 349525905; RV64-NEXT: lui a1, 209715906; RV64-NEXT: lui a2, 61681907; RV64-NEXT: lui a3, 4112908; RV64-NEXT: addi a0, a0, 1365909; RV64-NEXT: addi a1, a1, 819910; RV64-NEXT: addi a2, a2, -241911; RV64-NEXT: addi a3, a3, 257912; RV64-NEXT: slli a4, a0, 32913; RV64-NEXT: add a0, a0, a4914; RV64-NEXT: slli a4, a1, 32915; RV64-NEXT: add a1, a1, a4916; RV64-NEXT: slli a4, a2, 32917; RV64-NEXT: add a2, a2, a4918; RV64-NEXT: slli a4, a3, 32919; RV64-NEXT: add a3, a3, a4920; RV64-NEXT: li a4, 32921; RV64-NEXT: vor.vv v8, v8, v9, v0.t922; RV64-NEXT: vsrl.vi v9, v8, 2, v0.t923; RV64-NEXT: vor.vv v8, v8, v9, v0.t924; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t925; RV64-NEXT: vor.vv v8, v8, v9, v0.t926; RV64-NEXT: vsrl.vi v9, v8, 8, v0.t927; RV64-NEXT: vor.vv v8, v8, v9, v0.t928; RV64-NEXT: vsrl.vi v9, v8, 16, v0.t929; RV64-NEXT: vor.vv v8, v8, v9, v0.t930; RV64-NEXT: vsrl.vx v9, v8, a4, v0.t931; RV64-NEXT: vor.vv v8, v8, v9, v0.t932; RV64-NEXT: vnot.v v8, v8, v0.t933; RV64-NEXT: vsrl.vi v9, v8, 1, v0.t934; RV64-NEXT: vand.vx v9, v9, a0, v0.t935; RV64-NEXT: vsub.vv v8, v8, v9, v0.t936; RV64-NEXT: vand.vx v9, v8, a1, v0.t937; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t938; RV64-NEXT: vand.vx v8, v8, a1, v0.t939; RV64-NEXT: vadd.vv v8, v9, v8, v0.t940; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t941; RV64-NEXT: vadd.vv v8, v8, v9, v0.t942; RV64-NEXT: vand.vx v8, v8, a2, v0.t943; RV64-NEXT: li a0, 56944; RV64-NEXT: vmul.vx v8, v8, a3, v0.t945; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t946; RV64-NEXT: ret947 %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl)948 ret <2 x i64> %v949}950 951define <2 x i64> @vp_ctlz_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {952; RV32-LABEL: vp_ctlz_v2i64_unmasked:953; RV32: # %bb.0:954; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma955; RV32-NEXT: vsrl.vi v9, v8, 1956; RV32-NEXT: lui a1, 349525957; RV32-NEXT: addi a1, a1, 1365958; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma959; RV32-NEXT: vmv.v.x v10, a1960; RV32-NEXT: li a1, 32961; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma962; RV32-NEXT: vor.vv v8, v8, v9963; RV32-NEXT: vsrl.vi v9, v8, 2964; RV32-NEXT: vor.vv v8, v8, v9965; RV32-NEXT: vsrl.vi v9, v8, 4966; RV32-NEXT: vor.vv v8, v8, v9967; RV32-NEXT: vsrl.vi v9, v8, 8968; RV32-NEXT: vor.vv v8, v8, v9969; RV32-NEXT: vsrl.vi v9, v8, 16970; RV32-NEXT: vor.vv v8, v8, v9971; RV32-NEXT: vsrl.vx v9, v8, a1972; RV32-NEXT: lui a1, 209715973; RV32-NEXT: addi a1, a1, 819974; RV32-NEXT: vor.vv v8, v8, v9975; RV32-NEXT: vnot.v v8, v8976; RV32-NEXT: vsrl.vi v9, v8, 1977; RV32-NEXT: vand.vv v9, v9, v10978; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma979; RV32-NEXT: vmv.v.x v10, a1980; RV32-NEXT: lui a1, 61681981; RV32-NEXT: addi a1, a1, -241982; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma983; RV32-NEXT: vsub.vv v8, v8, v9984; RV32-NEXT: vand.vv v9, v8, v10985; RV32-NEXT: vsrl.vi v8, v8, 2986; RV32-NEXT: vand.vv v8, v8, v10987; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma988; RV32-NEXT: vmv.v.x v10, a1989; RV32-NEXT: lui a1, 4112990; RV32-NEXT: addi a1, a1, 257991; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma992; RV32-NEXT: vadd.vv v8, v9, v8993; RV32-NEXT: vsrl.vi v9, v8, 4994; RV32-NEXT: vadd.vv v8, v8, v9995; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma996; RV32-NEXT: vmv.v.x v9, a1997; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma998; RV32-NEXT: vand.vv v8, v8, v10999; RV32-NEXT: vmul.vv v8, v8, v91000; RV32-NEXT: li a0, 561001; RV32-NEXT: vsrl.vx v8, v8, a01002; RV32-NEXT: ret1003;1004; RV64-LABEL: vp_ctlz_v2i64_unmasked:1005; RV64: # %bb.0:1006; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma1007; RV64-NEXT: vsrl.vi v9, v8, 11008; RV64-NEXT: lui a0, 3495251009; RV64-NEXT: lui a1, 2097151010; RV64-NEXT: lui a2, 616811011; RV64-NEXT: lui a3, 41121012; RV64-NEXT: addi a0, a0, 13651013; RV64-NEXT: addi a1, a1, 8191014; RV64-NEXT: addi a2, a2, -2411015; RV64-NEXT: addi a3, a3, 2571016; RV64-NEXT: slli a4, a0, 321017; RV64-NEXT: add a0, a0, a41018; RV64-NEXT: slli a4, a1, 321019; RV64-NEXT: add a1, a1, a41020; RV64-NEXT: slli a4, a2, 321021; RV64-NEXT: add a2, a2, a41022; RV64-NEXT: slli a4, a3, 321023; RV64-NEXT: add a3, a3, a41024; RV64-NEXT: li a4, 321025; RV64-NEXT: vor.vv v8, v8, v91026; RV64-NEXT: vsrl.vi v9, v8, 21027; RV64-NEXT: vor.vv v8, v8, v91028; RV64-NEXT: vsrl.vi v9, v8, 41029; RV64-NEXT: vor.vv v8, v8, v91030; RV64-NEXT: vsrl.vi v9, v8, 81031; RV64-NEXT: vor.vv v8, v8, v91032; RV64-NEXT: vsrl.vi v9, v8, 161033; RV64-NEXT: vor.vv v8, v8, v91034; RV64-NEXT: vsrl.vx v9, v8, a41035; RV64-NEXT: vor.vv v8, v8, v91036; RV64-NEXT: vnot.v v8, v81037; RV64-NEXT: vsrl.vi v9, v8, 11038; RV64-NEXT: vand.vx v9, v9, a01039; RV64-NEXT: vsub.vv v8, v8, v91040; RV64-NEXT: vand.vx v9, v8, a11041; RV64-NEXT: vsrl.vi v8, v8, 21042; RV64-NEXT: vand.vx v8, v8, a11043; RV64-NEXT: vadd.vv v8, v9, v81044; RV64-NEXT: vsrl.vi v9, v8, 41045; RV64-NEXT: vadd.vv v8, v8, v91046; RV64-NEXT: vand.vx v8, v8, a21047; RV64-NEXT: vmul.vx v8, v8, a31048; RV64-NEXT: li a0, 561049; RV64-NEXT: vsrl.vx v8, v8, a01050; RV64-NEXT: ret1051 %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl)1052 ret <2 x i64> %v1053}1054 1055define <4 x i64> @vp_ctlz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {1056; RV32-LABEL: vp_ctlz_v4i64:1057; RV32: # %bb.0:1058; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1059; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t1060; RV32-NEXT: lui a1, 3495251061; RV32-NEXT: addi a1, a1, 13651062; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1063; RV32-NEXT: vmv.v.x v10, a11064; RV32-NEXT: li a1, 321065; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1066; RV32-NEXT: vor.vv v8, v8, v12, v0.t1067; RV32-NEXT: vsrl.vi v12, v8, 2, v0.t1068; RV32-NEXT: vor.vv v8, v8, v12, v0.t1069; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t1070; RV32-NEXT: vor.vv v8, v8, v12, v0.t1071; RV32-NEXT: vsrl.vi v12, v8, 8, v0.t1072; RV32-NEXT: vor.vv v8, v8, v12, v0.t1073; RV32-NEXT: vsrl.vi v12, v8, 16, v0.t1074; RV32-NEXT: vor.vv v8, v8, v12, v0.t1075; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t1076; RV32-NEXT: lui a1, 2097151077; RV32-NEXT: addi a1, a1, 8191078; RV32-NEXT: vor.vv v8, v8, v12, v0.t1079; RV32-NEXT: vnot.v v8, v8, v0.t1080; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t1081; RV32-NEXT: vand.vv v10, v12, v10, v0.t1082; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1083; RV32-NEXT: vmv.v.x v12, a11084; RV32-NEXT: lui a1, 616811085; RV32-NEXT: addi a1, a1, -2411086; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1087; RV32-NEXT: vsub.vv v8, v8, v10, v0.t1088; RV32-NEXT: vand.vv v10, v8, v12, v0.t1089; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t1090; RV32-NEXT: vand.vv v8, v8, v12, v0.t1091; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1092; RV32-NEXT: vmv.v.x v12, a11093; RV32-NEXT: lui a1, 41121094; RV32-NEXT: addi a1, a1, 2571095; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1096; RV32-NEXT: vadd.vv v8, v10, v8, v0.t1097; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t1098; RV32-NEXT: vadd.vv v8, v8, v10, v0.t1099; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1100; RV32-NEXT: vmv.v.x v10, a11101; RV32-NEXT: li a1, 561102; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1103; RV32-NEXT: vand.vv v8, v8, v12, v0.t1104; RV32-NEXT: vmul.vv v8, v8, v10, v0.t1105; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1106; RV32-NEXT: ret1107;1108; RV64-LABEL: vp_ctlz_v4i64:1109; RV64: # %bb.0:1110; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma1111; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t1112; RV64-NEXT: lui a0, 3495251113; RV64-NEXT: lui a1, 2097151114; RV64-NEXT: lui a2, 616811115; RV64-NEXT: lui a3, 41121116; RV64-NEXT: addi a0, a0, 13651117; RV64-NEXT: addi a1, a1, 8191118; RV64-NEXT: addi a2, a2, -2411119; RV64-NEXT: addi a3, a3, 2571120; RV64-NEXT: slli a4, a0, 321121; RV64-NEXT: add a0, a0, a41122; RV64-NEXT: slli a4, a1, 321123; RV64-NEXT: add a1, a1, a41124; RV64-NEXT: slli a4, a2, 321125; RV64-NEXT: add a2, a2, a41126; RV64-NEXT: slli a4, a3, 321127; RV64-NEXT: add a3, a3, a41128; RV64-NEXT: li a4, 321129; RV64-NEXT: vor.vv v8, v8, v10, v0.t1130; RV64-NEXT: vsrl.vi v10, v8, 2, v0.t1131; RV64-NEXT: vor.vv v8, v8, v10, v0.t1132; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t1133; RV64-NEXT: vor.vv v8, v8, v10, v0.t1134; RV64-NEXT: vsrl.vi v10, v8, 8, v0.t1135; RV64-NEXT: vor.vv v8, v8, v10, v0.t1136; RV64-NEXT: vsrl.vi v10, v8, 16, v0.t1137; RV64-NEXT: vor.vv v8, v8, v10, v0.t1138; RV64-NEXT: vsrl.vx v10, v8, a4, v0.t1139; RV64-NEXT: vor.vv v8, v8, v10, v0.t1140; RV64-NEXT: vnot.v v8, v8, v0.t1141; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t1142; RV64-NEXT: vand.vx v10, v10, a0, v0.t1143; RV64-NEXT: vsub.vv v8, v8, v10, v0.t1144; RV64-NEXT: vand.vx v10, v8, a1, v0.t1145; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1146; RV64-NEXT: vand.vx v8, v8, a1, v0.t1147; RV64-NEXT: vadd.vv v8, v10, v8, v0.t1148; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t1149; RV64-NEXT: vadd.vv v8, v8, v10, v0.t1150; RV64-NEXT: vand.vx v8, v8, a2, v0.t1151; RV64-NEXT: li a0, 561152; RV64-NEXT: vmul.vx v8, v8, a3, v0.t1153; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1154; RV64-NEXT: ret1155 %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl)1156 ret <4 x i64> %v1157}1158 1159define <4 x i64> @vp_ctlz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {1160; RV32-LABEL: vp_ctlz_v4i64_unmasked:1161; RV32: # %bb.0:1162; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1163; RV32-NEXT: vsrl.vi v10, v8, 11164; RV32-NEXT: lui a1, 3495251165; RV32-NEXT: addi a1, a1, 13651166; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1167; RV32-NEXT: vmv.v.x v12, a11168; RV32-NEXT: li a1, 321169; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1170; RV32-NEXT: vor.vv v8, v8, v101171; RV32-NEXT: vsrl.vi v10, v8, 21172; RV32-NEXT: vor.vv v8, v8, v101173; RV32-NEXT: vsrl.vi v10, v8, 41174; RV32-NEXT: vor.vv v8, v8, v101175; RV32-NEXT: vsrl.vi v10, v8, 81176; RV32-NEXT: vor.vv v8, v8, v101177; RV32-NEXT: vsrl.vi v10, v8, 161178; RV32-NEXT: vor.vv v8, v8, v101179; RV32-NEXT: vsrl.vx v10, v8, a11180; RV32-NEXT: lui a1, 2097151181; RV32-NEXT: addi a1, a1, 8191182; RV32-NEXT: vor.vv v8, v8, v101183; RV32-NEXT: vnot.v v8, v81184; RV32-NEXT: vsrl.vi v10, v8, 11185; RV32-NEXT: vand.vv v10, v10, v121186; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1187; RV32-NEXT: vmv.v.x v12, a11188; RV32-NEXT: lui a1, 616811189; RV32-NEXT: addi a1, a1, -2411190; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1191; RV32-NEXT: vsub.vv v8, v8, v101192; RV32-NEXT: vand.vv v10, v8, v121193; RV32-NEXT: vsrl.vi v8, v8, 21194; RV32-NEXT: vand.vv v8, v8, v121195; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1196; RV32-NEXT: vmv.v.x v12, a11197; RV32-NEXT: lui a1, 41121198; RV32-NEXT: addi a1, a1, 2571199; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1200; RV32-NEXT: vadd.vv v8, v10, v81201; RV32-NEXT: vsrl.vi v10, v8, 41202; RV32-NEXT: vadd.vv v8, v8, v101203; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1204; RV32-NEXT: vmv.v.x v10, a11205; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1206; RV32-NEXT: vand.vv v8, v8, v121207; RV32-NEXT: vmul.vv v8, v8, v101208; RV32-NEXT: li a0, 561209; RV32-NEXT: vsrl.vx v8, v8, a01210; RV32-NEXT: ret1211;1212; RV64-LABEL: vp_ctlz_v4i64_unmasked:1213; RV64: # %bb.0:1214; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma1215; RV64-NEXT: vsrl.vi v10, v8, 11216; RV64-NEXT: lui a0, 3495251217; RV64-NEXT: lui a1, 2097151218; RV64-NEXT: lui a2, 616811219; RV64-NEXT: lui a3, 41121220; RV64-NEXT: addi a0, a0, 13651221; RV64-NEXT: addi a1, a1, 8191222; RV64-NEXT: addi a2, a2, -2411223; RV64-NEXT: addi a3, a3, 2571224; RV64-NEXT: slli a4, a0, 321225; RV64-NEXT: add a0, a0, a41226; RV64-NEXT: slli a4, a1, 321227; RV64-NEXT: add a1, a1, a41228; RV64-NEXT: slli a4, a2, 321229; RV64-NEXT: add a2, a2, a41230; RV64-NEXT: slli a4, a3, 321231; RV64-NEXT: add a3, a3, a41232; RV64-NEXT: li a4, 321233; RV64-NEXT: vor.vv v8, v8, v101234; RV64-NEXT: vsrl.vi v10, v8, 21235; RV64-NEXT: vor.vv v8, v8, v101236; RV64-NEXT: vsrl.vi v10, v8, 41237; RV64-NEXT: vor.vv v8, v8, v101238; RV64-NEXT: vsrl.vi v10, v8, 81239; RV64-NEXT: vor.vv v8, v8, v101240; RV64-NEXT: vsrl.vi v10, v8, 161241; RV64-NEXT: vor.vv v8, v8, v101242; RV64-NEXT: vsrl.vx v10, v8, a41243; RV64-NEXT: vor.vv v8, v8, v101244; RV64-NEXT: vnot.v v8, v81245; RV64-NEXT: vsrl.vi v10, v8, 11246; RV64-NEXT: vand.vx v10, v10, a01247; RV64-NEXT: vsub.vv v8, v8, v101248; RV64-NEXT: vand.vx v10, v8, a11249; RV64-NEXT: vsrl.vi v8, v8, 21250; RV64-NEXT: vand.vx v8, v8, a11251; RV64-NEXT: vadd.vv v8, v10, v81252; RV64-NEXT: vsrl.vi v10, v8, 41253; RV64-NEXT: vadd.vv v8, v8, v101254; RV64-NEXT: vand.vx v8, v8, a21255; RV64-NEXT: vmul.vx v8, v8, a31256; RV64-NEXT: li a0, 561257; RV64-NEXT: vsrl.vx v8, v8, a01258; RV64-NEXT: ret1259 %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl)1260 ret <4 x i64> %v1261}1262 1263define <8 x i64> @vp_ctlz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {1264; RV32-LABEL: vp_ctlz_v8i64:1265; RV32: # %bb.0:1266; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1267; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t1268; RV32-NEXT: lui a1, 3495251269; RV32-NEXT: addi a1, a1, 13651270; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1271; RV32-NEXT: vmv.v.x v12, a11272; RV32-NEXT: li a1, 321273; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1274; RV32-NEXT: vor.vv v8, v8, v16, v0.t1275; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t1276; RV32-NEXT: vor.vv v8, v8, v16, v0.t1277; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t1278; RV32-NEXT: vor.vv v8, v8, v16, v0.t1279; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t1280; RV32-NEXT: vor.vv v8, v8, v16, v0.t1281; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t1282; RV32-NEXT: vor.vv v8, v8, v16, v0.t1283; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t1284; RV32-NEXT: lui a1, 2097151285; RV32-NEXT: addi a1, a1, 8191286; RV32-NEXT: vor.vv v8, v8, v16, v0.t1287; RV32-NEXT: vnot.v v16, v8, v0.t1288; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t1289; RV32-NEXT: vand.vv v12, v8, v12, v0.t1290; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1291; RV32-NEXT: vmv.v.x v8, a11292; RV32-NEXT: lui a1, 616811293; RV32-NEXT: addi a1, a1, -2411294; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1295; RV32-NEXT: vsub.vv v12, v16, v12, v0.t1296; RV32-NEXT: vand.vv v16, v12, v8, v0.t1297; RV32-NEXT: vsrl.vi v12, v12, 2, v0.t1298; RV32-NEXT: vand.vv v8, v12, v8, v0.t1299; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1300; RV32-NEXT: vmv.v.x v12, a11301; RV32-NEXT: lui a1, 41121302; RV32-NEXT: addi a1, a1, 2571303; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1304; RV32-NEXT: vadd.vv v8, v16, v8, v0.t1305; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t1306; RV32-NEXT: vadd.vv v8, v8, v16, v0.t1307; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1308; RV32-NEXT: vmv.v.x v16, a11309; RV32-NEXT: li a1, 561310; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1311; RV32-NEXT: vand.vv v8, v8, v12, v0.t1312; RV32-NEXT: vmul.vv v8, v8, v16, v0.t1313; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1314; RV32-NEXT: ret1315;1316; RV64-LABEL: vp_ctlz_v8i64:1317; RV64: # %bb.0:1318; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma1319; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t1320; RV64-NEXT: lui a0, 3495251321; RV64-NEXT: lui a1, 2097151322; RV64-NEXT: lui a2, 616811323; RV64-NEXT: lui a3, 41121324; RV64-NEXT: addi a0, a0, 13651325; RV64-NEXT: addi a1, a1, 8191326; RV64-NEXT: addi a2, a2, -2411327; RV64-NEXT: addi a3, a3, 2571328; RV64-NEXT: slli a4, a0, 321329; RV64-NEXT: add a0, a0, a41330; RV64-NEXT: slli a4, a1, 321331; RV64-NEXT: add a1, a1, a41332; RV64-NEXT: slli a4, a2, 321333; RV64-NEXT: add a2, a2, a41334; RV64-NEXT: slli a4, a3, 321335; RV64-NEXT: add a3, a3, a41336; RV64-NEXT: li a4, 321337; RV64-NEXT: vor.vv v8, v8, v12, v0.t1338; RV64-NEXT: vsrl.vi v12, v8, 2, v0.t1339; RV64-NEXT: vor.vv v8, v8, v12, v0.t1340; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t1341; RV64-NEXT: vor.vv v8, v8, v12, v0.t1342; RV64-NEXT: vsrl.vi v12, v8, 8, v0.t1343; RV64-NEXT: vor.vv v8, v8, v12, v0.t1344; RV64-NEXT: vsrl.vi v12, v8, 16, v0.t1345; RV64-NEXT: vor.vv v8, v8, v12, v0.t1346; RV64-NEXT: vsrl.vx v12, v8, a4, v0.t1347; RV64-NEXT: vor.vv v8, v8, v12, v0.t1348; RV64-NEXT: vnot.v v8, v8, v0.t1349; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t1350; RV64-NEXT: vand.vx v12, v12, a0, v0.t1351; RV64-NEXT: vsub.vv v8, v8, v12, v0.t1352; RV64-NEXT: vand.vx v12, v8, a1, v0.t1353; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1354; RV64-NEXT: vand.vx v8, v8, a1, v0.t1355; RV64-NEXT: vadd.vv v8, v12, v8, v0.t1356; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t1357; RV64-NEXT: vadd.vv v8, v8, v12, v0.t1358; RV64-NEXT: vand.vx v8, v8, a2, v0.t1359; RV64-NEXT: li a0, 561360; RV64-NEXT: vmul.vx v8, v8, a3, v0.t1361; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1362; RV64-NEXT: ret1363 %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl)1364 ret <8 x i64> %v1365}1366 1367define <8 x i64> @vp_ctlz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {1368; RV32-LABEL: vp_ctlz_v8i64_unmasked:1369; RV32: # %bb.0:1370; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1371; RV32-NEXT: vsrl.vi v12, v8, 11372; RV32-NEXT: lui a1, 3495251373; RV32-NEXT: addi a1, a1, 13651374; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1375; RV32-NEXT: vmv.v.x v16, a11376; RV32-NEXT: li a1, 321377; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1378; RV32-NEXT: vor.vv v8, v8, v121379; RV32-NEXT: vsrl.vi v12, v8, 21380; RV32-NEXT: vor.vv v8, v8, v121381; RV32-NEXT: vsrl.vi v12, v8, 41382; RV32-NEXT: vor.vv v8, v8, v121383; RV32-NEXT: vsrl.vi v12, v8, 81384; RV32-NEXT: vor.vv v8, v8, v121385; RV32-NEXT: vsrl.vi v12, v8, 161386; RV32-NEXT: vor.vv v8, v8, v121387; RV32-NEXT: vsrl.vx v12, v8, a11388; RV32-NEXT: lui a1, 2097151389; RV32-NEXT: addi a1, a1, 8191390; RV32-NEXT: vor.vv v8, v8, v121391; RV32-NEXT: vnot.v v8, v81392; RV32-NEXT: vsrl.vi v12, v8, 11393; RV32-NEXT: vand.vv v12, v12, v161394; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1395; RV32-NEXT: vmv.v.x v16, a11396; RV32-NEXT: lui a1, 616811397; RV32-NEXT: addi a1, a1, -2411398; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1399; RV32-NEXT: vsub.vv v8, v8, v121400; RV32-NEXT: vand.vv v12, v8, v161401; RV32-NEXT: vsrl.vi v8, v8, 21402; RV32-NEXT: vand.vv v8, v8, v161403; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1404; RV32-NEXT: vmv.v.x v16, a11405; RV32-NEXT: lui a1, 41121406; RV32-NEXT: addi a1, a1, 2571407; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1408; RV32-NEXT: vadd.vv v8, v12, v81409; RV32-NEXT: vsrl.vi v12, v8, 41410; RV32-NEXT: vadd.vv v8, v8, v121411; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1412; RV32-NEXT: vmv.v.x v12, a11413; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1414; RV32-NEXT: vand.vv v8, v8, v161415; RV32-NEXT: vmul.vv v8, v8, v121416; RV32-NEXT: li a0, 561417; RV32-NEXT: vsrl.vx v8, v8, a01418; RV32-NEXT: ret1419;1420; RV64-LABEL: vp_ctlz_v8i64_unmasked:1421; RV64: # %bb.0:1422; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma1423; RV64-NEXT: vsrl.vi v12, v8, 11424; RV64-NEXT: lui a0, 3495251425; RV64-NEXT: lui a1, 2097151426; RV64-NEXT: lui a2, 616811427; RV64-NEXT: lui a3, 41121428; RV64-NEXT: addi a0, a0, 13651429; RV64-NEXT: addi a1, a1, 8191430; RV64-NEXT: addi a2, a2, -2411431; RV64-NEXT: addi a3, a3, 2571432; RV64-NEXT: slli a4, a0, 321433; RV64-NEXT: add a0, a0, a41434; RV64-NEXT: slli a4, a1, 321435; RV64-NEXT: add a1, a1, a41436; RV64-NEXT: slli a4, a2, 321437; RV64-NEXT: add a2, a2, a41438; RV64-NEXT: slli a4, a3, 321439; RV64-NEXT: add a3, a3, a41440; RV64-NEXT: li a4, 321441; RV64-NEXT: vor.vv v8, v8, v121442; RV64-NEXT: vsrl.vi v12, v8, 21443; RV64-NEXT: vor.vv v8, v8, v121444; RV64-NEXT: vsrl.vi v12, v8, 41445; RV64-NEXT: vor.vv v8, v8, v121446; RV64-NEXT: vsrl.vi v12, v8, 81447; RV64-NEXT: vor.vv v8, v8, v121448; RV64-NEXT: vsrl.vi v12, v8, 161449; RV64-NEXT: vor.vv v8, v8, v121450; RV64-NEXT: vsrl.vx v12, v8, a41451; RV64-NEXT: vor.vv v8, v8, v121452; RV64-NEXT: vnot.v v8, v81453; RV64-NEXT: vsrl.vi v12, v8, 11454; RV64-NEXT: vand.vx v12, v12, a01455; RV64-NEXT: vsub.vv v8, v8, v121456; RV64-NEXT: vand.vx v12, v8, a11457; RV64-NEXT: vsrl.vi v8, v8, 21458; RV64-NEXT: vand.vx v8, v8, a11459; RV64-NEXT: vadd.vv v8, v12, v81460; RV64-NEXT: vsrl.vi v12, v8, 41461; RV64-NEXT: vadd.vv v8, v8, v121462; RV64-NEXT: vand.vx v8, v8, a21463; RV64-NEXT: vmul.vx v8, v8, a31464; RV64-NEXT: li a0, 561465; RV64-NEXT: vsrl.vx v8, v8, a01466; RV64-NEXT: ret1467 %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl)1468 ret <8 x i64> %v1469}1470 1471define <15 x i64> @vp_ctlz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {1472; RV32-LABEL: vp_ctlz_v15i64:1473; RV32: # %bb.0:1474; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1475; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t1476; RV32-NEXT: lui a1, 3495251477; RV32-NEXT: addi a1, a1, 13651478; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1479; RV32-NEXT: vmv.v.x v16, a11480; RV32-NEXT: li a1, 321481; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1482; RV32-NEXT: vor.vv v8, v8, v24, v0.t1483; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t1484; RV32-NEXT: vor.vv v8, v8, v24, v0.t1485; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t1486; RV32-NEXT: vor.vv v8, v8, v24, v0.t1487; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t1488; RV32-NEXT: vor.vv v8, v8, v24, v0.t1489; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t1490; RV32-NEXT: vor.vv v8, v8, v24, v0.t1491; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t1492; RV32-NEXT: lui a1, 2097151493; RV32-NEXT: addi a1, a1, 8191494; RV32-NEXT: vor.vv v8, v8, v24, v0.t1495; RV32-NEXT: vnot.v v24, v8, v0.t1496; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t1497; RV32-NEXT: vand.vv v16, v8, v16, v0.t1498; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1499; RV32-NEXT: vmv.v.x v8, a11500; RV32-NEXT: lui a1, 616811501; RV32-NEXT: addi a1, a1, -2411502; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1503; RV32-NEXT: vsub.vv v24, v24, v16, v0.t1504; RV32-NEXT: vand.vv v16, v24, v8, v0.t1505; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t1506; RV32-NEXT: vand.vv v24, v24, v8, v0.t1507; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1508; RV32-NEXT: vmv.v.x v8, a11509; RV32-NEXT: lui a1, 41121510; RV32-NEXT: addi a1, a1, 2571511; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1512; RV32-NEXT: vadd.vv v16, v16, v24, v0.t1513; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t1514; RV32-NEXT: vadd.vv v16, v16, v24, v0.t1515; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1516; RV32-NEXT: vmv.v.x v24, a11517; RV32-NEXT: li a1, 561518; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1519; RV32-NEXT: vand.vv v8, v16, v8, v0.t1520; RV32-NEXT: vmul.vv v8, v8, v24, v0.t1521; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1522; RV32-NEXT: ret1523;1524; RV64-LABEL: vp_ctlz_v15i64:1525; RV64: # %bb.0:1526; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1527; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t1528; RV64-NEXT: lui a0, 3495251529; RV64-NEXT: lui a1, 2097151530; RV64-NEXT: lui a2, 616811531; RV64-NEXT: lui a3, 41121532; RV64-NEXT: addi a0, a0, 13651533; RV64-NEXT: addi a1, a1, 8191534; RV64-NEXT: addi a2, a2, -2411535; RV64-NEXT: addi a3, a3, 2571536; RV64-NEXT: slli a4, a0, 321537; RV64-NEXT: add a0, a0, a41538; RV64-NEXT: slli a4, a1, 321539; RV64-NEXT: add a1, a1, a41540; RV64-NEXT: slli a4, a2, 321541; RV64-NEXT: add a2, a2, a41542; RV64-NEXT: slli a4, a3, 321543; RV64-NEXT: add a3, a3, a41544; RV64-NEXT: li a4, 321545; RV64-NEXT: vor.vv v8, v8, v16, v0.t1546; RV64-NEXT: vsrl.vi v16, v8, 2, v0.t1547; RV64-NEXT: vor.vv v8, v8, v16, v0.t1548; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t1549; RV64-NEXT: vor.vv v8, v8, v16, v0.t1550; RV64-NEXT: vsrl.vi v16, v8, 8, v0.t1551; RV64-NEXT: vor.vv v8, v8, v16, v0.t1552; RV64-NEXT: vsrl.vi v16, v8, 16, v0.t1553; RV64-NEXT: vor.vv v8, v8, v16, v0.t1554; RV64-NEXT: vsrl.vx v16, v8, a4, v0.t1555; RV64-NEXT: vor.vv v8, v8, v16, v0.t1556; RV64-NEXT: vnot.v v8, v8, v0.t1557; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t1558; RV64-NEXT: vand.vx v16, v16, a0, v0.t1559; RV64-NEXT: vsub.vv v8, v8, v16, v0.t1560; RV64-NEXT: vand.vx v16, v8, a1, v0.t1561; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1562; RV64-NEXT: vand.vx v8, v8, a1, v0.t1563; RV64-NEXT: vadd.vv v8, v16, v8, v0.t1564; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t1565; RV64-NEXT: vadd.vv v8, v8, v16, v0.t1566; RV64-NEXT: vand.vx v8, v8, a2, v0.t1567; RV64-NEXT: li a0, 561568; RV64-NEXT: vmul.vx v8, v8, a3, v0.t1569; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1570; RV64-NEXT: ret1571 %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl)1572 ret <15 x i64> %v1573}1574 1575define <15 x i64> @vp_ctlz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {1576; RV32-LABEL: vp_ctlz_v15i64_unmasked:1577; RV32: # %bb.0:1578; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1579; RV32-NEXT: vsrl.vi v16, v8, 11580; RV32-NEXT: lui a1, 3495251581; RV32-NEXT: addi a1, a1, 13651582; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1583; RV32-NEXT: vmv.v.x v24, a11584; RV32-NEXT: li a1, 321585; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1586; RV32-NEXT: vor.vv v8, v8, v161587; RV32-NEXT: vsrl.vi v16, v8, 21588; RV32-NEXT: vor.vv v8, v8, v161589; RV32-NEXT: vsrl.vi v16, v8, 41590; RV32-NEXT: vor.vv v8, v8, v161591; RV32-NEXT: vsrl.vi v16, v8, 81592; RV32-NEXT: vor.vv v8, v8, v161593; RV32-NEXT: vsrl.vi v16, v8, 161594; RV32-NEXT: vor.vv v8, v8, v161595; RV32-NEXT: vsrl.vx v16, v8, a11596; RV32-NEXT: lui a1, 2097151597; RV32-NEXT: addi a1, a1, 8191598; RV32-NEXT: vor.vv v8, v8, v161599; RV32-NEXT: vnot.v v8, v81600; RV32-NEXT: vsrl.vi v16, v8, 11601; RV32-NEXT: vand.vv v24, v16, v241602; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1603; RV32-NEXT: vmv.v.x v16, a11604; RV32-NEXT: lui a1, 616811605; RV32-NEXT: addi a1, a1, -2411606; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1607; RV32-NEXT: vsub.vv v8, v8, v241608; RV32-NEXT: vand.vv v24, v8, v161609; RV32-NEXT: vsrl.vi v8, v8, 21610; RV32-NEXT: vand.vv v8, v8, v161611; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1612; RV32-NEXT: vmv.v.x v16, a11613; RV32-NEXT: lui a1, 41121614; RV32-NEXT: addi a1, a1, 2571615; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1616; RV32-NEXT: vadd.vv v8, v24, v81617; RV32-NEXT: vsrl.vi v24, v8, 41618; RV32-NEXT: vadd.vv v8, v8, v241619; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1620; RV32-NEXT: vmv.v.x v24, a11621; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1622; RV32-NEXT: vand.vv v8, v8, v161623; RV32-NEXT: vmul.vv v8, v8, v241624; RV32-NEXT: li a0, 561625; RV32-NEXT: vsrl.vx v8, v8, a01626; RV32-NEXT: ret1627;1628; RV64-LABEL: vp_ctlz_v15i64_unmasked:1629; RV64: # %bb.0:1630; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1631; RV64-NEXT: vsrl.vi v16, v8, 11632; RV64-NEXT: lui a0, 3495251633; RV64-NEXT: lui a1, 2097151634; RV64-NEXT: lui a2, 616811635; RV64-NEXT: lui a3, 41121636; RV64-NEXT: addi a0, a0, 13651637; RV64-NEXT: addi a1, a1, 8191638; RV64-NEXT: addi a2, a2, -2411639; RV64-NEXT: addi a3, a3, 2571640; RV64-NEXT: slli a4, a0, 321641; RV64-NEXT: add a0, a0, a41642; RV64-NEXT: slli a4, a1, 321643; RV64-NEXT: add a1, a1, a41644; RV64-NEXT: slli a4, a2, 321645; RV64-NEXT: add a2, a2, a41646; RV64-NEXT: slli a4, a3, 321647; RV64-NEXT: add a3, a3, a41648; RV64-NEXT: li a4, 321649; RV64-NEXT: vor.vv v8, v8, v161650; RV64-NEXT: vsrl.vi v16, v8, 21651; RV64-NEXT: vor.vv v8, v8, v161652; RV64-NEXT: vsrl.vi v16, v8, 41653; RV64-NEXT: vor.vv v8, v8, v161654; RV64-NEXT: vsrl.vi v16, v8, 81655; RV64-NEXT: vor.vv v8, v8, v161656; RV64-NEXT: vsrl.vi v16, v8, 161657; RV64-NEXT: vor.vv v8, v8, v161658; RV64-NEXT: vsrl.vx v16, v8, a41659; RV64-NEXT: vor.vv v8, v8, v161660; RV64-NEXT: vnot.v v8, v81661; RV64-NEXT: vsrl.vi v16, v8, 11662; RV64-NEXT: vand.vx v16, v16, a01663; RV64-NEXT: vsub.vv v8, v8, v161664; RV64-NEXT: vand.vx v16, v8, a11665; RV64-NEXT: vsrl.vi v8, v8, 21666; RV64-NEXT: vand.vx v8, v8, a11667; RV64-NEXT: vadd.vv v8, v16, v81668; RV64-NEXT: vsrl.vi v16, v8, 41669; RV64-NEXT: vadd.vv v8, v8, v161670; RV64-NEXT: vand.vx v8, v8, a21671; RV64-NEXT: vmul.vx v8, v8, a31672; RV64-NEXT: li a0, 561673; RV64-NEXT: vsrl.vx v8, v8, a01674; RV64-NEXT: ret1675 %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 false, <15 x i1> splat (i1 true), i32 %evl)1676 ret <15 x i64> %v1677}1678 1679define <16 x i64> @vp_ctlz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {1680; RV32-LABEL: vp_ctlz_v16i64:1681; RV32: # %bb.0:1682; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1683; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t1684; RV32-NEXT: lui a1, 3495251685; RV32-NEXT: addi a1, a1, 13651686; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1687; RV32-NEXT: vmv.v.x v16, a11688; RV32-NEXT: li a1, 321689; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1690; RV32-NEXT: vor.vv v8, v8, v24, v0.t1691; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t1692; RV32-NEXT: vor.vv v8, v8, v24, v0.t1693; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t1694; RV32-NEXT: vor.vv v8, v8, v24, v0.t1695; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t1696; RV32-NEXT: vor.vv v8, v8, v24, v0.t1697; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t1698; RV32-NEXT: vor.vv v8, v8, v24, v0.t1699; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t1700; RV32-NEXT: lui a1, 2097151701; RV32-NEXT: addi a1, a1, 8191702; RV32-NEXT: vor.vv v8, v8, v24, v0.t1703; RV32-NEXT: vnot.v v24, v8, v0.t1704; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t1705; RV32-NEXT: vand.vv v16, v8, v16, v0.t1706; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1707; RV32-NEXT: vmv.v.x v8, a11708; RV32-NEXT: lui a1, 616811709; RV32-NEXT: addi a1, a1, -2411710; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1711; RV32-NEXT: vsub.vv v24, v24, v16, v0.t1712; RV32-NEXT: vand.vv v16, v24, v8, v0.t1713; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t1714; RV32-NEXT: vand.vv v24, v24, v8, v0.t1715; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1716; RV32-NEXT: vmv.v.x v8, a11717; RV32-NEXT: lui a1, 41121718; RV32-NEXT: addi a1, a1, 2571719; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1720; RV32-NEXT: vadd.vv v16, v16, v24, v0.t1721; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t1722; RV32-NEXT: vadd.vv v16, v16, v24, v0.t1723; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1724; RV32-NEXT: vmv.v.x v24, a11725; RV32-NEXT: li a1, 561726; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1727; RV32-NEXT: vand.vv v8, v16, v8, v0.t1728; RV32-NEXT: vmul.vv v8, v8, v24, v0.t1729; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1730; RV32-NEXT: ret1731;1732; RV64-LABEL: vp_ctlz_v16i64:1733; RV64: # %bb.0:1734; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1735; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t1736; RV64-NEXT: lui a0, 3495251737; RV64-NEXT: lui a1, 2097151738; RV64-NEXT: lui a2, 616811739; RV64-NEXT: lui a3, 41121740; RV64-NEXT: addi a0, a0, 13651741; RV64-NEXT: addi a1, a1, 8191742; RV64-NEXT: addi a2, a2, -2411743; RV64-NEXT: addi a3, a3, 2571744; RV64-NEXT: slli a4, a0, 321745; RV64-NEXT: add a0, a0, a41746; RV64-NEXT: slli a4, a1, 321747; RV64-NEXT: add a1, a1, a41748; RV64-NEXT: slli a4, a2, 321749; RV64-NEXT: add a2, a2, a41750; RV64-NEXT: slli a4, a3, 321751; RV64-NEXT: add a3, a3, a41752; RV64-NEXT: li a4, 321753; RV64-NEXT: vor.vv v8, v8, v16, v0.t1754; RV64-NEXT: vsrl.vi v16, v8, 2, v0.t1755; RV64-NEXT: vor.vv v8, v8, v16, v0.t1756; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t1757; RV64-NEXT: vor.vv v8, v8, v16, v0.t1758; RV64-NEXT: vsrl.vi v16, v8, 8, v0.t1759; RV64-NEXT: vor.vv v8, v8, v16, v0.t1760; RV64-NEXT: vsrl.vi v16, v8, 16, v0.t1761; RV64-NEXT: vor.vv v8, v8, v16, v0.t1762; RV64-NEXT: vsrl.vx v16, v8, a4, v0.t1763; RV64-NEXT: vor.vv v8, v8, v16, v0.t1764; RV64-NEXT: vnot.v v8, v8, v0.t1765; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t1766; RV64-NEXT: vand.vx v16, v16, a0, v0.t1767; RV64-NEXT: vsub.vv v8, v8, v16, v0.t1768; RV64-NEXT: vand.vx v16, v8, a1, v0.t1769; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1770; RV64-NEXT: vand.vx v8, v8, a1, v0.t1771; RV64-NEXT: vadd.vv v8, v16, v8, v0.t1772; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t1773; RV64-NEXT: vadd.vv v8, v8, v16, v0.t1774; RV64-NEXT: vand.vx v8, v8, a2, v0.t1775; RV64-NEXT: li a0, 561776; RV64-NEXT: vmul.vx v8, v8, a3, v0.t1777; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1778; RV64-NEXT: ret1779 %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl)1780 ret <16 x i64> %v1781}1782 1783define <16 x i64> @vp_ctlz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {1784; RV32-LABEL: vp_ctlz_v16i64_unmasked:1785; RV32: # %bb.0:1786; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1787; RV32-NEXT: vsrl.vi v16, v8, 11788; RV32-NEXT: lui a1, 3495251789; RV32-NEXT: addi a1, a1, 13651790; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1791; RV32-NEXT: vmv.v.x v24, a11792; RV32-NEXT: li a1, 321793; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1794; RV32-NEXT: vor.vv v8, v8, v161795; RV32-NEXT: vsrl.vi v16, v8, 21796; RV32-NEXT: vor.vv v8, v8, v161797; RV32-NEXT: vsrl.vi v16, v8, 41798; RV32-NEXT: vor.vv v8, v8, v161799; RV32-NEXT: vsrl.vi v16, v8, 81800; RV32-NEXT: vor.vv v8, v8, v161801; RV32-NEXT: vsrl.vi v16, v8, 161802; RV32-NEXT: vor.vv v8, v8, v161803; RV32-NEXT: vsrl.vx v16, v8, a11804; RV32-NEXT: lui a1, 2097151805; RV32-NEXT: addi a1, a1, 8191806; RV32-NEXT: vor.vv v8, v8, v161807; RV32-NEXT: vnot.v v8, v81808; RV32-NEXT: vsrl.vi v16, v8, 11809; RV32-NEXT: vand.vv v24, v16, v241810; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1811; RV32-NEXT: vmv.v.x v16, a11812; RV32-NEXT: lui a1, 616811813; RV32-NEXT: addi a1, a1, -2411814; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1815; RV32-NEXT: vsub.vv v8, v8, v241816; RV32-NEXT: vand.vv v24, v8, v161817; RV32-NEXT: vsrl.vi v8, v8, 21818; RV32-NEXT: vand.vv v8, v8, v161819; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1820; RV32-NEXT: vmv.v.x v16, a11821; RV32-NEXT: lui a1, 41121822; RV32-NEXT: addi a1, a1, 2571823; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1824; RV32-NEXT: vadd.vv v8, v24, v81825; RV32-NEXT: vsrl.vi v24, v8, 41826; RV32-NEXT: vadd.vv v8, v8, v241827; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1828; RV32-NEXT: vmv.v.x v24, a11829; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1830; RV32-NEXT: vand.vv v8, v8, v161831; RV32-NEXT: vmul.vv v8, v8, v241832; RV32-NEXT: li a0, 561833; RV32-NEXT: vsrl.vx v8, v8, a01834; RV32-NEXT: ret1835;1836; RV64-LABEL: vp_ctlz_v16i64_unmasked:1837; RV64: # %bb.0:1838; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1839; RV64-NEXT: vsrl.vi v16, v8, 11840; RV64-NEXT: lui a0, 3495251841; RV64-NEXT: lui a1, 2097151842; RV64-NEXT: lui a2, 616811843; RV64-NEXT: lui a3, 41121844; RV64-NEXT: addi a0, a0, 13651845; RV64-NEXT: addi a1, a1, 8191846; RV64-NEXT: addi a2, a2, -2411847; RV64-NEXT: addi a3, a3, 2571848; RV64-NEXT: slli a4, a0, 321849; RV64-NEXT: add a0, a0, a41850; RV64-NEXT: slli a4, a1, 321851; RV64-NEXT: add a1, a1, a41852; RV64-NEXT: slli a4, a2, 321853; RV64-NEXT: add a2, a2, a41854; RV64-NEXT: slli a4, a3, 321855; RV64-NEXT: add a3, a3, a41856; RV64-NEXT: li a4, 321857; RV64-NEXT: vor.vv v8, v8, v161858; RV64-NEXT: vsrl.vi v16, v8, 21859; RV64-NEXT: vor.vv v8, v8, v161860; RV64-NEXT: vsrl.vi v16, v8, 41861; RV64-NEXT: vor.vv v8, v8, v161862; RV64-NEXT: vsrl.vi v16, v8, 81863; RV64-NEXT: vor.vv v8, v8, v161864; RV64-NEXT: vsrl.vi v16, v8, 161865; RV64-NEXT: vor.vv v8, v8, v161866; RV64-NEXT: vsrl.vx v16, v8, a41867; RV64-NEXT: vor.vv v8, v8, v161868; RV64-NEXT: vnot.v v8, v81869; RV64-NEXT: vsrl.vi v16, v8, 11870; RV64-NEXT: vand.vx v16, v16, a01871; RV64-NEXT: vsub.vv v8, v8, v161872; RV64-NEXT: vand.vx v16, v8, a11873; RV64-NEXT: vsrl.vi v8, v8, 21874; RV64-NEXT: vand.vx v8, v8, a11875; RV64-NEXT: vadd.vv v8, v16, v81876; RV64-NEXT: vsrl.vi v16, v8, 41877; RV64-NEXT: vadd.vv v8, v8, v161878; RV64-NEXT: vand.vx v8, v8, a21879; RV64-NEXT: vmul.vx v8, v8, a31880; RV64-NEXT: li a0, 561881; RV64-NEXT: vsrl.vx v8, v8, a01882; RV64-NEXT: ret1883 %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl)1884 ret <16 x i64> %v1885}1886 1887define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {1888; RV32-LABEL: vp_ctlz_v32i64:1889; RV32: # %bb.0:1890; RV32-NEXT: addi sp, sp, -161891; RV32-NEXT: .cfi_def_cfa_offset 161892; RV32-NEXT: csrr a1, vlenb1893; RV32-NEXT: li a2, 481894; RV32-NEXT: mul a1, a1, a21895; RV32-NEXT: sub sp, sp, a11896; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb1897; RV32-NEXT: csrr a1, vlenb1898; RV32-NEXT: li a2, 401899; RV32-NEXT: mul a1, a1, a21900; RV32-NEXT: add a1, sp, a11901; RV32-NEXT: addi a1, a1, 161902; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1903; RV32-NEXT: li a1, 161904; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1905; RV32-NEXT: vslidedown.vi v7, v0, 21906; RV32-NEXT: mv a2, a01907; RV32-NEXT: bltu a0, a1, .LBB34_21908; RV32-NEXT: # %bb.1:1909; RV32-NEXT: li a2, 161910; RV32-NEXT: .LBB34_2:1911; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1912; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t1913; RV32-NEXT: li a1, 321914; RV32-NEXT: lui a3, 3495251915; RV32-NEXT: vor.vv v8, v8, v16, v0.t1916; RV32-NEXT: addi a3, a3, 13651917; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t1918; RV32-NEXT: vor.vv v8, v8, v16, v0.t1919; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t1920; RV32-NEXT: vor.vv v8, v8, v16, v0.t1921; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t1922; RV32-NEXT: vor.vv v8, v8, v16, v0.t1923; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t1924; RV32-NEXT: vor.vv v8, v8, v16, v0.t1925; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t1926; RV32-NEXT: vor.vv v8, v8, v16, v0.t1927; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma1928; RV32-NEXT: vmv.v.x v24, a31929; RV32-NEXT: csrr a3, vlenb1930; RV32-NEXT: slli a3, a3, 51931; RV32-NEXT: add a3, sp, a31932; RV32-NEXT: addi a3, a3, 161933; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill1934; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1935; RV32-NEXT: vnot.v v8, v8, v0.t1936; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t1937; RV32-NEXT: vand.vv v16, v16, v24, v0.t1938; RV32-NEXT: vsub.vv v8, v8, v16, v0.t1939; RV32-NEXT: lui a3, 2097151940; RV32-NEXT: addi a3, a3, 8191941; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma1942; RV32-NEXT: vmv.v.x v16, a31943; RV32-NEXT: csrr a3, vlenb1944; RV32-NEXT: slli a3, a3, 41945; RV32-NEXT: add a3, sp, a31946; RV32-NEXT: addi a3, a3, 161947; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill1948; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1949; RV32-NEXT: vand.vv v24, v8, v16, v0.t1950; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t1951; RV32-NEXT: vand.vv v8, v8, v16, v0.t1952; RV32-NEXT: vadd.vv v8, v24, v8, v0.t1953; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t1954; RV32-NEXT: vadd.vv v8, v8, v24, v0.t1955; RV32-NEXT: lui a3, 616811956; RV32-NEXT: addi a3, a3, -2411957; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma1958; RV32-NEXT: vmv.v.x v16, a31959; RV32-NEXT: csrr a3, vlenb1960; RV32-NEXT: li a4, 241961; RV32-NEXT: mul a3, a3, a41962; RV32-NEXT: add a3, sp, a31963; RV32-NEXT: addi a3, a3, 161964; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill1965; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1966; RV32-NEXT: vand.vv v8, v8, v16, v0.t1967; RV32-NEXT: lui a3, 41121968; RV32-NEXT: addi a3, a3, 2571969; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma1970; RV32-NEXT: vmv.v.x v16, a31971; RV32-NEXT: addi a3, sp, 161972; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill1973; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1974; RV32-NEXT: vmul.vv v8, v8, v16, v0.t1975; RV32-NEXT: li a2, 561976; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t1977; RV32-NEXT: csrr a3, vlenb1978; RV32-NEXT: slli a3, a3, 31979; RV32-NEXT: add a3, sp, a31980; RV32-NEXT: addi a3, a3, 161981; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill1982; RV32-NEXT: addi a3, a0, -161983; RV32-NEXT: sltu a0, a0, a31984; RV32-NEXT: addi a0, a0, -11985; RV32-NEXT: and a0, a0, a31986; RV32-NEXT: vmv1r.v v0, v71987; RV32-NEXT: csrr a3, vlenb1988; RV32-NEXT: li a4, 401989; RV32-NEXT: mul a3, a3, a41990; RV32-NEXT: add a3, sp, a31991; RV32-NEXT: addi a3, a3, 161992; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload1993; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1994; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t1995; RV32-NEXT: vor.vv v8, v16, v8, v0.t1996; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t1997; RV32-NEXT: vor.vv v8, v8, v16, v0.t1998; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t1999; RV32-NEXT: vor.vv v8, v8, v16, v0.t2000; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t2001; RV32-NEXT: vor.vv v8, v8, v16, v0.t2002; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t2003; RV32-NEXT: vor.vv v8, v8, v16, v0.t2004; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t2005; RV32-NEXT: vor.vv v8, v8, v16, v0.t2006; RV32-NEXT: vnot.v v8, v8, v0.t2007; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t2008; RV32-NEXT: csrr a0, vlenb2009; RV32-NEXT: slli a0, a0, 52010; RV32-NEXT: add a0, sp, a02011; RV32-NEXT: addi a0, a0, 162012; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload2013; RV32-NEXT: vand.vv v16, v16, v24, v0.t2014; RV32-NEXT: vsub.vv v8, v8, v16, v0.t2015; RV32-NEXT: csrr a0, vlenb2016; RV32-NEXT: slli a0, a0, 42017; RV32-NEXT: add a0, sp, a02018; RV32-NEXT: addi a0, a0, 162019; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload2020; RV32-NEXT: vand.vv v16, v8, v24, v0.t2021; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t2022; RV32-NEXT: vand.vv v8, v8, v24, v0.t2023; RV32-NEXT: vadd.vv v8, v16, v8, v0.t2024; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t2025; RV32-NEXT: vadd.vv v8, v8, v16, v0.t2026; RV32-NEXT: csrr a0, vlenb2027; RV32-NEXT: li a1, 242028; RV32-NEXT: mul a0, a0, a12029; RV32-NEXT: add a0, sp, a02030; RV32-NEXT: addi a0, a0, 162031; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2032; RV32-NEXT: vand.vv v8, v8, v16, v0.t2033; RV32-NEXT: addi a0, sp, 162034; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload2035; RV32-NEXT: vmul.vv v8, v8, v16, v0.t2036; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t2037; RV32-NEXT: csrr a0, vlenb2038; RV32-NEXT: slli a0, a0, 32039; RV32-NEXT: add a0, sp, a02040; RV32-NEXT: addi a0, a0, 162041; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload2042; RV32-NEXT: csrr a0, vlenb2043; RV32-NEXT: li a1, 482044; RV32-NEXT: mul a0, a0, a12045; RV32-NEXT: add sp, sp, a02046; RV32-NEXT: .cfi_def_cfa sp, 162047; RV32-NEXT: addi sp, sp, 162048; RV32-NEXT: .cfi_def_cfa_offset 02049; RV32-NEXT: ret2050;2051; RV64-LABEL: vp_ctlz_v32i64:2052; RV64: # %bb.0:2053; RV64-NEXT: li a2, 162054; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2055; RV64-NEXT: vslidedown.vi v7, v0, 22056; RV64-NEXT: mv a1, a02057; RV64-NEXT: bltu a0, a2, .LBB34_22058; RV64-NEXT: # %bb.1:2059; RV64-NEXT: li a1, 162060; RV64-NEXT: .LBB34_2:2061; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2062; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t2063; RV64-NEXT: li a1, 322064; RV64-NEXT: lui a2, 3495252065; RV64-NEXT: lui a3, 2097152066; RV64-NEXT: lui a4, 616812067; RV64-NEXT: lui a5, 41122068; RV64-NEXT: addi a2, a2, 13652069; RV64-NEXT: addi a3, a3, 8192070; RV64-NEXT: addi a6, a4, -2412071; RV64-NEXT: addi a7, a5, 2572072; RV64-NEXT: slli a5, a2, 322073; RV64-NEXT: add a5, a2, a52074; RV64-NEXT: slli a4, a3, 322075; RV64-NEXT: add a4, a3, a42076; RV64-NEXT: slli a2, a6, 322077; RV64-NEXT: add a2, a6, a22078; RV64-NEXT: slli a3, a7, 322079; RV64-NEXT: add a3, a7, a32080; RV64-NEXT: addi a6, a0, -162081; RV64-NEXT: sltu a0, a0, a62082; RV64-NEXT: addi a0, a0, -12083; RV64-NEXT: and a6, a0, a62084; RV64-NEXT: li a0, 562085; RV64-NEXT: vor.vv v8, v8, v24, v0.t2086; RV64-NEXT: vsrl.vi v24, v8, 2, v0.t2087; RV64-NEXT: vor.vv v8, v8, v24, v0.t2088; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t2089; RV64-NEXT: vor.vv v8, v8, v24, v0.t2090; RV64-NEXT: vsrl.vi v24, v8, 8, v0.t2091; RV64-NEXT: vor.vv v8, v8, v24, v0.t2092; RV64-NEXT: vsrl.vi v24, v8, 16, v0.t2093; RV64-NEXT: vor.vv v8, v8, v24, v0.t2094; RV64-NEXT: vsrl.vx v24, v8, a1, v0.t2095; RV64-NEXT: vor.vv v8, v8, v24, v0.t2096; RV64-NEXT: vnot.v v8, v8, v0.t2097; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t2098; RV64-NEXT: vand.vx v24, v24, a5, v0.t2099; RV64-NEXT: vsub.vv v8, v8, v24, v0.t2100; RV64-NEXT: vand.vx v24, v8, a4, v0.t2101; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t2102; RV64-NEXT: vand.vx v8, v8, a4, v0.t2103; RV64-NEXT: vadd.vv v8, v24, v8, v0.t2104; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t2105; RV64-NEXT: vadd.vv v8, v8, v24, v0.t2106; RV64-NEXT: vand.vx v8, v8, a2, v0.t2107; RV64-NEXT: vmul.vx v8, v8, a3, v0.t2108; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t2109; RV64-NEXT: vmv1r.v v0, v72110; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma2111; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t2112; RV64-NEXT: vor.vv v16, v16, v24, v0.t2113; RV64-NEXT: vsrl.vi v24, v16, 2, v0.t2114; RV64-NEXT: vor.vv v16, v16, v24, v0.t2115; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t2116; RV64-NEXT: vor.vv v16, v16, v24, v0.t2117; RV64-NEXT: vsrl.vi v24, v16, 8, v0.t2118; RV64-NEXT: vor.vv v16, v16, v24, v0.t2119; RV64-NEXT: vsrl.vi v24, v16, 16, v0.t2120; RV64-NEXT: vor.vv v16, v16, v24, v0.t2121; RV64-NEXT: vsrl.vx v24, v16, a1, v0.t2122; RV64-NEXT: vor.vv v16, v16, v24, v0.t2123; RV64-NEXT: vnot.v v16, v16, v0.t2124; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t2125; RV64-NEXT: vand.vx v24, v24, a5, v0.t2126; RV64-NEXT: vsub.vv v16, v16, v24, v0.t2127; RV64-NEXT: vand.vx v24, v16, a4, v0.t2128; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t2129; RV64-NEXT: vand.vx v16, v16, a4, v0.t2130; RV64-NEXT: vadd.vv v16, v24, v16, v0.t2131; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t2132; RV64-NEXT: vadd.vv v16, v16, v24, v0.t2133; RV64-NEXT: vand.vx v16, v16, a2, v0.t2134; RV64-NEXT: vmul.vx v16, v16, a3, v0.t2135; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t2136; RV64-NEXT: ret2137 %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)2138 ret <32 x i64> %v2139}2140 2141define <32 x i64> @vp_ctlz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {2142; RV32-LABEL: vp_ctlz_v32i64_unmasked:2143; RV32: # %bb.0:2144; RV32-NEXT: li a2, 162145; RV32-NEXT: mv a1, a02146; RV32-NEXT: bltu a0, a2, .LBB35_22147; RV32-NEXT: # %bb.1:2148; RV32-NEXT: li a1, 162149; RV32-NEXT: .LBB35_2:2150; RV32-NEXT: addi sp, sp, -162151; RV32-NEXT: .cfi_def_cfa_offset 162152; RV32-NEXT: csrr a2, vlenb2153; RV32-NEXT: slli a2, a2, 42154; RV32-NEXT: sub sp, sp, a22155; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb2156; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2157; RV32-NEXT: vsrl.vi v0, v8, 12158; RV32-NEXT: li a2, 322159; RV32-NEXT: lui a3, 3495252160; RV32-NEXT: addi a3, a3, 13652161; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2162; RV32-NEXT: vmv.v.x v24, a32163; RV32-NEXT: csrr a3, vlenb2164; RV32-NEXT: slli a3, a3, 32165; RV32-NEXT: add a3, sp, a32166; RV32-NEXT: addi a3, a3, 162167; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill2168; RV32-NEXT: addi a3, a0, -162169; RV32-NEXT: sltu a0, a0, a32170; RV32-NEXT: addi a0, a0, -12171; RV32-NEXT: and a0, a0, a32172; RV32-NEXT: lui a3, 2097152173; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2174; RV32-NEXT: vor.vv v8, v8, v02175; RV32-NEXT: addi a3, a3, 8192176; RV32-NEXT: vsrl.vi v0, v8, 22177; RV32-NEXT: vor.vv v8, v8, v02178; RV32-NEXT: vsrl.vi v0, v8, 42179; RV32-NEXT: vor.vv v8, v8, v02180; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2181; RV32-NEXT: vsrl.vi v0, v16, 12182; RV32-NEXT: vor.vv v16, v16, v02183; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2184; RV32-NEXT: vsrl.vi v0, v8, 82185; RV32-NEXT: vor.vv v8, v8, v02186; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2187; RV32-NEXT: vsrl.vi v0, v16, 22188; RV32-NEXT: vor.vv v16, v16, v02189; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2190; RV32-NEXT: vsrl.vi v0, v8, 162191; RV32-NEXT: vor.vv v8, v8, v02192; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2193; RV32-NEXT: vsrl.vi v0, v16, 42194; RV32-NEXT: vor.vv v16, v16, v02195; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2196; RV32-NEXT: vsrl.vx v0, v8, a22197; RV32-NEXT: vor.vv v8, v8, v02198; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2199; RV32-NEXT: vsrl.vi v0, v16, 82200; RV32-NEXT: vor.vv v16, v16, v02201; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2202; RV32-NEXT: vnot.v v8, v82203; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2204; RV32-NEXT: vsrl.vi v0, v16, 162205; RV32-NEXT: vor.vv v16, v16, v02206; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2207; RV32-NEXT: vsrl.vi v0, v8, 12208; RV32-NEXT: vand.vv v0, v0, v242209; RV32-NEXT: vsub.vv v0, v8, v02210; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2211; RV32-NEXT: vsrl.vx v8, v16, a22212; RV32-NEXT: vor.vv v24, v16, v82213; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma2214; RV32-NEXT: vmv.v.x v8, a32215; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2216; RV32-NEXT: vand.vv v16, v0, v82217; RV32-NEXT: vsrl.vi v0, v0, 22218; RV32-NEXT: vand.vv v0, v0, v82219; RV32-NEXT: vadd.vv v16, v16, v02220; RV32-NEXT: addi a2, sp, 162221; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill2222; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2223; RV32-NEXT: vnot.v v24, v242224; RV32-NEXT: vsrl.vi v0, v24, 12225; RV32-NEXT: csrr a2, vlenb2226; RV32-NEXT: slli a2, a2, 32227; RV32-NEXT: add a2, sp, a22228; RV32-NEXT: addi a2, a2, 162229; RV32-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload2230; RV32-NEXT: vand.vv v0, v0, v162231; RV32-NEXT: vsub.vv v24, v24, v02232; RV32-NEXT: addi a2, sp, 162233; RV32-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload2234; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2235; RV32-NEXT: vsrl.vi v0, v16, 42236; RV32-NEXT: vadd.vv v16, v16, v02237; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2238; RV32-NEXT: vand.vv v0, v24, v82239; RV32-NEXT: vsrl.vi v24, v24, 22240; RV32-NEXT: vand.vv v8, v24, v82241; RV32-NEXT: lui a2, 616812242; RV32-NEXT: lui a3, 41122243; RV32-NEXT: addi a2, a2, -2412244; RV32-NEXT: addi a3, a3, 2572245; RV32-NEXT: vadd.vv v8, v0, v82246; RV32-NEXT: vsrl.vi v24, v8, 42247; RV32-NEXT: vadd.vv v8, v8, v242248; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2249; RV32-NEXT: vmv.v.x v24, a22250; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2251; RV32-NEXT: vand.vv v16, v16, v242252; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2253; RV32-NEXT: vand.vv v8, v8, v242254; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma2255; RV32-NEXT: vmv.v.x v24, a32256; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2257; RV32-NEXT: vmul.vv v16, v16, v242258; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2259; RV32-NEXT: vmul.vv v24, v8, v242260; RV32-NEXT: li a2, 562261; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2262; RV32-NEXT: vsrl.vx v8, v16, a22263; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2264; RV32-NEXT: vsrl.vx v16, v24, a22265; RV32-NEXT: csrr a0, vlenb2266; RV32-NEXT: slli a0, a0, 42267; RV32-NEXT: add sp, sp, a02268; RV32-NEXT: .cfi_def_cfa sp, 162269; RV32-NEXT: addi sp, sp, 162270; RV32-NEXT: .cfi_def_cfa_offset 02271; RV32-NEXT: ret2272;2273; RV64-LABEL: vp_ctlz_v32i64_unmasked:2274; RV64: # %bb.0:2275; RV64-NEXT: li a2, 162276; RV64-NEXT: mv a1, a02277; RV64-NEXT: bltu a0, a2, .LBB35_22278; RV64-NEXT: # %bb.1:2279; RV64-NEXT: li a1, 162280; RV64-NEXT: .LBB35_2:2281; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2282; RV64-NEXT: vsrl.vi v24, v8, 12283; RV64-NEXT: li a2, 322284; RV64-NEXT: lui a3, 3495252285; RV64-NEXT: lui a4, 2097152286; RV64-NEXT: lui a5, 616812287; RV64-NEXT: lui a6, 41122288; RV64-NEXT: addi a7, a3, 13652289; RV64-NEXT: addi a3, a4, 8192290; RV64-NEXT: addi a4, a5, -2412291; RV64-NEXT: addi a6, a6, 2572292; RV64-NEXT: slli a5, a7, 322293; RV64-NEXT: add a7, a7, a52294; RV64-NEXT: slli a5, a3, 322295; RV64-NEXT: add a5, a3, a52296; RV64-NEXT: slli a3, a4, 322297; RV64-NEXT: add a3, a4, a32298; RV64-NEXT: slli a4, a6, 322299; RV64-NEXT: add a4, a6, a42300; RV64-NEXT: addi a6, a0, -162301; RV64-NEXT: sltu a0, a0, a62302; RV64-NEXT: addi a0, a0, -12303; RV64-NEXT: and a6, a0, a62304; RV64-NEXT: li a0, 562305; RV64-NEXT: vor.vv v8, v8, v242306; RV64-NEXT: vsrl.vi v24, v8, 22307; RV64-NEXT: vor.vv v8, v8, v242308; RV64-NEXT: vsrl.vi v24, v8, 42309; RV64-NEXT: vor.vv v8, v8, v242310; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma2311; RV64-NEXT: vsrl.vi v24, v16, 12312; RV64-NEXT: vor.vv v16, v16, v242313; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2314; RV64-NEXT: vsrl.vi v24, v8, 82315; RV64-NEXT: vor.vv v8, v8, v242316; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma2317; RV64-NEXT: vsrl.vi v24, v16, 22318; RV64-NEXT: vor.vv v16, v16, v242319; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2320; RV64-NEXT: vsrl.vi v24, v8, 162321; RV64-NEXT: vor.vv v8, v8, v242322; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma2323; RV64-NEXT: vsrl.vi v24, v16, 42324; RV64-NEXT: vor.vv v16, v16, v242325; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2326; RV64-NEXT: vsrl.vx v24, v8, a22327; RV64-NEXT: vor.vv v8, v8, v242328; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma2329; RV64-NEXT: vsrl.vi v24, v16, 82330; RV64-NEXT: vor.vv v16, v16, v242331; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2332; RV64-NEXT: vnot.v v8, v82333; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma2334; RV64-NEXT: vsrl.vi v24, v16, 162335; RV64-NEXT: vor.vv v16, v16, v242336; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2337; RV64-NEXT: vsrl.vi v24, v8, 12338; RV64-NEXT: vand.vx v24, v24, a72339; RV64-NEXT: vsub.vv v8, v8, v242340; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma2341; RV64-NEXT: vsrl.vx v24, v16, a22342; RV64-NEXT: vor.vv v16, v16, v242343; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2344; RV64-NEXT: vand.vx v24, v8, a52345; RV64-NEXT: vsrl.vi v8, v8, 22346; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma2347; RV64-NEXT: vnot.v v16, v162348; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2349; RV64-NEXT: vand.vx v8, v8, a52350; RV64-NEXT: vadd.vv v8, v24, v82351; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma2352; RV64-NEXT: vsrl.vi v24, v16, 12353; RV64-NEXT: vand.vx v24, v24, a72354; RV64-NEXT: vsub.vv v16, v16, v242355; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2356; RV64-NEXT: vsrl.vi v24, v8, 42357; RV64-NEXT: vadd.vv v8, v8, v242358; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma2359; RV64-NEXT: vand.vx v24, v16, a52360; RV64-NEXT: vsrl.vi v16, v16, 22361; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2362; RV64-NEXT: vand.vx v8, v8, a32363; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma2364; RV64-NEXT: vand.vx v16, v16, a52365; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2366; RV64-NEXT: vmul.vx v8, v8, a42367; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma2368; RV64-NEXT: vadd.vv v16, v24, v162369; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2370; RV64-NEXT: vsrl.vx v8, v8, a02371; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma2372; RV64-NEXT: vsrl.vi v24, v16, 42373; RV64-NEXT: vadd.vv v16, v16, v242374; RV64-NEXT: vand.vx v16, v16, a32375; RV64-NEXT: vmul.vx v16, v16, a42376; RV64-NEXT: vsrl.vx v16, v16, a02377; RV64-NEXT: ret2378 %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 false, <32 x i1> splat (i1 true), i32 %evl)2379 ret <32 x i64> %v2380}2381 2382define <2 x i8> @vp_ctlz_zero_undef_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {2383; CHECK-LABEL: vp_ctlz_zero_undef_v2i8:2384; CHECK: # %bb.0:2385; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma2386; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2387; CHECK-NEXT: li a0, 852388; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2389; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t2390; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2391; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2392; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2393; CHECK-NEXT: vnot.v v8, v8, v0.t2394; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2395; CHECK-NEXT: vand.vx v9, v9, a0, v0.t2396; CHECK-NEXT: li a0, 512397; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t2398; CHECK-NEXT: vand.vx v9, v8, a0, v0.t2399; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2400; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2401; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t2402; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2403; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t2404; CHECK-NEXT: vand.vi v8, v8, 15, v0.t2405; CHECK-NEXT: ret2406 %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 true, <2 x i1> %m, i32 %evl)2407 ret <2 x i8> %v2408}2409 2410define <2 x i8> @vp_ctlz_zero_undef_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {2411; CHECK-LABEL: vp_ctlz_zero_undef_v2i8_unmasked:2412; CHECK: # %bb.0:2413; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma2414; CHECK-NEXT: vsrl.vi v9, v8, 12415; CHECK-NEXT: li a0, 852416; CHECK-NEXT: vor.vv v8, v8, v92417; CHECK-NEXT: vsrl.vi v9, v8, 22418; CHECK-NEXT: vor.vv v8, v8, v92419; CHECK-NEXT: vsrl.vi v9, v8, 42420; CHECK-NEXT: vor.vv v8, v8, v92421; CHECK-NEXT: vnot.v v8, v82422; CHECK-NEXT: vsrl.vi v9, v8, 12423; CHECK-NEXT: vand.vx v9, v9, a02424; CHECK-NEXT: li a0, 512425; CHECK-NEXT: vsub.vv v8, v8, v92426; CHECK-NEXT: vand.vx v9, v8, a02427; CHECK-NEXT: vsrl.vi v8, v8, 22428; CHECK-NEXT: vand.vx v8, v8, a02429; CHECK-NEXT: vadd.vv v8, v9, v82430; CHECK-NEXT: vsrl.vi v9, v8, 42431; CHECK-NEXT: vadd.vv v8, v8, v92432; CHECK-NEXT: vand.vi v8, v8, 152433; CHECK-NEXT: ret2434 %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl)2435 ret <2 x i8> %v2436}2437 2438define <4 x i8> @vp_ctlz_zero_undef_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {2439; CHECK-LABEL: vp_ctlz_zero_undef_v4i8:2440; CHECK: # %bb.0:2441; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma2442; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2443; CHECK-NEXT: li a0, 852444; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2445; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t2446; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2447; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2448; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2449; CHECK-NEXT: vnot.v v8, v8, v0.t2450; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2451; CHECK-NEXT: vand.vx v9, v9, a0, v0.t2452; CHECK-NEXT: li a0, 512453; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t2454; CHECK-NEXT: vand.vx v9, v8, a0, v0.t2455; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2456; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2457; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t2458; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2459; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t2460; CHECK-NEXT: vand.vi v8, v8, 15, v0.t2461; CHECK-NEXT: ret2462 %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 true, <4 x i1> %m, i32 %evl)2463 ret <4 x i8> %v2464}2465 2466define <4 x i8> @vp_ctlz_zero_undef_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {2467; CHECK-LABEL: vp_ctlz_zero_undef_v4i8_unmasked:2468; CHECK: # %bb.0:2469; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma2470; CHECK-NEXT: vsrl.vi v9, v8, 12471; CHECK-NEXT: li a0, 852472; CHECK-NEXT: vor.vv v8, v8, v92473; CHECK-NEXT: vsrl.vi v9, v8, 22474; CHECK-NEXT: vor.vv v8, v8, v92475; CHECK-NEXT: vsrl.vi v9, v8, 42476; CHECK-NEXT: vor.vv v8, v8, v92477; CHECK-NEXT: vnot.v v8, v82478; CHECK-NEXT: vsrl.vi v9, v8, 12479; CHECK-NEXT: vand.vx v9, v9, a02480; CHECK-NEXT: li a0, 512481; CHECK-NEXT: vsub.vv v8, v8, v92482; CHECK-NEXT: vand.vx v9, v8, a02483; CHECK-NEXT: vsrl.vi v8, v8, 22484; CHECK-NEXT: vand.vx v8, v8, a02485; CHECK-NEXT: vadd.vv v8, v9, v82486; CHECK-NEXT: vsrl.vi v9, v8, 42487; CHECK-NEXT: vadd.vv v8, v8, v92488; CHECK-NEXT: vand.vi v8, v8, 152489; CHECK-NEXT: ret2490 %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl)2491 ret <4 x i8> %v2492}2493 2494define <8 x i8> @vp_ctlz_zero_undef_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {2495; CHECK-LABEL: vp_ctlz_zero_undef_v8i8:2496; CHECK: # %bb.0:2497; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma2498; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2499; CHECK-NEXT: li a0, 852500; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2501; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t2502; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2503; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2504; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2505; CHECK-NEXT: vnot.v v8, v8, v0.t2506; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2507; CHECK-NEXT: vand.vx v9, v9, a0, v0.t2508; CHECK-NEXT: li a0, 512509; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t2510; CHECK-NEXT: vand.vx v9, v8, a0, v0.t2511; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2512; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2513; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t2514; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2515; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t2516; CHECK-NEXT: vand.vi v8, v8, 15, v0.t2517; CHECK-NEXT: ret2518 %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 true, <8 x i1> %m, i32 %evl)2519 ret <8 x i8> %v2520}2521 2522define <8 x i8> @vp_ctlz_zero_undef_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {2523; CHECK-LABEL: vp_ctlz_zero_undef_v8i8_unmasked:2524; CHECK: # %bb.0:2525; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma2526; CHECK-NEXT: vsrl.vi v9, v8, 12527; CHECK-NEXT: li a0, 852528; CHECK-NEXT: vor.vv v8, v8, v92529; CHECK-NEXT: vsrl.vi v9, v8, 22530; CHECK-NEXT: vor.vv v8, v8, v92531; CHECK-NEXT: vsrl.vi v9, v8, 42532; CHECK-NEXT: vor.vv v8, v8, v92533; CHECK-NEXT: vnot.v v8, v82534; CHECK-NEXT: vsrl.vi v9, v8, 12535; CHECK-NEXT: vand.vx v9, v9, a02536; CHECK-NEXT: li a0, 512537; CHECK-NEXT: vsub.vv v8, v8, v92538; CHECK-NEXT: vand.vx v9, v8, a02539; CHECK-NEXT: vsrl.vi v8, v8, 22540; CHECK-NEXT: vand.vx v8, v8, a02541; CHECK-NEXT: vadd.vv v8, v9, v82542; CHECK-NEXT: vsrl.vi v9, v8, 42543; CHECK-NEXT: vadd.vv v8, v8, v92544; CHECK-NEXT: vand.vi v8, v8, 152545; CHECK-NEXT: ret2546 %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl)2547 ret <8 x i8> %v2548}2549 2550define <16 x i8> @vp_ctlz_zero_undef_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {2551; CHECK-LABEL: vp_ctlz_zero_undef_v16i8:2552; CHECK: # %bb.0:2553; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma2554; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2555; CHECK-NEXT: li a0, 852556; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2557; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t2558; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2559; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2560; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2561; CHECK-NEXT: vnot.v v8, v8, v0.t2562; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2563; CHECK-NEXT: vand.vx v9, v9, a0, v0.t2564; CHECK-NEXT: li a0, 512565; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t2566; CHECK-NEXT: vand.vx v9, v8, a0, v0.t2567; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2568; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2569; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t2570; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2571; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t2572; CHECK-NEXT: vand.vi v8, v8, 15, v0.t2573; CHECK-NEXT: ret2574 %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 true, <16 x i1> %m, i32 %evl)2575 ret <16 x i8> %v2576}2577 2578define <16 x i8> @vp_ctlz_zero_undef_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {2579; CHECK-LABEL: vp_ctlz_zero_undef_v16i8_unmasked:2580; CHECK: # %bb.0:2581; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma2582; CHECK-NEXT: vsrl.vi v9, v8, 12583; CHECK-NEXT: li a0, 852584; CHECK-NEXT: vor.vv v8, v8, v92585; CHECK-NEXT: vsrl.vi v9, v8, 22586; CHECK-NEXT: vor.vv v8, v8, v92587; CHECK-NEXT: vsrl.vi v9, v8, 42588; CHECK-NEXT: vor.vv v8, v8, v92589; CHECK-NEXT: vnot.v v8, v82590; CHECK-NEXT: vsrl.vi v9, v8, 12591; CHECK-NEXT: vand.vx v9, v9, a02592; CHECK-NEXT: li a0, 512593; CHECK-NEXT: vsub.vv v8, v8, v92594; CHECK-NEXT: vand.vx v9, v8, a02595; CHECK-NEXT: vsrl.vi v8, v8, 22596; CHECK-NEXT: vand.vx v8, v8, a02597; CHECK-NEXT: vadd.vv v8, v9, v82598; CHECK-NEXT: vsrl.vi v9, v8, 42599; CHECK-NEXT: vadd.vv v8, v8, v92600; CHECK-NEXT: vand.vi v8, v8, 152601; CHECK-NEXT: ret2602 %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl)2603 ret <16 x i8> %v2604}2605 2606define <2 x i16> @vp_ctlz_zero_undef_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {2607; CHECK-LABEL: vp_ctlz_zero_undef_v2i16:2608; CHECK: # %bb.0:2609; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma2610; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2611; CHECK-NEXT: lui a0, 52612; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2613; CHECK-NEXT: addi a0, a0, 13652614; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t2615; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2616; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2617; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2618; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t2619; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2620; CHECK-NEXT: vnot.v v8, v8, v0.t2621; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2622; CHECK-NEXT: vand.vx v9, v9, a0, v0.t2623; CHECK-NEXT: lui a0, 32624; CHECK-NEXT: addi a0, a0, 8192625; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t2626; CHECK-NEXT: vand.vx v9, v8, a0, v0.t2627; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2628; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2629; CHECK-NEXT: lui a0, 12630; CHECK-NEXT: addi a0, a0, -2412631; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t2632; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2633; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t2634; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2635; CHECK-NEXT: li a0, 2572636; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t2637; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t2638; CHECK-NEXT: ret2639 %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 true, <2 x i1> %m, i32 %evl)2640 ret <2 x i16> %v2641}2642 2643define <2 x i16> @vp_ctlz_zero_undef_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {2644; CHECK-LABEL: vp_ctlz_zero_undef_v2i16_unmasked:2645; CHECK: # %bb.0:2646; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma2647; CHECK-NEXT: vsrl.vi v9, v8, 12648; CHECK-NEXT: lui a0, 52649; CHECK-NEXT: vor.vv v8, v8, v92650; CHECK-NEXT: addi a0, a0, 13652651; CHECK-NEXT: vsrl.vi v9, v8, 22652; CHECK-NEXT: vor.vv v8, v8, v92653; CHECK-NEXT: vsrl.vi v9, v8, 42654; CHECK-NEXT: vor.vv v8, v8, v92655; CHECK-NEXT: vsrl.vi v9, v8, 82656; CHECK-NEXT: vor.vv v8, v8, v92657; CHECK-NEXT: vnot.v v8, v82658; CHECK-NEXT: vsrl.vi v9, v8, 12659; CHECK-NEXT: vand.vx v9, v9, a02660; CHECK-NEXT: lui a0, 32661; CHECK-NEXT: addi a0, a0, 8192662; CHECK-NEXT: vsub.vv v8, v8, v92663; CHECK-NEXT: vand.vx v9, v8, a02664; CHECK-NEXT: vsrl.vi v8, v8, 22665; CHECK-NEXT: vand.vx v8, v8, a02666; CHECK-NEXT: lui a0, 12667; CHECK-NEXT: addi a0, a0, -2412668; CHECK-NEXT: vadd.vv v8, v9, v82669; CHECK-NEXT: vsrl.vi v9, v8, 42670; CHECK-NEXT: vadd.vv v8, v8, v92671; CHECK-NEXT: vand.vx v8, v8, a02672; CHECK-NEXT: li a0, 2572673; CHECK-NEXT: vmul.vx v8, v8, a02674; CHECK-NEXT: vsrl.vi v8, v8, 82675; CHECK-NEXT: ret2676 %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl)2677 ret <2 x i16> %v2678}2679 2680define <4 x i16> @vp_ctlz_zero_undef_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {2681; CHECK-LABEL: vp_ctlz_zero_undef_v4i16:2682; CHECK: # %bb.0:2683; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma2684; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2685; CHECK-NEXT: lui a0, 52686; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2687; CHECK-NEXT: addi a0, a0, 13652688; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t2689; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2690; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2691; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2692; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t2693; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2694; CHECK-NEXT: vnot.v v8, v8, v0.t2695; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2696; CHECK-NEXT: vand.vx v9, v9, a0, v0.t2697; CHECK-NEXT: lui a0, 32698; CHECK-NEXT: addi a0, a0, 8192699; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t2700; CHECK-NEXT: vand.vx v9, v8, a0, v0.t2701; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2702; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2703; CHECK-NEXT: lui a0, 12704; CHECK-NEXT: addi a0, a0, -2412705; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t2706; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2707; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t2708; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2709; CHECK-NEXT: li a0, 2572710; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t2711; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t2712; CHECK-NEXT: ret2713 %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 true, <4 x i1> %m, i32 %evl)2714 ret <4 x i16> %v2715}2716 2717define <4 x i16> @vp_ctlz_zero_undef_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {2718; CHECK-LABEL: vp_ctlz_zero_undef_v4i16_unmasked:2719; CHECK: # %bb.0:2720; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma2721; CHECK-NEXT: vsrl.vi v9, v8, 12722; CHECK-NEXT: lui a0, 52723; CHECK-NEXT: vor.vv v8, v8, v92724; CHECK-NEXT: addi a0, a0, 13652725; CHECK-NEXT: vsrl.vi v9, v8, 22726; CHECK-NEXT: vor.vv v8, v8, v92727; CHECK-NEXT: vsrl.vi v9, v8, 42728; CHECK-NEXT: vor.vv v8, v8, v92729; CHECK-NEXT: vsrl.vi v9, v8, 82730; CHECK-NEXT: vor.vv v8, v8, v92731; CHECK-NEXT: vnot.v v8, v82732; CHECK-NEXT: vsrl.vi v9, v8, 12733; CHECK-NEXT: vand.vx v9, v9, a02734; CHECK-NEXT: lui a0, 32735; CHECK-NEXT: addi a0, a0, 8192736; CHECK-NEXT: vsub.vv v8, v8, v92737; CHECK-NEXT: vand.vx v9, v8, a02738; CHECK-NEXT: vsrl.vi v8, v8, 22739; CHECK-NEXT: vand.vx v8, v8, a02740; CHECK-NEXT: lui a0, 12741; CHECK-NEXT: addi a0, a0, -2412742; CHECK-NEXT: vadd.vv v8, v9, v82743; CHECK-NEXT: vsrl.vi v9, v8, 42744; CHECK-NEXT: vadd.vv v8, v8, v92745; CHECK-NEXT: vand.vx v8, v8, a02746; CHECK-NEXT: li a0, 2572747; CHECK-NEXT: vmul.vx v8, v8, a02748; CHECK-NEXT: vsrl.vi v8, v8, 82749; CHECK-NEXT: ret2750 %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl)2751 ret <4 x i16> %v2752}2753 2754define <8 x i16> @vp_ctlz_zero_undef_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {2755; CHECK-LABEL: vp_ctlz_zero_undef_v8i16:2756; CHECK: # %bb.0:2757; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma2758; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2759; CHECK-NEXT: lui a0, 52760; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2761; CHECK-NEXT: addi a0, a0, 13652762; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t2763; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2764; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2765; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2766; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t2767; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2768; CHECK-NEXT: vnot.v v8, v8, v0.t2769; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2770; CHECK-NEXT: vand.vx v9, v9, a0, v0.t2771; CHECK-NEXT: lui a0, 32772; CHECK-NEXT: addi a0, a0, 8192773; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t2774; CHECK-NEXT: vand.vx v9, v8, a0, v0.t2775; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2776; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2777; CHECK-NEXT: lui a0, 12778; CHECK-NEXT: addi a0, a0, -2412779; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t2780; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2781; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t2782; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2783; CHECK-NEXT: li a0, 2572784; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t2785; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t2786; CHECK-NEXT: ret2787 %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 true, <8 x i1> %m, i32 %evl)2788 ret <8 x i16> %v2789}2790 2791define <8 x i16> @vp_ctlz_zero_undef_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {2792; CHECK-LABEL: vp_ctlz_zero_undef_v8i16_unmasked:2793; CHECK: # %bb.0:2794; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma2795; CHECK-NEXT: vsrl.vi v9, v8, 12796; CHECK-NEXT: lui a0, 52797; CHECK-NEXT: vor.vv v8, v8, v92798; CHECK-NEXT: addi a0, a0, 13652799; CHECK-NEXT: vsrl.vi v9, v8, 22800; CHECK-NEXT: vor.vv v8, v8, v92801; CHECK-NEXT: vsrl.vi v9, v8, 42802; CHECK-NEXT: vor.vv v8, v8, v92803; CHECK-NEXT: vsrl.vi v9, v8, 82804; CHECK-NEXT: vor.vv v8, v8, v92805; CHECK-NEXT: vnot.v v8, v82806; CHECK-NEXT: vsrl.vi v9, v8, 12807; CHECK-NEXT: vand.vx v9, v9, a02808; CHECK-NEXT: lui a0, 32809; CHECK-NEXT: addi a0, a0, 8192810; CHECK-NEXT: vsub.vv v8, v8, v92811; CHECK-NEXT: vand.vx v9, v8, a02812; CHECK-NEXT: vsrl.vi v8, v8, 22813; CHECK-NEXT: vand.vx v8, v8, a02814; CHECK-NEXT: lui a0, 12815; CHECK-NEXT: addi a0, a0, -2412816; CHECK-NEXT: vadd.vv v8, v9, v82817; CHECK-NEXT: vsrl.vi v9, v8, 42818; CHECK-NEXT: vadd.vv v8, v8, v92819; CHECK-NEXT: vand.vx v8, v8, a02820; CHECK-NEXT: li a0, 2572821; CHECK-NEXT: vmul.vx v8, v8, a02822; CHECK-NEXT: vsrl.vi v8, v8, 82823; CHECK-NEXT: ret2824 %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl)2825 ret <8 x i16> %v2826}2827 2828define <16 x i16> @vp_ctlz_zero_undef_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {2829; CHECK-LABEL: vp_ctlz_zero_undef_v16i16:2830; CHECK: # %bb.0:2831; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma2832; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t2833; CHECK-NEXT: lui a0, 52834; CHECK-NEXT: vor.vv v8, v8, v10, v0.t2835; CHECK-NEXT: addi a0, a0, 13652836; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t2837; CHECK-NEXT: vor.vv v8, v8, v10, v0.t2838; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t2839; CHECK-NEXT: vor.vv v8, v8, v10, v0.t2840; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t2841; CHECK-NEXT: vor.vv v8, v8, v10, v0.t2842; CHECK-NEXT: vnot.v v8, v8, v0.t2843; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t2844; CHECK-NEXT: vand.vx v10, v10, a0, v0.t2845; CHECK-NEXT: lui a0, 32846; CHECK-NEXT: addi a0, a0, 8192847; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t2848; CHECK-NEXT: vand.vx v10, v8, a0, v0.t2849; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2850; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2851; CHECK-NEXT: lui a0, 12852; CHECK-NEXT: addi a0, a0, -2412853; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t2854; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t2855; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t2856; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2857; CHECK-NEXT: li a0, 2572858; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t2859; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t2860; CHECK-NEXT: ret2861 %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 true, <16 x i1> %m, i32 %evl)2862 ret <16 x i16> %v2863}2864 2865define <16 x i16> @vp_ctlz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {2866; CHECK-LABEL: vp_ctlz_zero_undef_v16i16_unmasked:2867; CHECK: # %bb.0:2868; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma2869; CHECK-NEXT: vsrl.vi v10, v8, 12870; CHECK-NEXT: lui a0, 52871; CHECK-NEXT: vor.vv v8, v8, v102872; CHECK-NEXT: addi a0, a0, 13652873; CHECK-NEXT: vsrl.vi v10, v8, 22874; CHECK-NEXT: vor.vv v8, v8, v102875; CHECK-NEXT: vsrl.vi v10, v8, 42876; CHECK-NEXT: vor.vv v8, v8, v102877; CHECK-NEXT: vsrl.vi v10, v8, 82878; CHECK-NEXT: vor.vv v8, v8, v102879; CHECK-NEXT: vnot.v v8, v82880; CHECK-NEXT: vsrl.vi v10, v8, 12881; CHECK-NEXT: vand.vx v10, v10, a02882; CHECK-NEXT: lui a0, 32883; CHECK-NEXT: addi a0, a0, 8192884; CHECK-NEXT: vsub.vv v8, v8, v102885; CHECK-NEXT: vand.vx v10, v8, a02886; CHECK-NEXT: vsrl.vi v8, v8, 22887; CHECK-NEXT: vand.vx v8, v8, a02888; CHECK-NEXT: lui a0, 12889; CHECK-NEXT: addi a0, a0, -2412890; CHECK-NEXT: vadd.vv v8, v10, v82891; CHECK-NEXT: vsrl.vi v10, v8, 42892; CHECK-NEXT: vadd.vv v8, v8, v102893; CHECK-NEXT: vand.vx v8, v8, a02894; CHECK-NEXT: li a0, 2572895; CHECK-NEXT: vmul.vx v8, v8, a02896; CHECK-NEXT: vsrl.vi v8, v8, 82897; CHECK-NEXT: ret2898 %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl)2899 ret <16 x i16> %v2900}2901 2902define <2 x i32> @vp_ctlz_zero_undef_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {2903; CHECK-LABEL: vp_ctlz_zero_undef_v2i32:2904; CHECK: # %bb.0:2905; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma2906; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2907; CHECK-NEXT: lui a0, 3495252908; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2909; CHECK-NEXT: addi a0, a0, 13652910; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t2911; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2912; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2913; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2914; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t2915; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2916; CHECK-NEXT: vsrl.vi v9, v8, 16, v0.t2917; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2918; CHECK-NEXT: vnot.v v8, v8, v0.t2919; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2920; CHECK-NEXT: vand.vx v9, v9, a0, v0.t2921; CHECK-NEXT: lui a0, 2097152922; CHECK-NEXT: addi a0, a0, 8192923; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t2924; CHECK-NEXT: vand.vx v9, v8, a0, v0.t2925; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2926; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2927; CHECK-NEXT: lui a0, 616812928; CHECK-NEXT: addi a0, a0, -2412929; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t2930; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2931; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t2932; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2933; CHECK-NEXT: lui a0, 41122934; CHECK-NEXT: addi a0, a0, 2572935; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t2936; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t2937; CHECK-NEXT: ret2938 %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 true, <2 x i1> %m, i32 %evl)2939 ret <2 x i32> %v2940}2941 2942define <2 x i32> @vp_ctlz_zero_undef_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {2943; CHECK-LABEL: vp_ctlz_zero_undef_v2i32_unmasked:2944; CHECK: # %bb.0:2945; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma2946; CHECK-NEXT: vsrl.vi v9, v8, 12947; CHECK-NEXT: lui a0, 3495252948; CHECK-NEXT: vor.vv v8, v8, v92949; CHECK-NEXT: addi a0, a0, 13652950; CHECK-NEXT: vsrl.vi v9, v8, 22951; CHECK-NEXT: vor.vv v8, v8, v92952; CHECK-NEXT: vsrl.vi v9, v8, 42953; CHECK-NEXT: vor.vv v8, v8, v92954; CHECK-NEXT: vsrl.vi v9, v8, 82955; CHECK-NEXT: vor.vv v8, v8, v92956; CHECK-NEXT: vsrl.vi v9, v8, 162957; CHECK-NEXT: vor.vv v8, v8, v92958; CHECK-NEXT: vnot.v v8, v82959; CHECK-NEXT: vsrl.vi v9, v8, 12960; CHECK-NEXT: vand.vx v9, v9, a02961; CHECK-NEXT: lui a0, 2097152962; CHECK-NEXT: addi a0, a0, 8192963; CHECK-NEXT: vsub.vv v8, v8, v92964; CHECK-NEXT: vand.vx v9, v8, a02965; CHECK-NEXT: vsrl.vi v8, v8, 22966; CHECK-NEXT: vand.vx v8, v8, a02967; CHECK-NEXT: lui a0, 616812968; CHECK-NEXT: addi a0, a0, -2412969; CHECK-NEXT: vadd.vv v8, v9, v82970; CHECK-NEXT: vsrl.vi v9, v8, 42971; CHECK-NEXT: vadd.vv v8, v8, v92972; CHECK-NEXT: vand.vx v8, v8, a02973; CHECK-NEXT: lui a0, 41122974; CHECK-NEXT: addi a0, a0, 2572975; CHECK-NEXT: vmul.vx v8, v8, a02976; CHECK-NEXT: vsrl.vi v8, v8, 242977; CHECK-NEXT: ret2978 %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl)2979 ret <2 x i32> %v2980}2981 2982define <4 x i32> @vp_ctlz_zero_undef_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {2983; CHECK-LABEL: vp_ctlz_zero_undef_v4i32:2984; CHECK: # %bb.0:2985; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma2986; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2987; CHECK-NEXT: lui a0, 3495252988; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2989; CHECK-NEXT: addi a0, a0, 13652990; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t2991; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2992; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2993; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2994; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t2995; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2996; CHECK-NEXT: vsrl.vi v9, v8, 16, v0.t2997; CHECK-NEXT: vor.vv v8, v8, v9, v0.t2998; CHECK-NEXT: vnot.v v8, v8, v0.t2999; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t3000; CHECK-NEXT: vand.vx v9, v9, a0, v0.t3001; CHECK-NEXT: lui a0, 2097153002; CHECK-NEXT: addi a0, a0, 8193003; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t3004; CHECK-NEXT: vand.vx v9, v8, a0, v0.t3005; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t3006; CHECK-NEXT: vand.vx v8, v8, a0, v0.t3007; CHECK-NEXT: lui a0, 616813008; CHECK-NEXT: addi a0, a0, -2413009; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t3010; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t3011; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t3012; CHECK-NEXT: vand.vx v8, v8, a0, v0.t3013; CHECK-NEXT: lui a0, 41123014; CHECK-NEXT: addi a0, a0, 2573015; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t3016; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t3017; CHECK-NEXT: ret3018 %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 true, <4 x i1> %m, i32 %evl)3019 ret <4 x i32> %v3020}3021 3022define <4 x i32> @vp_ctlz_zero_undef_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {3023; CHECK-LABEL: vp_ctlz_zero_undef_v4i32_unmasked:3024; CHECK: # %bb.0:3025; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma3026; CHECK-NEXT: vsrl.vi v9, v8, 13027; CHECK-NEXT: lui a0, 3495253028; CHECK-NEXT: vor.vv v8, v8, v93029; CHECK-NEXT: addi a0, a0, 13653030; CHECK-NEXT: vsrl.vi v9, v8, 23031; CHECK-NEXT: vor.vv v8, v8, v93032; CHECK-NEXT: vsrl.vi v9, v8, 43033; CHECK-NEXT: vor.vv v8, v8, v93034; CHECK-NEXT: vsrl.vi v9, v8, 83035; CHECK-NEXT: vor.vv v8, v8, v93036; CHECK-NEXT: vsrl.vi v9, v8, 163037; CHECK-NEXT: vor.vv v8, v8, v93038; CHECK-NEXT: vnot.v v8, v83039; CHECK-NEXT: vsrl.vi v9, v8, 13040; CHECK-NEXT: vand.vx v9, v9, a03041; CHECK-NEXT: lui a0, 2097153042; CHECK-NEXT: addi a0, a0, 8193043; CHECK-NEXT: vsub.vv v8, v8, v93044; CHECK-NEXT: vand.vx v9, v8, a03045; CHECK-NEXT: vsrl.vi v8, v8, 23046; CHECK-NEXT: vand.vx v8, v8, a03047; CHECK-NEXT: lui a0, 616813048; CHECK-NEXT: addi a0, a0, -2413049; CHECK-NEXT: vadd.vv v8, v9, v83050; CHECK-NEXT: vsrl.vi v9, v8, 43051; CHECK-NEXT: vadd.vv v8, v8, v93052; CHECK-NEXT: vand.vx v8, v8, a03053; CHECK-NEXT: lui a0, 41123054; CHECK-NEXT: addi a0, a0, 2573055; CHECK-NEXT: vmul.vx v8, v8, a03056; CHECK-NEXT: vsrl.vi v8, v8, 243057; CHECK-NEXT: ret3058 %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl)3059 ret <4 x i32> %v3060}3061 3062define <8 x i32> @vp_ctlz_zero_undef_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {3063; CHECK-LABEL: vp_ctlz_zero_undef_v8i32:3064; CHECK: # %bb.0:3065; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma3066; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t3067; CHECK-NEXT: lui a0, 3495253068; CHECK-NEXT: vor.vv v8, v8, v10, v0.t3069; CHECK-NEXT: addi a0, a0, 13653070; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t3071; CHECK-NEXT: vor.vv v8, v8, v10, v0.t3072; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t3073; CHECK-NEXT: vor.vv v8, v8, v10, v0.t3074; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t3075; CHECK-NEXT: vor.vv v8, v8, v10, v0.t3076; CHECK-NEXT: vsrl.vi v10, v8, 16, v0.t3077; CHECK-NEXT: vor.vv v8, v8, v10, v0.t3078; CHECK-NEXT: vnot.v v8, v8, v0.t3079; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t3080; CHECK-NEXT: vand.vx v10, v10, a0, v0.t3081; CHECK-NEXT: lui a0, 2097153082; CHECK-NEXT: addi a0, a0, 8193083; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t3084; CHECK-NEXT: vand.vx v10, v8, a0, v0.t3085; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t3086; CHECK-NEXT: vand.vx v8, v8, a0, v0.t3087; CHECK-NEXT: lui a0, 616813088; CHECK-NEXT: addi a0, a0, -2413089; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t3090; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t3091; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t3092; CHECK-NEXT: vand.vx v8, v8, a0, v0.t3093; CHECK-NEXT: lui a0, 41123094; CHECK-NEXT: addi a0, a0, 2573095; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t3096; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t3097; CHECK-NEXT: ret3098 %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 true, <8 x i1> %m, i32 %evl)3099 ret <8 x i32> %v3100}3101 3102define <8 x i32> @vp_ctlz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {3103; CHECK-LABEL: vp_ctlz_zero_undef_v8i32_unmasked:3104; CHECK: # %bb.0:3105; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma3106; CHECK-NEXT: vsrl.vi v10, v8, 13107; CHECK-NEXT: lui a0, 3495253108; CHECK-NEXT: vor.vv v8, v8, v103109; CHECK-NEXT: addi a0, a0, 13653110; CHECK-NEXT: vsrl.vi v10, v8, 23111; CHECK-NEXT: vor.vv v8, v8, v103112; CHECK-NEXT: vsrl.vi v10, v8, 43113; CHECK-NEXT: vor.vv v8, v8, v103114; CHECK-NEXT: vsrl.vi v10, v8, 83115; CHECK-NEXT: vor.vv v8, v8, v103116; CHECK-NEXT: vsrl.vi v10, v8, 163117; CHECK-NEXT: vor.vv v8, v8, v103118; CHECK-NEXT: vnot.v v8, v83119; CHECK-NEXT: vsrl.vi v10, v8, 13120; CHECK-NEXT: vand.vx v10, v10, a03121; CHECK-NEXT: lui a0, 2097153122; CHECK-NEXT: addi a0, a0, 8193123; CHECK-NEXT: vsub.vv v8, v8, v103124; CHECK-NEXT: vand.vx v10, v8, a03125; CHECK-NEXT: vsrl.vi v8, v8, 23126; CHECK-NEXT: vand.vx v8, v8, a03127; CHECK-NEXT: lui a0, 616813128; CHECK-NEXT: addi a0, a0, -2413129; CHECK-NEXT: vadd.vv v8, v10, v83130; CHECK-NEXT: vsrl.vi v10, v8, 43131; CHECK-NEXT: vadd.vv v8, v8, v103132; CHECK-NEXT: vand.vx v8, v8, a03133; CHECK-NEXT: lui a0, 41123134; CHECK-NEXT: addi a0, a0, 2573135; CHECK-NEXT: vmul.vx v8, v8, a03136; CHECK-NEXT: vsrl.vi v8, v8, 243137; CHECK-NEXT: ret3138 %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl)3139 ret <8 x i32> %v3140}3141 3142define <16 x i32> @vp_ctlz_zero_undef_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {3143; CHECK-LABEL: vp_ctlz_zero_undef_v16i32:3144; CHECK: # %bb.0:3145; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma3146; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t3147; CHECK-NEXT: lui a0, 3495253148; CHECK-NEXT: vor.vv v8, v8, v12, v0.t3149; CHECK-NEXT: addi a0, a0, 13653150; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t3151; CHECK-NEXT: vor.vv v8, v8, v12, v0.t3152; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t3153; CHECK-NEXT: vor.vv v8, v8, v12, v0.t3154; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t3155; CHECK-NEXT: vor.vv v8, v8, v12, v0.t3156; CHECK-NEXT: vsrl.vi v12, v8, 16, v0.t3157; CHECK-NEXT: vor.vv v8, v8, v12, v0.t3158; CHECK-NEXT: vnot.v v8, v8, v0.t3159; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t3160; CHECK-NEXT: vand.vx v12, v12, a0, v0.t3161; CHECK-NEXT: lui a0, 2097153162; CHECK-NEXT: addi a0, a0, 8193163; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t3164; CHECK-NEXT: vand.vx v12, v8, a0, v0.t3165; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t3166; CHECK-NEXT: vand.vx v8, v8, a0, v0.t3167; CHECK-NEXT: lui a0, 616813168; CHECK-NEXT: addi a0, a0, -2413169; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t3170; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t3171; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t3172; CHECK-NEXT: vand.vx v8, v8, a0, v0.t3173; CHECK-NEXT: lui a0, 41123174; CHECK-NEXT: addi a0, a0, 2573175; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t3176; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t3177; CHECK-NEXT: ret3178 %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 true, <16 x i1> %m, i32 %evl)3179 ret <16 x i32> %v3180}3181 3182define <16 x i32> @vp_ctlz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {3183; CHECK-LABEL: vp_ctlz_zero_undef_v16i32_unmasked:3184; CHECK: # %bb.0:3185; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma3186; CHECK-NEXT: vsrl.vi v12, v8, 13187; CHECK-NEXT: lui a0, 3495253188; CHECK-NEXT: vor.vv v8, v8, v123189; CHECK-NEXT: addi a0, a0, 13653190; CHECK-NEXT: vsrl.vi v12, v8, 23191; CHECK-NEXT: vor.vv v8, v8, v123192; CHECK-NEXT: vsrl.vi v12, v8, 43193; CHECK-NEXT: vor.vv v8, v8, v123194; CHECK-NEXT: vsrl.vi v12, v8, 83195; CHECK-NEXT: vor.vv v8, v8, v123196; CHECK-NEXT: vsrl.vi v12, v8, 163197; CHECK-NEXT: vor.vv v8, v8, v123198; CHECK-NEXT: vnot.v v8, v83199; CHECK-NEXT: vsrl.vi v12, v8, 13200; CHECK-NEXT: vand.vx v12, v12, a03201; CHECK-NEXT: lui a0, 2097153202; CHECK-NEXT: addi a0, a0, 8193203; CHECK-NEXT: vsub.vv v8, v8, v123204; CHECK-NEXT: vand.vx v12, v8, a03205; CHECK-NEXT: vsrl.vi v8, v8, 23206; CHECK-NEXT: vand.vx v8, v8, a03207; CHECK-NEXT: lui a0, 616813208; CHECK-NEXT: addi a0, a0, -2413209; CHECK-NEXT: vadd.vv v8, v12, v83210; CHECK-NEXT: vsrl.vi v12, v8, 43211; CHECK-NEXT: vadd.vv v8, v8, v123212; CHECK-NEXT: vand.vx v8, v8, a03213; CHECK-NEXT: lui a0, 41123214; CHECK-NEXT: addi a0, a0, 2573215; CHECK-NEXT: vmul.vx v8, v8, a03216; CHECK-NEXT: vsrl.vi v8, v8, 243217; CHECK-NEXT: ret3218 %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl)3219 ret <16 x i32> %v3220}3221 3222define <2 x i64> @vp_ctlz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {3223; RV32-LABEL: vp_ctlz_zero_undef_v2i64:3224; RV32: # %bb.0:3225; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma3226; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t3227; RV32-NEXT: lui a1, 3495253228; RV32-NEXT: addi a1, a1, 13653229; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma3230; RV32-NEXT: vmv.v.x v10, a13231; RV32-NEXT: li a1, 323232; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma3233; RV32-NEXT: vor.vv v8, v8, v9, v0.t3234; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t3235; RV32-NEXT: vor.vv v8, v8, v9, v0.t3236; RV32-NEXT: vsrl.vi v9, v8, 4, v0.t3237; RV32-NEXT: vor.vv v8, v8, v9, v0.t3238; RV32-NEXT: vsrl.vi v9, v8, 8, v0.t3239; RV32-NEXT: vor.vv v8, v8, v9, v0.t3240; RV32-NEXT: vsrl.vi v9, v8, 16, v0.t3241; RV32-NEXT: vor.vv v8, v8, v9, v0.t3242; RV32-NEXT: vsrl.vx v9, v8, a1, v0.t3243; RV32-NEXT: lui a1, 2097153244; RV32-NEXT: addi a1, a1, 8193245; RV32-NEXT: vor.vv v8, v8, v9, v0.t3246; RV32-NEXT: vnot.v v8, v8, v0.t3247; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t3248; RV32-NEXT: vand.vv v9, v9, v10, v0.t3249; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma3250; RV32-NEXT: vmv.v.x v10, a13251; RV32-NEXT: lui a1, 616813252; RV32-NEXT: addi a1, a1, -2413253; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma3254; RV32-NEXT: vsub.vv v8, v8, v9, v0.t3255; RV32-NEXT: vand.vv v9, v8, v10, v0.t3256; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t3257; RV32-NEXT: vand.vv v8, v8, v10, v0.t3258; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma3259; RV32-NEXT: vmv.v.x v10, a13260; RV32-NEXT: lui a1, 41123261; RV32-NEXT: addi a1, a1, 2573262; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma3263; RV32-NEXT: vadd.vv v8, v9, v8, v0.t3264; RV32-NEXT: vsrl.vi v9, v8, 4, v0.t3265; RV32-NEXT: vadd.vv v8, v8, v9, v0.t3266; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma3267; RV32-NEXT: vmv.v.x v9, a13268; RV32-NEXT: li a1, 563269; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma3270; RV32-NEXT: vand.vv v8, v8, v10, v0.t3271; RV32-NEXT: vmul.vv v8, v8, v9, v0.t3272; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t3273; RV32-NEXT: ret3274;3275; RV64-LABEL: vp_ctlz_zero_undef_v2i64:3276; RV64: # %bb.0:3277; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma3278; RV64-NEXT: vsrl.vi v9, v8, 1, v0.t3279; RV64-NEXT: lui a0, 3495253280; RV64-NEXT: lui a1, 2097153281; RV64-NEXT: lui a2, 616813282; RV64-NEXT: lui a3, 41123283; RV64-NEXT: addi a0, a0, 13653284; RV64-NEXT: addi a1, a1, 8193285; RV64-NEXT: addi a2, a2, -2413286; RV64-NEXT: addi a3, a3, 2573287; RV64-NEXT: slli a4, a0, 323288; RV64-NEXT: add a0, a0, a43289; RV64-NEXT: slli a4, a1, 323290; RV64-NEXT: add a1, a1, a43291; RV64-NEXT: slli a4, a2, 323292; RV64-NEXT: add a2, a2, a43293; RV64-NEXT: slli a4, a3, 323294; RV64-NEXT: add a3, a3, a43295; RV64-NEXT: li a4, 323296; RV64-NEXT: vor.vv v8, v8, v9, v0.t3297; RV64-NEXT: vsrl.vi v9, v8, 2, v0.t3298; RV64-NEXT: vor.vv v8, v8, v9, v0.t3299; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t3300; RV64-NEXT: vor.vv v8, v8, v9, v0.t3301; RV64-NEXT: vsrl.vi v9, v8, 8, v0.t3302; RV64-NEXT: vor.vv v8, v8, v9, v0.t3303; RV64-NEXT: vsrl.vi v9, v8, 16, v0.t3304; RV64-NEXT: vor.vv v8, v8, v9, v0.t3305; RV64-NEXT: vsrl.vx v9, v8, a4, v0.t3306; RV64-NEXT: vor.vv v8, v8, v9, v0.t3307; RV64-NEXT: vnot.v v8, v8, v0.t3308; RV64-NEXT: vsrl.vi v9, v8, 1, v0.t3309; RV64-NEXT: vand.vx v9, v9, a0, v0.t3310; RV64-NEXT: vsub.vv v8, v8, v9, v0.t3311; RV64-NEXT: vand.vx v9, v8, a1, v0.t3312; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t3313; RV64-NEXT: vand.vx v8, v8, a1, v0.t3314; RV64-NEXT: vadd.vv v8, v9, v8, v0.t3315; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t3316; RV64-NEXT: vadd.vv v8, v8, v9, v0.t3317; RV64-NEXT: vand.vx v8, v8, a2, v0.t3318; RV64-NEXT: li a0, 563319; RV64-NEXT: vmul.vx v8, v8, a3, v0.t3320; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t3321; RV64-NEXT: ret3322 %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 true, <2 x i1> %m, i32 %evl)3323 ret <2 x i64> %v3324}3325 3326define <2 x i64> @vp_ctlz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {3327; RV32-LABEL: vp_ctlz_zero_undef_v2i64_unmasked:3328; RV32: # %bb.0:3329; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma3330; RV32-NEXT: vsrl.vi v9, v8, 13331; RV32-NEXT: lui a1, 3495253332; RV32-NEXT: addi a1, a1, 13653333; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma3334; RV32-NEXT: vmv.v.x v10, a13335; RV32-NEXT: li a1, 323336; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma3337; RV32-NEXT: vor.vv v8, v8, v93338; RV32-NEXT: vsrl.vi v9, v8, 23339; RV32-NEXT: vor.vv v8, v8, v93340; RV32-NEXT: vsrl.vi v9, v8, 43341; RV32-NEXT: vor.vv v8, v8, v93342; RV32-NEXT: vsrl.vi v9, v8, 83343; RV32-NEXT: vor.vv v8, v8, v93344; RV32-NEXT: vsrl.vi v9, v8, 163345; RV32-NEXT: vor.vv v8, v8, v93346; RV32-NEXT: vsrl.vx v9, v8, a13347; RV32-NEXT: lui a1, 2097153348; RV32-NEXT: addi a1, a1, 8193349; RV32-NEXT: vor.vv v8, v8, v93350; RV32-NEXT: vnot.v v8, v83351; RV32-NEXT: vsrl.vi v9, v8, 13352; RV32-NEXT: vand.vv v9, v9, v103353; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma3354; RV32-NEXT: vmv.v.x v10, a13355; RV32-NEXT: lui a1, 616813356; RV32-NEXT: addi a1, a1, -2413357; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma3358; RV32-NEXT: vsub.vv v8, v8, v93359; RV32-NEXT: vand.vv v9, v8, v103360; RV32-NEXT: vsrl.vi v8, v8, 23361; RV32-NEXT: vand.vv v8, v8, v103362; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma3363; RV32-NEXT: vmv.v.x v10, a13364; RV32-NEXT: lui a1, 41123365; RV32-NEXT: addi a1, a1, 2573366; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma3367; RV32-NEXT: vadd.vv v8, v9, v83368; RV32-NEXT: vsrl.vi v9, v8, 43369; RV32-NEXT: vadd.vv v8, v8, v93370; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma3371; RV32-NEXT: vmv.v.x v9, a13372; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma3373; RV32-NEXT: vand.vv v8, v8, v103374; RV32-NEXT: vmul.vv v8, v8, v93375; RV32-NEXT: li a0, 563376; RV32-NEXT: vsrl.vx v8, v8, a03377; RV32-NEXT: ret3378;3379; RV64-LABEL: vp_ctlz_zero_undef_v2i64_unmasked:3380; RV64: # %bb.0:3381; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma3382; RV64-NEXT: vsrl.vi v9, v8, 13383; RV64-NEXT: lui a0, 3495253384; RV64-NEXT: lui a1, 2097153385; RV64-NEXT: lui a2, 616813386; RV64-NEXT: lui a3, 41123387; RV64-NEXT: addi a0, a0, 13653388; RV64-NEXT: addi a1, a1, 8193389; RV64-NEXT: addi a2, a2, -2413390; RV64-NEXT: addi a3, a3, 2573391; RV64-NEXT: slli a4, a0, 323392; RV64-NEXT: add a0, a0, a43393; RV64-NEXT: slli a4, a1, 323394; RV64-NEXT: add a1, a1, a43395; RV64-NEXT: slli a4, a2, 323396; RV64-NEXT: add a2, a2, a43397; RV64-NEXT: slli a4, a3, 323398; RV64-NEXT: add a3, a3, a43399; RV64-NEXT: li a4, 323400; RV64-NEXT: vor.vv v8, v8, v93401; RV64-NEXT: vsrl.vi v9, v8, 23402; RV64-NEXT: vor.vv v8, v8, v93403; RV64-NEXT: vsrl.vi v9, v8, 43404; RV64-NEXT: vor.vv v8, v8, v93405; RV64-NEXT: vsrl.vi v9, v8, 83406; RV64-NEXT: vor.vv v8, v8, v93407; RV64-NEXT: vsrl.vi v9, v8, 163408; RV64-NEXT: vor.vv v8, v8, v93409; RV64-NEXT: vsrl.vx v9, v8, a43410; RV64-NEXT: vor.vv v8, v8, v93411; RV64-NEXT: vnot.v v8, v83412; RV64-NEXT: vsrl.vi v9, v8, 13413; RV64-NEXT: vand.vx v9, v9, a03414; RV64-NEXT: vsub.vv v8, v8, v93415; RV64-NEXT: vand.vx v9, v8, a13416; RV64-NEXT: vsrl.vi v8, v8, 23417; RV64-NEXT: vand.vx v8, v8, a13418; RV64-NEXT: vadd.vv v8, v9, v83419; RV64-NEXT: vsrl.vi v9, v8, 43420; RV64-NEXT: vadd.vv v8, v8, v93421; RV64-NEXT: vand.vx v8, v8, a23422; RV64-NEXT: vmul.vx v8, v8, a33423; RV64-NEXT: li a0, 563424; RV64-NEXT: vsrl.vx v8, v8, a03425; RV64-NEXT: ret3426 %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl)3427 ret <2 x i64> %v3428}3429 3430define <4 x i64> @vp_ctlz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {3431; RV32-LABEL: vp_ctlz_zero_undef_v4i64:3432; RV32: # %bb.0:3433; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma3434; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t3435; RV32-NEXT: lui a1, 3495253436; RV32-NEXT: addi a1, a1, 13653437; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma3438; RV32-NEXT: vmv.v.x v10, a13439; RV32-NEXT: li a1, 323440; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma3441; RV32-NEXT: vor.vv v8, v8, v12, v0.t3442; RV32-NEXT: vsrl.vi v12, v8, 2, v0.t3443; RV32-NEXT: vor.vv v8, v8, v12, v0.t3444; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t3445; RV32-NEXT: vor.vv v8, v8, v12, v0.t3446; RV32-NEXT: vsrl.vi v12, v8, 8, v0.t3447; RV32-NEXT: vor.vv v8, v8, v12, v0.t3448; RV32-NEXT: vsrl.vi v12, v8, 16, v0.t3449; RV32-NEXT: vor.vv v8, v8, v12, v0.t3450; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t3451; RV32-NEXT: lui a1, 2097153452; RV32-NEXT: addi a1, a1, 8193453; RV32-NEXT: vor.vv v8, v8, v12, v0.t3454; RV32-NEXT: vnot.v v8, v8, v0.t3455; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t3456; RV32-NEXT: vand.vv v10, v12, v10, v0.t3457; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma3458; RV32-NEXT: vmv.v.x v12, a13459; RV32-NEXT: lui a1, 616813460; RV32-NEXT: addi a1, a1, -2413461; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma3462; RV32-NEXT: vsub.vv v8, v8, v10, v0.t3463; RV32-NEXT: vand.vv v10, v8, v12, v0.t3464; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t3465; RV32-NEXT: vand.vv v8, v8, v12, v0.t3466; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma3467; RV32-NEXT: vmv.v.x v12, a13468; RV32-NEXT: lui a1, 41123469; RV32-NEXT: addi a1, a1, 2573470; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma3471; RV32-NEXT: vadd.vv v8, v10, v8, v0.t3472; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t3473; RV32-NEXT: vadd.vv v8, v8, v10, v0.t3474; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma3475; RV32-NEXT: vmv.v.x v10, a13476; RV32-NEXT: li a1, 563477; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma3478; RV32-NEXT: vand.vv v8, v8, v12, v0.t3479; RV32-NEXT: vmul.vv v8, v8, v10, v0.t3480; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t3481; RV32-NEXT: ret3482;3483; RV64-LABEL: vp_ctlz_zero_undef_v4i64:3484; RV64: # %bb.0:3485; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma3486; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t3487; RV64-NEXT: lui a0, 3495253488; RV64-NEXT: lui a1, 2097153489; RV64-NEXT: lui a2, 616813490; RV64-NEXT: lui a3, 41123491; RV64-NEXT: addi a0, a0, 13653492; RV64-NEXT: addi a1, a1, 8193493; RV64-NEXT: addi a2, a2, -2413494; RV64-NEXT: addi a3, a3, 2573495; RV64-NEXT: slli a4, a0, 323496; RV64-NEXT: add a0, a0, a43497; RV64-NEXT: slli a4, a1, 323498; RV64-NEXT: add a1, a1, a43499; RV64-NEXT: slli a4, a2, 323500; RV64-NEXT: add a2, a2, a43501; RV64-NEXT: slli a4, a3, 323502; RV64-NEXT: add a3, a3, a43503; RV64-NEXT: li a4, 323504; RV64-NEXT: vor.vv v8, v8, v10, v0.t3505; RV64-NEXT: vsrl.vi v10, v8, 2, v0.t3506; RV64-NEXT: vor.vv v8, v8, v10, v0.t3507; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t3508; RV64-NEXT: vor.vv v8, v8, v10, v0.t3509; RV64-NEXT: vsrl.vi v10, v8, 8, v0.t3510; RV64-NEXT: vor.vv v8, v8, v10, v0.t3511; RV64-NEXT: vsrl.vi v10, v8, 16, v0.t3512; RV64-NEXT: vor.vv v8, v8, v10, v0.t3513; RV64-NEXT: vsrl.vx v10, v8, a4, v0.t3514; RV64-NEXT: vor.vv v8, v8, v10, v0.t3515; RV64-NEXT: vnot.v v8, v8, v0.t3516; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t3517; RV64-NEXT: vand.vx v10, v10, a0, v0.t3518; RV64-NEXT: vsub.vv v8, v8, v10, v0.t3519; RV64-NEXT: vand.vx v10, v8, a1, v0.t3520; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t3521; RV64-NEXT: vand.vx v8, v8, a1, v0.t3522; RV64-NEXT: vadd.vv v8, v10, v8, v0.t3523; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t3524; RV64-NEXT: vadd.vv v8, v8, v10, v0.t3525; RV64-NEXT: vand.vx v8, v8, a2, v0.t3526; RV64-NEXT: li a0, 563527; RV64-NEXT: vmul.vx v8, v8, a3, v0.t3528; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t3529; RV64-NEXT: ret3530 %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 true, <4 x i1> %m, i32 %evl)3531 ret <4 x i64> %v3532}3533 3534define <4 x i64> @vp_ctlz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {3535; RV32-LABEL: vp_ctlz_zero_undef_v4i64_unmasked:3536; RV32: # %bb.0:3537; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma3538; RV32-NEXT: vsrl.vi v10, v8, 13539; RV32-NEXT: lui a1, 3495253540; RV32-NEXT: addi a1, a1, 13653541; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma3542; RV32-NEXT: vmv.v.x v12, a13543; RV32-NEXT: li a1, 323544; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma3545; RV32-NEXT: vor.vv v8, v8, v103546; RV32-NEXT: vsrl.vi v10, v8, 23547; RV32-NEXT: vor.vv v8, v8, v103548; RV32-NEXT: vsrl.vi v10, v8, 43549; RV32-NEXT: vor.vv v8, v8, v103550; RV32-NEXT: vsrl.vi v10, v8, 83551; RV32-NEXT: vor.vv v8, v8, v103552; RV32-NEXT: vsrl.vi v10, v8, 163553; RV32-NEXT: vor.vv v8, v8, v103554; RV32-NEXT: vsrl.vx v10, v8, a13555; RV32-NEXT: lui a1, 2097153556; RV32-NEXT: addi a1, a1, 8193557; RV32-NEXT: vor.vv v8, v8, v103558; RV32-NEXT: vnot.v v8, v83559; RV32-NEXT: vsrl.vi v10, v8, 13560; RV32-NEXT: vand.vv v10, v10, v123561; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma3562; RV32-NEXT: vmv.v.x v12, a13563; RV32-NEXT: lui a1, 616813564; RV32-NEXT: addi a1, a1, -2413565; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma3566; RV32-NEXT: vsub.vv v8, v8, v103567; RV32-NEXT: vand.vv v10, v8, v123568; RV32-NEXT: vsrl.vi v8, v8, 23569; RV32-NEXT: vand.vv v8, v8, v123570; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma3571; RV32-NEXT: vmv.v.x v12, a13572; RV32-NEXT: lui a1, 41123573; RV32-NEXT: addi a1, a1, 2573574; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma3575; RV32-NEXT: vadd.vv v8, v10, v83576; RV32-NEXT: vsrl.vi v10, v8, 43577; RV32-NEXT: vadd.vv v8, v8, v103578; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma3579; RV32-NEXT: vmv.v.x v10, a13580; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma3581; RV32-NEXT: vand.vv v8, v8, v123582; RV32-NEXT: vmul.vv v8, v8, v103583; RV32-NEXT: li a0, 563584; RV32-NEXT: vsrl.vx v8, v8, a03585; RV32-NEXT: ret3586;3587; RV64-LABEL: vp_ctlz_zero_undef_v4i64_unmasked:3588; RV64: # %bb.0:3589; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma3590; RV64-NEXT: vsrl.vi v10, v8, 13591; RV64-NEXT: lui a0, 3495253592; RV64-NEXT: lui a1, 2097153593; RV64-NEXT: lui a2, 616813594; RV64-NEXT: lui a3, 41123595; RV64-NEXT: addi a0, a0, 13653596; RV64-NEXT: addi a1, a1, 8193597; RV64-NEXT: addi a2, a2, -2413598; RV64-NEXT: addi a3, a3, 2573599; RV64-NEXT: slli a4, a0, 323600; RV64-NEXT: add a0, a0, a43601; RV64-NEXT: slli a4, a1, 323602; RV64-NEXT: add a1, a1, a43603; RV64-NEXT: slli a4, a2, 323604; RV64-NEXT: add a2, a2, a43605; RV64-NEXT: slli a4, a3, 323606; RV64-NEXT: add a3, a3, a43607; RV64-NEXT: li a4, 323608; RV64-NEXT: vor.vv v8, v8, v103609; RV64-NEXT: vsrl.vi v10, v8, 23610; RV64-NEXT: vor.vv v8, v8, v103611; RV64-NEXT: vsrl.vi v10, v8, 43612; RV64-NEXT: vor.vv v8, v8, v103613; RV64-NEXT: vsrl.vi v10, v8, 83614; RV64-NEXT: vor.vv v8, v8, v103615; RV64-NEXT: vsrl.vi v10, v8, 163616; RV64-NEXT: vor.vv v8, v8, v103617; RV64-NEXT: vsrl.vx v10, v8, a43618; RV64-NEXT: vor.vv v8, v8, v103619; RV64-NEXT: vnot.v v8, v83620; RV64-NEXT: vsrl.vi v10, v8, 13621; RV64-NEXT: vand.vx v10, v10, a03622; RV64-NEXT: vsub.vv v8, v8, v103623; RV64-NEXT: vand.vx v10, v8, a13624; RV64-NEXT: vsrl.vi v8, v8, 23625; RV64-NEXT: vand.vx v8, v8, a13626; RV64-NEXT: vadd.vv v8, v10, v83627; RV64-NEXT: vsrl.vi v10, v8, 43628; RV64-NEXT: vadd.vv v8, v8, v103629; RV64-NEXT: vand.vx v8, v8, a23630; RV64-NEXT: vmul.vx v8, v8, a33631; RV64-NEXT: li a0, 563632; RV64-NEXT: vsrl.vx v8, v8, a03633; RV64-NEXT: ret3634 %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl)3635 ret <4 x i64> %v3636}3637 3638define <8 x i64> @vp_ctlz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {3639; RV32-LABEL: vp_ctlz_zero_undef_v8i64:3640; RV32: # %bb.0:3641; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma3642; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t3643; RV32-NEXT: lui a1, 3495253644; RV32-NEXT: addi a1, a1, 13653645; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma3646; RV32-NEXT: vmv.v.x v12, a13647; RV32-NEXT: li a1, 323648; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma3649; RV32-NEXT: vor.vv v8, v8, v16, v0.t3650; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t3651; RV32-NEXT: vor.vv v8, v8, v16, v0.t3652; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t3653; RV32-NEXT: vor.vv v8, v8, v16, v0.t3654; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t3655; RV32-NEXT: vor.vv v8, v8, v16, v0.t3656; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t3657; RV32-NEXT: vor.vv v8, v8, v16, v0.t3658; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t3659; RV32-NEXT: lui a1, 2097153660; RV32-NEXT: addi a1, a1, 8193661; RV32-NEXT: vor.vv v8, v8, v16, v0.t3662; RV32-NEXT: vnot.v v16, v8, v0.t3663; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t3664; RV32-NEXT: vand.vv v12, v8, v12, v0.t3665; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma3666; RV32-NEXT: vmv.v.x v8, a13667; RV32-NEXT: lui a1, 616813668; RV32-NEXT: addi a1, a1, -2413669; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma3670; RV32-NEXT: vsub.vv v12, v16, v12, v0.t3671; RV32-NEXT: vand.vv v16, v12, v8, v0.t3672; RV32-NEXT: vsrl.vi v12, v12, 2, v0.t3673; RV32-NEXT: vand.vv v8, v12, v8, v0.t3674; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma3675; RV32-NEXT: vmv.v.x v12, a13676; RV32-NEXT: lui a1, 41123677; RV32-NEXT: addi a1, a1, 2573678; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma3679; RV32-NEXT: vadd.vv v8, v16, v8, v0.t3680; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t3681; RV32-NEXT: vadd.vv v8, v8, v16, v0.t3682; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma3683; RV32-NEXT: vmv.v.x v16, a13684; RV32-NEXT: li a1, 563685; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma3686; RV32-NEXT: vand.vv v8, v8, v12, v0.t3687; RV32-NEXT: vmul.vv v8, v8, v16, v0.t3688; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t3689; RV32-NEXT: ret3690;3691; RV64-LABEL: vp_ctlz_zero_undef_v8i64:3692; RV64: # %bb.0:3693; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma3694; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t3695; RV64-NEXT: lui a0, 3495253696; RV64-NEXT: lui a1, 2097153697; RV64-NEXT: lui a2, 616813698; RV64-NEXT: lui a3, 41123699; RV64-NEXT: addi a0, a0, 13653700; RV64-NEXT: addi a1, a1, 8193701; RV64-NEXT: addi a2, a2, -2413702; RV64-NEXT: addi a3, a3, 2573703; RV64-NEXT: slli a4, a0, 323704; RV64-NEXT: add a0, a0, a43705; RV64-NEXT: slli a4, a1, 323706; RV64-NEXT: add a1, a1, a43707; RV64-NEXT: slli a4, a2, 323708; RV64-NEXT: add a2, a2, a43709; RV64-NEXT: slli a4, a3, 323710; RV64-NEXT: add a3, a3, a43711; RV64-NEXT: li a4, 323712; RV64-NEXT: vor.vv v8, v8, v12, v0.t3713; RV64-NEXT: vsrl.vi v12, v8, 2, v0.t3714; RV64-NEXT: vor.vv v8, v8, v12, v0.t3715; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t3716; RV64-NEXT: vor.vv v8, v8, v12, v0.t3717; RV64-NEXT: vsrl.vi v12, v8, 8, v0.t3718; RV64-NEXT: vor.vv v8, v8, v12, v0.t3719; RV64-NEXT: vsrl.vi v12, v8, 16, v0.t3720; RV64-NEXT: vor.vv v8, v8, v12, v0.t3721; RV64-NEXT: vsrl.vx v12, v8, a4, v0.t3722; RV64-NEXT: vor.vv v8, v8, v12, v0.t3723; RV64-NEXT: vnot.v v8, v8, v0.t3724; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t3725; RV64-NEXT: vand.vx v12, v12, a0, v0.t3726; RV64-NEXT: vsub.vv v8, v8, v12, v0.t3727; RV64-NEXT: vand.vx v12, v8, a1, v0.t3728; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t3729; RV64-NEXT: vand.vx v8, v8, a1, v0.t3730; RV64-NEXT: vadd.vv v8, v12, v8, v0.t3731; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t3732; RV64-NEXT: vadd.vv v8, v8, v12, v0.t3733; RV64-NEXT: vand.vx v8, v8, a2, v0.t3734; RV64-NEXT: li a0, 563735; RV64-NEXT: vmul.vx v8, v8, a3, v0.t3736; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t3737; RV64-NEXT: ret3738 %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 true, <8 x i1> %m, i32 %evl)3739 ret <8 x i64> %v3740}3741 3742define <8 x i64> @vp_ctlz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {3743; RV32-LABEL: vp_ctlz_zero_undef_v8i64_unmasked:3744; RV32: # %bb.0:3745; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma3746; RV32-NEXT: vsrl.vi v12, v8, 13747; RV32-NEXT: lui a1, 3495253748; RV32-NEXT: addi a1, a1, 13653749; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma3750; RV32-NEXT: vmv.v.x v16, a13751; RV32-NEXT: li a1, 323752; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma3753; RV32-NEXT: vor.vv v8, v8, v123754; RV32-NEXT: vsrl.vi v12, v8, 23755; RV32-NEXT: vor.vv v8, v8, v123756; RV32-NEXT: vsrl.vi v12, v8, 43757; RV32-NEXT: vor.vv v8, v8, v123758; RV32-NEXT: vsrl.vi v12, v8, 83759; RV32-NEXT: vor.vv v8, v8, v123760; RV32-NEXT: vsrl.vi v12, v8, 163761; RV32-NEXT: vor.vv v8, v8, v123762; RV32-NEXT: vsrl.vx v12, v8, a13763; RV32-NEXT: lui a1, 2097153764; RV32-NEXT: addi a1, a1, 8193765; RV32-NEXT: vor.vv v8, v8, v123766; RV32-NEXT: vnot.v v8, v83767; RV32-NEXT: vsrl.vi v12, v8, 13768; RV32-NEXT: vand.vv v12, v12, v163769; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma3770; RV32-NEXT: vmv.v.x v16, a13771; RV32-NEXT: lui a1, 616813772; RV32-NEXT: addi a1, a1, -2413773; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma3774; RV32-NEXT: vsub.vv v8, v8, v123775; RV32-NEXT: vand.vv v12, v8, v163776; RV32-NEXT: vsrl.vi v8, v8, 23777; RV32-NEXT: vand.vv v8, v8, v163778; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma3779; RV32-NEXT: vmv.v.x v16, a13780; RV32-NEXT: lui a1, 41123781; RV32-NEXT: addi a1, a1, 2573782; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma3783; RV32-NEXT: vadd.vv v8, v12, v83784; RV32-NEXT: vsrl.vi v12, v8, 43785; RV32-NEXT: vadd.vv v8, v8, v123786; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma3787; RV32-NEXT: vmv.v.x v12, a13788; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma3789; RV32-NEXT: vand.vv v8, v8, v163790; RV32-NEXT: vmul.vv v8, v8, v123791; RV32-NEXT: li a0, 563792; RV32-NEXT: vsrl.vx v8, v8, a03793; RV32-NEXT: ret3794;3795; RV64-LABEL: vp_ctlz_zero_undef_v8i64_unmasked:3796; RV64: # %bb.0:3797; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma3798; RV64-NEXT: vsrl.vi v12, v8, 13799; RV64-NEXT: lui a0, 3495253800; RV64-NEXT: lui a1, 2097153801; RV64-NEXT: lui a2, 616813802; RV64-NEXT: lui a3, 41123803; RV64-NEXT: addi a0, a0, 13653804; RV64-NEXT: addi a1, a1, 8193805; RV64-NEXT: addi a2, a2, -2413806; RV64-NEXT: addi a3, a3, 2573807; RV64-NEXT: slli a4, a0, 323808; RV64-NEXT: add a0, a0, a43809; RV64-NEXT: slli a4, a1, 323810; RV64-NEXT: add a1, a1, a43811; RV64-NEXT: slli a4, a2, 323812; RV64-NEXT: add a2, a2, a43813; RV64-NEXT: slli a4, a3, 323814; RV64-NEXT: add a3, a3, a43815; RV64-NEXT: li a4, 323816; RV64-NEXT: vor.vv v8, v8, v123817; RV64-NEXT: vsrl.vi v12, v8, 23818; RV64-NEXT: vor.vv v8, v8, v123819; RV64-NEXT: vsrl.vi v12, v8, 43820; RV64-NEXT: vor.vv v8, v8, v123821; RV64-NEXT: vsrl.vi v12, v8, 83822; RV64-NEXT: vor.vv v8, v8, v123823; RV64-NEXT: vsrl.vi v12, v8, 163824; RV64-NEXT: vor.vv v8, v8, v123825; RV64-NEXT: vsrl.vx v12, v8, a43826; RV64-NEXT: vor.vv v8, v8, v123827; RV64-NEXT: vnot.v v8, v83828; RV64-NEXT: vsrl.vi v12, v8, 13829; RV64-NEXT: vand.vx v12, v12, a03830; RV64-NEXT: vsub.vv v8, v8, v123831; RV64-NEXT: vand.vx v12, v8, a13832; RV64-NEXT: vsrl.vi v8, v8, 23833; RV64-NEXT: vand.vx v8, v8, a13834; RV64-NEXT: vadd.vv v8, v12, v83835; RV64-NEXT: vsrl.vi v12, v8, 43836; RV64-NEXT: vadd.vv v8, v8, v123837; RV64-NEXT: vand.vx v8, v8, a23838; RV64-NEXT: vmul.vx v8, v8, a33839; RV64-NEXT: li a0, 563840; RV64-NEXT: vsrl.vx v8, v8, a03841; RV64-NEXT: ret3842 %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl)3843 ret <8 x i64> %v3844}3845 3846define <15 x i64> @vp_ctlz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {3847; RV32-LABEL: vp_ctlz_zero_undef_v15i64:3848; RV32: # %bb.0:3849; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3850; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t3851; RV32-NEXT: lui a1, 3495253852; RV32-NEXT: addi a1, a1, 13653853; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3854; RV32-NEXT: vmv.v.x v16, a13855; RV32-NEXT: li a1, 323856; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3857; RV32-NEXT: vor.vv v8, v8, v24, v0.t3858; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t3859; RV32-NEXT: vor.vv v8, v8, v24, v0.t3860; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t3861; RV32-NEXT: vor.vv v8, v8, v24, v0.t3862; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t3863; RV32-NEXT: vor.vv v8, v8, v24, v0.t3864; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t3865; RV32-NEXT: vor.vv v8, v8, v24, v0.t3866; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t3867; RV32-NEXT: lui a1, 2097153868; RV32-NEXT: addi a1, a1, 8193869; RV32-NEXT: vor.vv v8, v8, v24, v0.t3870; RV32-NEXT: vnot.v v24, v8, v0.t3871; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t3872; RV32-NEXT: vand.vv v16, v8, v16, v0.t3873; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3874; RV32-NEXT: vmv.v.x v8, a13875; RV32-NEXT: lui a1, 616813876; RV32-NEXT: addi a1, a1, -2413877; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3878; RV32-NEXT: vsub.vv v24, v24, v16, v0.t3879; RV32-NEXT: vand.vv v16, v24, v8, v0.t3880; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t3881; RV32-NEXT: vand.vv v24, v24, v8, v0.t3882; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3883; RV32-NEXT: vmv.v.x v8, a13884; RV32-NEXT: lui a1, 41123885; RV32-NEXT: addi a1, a1, 2573886; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3887; RV32-NEXT: vadd.vv v16, v16, v24, v0.t3888; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t3889; RV32-NEXT: vadd.vv v16, v16, v24, v0.t3890; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3891; RV32-NEXT: vmv.v.x v24, a13892; RV32-NEXT: li a1, 563893; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3894; RV32-NEXT: vand.vv v8, v16, v8, v0.t3895; RV32-NEXT: vmul.vv v8, v8, v24, v0.t3896; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t3897; RV32-NEXT: ret3898;3899; RV64-LABEL: vp_ctlz_zero_undef_v15i64:3900; RV64: # %bb.0:3901; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma3902; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t3903; RV64-NEXT: lui a0, 3495253904; RV64-NEXT: lui a1, 2097153905; RV64-NEXT: lui a2, 616813906; RV64-NEXT: lui a3, 41123907; RV64-NEXT: addi a0, a0, 13653908; RV64-NEXT: addi a1, a1, 8193909; RV64-NEXT: addi a2, a2, -2413910; RV64-NEXT: addi a3, a3, 2573911; RV64-NEXT: slli a4, a0, 323912; RV64-NEXT: add a0, a0, a43913; RV64-NEXT: slli a4, a1, 323914; RV64-NEXT: add a1, a1, a43915; RV64-NEXT: slli a4, a2, 323916; RV64-NEXT: add a2, a2, a43917; RV64-NEXT: slli a4, a3, 323918; RV64-NEXT: add a3, a3, a43919; RV64-NEXT: li a4, 323920; RV64-NEXT: vor.vv v8, v8, v16, v0.t3921; RV64-NEXT: vsrl.vi v16, v8, 2, v0.t3922; RV64-NEXT: vor.vv v8, v8, v16, v0.t3923; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t3924; RV64-NEXT: vor.vv v8, v8, v16, v0.t3925; RV64-NEXT: vsrl.vi v16, v8, 8, v0.t3926; RV64-NEXT: vor.vv v8, v8, v16, v0.t3927; RV64-NEXT: vsrl.vi v16, v8, 16, v0.t3928; RV64-NEXT: vor.vv v8, v8, v16, v0.t3929; RV64-NEXT: vsrl.vx v16, v8, a4, v0.t3930; RV64-NEXT: vor.vv v8, v8, v16, v0.t3931; RV64-NEXT: vnot.v v8, v8, v0.t3932; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t3933; RV64-NEXT: vand.vx v16, v16, a0, v0.t3934; RV64-NEXT: vsub.vv v8, v8, v16, v0.t3935; RV64-NEXT: vand.vx v16, v8, a1, v0.t3936; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t3937; RV64-NEXT: vand.vx v8, v8, a1, v0.t3938; RV64-NEXT: vadd.vv v8, v16, v8, v0.t3939; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t3940; RV64-NEXT: vadd.vv v8, v8, v16, v0.t3941; RV64-NEXT: vand.vx v8, v8, a2, v0.t3942; RV64-NEXT: li a0, 563943; RV64-NEXT: vmul.vx v8, v8, a3, v0.t3944; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t3945; RV64-NEXT: ret3946 %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 true, <15 x i1> %m, i32 %evl)3947 ret <15 x i64> %v3948}3949 3950define <15 x i64> @vp_ctlz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {3951; RV32-LABEL: vp_ctlz_zero_undef_v15i64_unmasked:3952; RV32: # %bb.0:3953; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3954; RV32-NEXT: vsrl.vi v16, v8, 13955; RV32-NEXT: lui a1, 3495253956; RV32-NEXT: addi a1, a1, 13653957; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3958; RV32-NEXT: vmv.v.x v24, a13959; RV32-NEXT: li a1, 323960; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3961; RV32-NEXT: vor.vv v8, v8, v163962; RV32-NEXT: vsrl.vi v16, v8, 23963; RV32-NEXT: vor.vv v8, v8, v163964; RV32-NEXT: vsrl.vi v16, v8, 43965; RV32-NEXT: vor.vv v8, v8, v163966; RV32-NEXT: vsrl.vi v16, v8, 83967; RV32-NEXT: vor.vv v8, v8, v163968; RV32-NEXT: vsrl.vi v16, v8, 163969; RV32-NEXT: vor.vv v8, v8, v163970; RV32-NEXT: vsrl.vx v16, v8, a13971; RV32-NEXT: lui a1, 2097153972; RV32-NEXT: addi a1, a1, 8193973; RV32-NEXT: vor.vv v8, v8, v163974; RV32-NEXT: vnot.v v8, v83975; RV32-NEXT: vsrl.vi v16, v8, 13976; RV32-NEXT: vand.vv v24, v16, v243977; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3978; RV32-NEXT: vmv.v.x v16, a13979; RV32-NEXT: lui a1, 616813980; RV32-NEXT: addi a1, a1, -2413981; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3982; RV32-NEXT: vsub.vv v8, v8, v243983; RV32-NEXT: vand.vv v24, v8, v163984; RV32-NEXT: vsrl.vi v8, v8, 23985; RV32-NEXT: vand.vv v8, v8, v163986; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3987; RV32-NEXT: vmv.v.x v16, a13988; RV32-NEXT: lui a1, 41123989; RV32-NEXT: addi a1, a1, 2573990; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3991; RV32-NEXT: vadd.vv v8, v24, v83992; RV32-NEXT: vsrl.vi v24, v8, 43993; RV32-NEXT: vadd.vv v8, v8, v243994; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3995; RV32-NEXT: vmv.v.x v24, a13996; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3997; RV32-NEXT: vand.vv v8, v8, v163998; RV32-NEXT: vmul.vv v8, v8, v243999; RV32-NEXT: li a0, 564000; RV32-NEXT: vsrl.vx v8, v8, a04001; RV32-NEXT: ret4002;4003; RV64-LABEL: vp_ctlz_zero_undef_v15i64_unmasked:4004; RV64: # %bb.0:4005; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma4006; RV64-NEXT: vsrl.vi v16, v8, 14007; RV64-NEXT: lui a0, 3495254008; RV64-NEXT: lui a1, 2097154009; RV64-NEXT: lui a2, 616814010; RV64-NEXT: lui a3, 41124011; RV64-NEXT: addi a0, a0, 13654012; RV64-NEXT: addi a1, a1, 8194013; RV64-NEXT: addi a2, a2, -2414014; RV64-NEXT: addi a3, a3, 2574015; RV64-NEXT: slli a4, a0, 324016; RV64-NEXT: add a0, a0, a44017; RV64-NEXT: slli a4, a1, 324018; RV64-NEXT: add a1, a1, a44019; RV64-NEXT: slli a4, a2, 324020; RV64-NEXT: add a2, a2, a44021; RV64-NEXT: slli a4, a3, 324022; RV64-NEXT: add a3, a3, a44023; RV64-NEXT: li a4, 324024; RV64-NEXT: vor.vv v8, v8, v164025; RV64-NEXT: vsrl.vi v16, v8, 24026; RV64-NEXT: vor.vv v8, v8, v164027; RV64-NEXT: vsrl.vi v16, v8, 44028; RV64-NEXT: vor.vv v8, v8, v164029; RV64-NEXT: vsrl.vi v16, v8, 84030; RV64-NEXT: vor.vv v8, v8, v164031; RV64-NEXT: vsrl.vi v16, v8, 164032; RV64-NEXT: vor.vv v8, v8, v164033; RV64-NEXT: vsrl.vx v16, v8, a44034; RV64-NEXT: vor.vv v8, v8, v164035; RV64-NEXT: vnot.v v8, v84036; RV64-NEXT: vsrl.vi v16, v8, 14037; RV64-NEXT: vand.vx v16, v16, a04038; RV64-NEXT: vsub.vv v8, v8, v164039; RV64-NEXT: vand.vx v16, v8, a14040; RV64-NEXT: vsrl.vi v8, v8, 24041; RV64-NEXT: vand.vx v8, v8, a14042; RV64-NEXT: vadd.vv v8, v16, v84043; RV64-NEXT: vsrl.vi v16, v8, 44044; RV64-NEXT: vadd.vv v8, v8, v164045; RV64-NEXT: vand.vx v8, v8, a24046; RV64-NEXT: vmul.vx v8, v8, a34047; RV64-NEXT: li a0, 564048; RV64-NEXT: vsrl.vx v8, v8, a04049; RV64-NEXT: ret4050 %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 true, <15 x i1> splat (i1 true), i32 %evl)4051 ret <15 x i64> %v4052}4053 4054define <16 x i64> @vp_ctlz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {4055; RV32-LABEL: vp_ctlz_zero_undef_v16i64:4056; RV32: # %bb.0:4057; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4058; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t4059; RV32-NEXT: lui a1, 3495254060; RV32-NEXT: addi a1, a1, 13654061; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma4062; RV32-NEXT: vmv.v.x v16, a14063; RV32-NEXT: li a1, 324064; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4065; RV32-NEXT: vor.vv v8, v8, v24, v0.t4066; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t4067; RV32-NEXT: vor.vv v8, v8, v24, v0.t4068; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t4069; RV32-NEXT: vor.vv v8, v8, v24, v0.t4070; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t4071; RV32-NEXT: vor.vv v8, v8, v24, v0.t4072; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t4073; RV32-NEXT: vor.vv v8, v8, v24, v0.t4074; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t4075; RV32-NEXT: lui a1, 2097154076; RV32-NEXT: addi a1, a1, 8194077; RV32-NEXT: vor.vv v8, v8, v24, v0.t4078; RV32-NEXT: vnot.v v24, v8, v0.t4079; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t4080; RV32-NEXT: vand.vv v16, v8, v16, v0.t4081; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma4082; RV32-NEXT: vmv.v.x v8, a14083; RV32-NEXT: lui a1, 616814084; RV32-NEXT: addi a1, a1, -2414085; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4086; RV32-NEXT: vsub.vv v24, v24, v16, v0.t4087; RV32-NEXT: vand.vv v16, v24, v8, v0.t4088; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t4089; RV32-NEXT: vand.vv v24, v24, v8, v0.t4090; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma4091; RV32-NEXT: vmv.v.x v8, a14092; RV32-NEXT: lui a1, 41124093; RV32-NEXT: addi a1, a1, 2574094; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4095; RV32-NEXT: vadd.vv v16, v16, v24, v0.t4096; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t4097; RV32-NEXT: vadd.vv v16, v16, v24, v0.t4098; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma4099; RV32-NEXT: vmv.v.x v24, a14100; RV32-NEXT: li a1, 564101; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4102; RV32-NEXT: vand.vv v8, v16, v8, v0.t4103; RV32-NEXT: vmul.vv v8, v8, v24, v0.t4104; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t4105; RV32-NEXT: ret4106;4107; RV64-LABEL: vp_ctlz_zero_undef_v16i64:4108; RV64: # %bb.0:4109; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma4110; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t4111; RV64-NEXT: lui a0, 3495254112; RV64-NEXT: lui a1, 2097154113; RV64-NEXT: lui a2, 616814114; RV64-NEXT: lui a3, 41124115; RV64-NEXT: addi a0, a0, 13654116; RV64-NEXT: addi a1, a1, 8194117; RV64-NEXT: addi a2, a2, -2414118; RV64-NEXT: addi a3, a3, 2574119; RV64-NEXT: slli a4, a0, 324120; RV64-NEXT: add a0, a0, a44121; RV64-NEXT: slli a4, a1, 324122; RV64-NEXT: add a1, a1, a44123; RV64-NEXT: slli a4, a2, 324124; RV64-NEXT: add a2, a2, a44125; RV64-NEXT: slli a4, a3, 324126; RV64-NEXT: add a3, a3, a44127; RV64-NEXT: li a4, 324128; RV64-NEXT: vor.vv v8, v8, v16, v0.t4129; RV64-NEXT: vsrl.vi v16, v8, 2, v0.t4130; RV64-NEXT: vor.vv v8, v8, v16, v0.t4131; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t4132; RV64-NEXT: vor.vv v8, v8, v16, v0.t4133; RV64-NEXT: vsrl.vi v16, v8, 8, v0.t4134; RV64-NEXT: vor.vv v8, v8, v16, v0.t4135; RV64-NEXT: vsrl.vi v16, v8, 16, v0.t4136; RV64-NEXT: vor.vv v8, v8, v16, v0.t4137; RV64-NEXT: vsrl.vx v16, v8, a4, v0.t4138; RV64-NEXT: vor.vv v8, v8, v16, v0.t4139; RV64-NEXT: vnot.v v8, v8, v0.t4140; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t4141; RV64-NEXT: vand.vx v16, v16, a0, v0.t4142; RV64-NEXT: vsub.vv v8, v8, v16, v0.t4143; RV64-NEXT: vand.vx v16, v8, a1, v0.t4144; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t4145; RV64-NEXT: vand.vx v8, v8, a1, v0.t4146; RV64-NEXT: vadd.vv v8, v16, v8, v0.t4147; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t4148; RV64-NEXT: vadd.vv v8, v8, v16, v0.t4149; RV64-NEXT: vand.vx v8, v8, a2, v0.t4150; RV64-NEXT: li a0, 564151; RV64-NEXT: vmul.vx v8, v8, a3, v0.t4152; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t4153; RV64-NEXT: ret4154 %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 true, <16 x i1> %m, i32 %evl)4155 ret <16 x i64> %v4156}4157 4158define <16 x i64> @vp_ctlz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {4159; RV32-LABEL: vp_ctlz_zero_undef_v16i64_unmasked:4160; RV32: # %bb.0:4161; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4162; RV32-NEXT: vsrl.vi v16, v8, 14163; RV32-NEXT: lui a1, 3495254164; RV32-NEXT: addi a1, a1, 13654165; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma4166; RV32-NEXT: vmv.v.x v24, a14167; RV32-NEXT: li a1, 324168; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4169; RV32-NEXT: vor.vv v8, v8, v164170; RV32-NEXT: vsrl.vi v16, v8, 24171; RV32-NEXT: vor.vv v8, v8, v164172; RV32-NEXT: vsrl.vi v16, v8, 44173; RV32-NEXT: vor.vv v8, v8, v164174; RV32-NEXT: vsrl.vi v16, v8, 84175; RV32-NEXT: vor.vv v8, v8, v164176; RV32-NEXT: vsrl.vi v16, v8, 164177; RV32-NEXT: vor.vv v8, v8, v164178; RV32-NEXT: vsrl.vx v16, v8, a14179; RV32-NEXT: lui a1, 2097154180; RV32-NEXT: addi a1, a1, 8194181; RV32-NEXT: vor.vv v8, v8, v164182; RV32-NEXT: vnot.v v8, v84183; RV32-NEXT: vsrl.vi v16, v8, 14184; RV32-NEXT: vand.vv v24, v16, v244185; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma4186; RV32-NEXT: vmv.v.x v16, a14187; RV32-NEXT: lui a1, 616814188; RV32-NEXT: addi a1, a1, -2414189; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4190; RV32-NEXT: vsub.vv v8, v8, v244191; RV32-NEXT: vand.vv v24, v8, v164192; RV32-NEXT: vsrl.vi v8, v8, 24193; RV32-NEXT: vand.vv v8, v8, v164194; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma4195; RV32-NEXT: vmv.v.x v16, a14196; RV32-NEXT: lui a1, 41124197; RV32-NEXT: addi a1, a1, 2574198; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4199; RV32-NEXT: vadd.vv v8, v24, v84200; RV32-NEXT: vsrl.vi v24, v8, 44201; RV32-NEXT: vadd.vv v8, v8, v244202; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma4203; RV32-NEXT: vmv.v.x v24, a14204; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4205; RV32-NEXT: vand.vv v8, v8, v164206; RV32-NEXT: vmul.vv v8, v8, v244207; RV32-NEXT: li a0, 564208; RV32-NEXT: vsrl.vx v8, v8, a04209; RV32-NEXT: ret4210;4211; RV64-LABEL: vp_ctlz_zero_undef_v16i64_unmasked:4212; RV64: # %bb.0:4213; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma4214; RV64-NEXT: vsrl.vi v16, v8, 14215; RV64-NEXT: lui a0, 3495254216; RV64-NEXT: lui a1, 2097154217; RV64-NEXT: lui a2, 616814218; RV64-NEXT: lui a3, 41124219; RV64-NEXT: addi a0, a0, 13654220; RV64-NEXT: addi a1, a1, 8194221; RV64-NEXT: addi a2, a2, -2414222; RV64-NEXT: addi a3, a3, 2574223; RV64-NEXT: slli a4, a0, 324224; RV64-NEXT: add a0, a0, a44225; RV64-NEXT: slli a4, a1, 324226; RV64-NEXT: add a1, a1, a44227; RV64-NEXT: slli a4, a2, 324228; RV64-NEXT: add a2, a2, a44229; RV64-NEXT: slli a4, a3, 324230; RV64-NEXT: add a3, a3, a44231; RV64-NEXT: li a4, 324232; RV64-NEXT: vor.vv v8, v8, v164233; RV64-NEXT: vsrl.vi v16, v8, 24234; RV64-NEXT: vor.vv v8, v8, v164235; RV64-NEXT: vsrl.vi v16, v8, 44236; RV64-NEXT: vor.vv v8, v8, v164237; RV64-NEXT: vsrl.vi v16, v8, 84238; RV64-NEXT: vor.vv v8, v8, v164239; RV64-NEXT: vsrl.vi v16, v8, 164240; RV64-NEXT: vor.vv v8, v8, v164241; RV64-NEXT: vsrl.vx v16, v8, a44242; RV64-NEXT: vor.vv v8, v8, v164243; RV64-NEXT: vnot.v v8, v84244; RV64-NEXT: vsrl.vi v16, v8, 14245; RV64-NEXT: vand.vx v16, v16, a04246; RV64-NEXT: vsub.vv v8, v8, v164247; RV64-NEXT: vand.vx v16, v8, a14248; RV64-NEXT: vsrl.vi v8, v8, 24249; RV64-NEXT: vand.vx v8, v8, a14250; RV64-NEXT: vadd.vv v8, v16, v84251; RV64-NEXT: vsrl.vi v16, v8, 44252; RV64-NEXT: vadd.vv v8, v8, v164253; RV64-NEXT: vand.vx v8, v8, a24254; RV64-NEXT: vmul.vx v8, v8, a34255; RV64-NEXT: li a0, 564256; RV64-NEXT: vsrl.vx v8, v8, a04257; RV64-NEXT: ret4258 %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl)4259 ret <16 x i64> %v4260}4261 4262define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {4263; RV32-LABEL: vp_ctlz_zero_undef_v32i64:4264; RV32: # %bb.0:4265; RV32-NEXT: addi sp, sp, -164266; RV32-NEXT: .cfi_def_cfa_offset 164267; RV32-NEXT: csrr a1, vlenb4268; RV32-NEXT: li a2, 484269; RV32-NEXT: mul a1, a1, a24270; RV32-NEXT: sub sp, sp, a14271; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb4272; RV32-NEXT: csrr a1, vlenb4273; RV32-NEXT: li a2, 404274; RV32-NEXT: mul a1, a1, a24275; RV32-NEXT: add a1, sp, a14276; RV32-NEXT: addi a1, a1, 164277; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill4278; RV32-NEXT: li a1, 164279; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma4280; RV32-NEXT: vslidedown.vi v7, v0, 24281; RV32-NEXT: mv a2, a04282; RV32-NEXT: bltu a0, a1, .LBB70_24283; RV32-NEXT: # %bb.1:4284; RV32-NEXT: li a2, 164285; RV32-NEXT: .LBB70_2:4286; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma4287; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t4288; RV32-NEXT: li a1, 324289; RV32-NEXT: lui a3, 3495254290; RV32-NEXT: vor.vv v8, v8, v16, v0.t4291; RV32-NEXT: addi a3, a3, 13654292; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t4293; RV32-NEXT: vor.vv v8, v8, v16, v0.t4294; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t4295; RV32-NEXT: vor.vv v8, v8, v16, v0.t4296; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t4297; RV32-NEXT: vor.vv v8, v8, v16, v0.t4298; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t4299; RV32-NEXT: vor.vv v8, v8, v16, v0.t4300; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t4301; RV32-NEXT: vor.vv v8, v8, v16, v0.t4302; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma4303; RV32-NEXT: vmv.v.x v24, a34304; RV32-NEXT: csrr a3, vlenb4305; RV32-NEXT: slli a3, a3, 54306; RV32-NEXT: add a3, sp, a34307; RV32-NEXT: addi a3, a3, 164308; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill4309; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma4310; RV32-NEXT: vnot.v v8, v8, v0.t4311; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t4312; RV32-NEXT: vand.vv v16, v16, v24, v0.t4313; RV32-NEXT: vsub.vv v8, v8, v16, v0.t4314; RV32-NEXT: lui a3, 2097154315; RV32-NEXT: addi a3, a3, 8194316; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma4317; RV32-NEXT: vmv.v.x v16, a34318; RV32-NEXT: csrr a3, vlenb4319; RV32-NEXT: slli a3, a3, 44320; RV32-NEXT: add a3, sp, a34321; RV32-NEXT: addi a3, a3, 164322; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill4323; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma4324; RV32-NEXT: vand.vv v24, v8, v16, v0.t4325; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t4326; RV32-NEXT: vand.vv v8, v8, v16, v0.t4327; RV32-NEXT: vadd.vv v8, v24, v8, v0.t4328; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t4329; RV32-NEXT: vadd.vv v8, v8, v24, v0.t4330; RV32-NEXT: lui a3, 616814331; RV32-NEXT: addi a3, a3, -2414332; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma4333; RV32-NEXT: vmv.v.x v16, a34334; RV32-NEXT: csrr a3, vlenb4335; RV32-NEXT: li a4, 244336; RV32-NEXT: mul a3, a3, a44337; RV32-NEXT: add a3, sp, a34338; RV32-NEXT: addi a3, a3, 164339; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill4340; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma4341; RV32-NEXT: vand.vv v8, v8, v16, v0.t4342; RV32-NEXT: lui a3, 41124343; RV32-NEXT: addi a3, a3, 2574344; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma4345; RV32-NEXT: vmv.v.x v16, a34346; RV32-NEXT: addi a3, sp, 164347; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill4348; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma4349; RV32-NEXT: vmul.vv v8, v8, v16, v0.t4350; RV32-NEXT: li a2, 564351; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t4352; RV32-NEXT: csrr a3, vlenb4353; RV32-NEXT: slli a3, a3, 34354; RV32-NEXT: add a3, sp, a34355; RV32-NEXT: addi a3, a3, 164356; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill4357; RV32-NEXT: addi a3, a0, -164358; RV32-NEXT: sltu a0, a0, a34359; RV32-NEXT: addi a0, a0, -14360; RV32-NEXT: and a0, a0, a34361; RV32-NEXT: vmv1r.v v0, v74362; RV32-NEXT: csrr a3, vlenb4363; RV32-NEXT: li a4, 404364; RV32-NEXT: mul a3, a3, a44365; RV32-NEXT: add a3, sp, a34366; RV32-NEXT: addi a3, a3, 164367; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload4368; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4369; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t4370; RV32-NEXT: vor.vv v8, v16, v8, v0.t4371; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t4372; RV32-NEXT: vor.vv v8, v8, v16, v0.t4373; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t4374; RV32-NEXT: vor.vv v8, v8, v16, v0.t4375; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t4376; RV32-NEXT: vor.vv v8, v8, v16, v0.t4377; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t4378; RV32-NEXT: vor.vv v8, v8, v16, v0.t4379; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t4380; RV32-NEXT: vor.vv v8, v8, v16, v0.t4381; RV32-NEXT: vnot.v v8, v8, v0.t4382; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t4383; RV32-NEXT: csrr a0, vlenb4384; RV32-NEXT: slli a0, a0, 54385; RV32-NEXT: add a0, sp, a04386; RV32-NEXT: addi a0, a0, 164387; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload4388; RV32-NEXT: vand.vv v16, v16, v24, v0.t4389; RV32-NEXT: vsub.vv v8, v8, v16, v0.t4390; RV32-NEXT: csrr a0, vlenb4391; RV32-NEXT: slli a0, a0, 44392; RV32-NEXT: add a0, sp, a04393; RV32-NEXT: addi a0, a0, 164394; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload4395; RV32-NEXT: vand.vv v16, v8, v24, v0.t4396; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t4397; RV32-NEXT: vand.vv v8, v8, v24, v0.t4398; RV32-NEXT: vadd.vv v8, v16, v8, v0.t4399; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t4400; RV32-NEXT: vadd.vv v8, v8, v16, v0.t4401; RV32-NEXT: csrr a0, vlenb4402; RV32-NEXT: li a1, 244403; RV32-NEXT: mul a0, a0, a14404; RV32-NEXT: add a0, sp, a04405; RV32-NEXT: addi a0, a0, 164406; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload4407; RV32-NEXT: vand.vv v8, v8, v16, v0.t4408; RV32-NEXT: addi a0, sp, 164409; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload4410; RV32-NEXT: vmul.vv v8, v8, v16, v0.t4411; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t4412; RV32-NEXT: csrr a0, vlenb4413; RV32-NEXT: slli a0, a0, 34414; RV32-NEXT: add a0, sp, a04415; RV32-NEXT: addi a0, a0, 164416; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload4417; RV32-NEXT: csrr a0, vlenb4418; RV32-NEXT: li a1, 484419; RV32-NEXT: mul a0, a0, a14420; RV32-NEXT: add sp, sp, a04421; RV32-NEXT: .cfi_def_cfa sp, 164422; RV32-NEXT: addi sp, sp, 164423; RV32-NEXT: .cfi_def_cfa_offset 04424; RV32-NEXT: ret4425;4426; RV64-LABEL: vp_ctlz_zero_undef_v32i64:4427; RV64: # %bb.0:4428; RV64-NEXT: li a2, 164429; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma4430; RV64-NEXT: vslidedown.vi v7, v0, 24431; RV64-NEXT: mv a1, a04432; RV64-NEXT: bltu a0, a2, .LBB70_24433; RV64-NEXT: # %bb.1:4434; RV64-NEXT: li a1, 164435; RV64-NEXT: .LBB70_2:4436; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma4437; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t4438; RV64-NEXT: li a1, 324439; RV64-NEXT: lui a2, 3495254440; RV64-NEXT: lui a3, 2097154441; RV64-NEXT: lui a4, 616814442; RV64-NEXT: lui a5, 41124443; RV64-NEXT: addi a2, a2, 13654444; RV64-NEXT: addi a3, a3, 8194445; RV64-NEXT: addi a6, a4, -2414446; RV64-NEXT: addi a7, a5, 2574447; RV64-NEXT: slli a5, a2, 324448; RV64-NEXT: add a5, a2, a54449; RV64-NEXT: slli a4, a3, 324450; RV64-NEXT: add a4, a3, a44451; RV64-NEXT: slli a2, a6, 324452; RV64-NEXT: add a2, a6, a24453; RV64-NEXT: slli a3, a7, 324454; RV64-NEXT: add a3, a7, a34455; RV64-NEXT: addi a6, a0, -164456; RV64-NEXT: sltu a0, a0, a64457; RV64-NEXT: addi a0, a0, -14458; RV64-NEXT: and a6, a0, a64459; RV64-NEXT: li a0, 564460; RV64-NEXT: vor.vv v8, v8, v24, v0.t4461; RV64-NEXT: vsrl.vi v24, v8, 2, v0.t4462; RV64-NEXT: vor.vv v8, v8, v24, v0.t4463; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t4464; RV64-NEXT: vor.vv v8, v8, v24, v0.t4465; RV64-NEXT: vsrl.vi v24, v8, 8, v0.t4466; RV64-NEXT: vor.vv v8, v8, v24, v0.t4467; RV64-NEXT: vsrl.vi v24, v8, 16, v0.t4468; RV64-NEXT: vor.vv v8, v8, v24, v0.t4469; RV64-NEXT: vsrl.vx v24, v8, a1, v0.t4470; RV64-NEXT: vor.vv v8, v8, v24, v0.t4471; RV64-NEXT: vnot.v v8, v8, v0.t4472; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t4473; RV64-NEXT: vand.vx v24, v24, a5, v0.t4474; RV64-NEXT: vsub.vv v8, v8, v24, v0.t4475; RV64-NEXT: vand.vx v24, v8, a4, v0.t4476; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t4477; RV64-NEXT: vand.vx v8, v8, a4, v0.t4478; RV64-NEXT: vadd.vv v8, v24, v8, v0.t4479; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t4480; RV64-NEXT: vadd.vv v8, v8, v24, v0.t4481; RV64-NEXT: vand.vx v8, v8, a2, v0.t4482; RV64-NEXT: vmul.vx v8, v8, a3, v0.t4483; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t4484; RV64-NEXT: vmv1r.v v0, v74485; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma4486; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t4487; RV64-NEXT: vor.vv v16, v16, v24, v0.t4488; RV64-NEXT: vsrl.vi v24, v16, 2, v0.t4489; RV64-NEXT: vor.vv v16, v16, v24, v0.t4490; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t4491; RV64-NEXT: vor.vv v16, v16, v24, v0.t4492; RV64-NEXT: vsrl.vi v24, v16, 8, v0.t4493; RV64-NEXT: vor.vv v16, v16, v24, v0.t4494; RV64-NEXT: vsrl.vi v24, v16, 16, v0.t4495; RV64-NEXT: vor.vv v16, v16, v24, v0.t4496; RV64-NEXT: vsrl.vx v24, v16, a1, v0.t4497; RV64-NEXT: vor.vv v16, v16, v24, v0.t4498; RV64-NEXT: vnot.v v16, v16, v0.t4499; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t4500; RV64-NEXT: vand.vx v24, v24, a5, v0.t4501; RV64-NEXT: vsub.vv v16, v16, v24, v0.t4502; RV64-NEXT: vand.vx v24, v16, a4, v0.t4503; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t4504; RV64-NEXT: vand.vx v16, v16, a4, v0.t4505; RV64-NEXT: vadd.vv v16, v24, v16, v0.t4506; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t4507; RV64-NEXT: vadd.vv v16, v16, v24, v0.t4508; RV64-NEXT: vand.vx v16, v16, a2, v0.t4509; RV64-NEXT: vmul.vx v16, v16, a3, v0.t4510; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t4511; RV64-NEXT: ret4512 %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl)4513 ret <32 x i64> %v4514}4515 4516define <32 x i64> @vp_ctlz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {4517; RV32-LABEL: vp_ctlz_zero_undef_v32i64_unmasked:4518; RV32: # %bb.0:4519; RV32-NEXT: li a2, 164520; RV32-NEXT: mv a1, a04521; RV32-NEXT: bltu a0, a2, .LBB71_24522; RV32-NEXT: # %bb.1:4523; RV32-NEXT: li a1, 164524; RV32-NEXT: .LBB71_2:4525; RV32-NEXT: addi sp, sp, -164526; RV32-NEXT: .cfi_def_cfa_offset 164527; RV32-NEXT: csrr a2, vlenb4528; RV32-NEXT: slli a2, a2, 44529; RV32-NEXT: sub sp, sp, a24530; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb4531; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma4532; RV32-NEXT: vsrl.vi v0, v8, 14533; RV32-NEXT: li a2, 324534; RV32-NEXT: lui a3, 3495254535; RV32-NEXT: addi a3, a3, 13654536; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma4537; RV32-NEXT: vmv.v.x v24, a34538; RV32-NEXT: csrr a3, vlenb4539; RV32-NEXT: slli a3, a3, 34540; RV32-NEXT: add a3, sp, a34541; RV32-NEXT: addi a3, a3, 164542; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill4543; RV32-NEXT: addi a3, a0, -164544; RV32-NEXT: sltu a0, a0, a34545; RV32-NEXT: addi a0, a0, -14546; RV32-NEXT: and a0, a0, a34547; RV32-NEXT: lui a3, 2097154548; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma4549; RV32-NEXT: vor.vv v8, v8, v04550; RV32-NEXT: addi a3, a3, 8194551; RV32-NEXT: vsrl.vi v0, v8, 24552; RV32-NEXT: vor.vv v8, v8, v04553; RV32-NEXT: vsrl.vi v0, v8, 44554; RV32-NEXT: vor.vv v8, v8, v04555; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4556; RV32-NEXT: vsrl.vi v0, v16, 14557; RV32-NEXT: vor.vv v16, v16, v04558; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma4559; RV32-NEXT: vsrl.vi v0, v8, 84560; RV32-NEXT: vor.vv v8, v8, v04561; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4562; RV32-NEXT: vsrl.vi v0, v16, 24563; RV32-NEXT: vor.vv v16, v16, v04564; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma4565; RV32-NEXT: vsrl.vi v0, v8, 164566; RV32-NEXT: vor.vv v8, v8, v04567; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4568; RV32-NEXT: vsrl.vi v0, v16, 44569; RV32-NEXT: vor.vv v16, v16, v04570; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma4571; RV32-NEXT: vsrl.vx v0, v8, a24572; RV32-NEXT: vor.vv v8, v8, v04573; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4574; RV32-NEXT: vsrl.vi v0, v16, 84575; RV32-NEXT: vor.vv v16, v16, v04576; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma4577; RV32-NEXT: vnot.v v8, v84578; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4579; RV32-NEXT: vsrl.vi v0, v16, 164580; RV32-NEXT: vor.vv v16, v16, v04581; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma4582; RV32-NEXT: vsrl.vi v0, v8, 14583; RV32-NEXT: vand.vv v0, v0, v244584; RV32-NEXT: vsub.vv v0, v8, v04585; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4586; RV32-NEXT: vsrl.vx v8, v16, a24587; RV32-NEXT: vor.vv v24, v16, v84588; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma4589; RV32-NEXT: vmv.v.x v8, a34590; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma4591; RV32-NEXT: vand.vv v16, v0, v84592; RV32-NEXT: vsrl.vi v0, v0, 24593; RV32-NEXT: vand.vv v0, v0, v84594; RV32-NEXT: vadd.vv v16, v16, v04595; RV32-NEXT: addi a2, sp, 164596; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill4597; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4598; RV32-NEXT: vnot.v v24, v244599; RV32-NEXT: vsrl.vi v0, v24, 14600; RV32-NEXT: csrr a2, vlenb4601; RV32-NEXT: slli a2, a2, 34602; RV32-NEXT: add a2, sp, a24603; RV32-NEXT: addi a2, a2, 164604; RV32-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload4605; RV32-NEXT: vand.vv v0, v0, v164606; RV32-NEXT: vsub.vv v24, v24, v04607; RV32-NEXT: addi a2, sp, 164608; RV32-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload4609; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma4610; RV32-NEXT: vsrl.vi v0, v16, 44611; RV32-NEXT: vadd.vv v16, v16, v04612; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4613; RV32-NEXT: vand.vv v0, v24, v84614; RV32-NEXT: vsrl.vi v24, v24, 24615; RV32-NEXT: vand.vv v8, v24, v84616; RV32-NEXT: lui a2, 616814617; RV32-NEXT: lui a3, 41124618; RV32-NEXT: addi a2, a2, -2414619; RV32-NEXT: addi a3, a3, 2574620; RV32-NEXT: vadd.vv v8, v0, v84621; RV32-NEXT: vsrl.vi v24, v8, 44622; RV32-NEXT: vadd.vv v8, v8, v244623; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma4624; RV32-NEXT: vmv.v.x v24, a24625; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma4626; RV32-NEXT: vand.vv v16, v16, v244627; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4628; RV32-NEXT: vand.vv v8, v8, v244629; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma4630; RV32-NEXT: vmv.v.x v24, a34631; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma4632; RV32-NEXT: vmul.vv v16, v16, v244633; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4634; RV32-NEXT: vmul.vv v24, v8, v244635; RV32-NEXT: li a2, 564636; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma4637; RV32-NEXT: vsrl.vx v8, v16, a24638; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma4639; RV32-NEXT: vsrl.vx v16, v24, a24640; RV32-NEXT: csrr a0, vlenb4641; RV32-NEXT: slli a0, a0, 44642; RV32-NEXT: add sp, sp, a04643; RV32-NEXT: .cfi_def_cfa sp, 164644; RV32-NEXT: addi sp, sp, 164645; RV32-NEXT: .cfi_def_cfa_offset 04646; RV32-NEXT: ret4647;4648; RV64-LABEL: vp_ctlz_zero_undef_v32i64_unmasked:4649; RV64: # %bb.0:4650; RV64-NEXT: li a2, 164651; RV64-NEXT: mv a1, a04652; RV64-NEXT: bltu a0, a2, .LBB71_24653; RV64-NEXT: # %bb.1:4654; RV64-NEXT: li a1, 164655; RV64-NEXT: .LBB71_2:4656; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma4657; RV64-NEXT: vsrl.vi v24, v8, 14658; RV64-NEXT: li a2, 324659; RV64-NEXT: lui a3, 3495254660; RV64-NEXT: lui a4, 2097154661; RV64-NEXT: lui a5, 616814662; RV64-NEXT: lui a6, 41124663; RV64-NEXT: addi a7, a3, 13654664; RV64-NEXT: addi a3, a4, 8194665; RV64-NEXT: addi a4, a5, -2414666; RV64-NEXT: addi a6, a6, 2574667; RV64-NEXT: slli a5, a7, 324668; RV64-NEXT: add a7, a7, a54669; RV64-NEXT: slli a5, a3, 324670; RV64-NEXT: add a5, a3, a54671; RV64-NEXT: slli a3, a4, 324672; RV64-NEXT: add a3, a4, a34673; RV64-NEXT: slli a4, a6, 324674; RV64-NEXT: add a4, a6, a44675; RV64-NEXT: addi a6, a0, -164676; RV64-NEXT: sltu a0, a0, a64677; RV64-NEXT: addi a0, a0, -14678; RV64-NEXT: and a6, a0, a64679; RV64-NEXT: li a0, 564680; RV64-NEXT: vor.vv v8, v8, v244681; RV64-NEXT: vsrl.vi v24, v8, 24682; RV64-NEXT: vor.vv v8, v8, v244683; RV64-NEXT: vsrl.vi v24, v8, 44684; RV64-NEXT: vor.vv v8, v8, v244685; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma4686; RV64-NEXT: vsrl.vi v24, v16, 14687; RV64-NEXT: vor.vv v16, v16, v244688; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma4689; RV64-NEXT: vsrl.vi v24, v8, 84690; RV64-NEXT: vor.vv v8, v8, v244691; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma4692; RV64-NEXT: vsrl.vi v24, v16, 24693; RV64-NEXT: vor.vv v16, v16, v244694; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma4695; RV64-NEXT: vsrl.vi v24, v8, 164696; RV64-NEXT: vor.vv v8, v8, v244697; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma4698; RV64-NEXT: vsrl.vi v24, v16, 44699; RV64-NEXT: vor.vv v16, v16, v244700; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma4701; RV64-NEXT: vsrl.vx v24, v8, a24702; RV64-NEXT: vor.vv v8, v8, v244703; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma4704; RV64-NEXT: vsrl.vi v24, v16, 84705; RV64-NEXT: vor.vv v16, v16, v244706; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma4707; RV64-NEXT: vnot.v v8, v84708; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma4709; RV64-NEXT: vsrl.vi v24, v16, 164710; RV64-NEXT: vor.vv v16, v16, v244711; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma4712; RV64-NEXT: vsrl.vi v24, v8, 14713; RV64-NEXT: vand.vx v24, v24, a74714; RV64-NEXT: vsub.vv v8, v8, v244715; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma4716; RV64-NEXT: vsrl.vx v24, v16, a24717; RV64-NEXT: vor.vv v16, v16, v244718; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma4719; RV64-NEXT: vand.vx v24, v8, a54720; RV64-NEXT: vsrl.vi v8, v8, 24721; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma4722; RV64-NEXT: vnot.v v16, v164723; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma4724; RV64-NEXT: vand.vx v8, v8, a54725; RV64-NEXT: vadd.vv v8, v24, v84726; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma4727; RV64-NEXT: vsrl.vi v24, v16, 14728; RV64-NEXT: vand.vx v24, v24, a74729; RV64-NEXT: vsub.vv v16, v16, v244730; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma4731; RV64-NEXT: vsrl.vi v24, v8, 44732; RV64-NEXT: vadd.vv v8, v8, v244733; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma4734; RV64-NEXT: vand.vx v24, v16, a54735; RV64-NEXT: vsrl.vi v16, v16, 24736; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma4737; RV64-NEXT: vand.vx v8, v8, a34738; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma4739; RV64-NEXT: vand.vx v16, v16, a54740; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma4741; RV64-NEXT: vmul.vx v8, v8, a44742; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma4743; RV64-NEXT: vadd.vv v16, v24, v164744; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma4745; RV64-NEXT: vsrl.vx v8, v8, a04746; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma4747; RV64-NEXT: vsrl.vi v24, v16, 44748; RV64-NEXT: vadd.vv v16, v16, v244749; RV64-NEXT: vand.vx v16, v16, a34750; RV64-NEXT: vmul.vx v16, v16, a44751; RV64-NEXT: vsrl.vx v16, v16, a04752; RV64-NEXT: ret4753 %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 true, <32 x i1> splat (i1 true), i32 %evl)4754 ret <32 x i64> %v4755}4756