1730 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV646 7define <2 x i8> @vp_ctpop_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vp_ctpop_v2i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t12; CHECK-NEXT: li a0, 8513; CHECK-NEXT: vand.vx v9, v9, a0, v0.t14; CHECK-NEXT: li a0, 5115; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t16; CHECK-NEXT: vand.vx v9, v8, a0, v0.t17; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t18; CHECK-NEXT: vand.vx v8, v8, a0, v0.t19; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t20; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t21; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t22; CHECK-NEXT: vand.vi v8, v8, 15, v0.t23; CHECK-NEXT: ret24 %v = call <2 x i8> @llvm.vp.ctpop.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl)25 ret <2 x i8> %v26}27 28define <2 x i8> @vp_ctpop_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {29; CHECK-LABEL: vp_ctpop_v2i8_unmasked:30; CHECK: # %bb.0:31; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma32; CHECK-NEXT: vsrl.vi v9, v8, 133; CHECK-NEXT: li a0, 8534; CHECK-NEXT: vand.vx v9, v9, a035; CHECK-NEXT: li a0, 5136; CHECK-NEXT: vsub.vv v8, v8, v937; CHECK-NEXT: vand.vx v9, v8, a038; CHECK-NEXT: vsrl.vi v8, v8, 239; CHECK-NEXT: vand.vx v8, v8, a040; CHECK-NEXT: vadd.vv v8, v9, v841; CHECK-NEXT: vsrl.vi v9, v8, 442; CHECK-NEXT: vadd.vv v8, v8, v943; CHECK-NEXT: vand.vi v8, v8, 1544; CHECK-NEXT: ret45 %v = call <2 x i8> @llvm.vp.ctpop.v2i8(<2 x i8> %va, <2 x i1> splat (i1 true), i32 %evl)46 ret <2 x i8> %v47}48 49define <4 x i8> @vp_ctpop_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {50; CHECK-LABEL: vp_ctpop_v4i8:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma53; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t54; CHECK-NEXT: li a0, 8555; CHECK-NEXT: vand.vx v9, v9, a0, v0.t56; CHECK-NEXT: li a0, 5157; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t58; CHECK-NEXT: vand.vx v9, v8, a0, v0.t59; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t60; CHECK-NEXT: vand.vx v8, v8, a0, v0.t61; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t62; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t63; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t64; CHECK-NEXT: vand.vi v8, v8, 15, v0.t65; CHECK-NEXT: ret66 %v = call <4 x i8> @llvm.vp.ctpop.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)67 ret <4 x i8> %v68}69 70define <4 x i8> @vp_ctpop_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {71; CHECK-LABEL: vp_ctpop_v4i8_unmasked:72; CHECK: # %bb.0:73; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma74; CHECK-NEXT: vsrl.vi v9, v8, 175; CHECK-NEXT: li a0, 8576; CHECK-NEXT: vand.vx v9, v9, a077; CHECK-NEXT: li a0, 5178; CHECK-NEXT: vsub.vv v8, v8, v979; CHECK-NEXT: vand.vx v9, v8, a080; CHECK-NEXT: vsrl.vi v8, v8, 281; CHECK-NEXT: vand.vx v8, v8, a082; CHECK-NEXT: vadd.vv v8, v9, v883; CHECK-NEXT: vsrl.vi v9, v8, 484; CHECK-NEXT: vadd.vv v8, v8, v985; CHECK-NEXT: vand.vi v8, v8, 1586; CHECK-NEXT: ret87 %v = call <4 x i8> @llvm.vp.ctpop.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)88 ret <4 x i8> %v89}90 91define <8 x i8> @vp_ctpop_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {92; CHECK-LABEL: vp_ctpop_v8i8:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma95; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t96; CHECK-NEXT: li a0, 8597; CHECK-NEXT: vand.vx v9, v9, a0, v0.t98; CHECK-NEXT: li a0, 5199; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t100; CHECK-NEXT: vand.vx v9, v8, a0, v0.t101; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t102; CHECK-NEXT: vand.vx v8, v8, a0, v0.t103; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t104; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t105; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t106; CHECK-NEXT: vand.vi v8, v8, 15, v0.t107; CHECK-NEXT: ret108 %v = call <8 x i8> @llvm.vp.ctpop.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl)109 ret <8 x i8> %v110}111 112define <8 x i8> @vp_ctpop_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {113; CHECK-LABEL: vp_ctpop_v8i8_unmasked:114; CHECK: # %bb.0:115; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma116; CHECK-NEXT: vsrl.vi v9, v8, 1117; CHECK-NEXT: li a0, 85118; CHECK-NEXT: vand.vx v9, v9, a0119; CHECK-NEXT: li a0, 51120; CHECK-NEXT: vsub.vv v8, v8, v9121; CHECK-NEXT: vand.vx v9, v8, a0122; CHECK-NEXT: vsrl.vi v8, v8, 2123; CHECK-NEXT: vand.vx v8, v8, a0124; CHECK-NEXT: vadd.vv v8, v9, v8125; CHECK-NEXT: vsrl.vi v9, v8, 4126; CHECK-NEXT: vadd.vv v8, v8, v9127; CHECK-NEXT: vand.vi v8, v8, 15128; CHECK-NEXT: ret129 %v = call <8 x i8> @llvm.vp.ctpop.v8i8(<8 x i8> %va, <8 x i1> splat (i1 true), i32 %evl)130 ret <8 x i8> %v131}132 133define <16 x i8> @vp_ctpop_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {134; CHECK-LABEL: vp_ctpop_v16i8:135; CHECK: # %bb.0:136; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma137; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t138; CHECK-NEXT: li a0, 85139; CHECK-NEXT: vand.vx v9, v9, a0, v0.t140; CHECK-NEXT: li a0, 51141; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t142; CHECK-NEXT: vand.vx v9, v8, a0, v0.t143; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t144; CHECK-NEXT: vand.vx v8, v8, a0, v0.t145; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t146; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t147; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t148; CHECK-NEXT: vand.vi v8, v8, 15, v0.t149; CHECK-NEXT: ret150 %v = call <16 x i8> @llvm.vp.ctpop.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl)151 ret <16 x i8> %v152}153 154define <16 x i8> @vp_ctpop_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {155; CHECK-LABEL: vp_ctpop_v16i8_unmasked:156; CHECK: # %bb.0:157; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma158; CHECK-NEXT: vsrl.vi v9, v8, 1159; CHECK-NEXT: li a0, 85160; CHECK-NEXT: vand.vx v9, v9, a0161; CHECK-NEXT: li a0, 51162; CHECK-NEXT: vsub.vv v8, v8, v9163; CHECK-NEXT: vand.vx v9, v8, a0164; CHECK-NEXT: vsrl.vi v8, v8, 2165; CHECK-NEXT: vand.vx v8, v8, a0166; CHECK-NEXT: vadd.vv v8, v9, v8167; CHECK-NEXT: vsrl.vi v9, v8, 4168; CHECK-NEXT: vadd.vv v8, v8, v9169; CHECK-NEXT: vand.vi v8, v8, 15170; CHECK-NEXT: ret171 %v = call <16 x i8> @llvm.vp.ctpop.v16i8(<16 x i8> %va, <16 x i1> splat (i1 true), i32 %evl)172 ret <16 x i8> %v173}174 175define <2 x i16> @vp_ctpop_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {176; CHECK-LABEL: vp_ctpop_v2i16:177; CHECK: # %bb.0:178; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma179; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t180; CHECK-NEXT: lui a0, 5181; CHECK-NEXT: addi a0, a0, 1365182; CHECK-NEXT: vand.vx v9, v9, a0, v0.t183; CHECK-NEXT: lui a0, 3184; CHECK-NEXT: addi a0, a0, 819185; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t186; CHECK-NEXT: vand.vx v9, v8, a0, v0.t187; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t188; CHECK-NEXT: vand.vx v8, v8, a0, v0.t189; CHECK-NEXT: lui a0, 1190; CHECK-NEXT: addi a0, a0, -241191; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t192; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t193; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t194; CHECK-NEXT: vand.vx v8, v8, a0, v0.t195; CHECK-NEXT: li a0, 257196; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t197; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t198; CHECK-NEXT: ret199 %v = call <2 x i16> @llvm.vp.ctpop.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl)200 ret <2 x i16> %v201}202 203define <2 x i16> @vp_ctpop_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {204; CHECK-LABEL: vp_ctpop_v2i16_unmasked:205; CHECK: # %bb.0:206; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma207; CHECK-NEXT: vsrl.vi v9, v8, 1208; CHECK-NEXT: lui a0, 5209; CHECK-NEXT: addi a0, a0, 1365210; CHECK-NEXT: vand.vx v9, v9, a0211; CHECK-NEXT: lui a0, 3212; CHECK-NEXT: addi a0, a0, 819213; CHECK-NEXT: vsub.vv v8, v8, v9214; CHECK-NEXT: vand.vx v9, v8, a0215; CHECK-NEXT: vsrl.vi v8, v8, 2216; CHECK-NEXT: vand.vx v8, v8, a0217; CHECK-NEXT: lui a0, 1218; CHECK-NEXT: addi a0, a0, -241219; CHECK-NEXT: vadd.vv v8, v9, v8220; CHECK-NEXT: vsrl.vi v9, v8, 4221; CHECK-NEXT: vadd.vv v8, v8, v9222; CHECK-NEXT: vand.vx v8, v8, a0223; CHECK-NEXT: li a0, 257224; CHECK-NEXT: vmul.vx v8, v8, a0225; CHECK-NEXT: vsrl.vi v8, v8, 8226; CHECK-NEXT: ret227 %v = call <2 x i16> @llvm.vp.ctpop.v2i16(<2 x i16> %va, <2 x i1> splat (i1 true), i32 %evl)228 ret <2 x i16> %v229}230 231define <4 x i16> @vp_ctpop_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {232; CHECK-LABEL: vp_ctpop_v4i16:233; CHECK: # %bb.0:234; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma235; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t236; CHECK-NEXT: lui a0, 5237; CHECK-NEXT: addi a0, a0, 1365238; CHECK-NEXT: vand.vx v9, v9, a0, v0.t239; CHECK-NEXT: lui a0, 3240; CHECK-NEXT: addi a0, a0, 819241; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t242; CHECK-NEXT: vand.vx v9, v8, a0, v0.t243; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t244; CHECK-NEXT: vand.vx v8, v8, a0, v0.t245; CHECK-NEXT: lui a0, 1246; CHECK-NEXT: addi a0, a0, -241247; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t248; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t249; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t250; CHECK-NEXT: vand.vx v8, v8, a0, v0.t251; CHECK-NEXT: li a0, 257252; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t253; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t254; CHECK-NEXT: ret255 %v = call <4 x i16> @llvm.vp.ctpop.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)256 ret <4 x i16> %v257}258 259define <4 x i16> @vp_ctpop_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {260; CHECK-LABEL: vp_ctpop_v4i16_unmasked:261; CHECK: # %bb.0:262; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma263; CHECK-NEXT: vsrl.vi v9, v8, 1264; CHECK-NEXT: lui a0, 5265; CHECK-NEXT: addi a0, a0, 1365266; CHECK-NEXT: vand.vx v9, v9, a0267; CHECK-NEXT: lui a0, 3268; CHECK-NEXT: addi a0, a0, 819269; CHECK-NEXT: vsub.vv v8, v8, v9270; CHECK-NEXT: vand.vx v9, v8, a0271; CHECK-NEXT: vsrl.vi v8, v8, 2272; CHECK-NEXT: vand.vx v8, v8, a0273; CHECK-NEXT: lui a0, 1274; CHECK-NEXT: addi a0, a0, -241275; CHECK-NEXT: vadd.vv v8, v9, v8276; CHECK-NEXT: vsrl.vi v9, v8, 4277; CHECK-NEXT: vadd.vv v8, v8, v9278; CHECK-NEXT: vand.vx v8, v8, a0279; CHECK-NEXT: li a0, 257280; CHECK-NEXT: vmul.vx v8, v8, a0281; CHECK-NEXT: vsrl.vi v8, v8, 8282; CHECK-NEXT: ret283 %v = call <4 x i16> @llvm.vp.ctpop.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl)284 ret <4 x i16> %v285}286 287define <8 x i16> @vp_ctpop_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {288; CHECK-LABEL: vp_ctpop_v8i16:289; CHECK: # %bb.0:290; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma291; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t292; CHECK-NEXT: lui a0, 5293; CHECK-NEXT: addi a0, a0, 1365294; CHECK-NEXT: vand.vx v9, v9, a0, v0.t295; CHECK-NEXT: lui a0, 3296; CHECK-NEXT: addi a0, a0, 819297; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t298; CHECK-NEXT: vand.vx v9, v8, a0, v0.t299; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t300; CHECK-NEXT: vand.vx v8, v8, a0, v0.t301; CHECK-NEXT: lui a0, 1302; CHECK-NEXT: addi a0, a0, -241303; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t304; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t305; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t306; CHECK-NEXT: vand.vx v8, v8, a0, v0.t307; CHECK-NEXT: li a0, 257308; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t309; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t310; CHECK-NEXT: ret311 %v = call <8 x i16> @llvm.vp.ctpop.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl)312 ret <8 x i16> %v313}314 315define <8 x i16> @vp_ctpop_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {316; CHECK-LABEL: vp_ctpop_v8i16_unmasked:317; CHECK: # %bb.0:318; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma319; CHECK-NEXT: vsrl.vi v9, v8, 1320; CHECK-NEXT: lui a0, 5321; CHECK-NEXT: addi a0, a0, 1365322; CHECK-NEXT: vand.vx v9, v9, a0323; CHECK-NEXT: lui a0, 3324; CHECK-NEXT: addi a0, a0, 819325; CHECK-NEXT: vsub.vv v8, v8, v9326; CHECK-NEXT: vand.vx v9, v8, a0327; CHECK-NEXT: vsrl.vi v8, v8, 2328; CHECK-NEXT: vand.vx v8, v8, a0329; CHECK-NEXT: lui a0, 1330; CHECK-NEXT: addi a0, a0, -241331; CHECK-NEXT: vadd.vv v8, v9, v8332; CHECK-NEXT: vsrl.vi v9, v8, 4333; CHECK-NEXT: vadd.vv v8, v8, v9334; CHECK-NEXT: vand.vx v8, v8, a0335; CHECK-NEXT: li a0, 257336; CHECK-NEXT: vmul.vx v8, v8, a0337; CHECK-NEXT: vsrl.vi v8, v8, 8338; CHECK-NEXT: ret339 %v = call <8 x i16> @llvm.vp.ctpop.v8i16(<8 x i16> %va, <8 x i1> splat (i1 true), i32 %evl)340 ret <8 x i16> %v341}342 343define <16 x i16> @vp_ctpop_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {344; CHECK-LABEL: vp_ctpop_v16i16:345; CHECK: # %bb.0:346; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma347; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t348; CHECK-NEXT: lui a0, 5349; CHECK-NEXT: addi a0, a0, 1365350; CHECK-NEXT: vand.vx v10, v10, a0, v0.t351; CHECK-NEXT: lui a0, 3352; CHECK-NEXT: addi a0, a0, 819353; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t354; CHECK-NEXT: vand.vx v10, v8, a0, v0.t355; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t356; CHECK-NEXT: vand.vx v8, v8, a0, v0.t357; CHECK-NEXT: lui a0, 1358; CHECK-NEXT: addi a0, a0, -241359; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t360; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t361; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t362; CHECK-NEXT: vand.vx v8, v8, a0, v0.t363; CHECK-NEXT: li a0, 257364; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t365; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t366; CHECK-NEXT: ret367 %v = call <16 x i16> @llvm.vp.ctpop.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl)368 ret <16 x i16> %v369}370 371define <16 x i16> @vp_ctpop_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {372; CHECK-LABEL: vp_ctpop_v16i16_unmasked:373; CHECK: # %bb.0:374; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma375; CHECK-NEXT: vsrl.vi v10, v8, 1376; CHECK-NEXT: lui a0, 5377; CHECK-NEXT: addi a0, a0, 1365378; CHECK-NEXT: vand.vx v10, v10, a0379; CHECK-NEXT: lui a0, 3380; CHECK-NEXT: addi a0, a0, 819381; CHECK-NEXT: vsub.vv v8, v8, v10382; CHECK-NEXT: vand.vx v10, v8, a0383; CHECK-NEXT: vsrl.vi v8, v8, 2384; CHECK-NEXT: vand.vx v8, v8, a0385; CHECK-NEXT: lui a0, 1386; CHECK-NEXT: addi a0, a0, -241387; CHECK-NEXT: vadd.vv v8, v10, v8388; CHECK-NEXT: vsrl.vi v10, v8, 4389; CHECK-NEXT: vadd.vv v8, v8, v10390; CHECK-NEXT: vand.vx v8, v8, a0391; CHECK-NEXT: li a0, 257392; CHECK-NEXT: vmul.vx v8, v8, a0393; CHECK-NEXT: vsrl.vi v8, v8, 8394; CHECK-NEXT: ret395 %v = call <16 x i16> @llvm.vp.ctpop.v16i16(<16 x i16> %va, <16 x i1> splat (i1 true), i32 %evl)396 ret <16 x i16> %v397}398 399define <2 x i32> @vp_ctpop_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {400; CHECK-LABEL: vp_ctpop_v2i32:401; CHECK: # %bb.0:402; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma403; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t404; CHECK-NEXT: lui a0, 349525405; CHECK-NEXT: addi a0, a0, 1365406; CHECK-NEXT: vand.vx v9, v9, a0, v0.t407; CHECK-NEXT: lui a0, 209715408; CHECK-NEXT: addi a0, a0, 819409; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t410; CHECK-NEXT: vand.vx v9, v8, a0, v0.t411; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t412; CHECK-NEXT: vand.vx v8, v8, a0, v0.t413; CHECK-NEXT: lui a0, 61681414; CHECK-NEXT: addi a0, a0, -241415; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t416; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t417; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t418; CHECK-NEXT: vand.vx v8, v8, a0, v0.t419; CHECK-NEXT: lui a0, 4112420; CHECK-NEXT: addi a0, a0, 257421; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t422; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t423; CHECK-NEXT: ret424 %v = call <2 x i32> @llvm.vp.ctpop.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl)425 ret <2 x i32> %v426}427 428define <2 x i32> @vp_ctpop_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {429; CHECK-LABEL: vp_ctpop_v2i32_unmasked:430; CHECK: # %bb.0:431; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma432; CHECK-NEXT: vsrl.vi v9, v8, 1433; CHECK-NEXT: lui a0, 349525434; CHECK-NEXT: addi a0, a0, 1365435; CHECK-NEXT: vand.vx v9, v9, a0436; CHECK-NEXT: lui a0, 209715437; CHECK-NEXT: addi a0, a0, 819438; CHECK-NEXT: vsub.vv v8, v8, v9439; CHECK-NEXT: vand.vx v9, v8, a0440; CHECK-NEXT: vsrl.vi v8, v8, 2441; CHECK-NEXT: vand.vx v8, v8, a0442; CHECK-NEXT: lui a0, 61681443; CHECK-NEXT: addi a0, a0, -241444; CHECK-NEXT: vadd.vv v8, v9, v8445; CHECK-NEXT: vsrl.vi v9, v8, 4446; CHECK-NEXT: vadd.vv v8, v8, v9447; CHECK-NEXT: vand.vx v8, v8, a0448; CHECK-NEXT: lui a0, 4112449; CHECK-NEXT: addi a0, a0, 257450; CHECK-NEXT: vmul.vx v8, v8, a0451; CHECK-NEXT: vsrl.vi v8, v8, 24452; CHECK-NEXT: ret453 %v = call <2 x i32> @llvm.vp.ctpop.v2i32(<2 x i32> %va, <2 x i1> splat (i1 true), i32 %evl)454 ret <2 x i32> %v455}456 457define <4 x i32> @vp_ctpop_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {458; CHECK-LABEL: vp_ctpop_v4i32:459; CHECK: # %bb.0:460; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma461; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t462; CHECK-NEXT: lui a0, 349525463; CHECK-NEXT: addi a0, a0, 1365464; CHECK-NEXT: vand.vx v9, v9, a0, v0.t465; CHECK-NEXT: lui a0, 209715466; CHECK-NEXT: addi a0, a0, 819467; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t468; CHECK-NEXT: vand.vx v9, v8, a0, v0.t469; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t470; CHECK-NEXT: vand.vx v8, v8, a0, v0.t471; CHECK-NEXT: lui a0, 61681472; CHECK-NEXT: addi a0, a0, -241473; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t474; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t475; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t476; CHECK-NEXT: vand.vx v8, v8, a0, v0.t477; CHECK-NEXT: lui a0, 4112478; CHECK-NEXT: addi a0, a0, 257479; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t480; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t481; CHECK-NEXT: ret482 %v = call <4 x i32> @llvm.vp.ctpop.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)483 ret <4 x i32> %v484}485 486define <4 x i32> @vp_ctpop_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {487; CHECK-LABEL: vp_ctpop_v4i32_unmasked:488; CHECK: # %bb.0:489; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma490; CHECK-NEXT: vsrl.vi v9, v8, 1491; CHECK-NEXT: lui a0, 349525492; CHECK-NEXT: addi a0, a0, 1365493; CHECK-NEXT: vand.vx v9, v9, a0494; CHECK-NEXT: lui a0, 209715495; CHECK-NEXT: addi a0, a0, 819496; CHECK-NEXT: vsub.vv v8, v8, v9497; CHECK-NEXT: vand.vx v9, v8, a0498; CHECK-NEXT: vsrl.vi v8, v8, 2499; CHECK-NEXT: vand.vx v8, v8, a0500; CHECK-NEXT: lui a0, 61681501; CHECK-NEXT: addi a0, a0, -241502; CHECK-NEXT: vadd.vv v8, v9, v8503; CHECK-NEXT: vsrl.vi v9, v8, 4504; CHECK-NEXT: vadd.vv v8, v8, v9505; CHECK-NEXT: vand.vx v8, v8, a0506; CHECK-NEXT: lui a0, 4112507; CHECK-NEXT: addi a0, a0, 257508; CHECK-NEXT: vmul.vx v8, v8, a0509; CHECK-NEXT: vsrl.vi v8, v8, 24510; CHECK-NEXT: ret511 %v = call <4 x i32> @llvm.vp.ctpop.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl)512 ret <4 x i32> %v513}514 515define <8 x i32> @vp_ctpop_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {516; CHECK-LABEL: vp_ctpop_v8i32:517; CHECK: # %bb.0:518; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma519; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t520; CHECK-NEXT: lui a0, 349525521; CHECK-NEXT: addi a0, a0, 1365522; CHECK-NEXT: vand.vx v10, v10, a0, v0.t523; CHECK-NEXT: lui a0, 209715524; CHECK-NEXT: addi a0, a0, 819525; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t526; CHECK-NEXT: vand.vx v10, v8, a0, v0.t527; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t528; CHECK-NEXT: vand.vx v8, v8, a0, v0.t529; CHECK-NEXT: lui a0, 61681530; CHECK-NEXT: addi a0, a0, -241531; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t532; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t533; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t534; CHECK-NEXT: vand.vx v8, v8, a0, v0.t535; CHECK-NEXT: lui a0, 4112536; CHECK-NEXT: addi a0, a0, 257537; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t538; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t539; CHECK-NEXT: ret540 %v = call <8 x i32> @llvm.vp.ctpop.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl)541 ret <8 x i32> %v542}543 544define <8 x i32> @vp_ctpop_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {545; CHECK-LABEL: vp_ctpop_v8i32_unmasked:546; CHECK: # %bb.0:547; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma548; CHECK-NEXT: vsrl.vi v10, v8, 1549; CHECK-NEXT: lui a0, 349525550; CHECK-NEXT: addi a0, a0, 1365551; CHECK-NEXT: vand.vx v10, v10, a0552; CHECK-NEXT: lui a0, 209715553; CHECK-NEXT: addi a0, a0, 819554; CHECK-NEXT: vsub.vv v8, v8, v10555; CHECK-NEXT: vand.vx v10, v8, a0556; CHECK-NEXT: vsrl.vi v8, v8, 2557; CHECK-NEXT: vand.vx v8, v8, a0558; CHECK-NEXT: lui a0, 61681559; CHECK-NEXT: addi a0, a0, -241560; CHECK-NEXT: vadd.vv v8, v10, v8561; CHECK-NEXT: vsrl.vi v10, v8, 4562; CHECK-NEXT: vadd.vv v8, v8, v10563; CHECK-NEXT: vand.vx v8, v8, a0564; CHECK-NEXT: lui a0, 4112565; CHECK-NEXT: addi a0, a0, 257566; CHECK-NEXT: vmul.vx v8, v8, a0567; CHECK-NEXT: vsrl.vi v8, v8, 24568; CHECK-NEXT: ret569 %v = call <8 x i32> @llvm.vp.ctpop.v8i32(<8 x i32> %va, <8 x i1> splat (i1 true), i32 %evl)570 ret <8 x i32> %v571}572 573define <16 x i32> @vp_ctpop_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {574; CHECK-LABEL: vp_ctpop_v16i32:575; CHECK: # %bb.0:576; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma577; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t578; CHECK-NEXT: lui a0, 349525579; CHECK-NEXT: addi a0, a0, 1365580; CHECK-NEXT: vand.vx v12, v12, a0, v0.t581; CHECK-NEXT: lui a0, 209715582; CHECK-NEXT: addi a0, a0, 819583; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t584; CHECK-NEXT: vand.vx v12, v8, a0, v0.t585; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t586; CHECK-NEXT: vand.vx v8, v8, a0, v0.t587; CHECK-NEXT: lui a0, 61681588; CHECK-NEXT: addi a0, a0, -241589; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t590; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t591; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t592; CHECK-NEXT: vand.vx v8, v8, a0, v0.t593; CHECK-NEXT: lui a0, 4112594; CHECK-NEXT: addi a0, a0, 257595; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t596; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t597; CHECK-NEXT: ret598 %v = call <16 x i32> @llvm.vp.ctpop.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl)599 ret <16 x i32> %v600}601 602define <16 x i32> @vp_ctpop_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {603; CHECK-LABEL: vp_ctpop_v16i32_unmasked:604; CHECK: # %bb.0:605; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma606; CHECK-NEXT: vsrl.vi v12, v8, 1607; CHECK-NEXT: lui a0, 349525608; CHECK-NEXT: addi a0, a0, 1365609; CHECK-NEXT: vand.vx v12, v12, a0610; CHECK-NEXT: lui a0, 209715611; CHECK-NEXT: addi a0, a0, 819612; CHECK-NEXT: vsub.vv v8, v8, v12613; CHECK-NEXT: vand.vx v12, v8, a0614; CHECK-NEXT: vsrl.vi v8, v8, 2615; CHECK-NEXT: vand.vx v8, v8, a0616; CHECK-NEXT: lui a0, 61681617; CHECK-NEXT: addi a0, a0, -241618; CHECK-NEXT: vadd.vv v8, v12, v8619; CHECK-NEXT: vsrl.vi v12, v8, 4620; CHECK-NEXT: vadd.vv v8, v8, v12621; CHECK-NEXT: vand.vx v8, v8, a0622; CHECK-NEXT: lui a0, 4112623; CHECK-NEXT: addi a0, a0, 257624; CHECK-NEXT: vmul.vx v8, v8, a0625; CHECK-NEXT: vsrl.vi v8, v8, 24626; CHECK-NEXT: ret627 %v = call <16 x i32> @llvm.vp.ctpop.v16i32(<16 x i32> %va, <16 x i1> splat (i1 true), i32 %evl)628 ret <16 x i32> %v629}630 631define <2 x i64> @vp_ctpop_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {632; RV32-LABEL: vp_ctpop_v2i64:633; RV32: # %bb.0:634; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma635; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t636; RV32-NEXT: lui a1, 349525637; RV32-NEXT: addi a1, a1, 1365638; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma639; RV32-NEXT: vmv.v.x v10, a1640; RV32-NEXT: lui a1, 209715641; RV32-NEXT: addi a1, a1, 819642; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma643; RV32-NEXT: vand.vv v9, v9, v10, v0.t644; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma645; RV32-NEXT: vmv.v.x v10, a1646; RV32-NEXT: lui a1, 61681647; RV32-NEXT: addi a1, a1, -241648; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma649; RV32-NEXT: vsub.vv v8, v8, v9, v0.t650; RV32-NEXT: vand.vv v9, v8, v10, v0.t651; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t652; RV32-NEXT: vand.vv v8, v8, v10, v0.t653; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma654; RV32-NEXT: vmv.v.x v10, a1655; RV32-NEXT: lui a1, 4112656; RV32-NEXT: addi a1, a1, 257657; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma658; RV32-NEXT: vadd.vv v8, v9, v8, v0.t659; RV32-NEXT: vsrl.vi v9, v8, 4, v0.t660; RV32-NEXT: vadd.vv v8, v8, v9, v0.t661; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma662; RV32-NEXT: vmv.v.x v9, a1663; RV32-NEXT: li a1, 56664; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma665; RV32-NEXT: vand.vv v8, v8, v10, v0.t666; RV32-NEXT: vmul.vv v8, v8, v9, v0.t667; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t668; RV32-NEXT: ret669;670; RV64-LABEL: vp_ctpop_v2i64:671; RV64: # %bb.0:672; RV64-NEXT: lui a1, 349525673; RV64-NEXT: lui a2, 209715674; RV64-NEXT: lui a3, 61681675; RV64-NEXT: lui a4, 4112676; RV64-NEXT: addi a1, a1, 1365677; RV64-NEXT: addi a2, a2, 819678; RV64-NEXT: addi a3, a3, -241679; RV64-NEXT: addi a4, a4, 257680; RV64-NEXT: slli a5, a1, 32681; RV64-NEXT: add a1, a1, a5682; RV64-NEXT: slli a5, a2, 32683; RV64-NEXT: add a2, a2, a5684; RV64-NEXT: slli a5, a3, 32685; RV64-NEXT: add a3, a3, a5686; RV64-NEXT: slli a5, a4, 32687; RV64-NEXT: add a4, a4, a5688; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma689; RV64-NEXT: vsrl.vi v9, v8, 1, v0.t690; RV64-NEXT: vand.vx v9, v9, a1, v0.t691; RV64-NEXT: vsub.vv v8, v8, v9, v0.t692; RV64-NEXT: vand.vx v9, v8, a2, v0.t693; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t694; RV64-NEXT: vand.vx v8, v8, a2, v0.t695; RV64-NEXT: vadd.vv v8, v9, v8, v0.t696; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t697; RV64-NEXT: vadd.vv v8, v8, v9, v0.t698; RV64-NEXT: vand.vx v8, v8, a3, v0.t699; RV64-NEXT: li a0, 56700; RV64-NEXT: vmul.vx v8, v8, a4, v0.t701; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t702; RV64-NEXT: ret703 %v = call <2 x i64> @llvm.vp.ctpop.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl)704 ret <2 x i64> %v705}706 707define <2 x i64> @vp_ctpop_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {708; RV32-LABEL: vp_ctpop_v2i64_unmasked:709; RV32: # %bb.0:710; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma711; RV32-NEXT: vsrl.vi v9, v8, 1712; RV32-NEXT: lui a1, 349525713; RV32-NEXT: addi a1, a1, 1365714; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma715; RV32-NEXT: vmv.v.x v10, a1716; RV32-NEXT: lui a1, 209715717; RV32-NEXT: addi a1, a1, 819718; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma719; RV32-NEXT: vand.vv v9, v9, v10720; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma721; RV32-NEXT: vmv.v.x v10, a1722; RV32-NEXT: lui a1, 61681723; RV32-NEXT: addi a1, a1, -241724; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma725; RV32-NEXT: vsub.vv v8, v8, v9726; RV32-NEXT: vand.vv v9, v8, v10727; RV32-NEXT: vsrl.vi v8, v8, 2728; RV32-NEXT: vand.vv v8, v8, v10729; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma730; RV32-NEXT: vmv.v.x v10, a1731; RV32-NEXT: lui a1, 4112732; RV32-NEXT: addi a1, a1, 257733; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma734; RV32-NEXT: vadd.vv v8, v9, v8735; RV32-NEXT: vsrl.vi v9, v8, 4736; RV32-NEXT: vadd.vv v8, v8, v9737; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma738; RV32-NEXT: vmv.v.x v9, a1739; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma740; RV32-NEXT: vand.vv v8, v8, v10741; RV32-NEXT: vmul.vv v8, v8, v9742; RV32-NEXT: li a0, 56743; RV32-NEXT: vsrl.vx v8, v8, a0744; RV32-NEXT: ret745;746; RV64-LABEL: vp_ctpop_v2i64_unmasked:747; RV64: # %bb.0:748; RV64-NEXT: lui a1, 349525749; RV64-NEXT: lui a2, 209715750; RV64-NEXT: lui a3, 61681751; RV64-NEXT: lui a4, 4112752; RV64-NEXT: addi a1, a1, 1365753; RV64-NEXT: addi a2, a2, 819754; RV64-NEXT: addi a3, a3, -241755; RV64-NEXT: addi a4, a4, 257756; RV64-NEXT: slli a5, a1, 32757; RV64-NEXT: add a1, a1, a5758; RV64-NEXT: slli a5, a2, 32759; RV64-NEXT: add a2, a2, a5760; RV64-NEXT: slli a5, a3, 32761; RV64-NEXT: add a3, a3, a5762; RV64-NEXT: slli a5, a4, 32763; RV64-NEXT: add a4, a4, a5764; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma765; RV64-NEXT: vsrl.vi v9, v8, 1766; RV64-NEXT: vand.vx v9, v9, a1767; RV64-NEXT: vsub.vv v8, v8, v9768; RV64-NEXT: vand.vx v9, v8, a2769; RV64-NEXT: vsrl.vi v8, v8, 2770; RV64-NEXT: vand.vx v8, v8, a2771; RV64-NEXT: vadd.vv v8, v9, v8772; RV64-NEXT: vsrl.vi v9, v8, 4773; RV64-NEXT: vadd.vv v8, v8, v9774; RV64-NEXT: vand.vx v8, v8, a3775; RV64-NEXT: vmul.vx v8, v8, a4776; RV64-NEXT: li a0, 56777; RV64-NEXT: vsrl.vx v8, v8, a0778; RV64-NEXT: ret779 %v = call <2 x i64> @llvm.vp.ctpop.v2i64(<2 x i64> %va, <2 x i1> splat (i1 true), i32 %evl)780 ret <2 x i64> %v781}782 783define <4 x i64> @vp_ctpop_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {784; RV32-LABEL: vp_ctpop_v4i64:785; RV32: # %bb.0:786; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma787; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t788; RV32-NEXT: lui a1, 349525789; RV32-NEXT: addi a1, a1, 1365790; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma791; RV32-NEXT: vmv.v.x v12, a1792; RV32-NEXT: lui a1, 209715793; RV32-NEXT: addi a1, a1, 819794; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma795; RV32-NEXT: vand.vv v10, v10, v12, v0.t796; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma797; RV32-NEXT: vmv.v.x v12, a1798; RV32-NEXT: lui a1, 61681799; RV32-NEXT: addi a1, a1, -241800; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma801; RV32-NEXT: vsub.vv v8, v8, v10, v0.t802; RV32-NEXT: vand.vv v10, v8, v12, v0.t803; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t804; RV32-NEXT: vand.vv v8, v8, v12, v0.t805; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma806; RV32-NEXT: vmv.v.x v12, a1807; RV32-NEXT: lui a1, 4112808; RV32-NEXT: addi a1, a1, 257809; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma810; RV32-NEXT: vadd.vv v8, v10, v8, v0.t811; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t812; RV32-NEXT: vadd.vv v8, v8, v10, v0.t813; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma814; RV32-NEXT: vmv.v.x v10, a1815; RV32-NEXT: li a1, 56816; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma817; RV32-NEXT: vand.vv v8, v8, v12, v0.t818; RV32-NEXT: vmul.vv v8, v8, v10, v0.t819; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t820; RV32-NEXT: ret821;822; RV64-LABEL: vp_ctpop_v4i64:823; RV64: # %bb.0:824; RV64-NEXT: lui a1, 349525825; RV64-NEXT: lui a2, 209715826; RV64-NEXT: lui a3, 61681827; RV64-NEXT: lui a4, 4112828; RV64-NEXT: addi a1, a1, 1365829; RV64-NEXT: addi a2, a2, 819830; RV64-NEXT: addi a3, a3, -241831; RV64-NEXT: addi a4, a4, 257832; RV64-NEXT: slli a5, a1, 32833; RV64-NEXT: add a1, a1, a5834; RV64-NEXT: slli a5, a2, 32835; RV64-NEXT: add a2, a2, a5836; RV64-NEXT: slli a5, a3, 32837; RV64-NEXT: add a3, a3, a5838; RV64-NEXT: slli a5, a4, 32839; RV64-NEXT: add a4, a4, a5840; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma841; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t842; RV64-NEXT: vand.vx v10, v10, a1, v0.t843; RV64-NEXT: vsub.vv v8, v8, v10, v0.t844; RV64-NEXT: vand.vx v10, v8, a2, v0.t845; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t846; RV64-NEXT: vand.vx v8, v8, a2, v0.t847; RV64-NEXT: vadd.vv v8, v10, v8, v0.t848; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t849; RV64-NEXT: vadd.vv v8, v8, v10, v0.t850; RV64-NEXT: vand.vx v8, v8, a3, v0.t851; RV64-NEXT: li a0, 56852; RV64-NEXT: vmul.vx v8, v8, a4, v0.t853; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t854; RV64-NEXT: ret855 %v = call <4 x i64> @llvm.vp.ctpop.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)856 ret <4 x i64> %v857}858 859define <4 x i64> @vp_ctpop_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {860; RV32-LABEL: vp_ctpop_v4i64_unmasked:861; RV32: # %bb.0:862; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma863; RV32-NEXT: vsrl.vi v10, v8, 1864; RV32-NEXT: lui a1, 349525865; RV32-NEXT: addi a1, a1, 1365866; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma867; RV32-NEXT: vmv.v.x v12, a1868; RV32-NEXT: lui a1, 209715869; RV32-NEXT: addi a1, a1, 819870; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma871; RV32-NEXT: vand.vv v10, v10, v12872; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma873; RV32-NEXT: vmv.v.x v12, a1874; RV32-NEXT: lui a1, 61681875; RV32-NEXT: addi a1, a1, -241876; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma877; RV32-NEXT: vsub.vv v8, v8, v10878; RV32-NEXT: vand.vv v10, v8, v12879; RV32-NEXT: vsrl.vi v8, v8, 2880; RV32-NEXT: vand.vv v8, v8, v12881; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma882; RV32-NEXT: vmv.v.x v12, a1883; RV32-NEXT: lui a1, 4112884; RV32-NEXT: addi a1, a1, 257885; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma886; RV32-NEXT: vadd.vv v8, v10, v8887; RV32-NEXT: vsrl.vi v10, v8, 4888; RV32-NEXT: vadd.vv v8, v8, v10889; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma890; RV32-NEXT: vmv.v.x v10, a1891; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma892; RV32-NEXT: vand.vv v8, v8, v12893; RV32-NEXT: vmul.vv v8, v8, v10894; RV32-NEXT: li a0, 56895; RV32-NEXT: vsrl.vx v8, v8, a0896; RV32-NEXT: ret897;898; RV64-LABEL: vp_ctpop_v4i64_unmasked:899; RV64: # %bb.0:900; RV64-NEXT: lui a1, 349525901; RV64-NEXT: lui a2, 209715902; RV64-NEXT: lui a3, 61681903; RV64-NEXT: lui a4, 4112904; RV64-NEXT: addi a1, a1, 1365905; RV64-NEXT: addi a2, a2, 819906; RV64-NEXT: addi a3, a3, -241907; RV64-NEXT: addi a4, a4, 257908; RV64-NEXT: slli a5, a1, 32909; RV64-NEXT: add a1, a1, a5910; RV64-NEXT: slli a5, a2, 32911; RV64-NEXT: add a2, a2, a5912; RV64-NEXT: slli a5, a3, 32913; RV64-NEXT: add a3, a3, a5914; RV64-NEXT: slli a5, a4, 32915; RV64-NEXT: add a4, a4, a5916; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma917; RV64-NEXT: vsrl.vi v10, v8, 1918; RV64-NEXT: vand.vx v10, v10, a1919; RV64-NEXT: vsub.vv v8, v8, v10920; RV64-NEXT: vand.vx v10, v8, a2921; RV64-NEXT: vsrl.vi v8, v8, 2922; RV64-NEXT: vand.vx v8, v8, a2923; RV64-NEXT: vadd.vv v8, v10, v8924; RV64-NEXT: vsrl.vi v10, v8, 4925; RV64-NEXT: vadd.vv v8, v8, v10926; RV64-NEXT: vand.vx v8, v8, a3927; RV64-NEXT: vmul.vx v8, v8, a4928; RV64-NEXT: li a0, 56929; RV64-NEXT: vsrl.vx v8, v8, a0930; RV64-NEXT: ret931 %v = call <4 x i64> @llvm.vp.ctpop.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl)932 ret <4 x i64> %v933}934 935define <8 x i64> @vp_ctpop_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {936; RV32-LABEL: vp_ctpop_v8i64:937; RV32: # %bb.0:938; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma939; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t940; RV32-NEXT: lui a1, 349525941; RV32-NEXT: addi a1, a1, 1365942; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma943; RV32-NEXT: vmv.v.x v16, a1944; RV32-NEXT: lui a1, 209715945; RV32-NEXT: addi a1, a1, 819946; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma947; RV32-NEXT: vand.vv v16, v12, v16, v0.t948; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma949; RV32-NEXT: vmv.v.x v12, a1950; RV32-NEXT: lui a1, 61681951; RV32-NEXT: addi a1, a1, -241952; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma953; RV32-NEXT: vsub.vv v8, v8, v16, v0.t954; RV32-NEXT: vand.vv v16, v8, v12, v0.t955; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t956; RV32-NEXT: vand.vv v8, v8, v12, v0.t957; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma958; RV32-NEXT: vmv.v.x v12, a1959; RV32-NEXT: lui a1, 4112960; RV32-NEXT: addi a1, a1, 257961; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma962; RV32-NEXT: vadd.vv v8, v16, v8, v0.t963; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t964; RV32-NEXT: vadd.vv v8, v8, v16, v0.t965; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma966; RV32-NEXT: vmv.v.x v16, a1967; RV32-NEXT: li a1, 56968; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma969; RV32-NEXT: vand.vv v8, v8, v12, v0.t970; RV32-NEXT: vmul.vv v8, v8, v16, v0.t971; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t972; RV32-NEXT: ret973;974; RV64-LABEL: vp_ctpop_v8i64:975; RV64: # %bb.0:976; RV64-NEXT: lui a1, 349525977; RV64-NEXT: lui a2, 209715978; RV64-NEXT: lui a3, 61681979; RV64-NEXT: lui a4, 4112980; RV64-NEXT: addi a1, a1, 1365981; RV64-NEXT: addi a2, a2, 819982; RV64-NEXT: addi a3, a3, -241983; RV64-NEXT: addi a4, a4, 257984; RV64-NEXT: slli a5, a1, 32985; RV64-NEXT: add a1, a1, a5986; RV64-NEXT: slli a5, a2, 32987; RV64-NEXT: add a2, a2, a5988; RV64-NEXT: slli a5, a3, 32989; RV64-NEXT: add a3, a3, a5990; RV64-NEXT: slli a5, a4, 32991; RV64-NEXT: add a4, a4, a5992; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma993; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t994; RV64-NEXT: vand.vx v12, v12, a1, v0.t995; RV64-NEXT: vsub.vv v8, v8, v12, v0.t996; RV64-NEXT: vand.vx v12, v8, a2, v0.t997; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t998; RV64-NEXT: vand.vx v8, v8, a2, v0.t999; RV64-NEXT: vadd.vv v8, v12, v8, v0.t1000; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t1001; RV64-NEXT: vadd.vv v8, v8, v12, v0.t1002; RV64-NEXT: vand.vx v8, v8, a3, v0.t1003; RV64-NEXT: li a0, 561004; RV64-NEXT: vmul.vx v8, v8, a4, v0.t1005; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1006; RV64-NEXT: ret1007 %v = call <8 x i64> @llvm.vp.ctpop.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl)1008 ret <8 x i64> %v1009}1010 1011define <8 x i64> @vp_ctpop_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {1012; RV32-LABEL: vp_ctpop_v8i64_unmasked:1013; RV32: # %bb.0:1014; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1015; RV32-NEXT: vsrl.vi v12, v8, 11016; RV32-NEXT: lui a1, 3495251017; RV32-NEXT: addi a1, a1, 13651018; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1019; RV32-NEXT: vmv.v.x v16, a11020; RV32-NEXT: lui a1, 2097151021; RV32-NEXT: addi a1, a1, 8191022; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1023; RV32-NEXT: vand.vv v12, v12, v161024; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1025; RV32-NEXT: vmv.v.x v16, a11026; RV32-NEXT: lui a1, 616811027; RV32-NEXT: addi a1, a1, -2411028; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1029; RV32-NEXT: vsub.vv v8, v8, v121030; RV32-NEXT: vand.vv v12, v8, v161031; RV32-NEXT: vsrl.vi v8, v8, 21032; RV32-NEXT: vand.vv v8, v8, v161033; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1034; RV32-NEXT: vmv.v.x v16, a11035; RV32-NEXT: lui a1, 41121036; RV32-NEXT: addi a1, a1, 2571037; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1038; RV32-NEXT: vadd.vv v8, v12, v81039; RV32-NEXT: vsrl.vi v12, v8, 41040; RV32-NEXT: vadd.vv v8, v8, v121041; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1042; RV32-NEXT: vmv.v.x v12, a11043; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1044; RV32-NEXT: vand.vv v8, v8, v161045; RV32-NEXT: vmul.vv v8, v8, v121046; RV32-NEXT: li a0, 561047; RV32-NEXT: vsrl.vx v8, v8, a01048; RV32-NEXT: ret1049;1050; RV64-LABEL: vp_ctpop_v8i64_unmasked:1051; RV64: # %bb.0:1052; RV64-NEXT: lui a1, 3495251053; RV64-NEXT: lui a2, 2097151054; RV64-NEXT: lui a3, 616811055; RV64-NEXT: lui a4, 41121056; RV64-NEXT: addi a1, a1, 13651057; RV64-NEXT: addi a2, a2, 8191058; RV64-NEXT: addi a3, a3, -2411059; RV64-NEXT: addi a4, a4, 2571060; RV64-NEXT: slli a5, a1, 321061; RV64-NEXT: add a1, a1, a51062; RV64-NEXT: slli a5, a2, 321063; RV64-NEXT: add a2, a2, a51064; RV64-NEXT: slli a5, a3, 321065; RV64-NEXT: add a3, a3, a51066; RV64-NEXT: slli a5, a4, 321067; RV64-NEXT: add a4, a4, a51068; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma1069; RV64-NEXT: vsrl.vi v12, v8, 11070; RV64-NEXT: vand.vx v12, v12, a11071; RV64-NEXT: vsub.vv v8, v8, v121072; RV64-NEXT: vand.vx v12, v8, a21073; RV64-NEXT: vsrl.vi v8, v8, 21074; RV64-NEXT: vand.vx v8, v8, a21075; RV64-NEXT: vadd.vv v8, v12, v81076; RV64-NEXT: vsrl.vi v12, v8, 41077; RV64-NEXT: vadd.vv v8, v8, v121078; RV64-NEXT: vand.vx v8, v8, a31079; RV64-NEXT: vmul.vx v8, v8, a41080; RV64-NEXT: li a0, 561081; RV64-NEXT: vsrl.vx v8, v8, a01082; RV64-NEXT: ret1083 %v = call <8 x i64> @llvm.vp.ctpop.v8i64(<8 x i64> %va, <8 x i1> splat (i1 true), i32 %evl)1084 ret <8 x i64> %v1085}1086 1087define <15 x i64> @vp_ctpop_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {1088; RV32-LABEL: vp_ctpop_v15i64:1089; RV32: # %bb.0:1090; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1091; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t1092; RV32-NEXT: lui a1, 3495251093; RV32-NEXT: addi a1, a1, 13651094; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1095; RV32-NEXT: vmv.v.x v24, a11096; RV32-NEXT: lui a1, 2097151097; RV32-NEXT: addi a1, a1, 8191098; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1099; RV32-NEXT: vand.vv v24, v16, v24, v0.t1100; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1101; RV32-NEXT: vmv.v.x v16, a11102; RV32-NEXT: lui a1, 616811103; RV32-NEXT: addi a1, a1, -2411104; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1105; RV32-NEXT: vsub.vv v8, v8, v24, v0.t1106; RV32-NEXT: vand.vv v24, v8, v16, v0.t1107; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t1108; RV32-NEXT: vand.vv v16, v8, v16, v0.t1109; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1110; RV32-NEXT: vmv.v.x v8, a11111; RV32-NEXT: lui a1, 41121112; RV32-NEXT: addi a1, a1, 2571113; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1114; RV32-NEXT: vadd.vv v16, v24, v16, v0.t1115; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t1116; RV32-NEXT: vadd.vv v16, v16, v24, v0.t1117; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1118; RV32-NEXT: vmv.v.x v24, a11119; RV32-NEXT: li a1, 561120; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1121; RV32-NEXT: vand.vv v8, v16, v8, v0.t1122; RV32-NEXT: vmul.vv v8, v8, v24, v0.t1123; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1124; RV32-NEXT: ret1125;1126; RV64-LABEL: vp_ctpop_v15i64:1127; RV64: # %bb.0:1128; RV64-NEXT: lui a1, 3495251129; RV64-NEXT: lui a2, 2097151130; RV64-NEXT: lui a3, 616811131; RV64-NEXT: lui a4, 41121132; RV64-NEXT: addi a1, a1, 13651133; RV64-NEXT: addi a2, a2, 8191134; RV64-NEXT: addi a3, a3, -2411135; RV64-NEXT: addi a4, a4, 2571136; RV64-NEXT: slli a5, a1, 321137; RV64-NEXT: add a1, a1, a51138; RV64-NEXT: slli a5, a2, 321139; RV64-NEXT: add a2, a2, a51140; RV64-NEXT: slli a5, a3, 321141; RV64-NEXT: add a3, a3, a51142; RV64-NEXT: slli a5, a4, 321143; RV64-NEXT: add a4, a4, a51144; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1145; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t1146; RV64-NEXT: vand.vx v16, v16, a1, v0.t1147; RV64-NEXT: vsub.vv v8, v8, v16, v0.t1148; RV64-NEXT: vand.vx v16, v8, a2, v0.t1149; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1150; RV64-NEXT: vand.vx v8, v8, a2, v0.t1151; RV64-NEXT: vadd.vv v8, v16, v8, v0.t1152; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t1153; RV64-NEXT: vadd.vv v8, v8, v16, v0.t1154; RV64-NEXT: vand.vx v8, v8, a3, v0.t1155; RV64-NEXT: li a0, 561156; RV64-NEXT: vmul.vx v8, v8, a4, v0.t1157; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1158; RV64-NEXT: ret1159 %v = call <15 x i64> @llvm.vp.ctpop.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl)1160 ret <15 x i64> %v1161}1162 1163define <15 x i64> @vp_ctpop_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {1164; RV32-LABEL: vp_ctpop_v15i64_unmasked:1165; RV32: # %bb.0:1166; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1167; RV32-NEXT: vsrl.vi v16, v8, 11168; RV32-NEXT: lui a1, 3495251169; RV32-NEXT: addi a1, a1, 13651170; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1171; RV32-NEXT: vmv.v.x v24, a11172; RV32-NEXT: lui a1, 2097151173; RV32-NEXT: addi a1, a1, 8191174; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1175; RV32-NEXT: vand.vv v24, v16, v241176; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1177; RV32-NEXT: vmv.v.x v16, a11178; RV32-NEXT: lui a1, 616811179; RV32-NEXT: addi a1, a1, -2411180; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1181; RV32-NEXT: vsub.vv v8, v8, v241182; RV32-NEXT: vand.vv v24, v8, v161183; RV32-NEXT: vsrl.vi v8, v8, 21184; RV32-NEXT: vand.vv v8, v8, v161185; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1186; RV32-NEXT: vmv.v.x v16, a11187; RV32-NEXT: lui a1, 41121188; RV32-NEXT: addi a1, a1, 2571189; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1190; RV32-NEXT: vadd.vv v8, v24, v81191; RV32-NEXT: vsrl.vi v24, v8, 41192; RV32-NEXT: vadd.vv v8, v8, v241193; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1194; RV32-NEXT: vmv.v.x v24, a11195; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1196; RV32-NEXT: vand.vv v8, v8, v161197; RV32-NEXT: vmul.vv v8, v8, v241198; RV32-NEXT: li a0, 561199; RV32-NEXT: vsrl.vx v8, v8, a01200; RV32-NEXT: ret1201;1202; RV64-LABEL: vp_ctpop_v15i64_unmasked:1203; RV64: # %bb.0:1204; RV64-NEXT: lui a1, 3495251205; RV64-NEXT: lui a2, 2097151206; RV64-NEXT: lui a3, 616811207; RV64-NEXT: lui a4, 41121208; RV64-NEXT: addi a1, a1, 13651209; RV64-NEXT: addi a2, a2, 8191210; RV64-NEXT: addi a3, a3, -2411211; RV64-NEXT: addi a4, a4, 2571212; RV64-NEXT: slli a5, a1, 321213; RV64-NEXT: add a1, a1, a51214; RV64-NEXT: slli a5, a2, 321215; RV64-NEXT: add a2, a2, a51216; RV64-NEXT: slli a5, a3, 321217; RV64-NEXT: add a3, a3, a51218; RV64-NEXT: slli a5, a4, 321219; RV64-NEXT: add a4, a4, a51220; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1221; RV64-NEXT: vsrl.vi v16, v8, 11222; RV64-NEXT: vand.vx v16, v16, a11223; RV64-NEXT: vsub.vv v8, v8, v161224; RV64-NEXT: vand.vx v16, v8, a21225; RV64-NEXT: vsrl.vi v8, v8, 21226; RV64-NEXT: vand.vx v8, v8, a21227; RV64-NEXT: vadd.vv v8, v16, v81228; RV64-NEXT: vsrl.vi v16, v8, 41229; RV64-NEXT: vadd.vv v8, v8, v161230; RV64-NEXT: vand.vx v8, v8, a31231; RV64-NEXT: vmul.vx v8, v8, a41232; RV64-NEXT: li a0, 561233; RV64-NEXT: vsrl.vx v8, v8, a01234; RV64-NEXT: ret1235 %v = call <15 x i64> @llvm.vp.ctpop.v15i64(<15 x i64> %va, <15 x i1> splat (i1 true), i32 %evl)1236 ret <15 x i64> %v1237}1238 1239define <16 x i64> @vp_ctpop_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {1240; RV32-LABEL: vp_ctpop_v16i64:1241; RV32: # %bb.0:1242; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1243; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t1244; RV32-NEXT: lui a1, 3495251245; RV32-NEXT: addi a1, a1, 13651246; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1247; RV32-NEXT: vmv.v.x v24, a11248; RV32-NEXT: lui a1, 2097151249; RV32-NEXT: addi a1, a1, 8191250; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1251; RV32-NEXT: vand.vv v24, v16, v24, v0.t1252; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1253; RV32-NEXT: vmv.v.x v16, a11254; RV32-NEXT: lui a1, 616811255; RV32-NEXT: addi a1, a1, -2411256; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1257; RV32-NEXT: vsub.vv v8, v8, v24, v0.t1258; RV32-NEXT: vand.vv v24, v8, v16, v0.t1259; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t1260; RV32-NEXT: vand.vv v16, v8, v16, v0.t1261; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1262; RV32-NEXT: vmv.v.x v8, a11263; RV32-NEXT: lui a1, 41121264; RV32-NEXT: addi a1, a1, 2571265; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1266; RV32-NEXT: vadd.vv v16, v24, v16, v0.t1267; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t1268; RV32-NEXT: vadd.vv v16, v16, v24, v0.t1269; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1270; RV32-NEXT: vmv.v.x v24, a11271; RV32-NEXT: li a1, 561272; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1273; RV32-NEXT: vand.vv v8, v16, v8, v0.t1274; RV32-NEXT: vmul.vv v8, v8, v24, v0.t1275; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1276; RV32-NEXT: ret1277;1278; RV64-LABEL: vp_ctpop_v16i64:1279; RV64: # %bb.0:1280; RV64-NEXT: lui a1, 3495251281; RV64-NEXT: lui a2, 2097151282; RV64-NEXT: lui a3, 616811283; RV64-NEXT: lui a4, 41121284; RV64-NEXT: addi a1, a1, 13651285; RV64-NEXT: addi a2, a2, 8191286; RV64-NEXT: addi a3, a3, -2411287; RV64-NEXT: addi a4, a4, 2571288; RV64-NEXT: slli a5, a1, 321289; RV64-NEXT: add a1, a1, a51290; RV64-NEXT: slli a5, a2, 321291; RV64-NEXT: add a2, a2, a51292; RV64-NEXT: slli a5, a3, 321293; RV64-NEXT: add a3, a3, a51294; RV64-NEXT: slli a5, a4, 321295; RV64-NEXT: add a4, a4, a51296; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1297; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t1298; RV64-NEXT: vand.vx v16, v16, a1, v0.t1299; RV64-NEXT: vsub.vv v8, v8, v16, v0.t1300; RV64-NEXT: vand.vx v16, v8, a2, v0.t1301; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1302; RV64-NEXT: vand.vx v8, v8, a2, v0.t1303; RV64-NEXT: vadd.vv v8, v16, v8, v0.t1304; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t1305; RV64-NEXT: vadd.vv v8, v8, v16, v0.t1306; RV64-NEXT: vand.vx v8, v8, a3, v0.t1307; RV64-NEXT: li a0, 561308; RV64-NEXT: vmul.vx v8, v8, a4, v0.t1309; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1310; RV64-NEXT: ret1311 %v = call <16 x i64> @llvm.vp.ctpop.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl)1312 ret <16 x i64> %v1313}1314 1315define <16 x i64> @vp_ctpop_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {1316; RV32-LABEL: vp_ctpop_v16i64_unmasked:1317; RV32: # %bb.0:1318; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1319; RV32-NEXT: vsrl.vi v16, v8, 11320; RV32-NEXT: lui a1, 3495251321; RV32-NEXT: addi a1, a1, 13651322; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1323; RV32-NEXT: vmv.v.x v24, a11324; RV32-NEXT: lui a1, 2097151325; RV32-NEXT: addi a1, a1, 8191326; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1327; RV32-NEXT: vand.vv v24, v16, v241328; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1329; RV32-NEXT: vmv.v.x v16, a11330; RV32-NEXT: lui a1, 616811331; RV32-NEXT: addi a1, a1, -2411332; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1333; RV32-NEXT: vsub.vv v8, v8, v241334; RV32-NEXT: vand.vv v24, v8, v161335; RV32-NEXT: vsrl.vi v8, v8, 21336; RV32-NEXT: vand.vv v8, v8, v161337; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1338; RV32-NEXT: vmv.v.x v16, a11339; RV32-NEXT: lui a1, 41121340; RV32-NEXT: addi a1, a1, 2571341; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1342; RV32-NEXT: vadd.vv v8, v24, v81343; RV32-NEXT: vsrl.vi v24, v8, 41344; RV32-NEXT: vadd.vv v8, v8, v241345; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1346; RV32-NEXT: vmv.v.x v24, a11347; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1348; RV32-NEXT: vand.vv v8, v8, v161349; RV32-NEXT: vmul.vv v8, v8, v241350; RV32-NEXT: li a0, 561351; RV32-NEXT: vsrl.vx v8, v8, a01352; RV32-NEXT: ret1353;1354; RV64-LABEL: vp_ctpop_v16i64_unmasked:1355; RV64: # %bb.0:1356; RV64-NEXT: lui a1, 3495251357; RV64-NEXT: lui a2, 2097151358; RV64-NEXT: lui a3, 616811359; RV64-NEXT: lui a4, 41121360; RV64-NEXT: addi a1, a1, 13651361; RV64-NEXT: addi a2, a2, 8191362; RV64-NEXT: addi a3, a3, -2411363; RV64-NEXT: addi a4, a4, 2571364; RV64-NEXT: slli a5, a1, 321365; RV64-NEXT: add a1, a1, a51366; RV64-NEXT: slli a5, a2, 321367; RV64-NEXT: add a2, a2, a51368; RV64-NEXT: slli a5, a3, 321369; RV64-NEXT: add a3, a3, a51370; RV64-NEXT: slli a5, a4, 321371; RV64-NEXT: add a4, a4, a51372; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1373; RV64-NEXT: vsrl.vi v16, v8, 11374; RV64-NEXT: vand.vx v16, v16, a11375; RV64-NEXT: vsub.vv v8, v8, v161376; RV64-NEXT: vand.vx v16, v8, a21377; RV64-NEXT: vsrl.vi v8, v8, 21378; RV64-NEXT: vand.vx v8, v8, a21379; RV64-NEXT: vadd.vv v8, v16, v81380; RV64-NEXT: vsrl.vi v16, v8, 41381; RV64-NEXT: vadd.vv v8, v8, v161382; RV64-NEXT: vand.vx v8, v8, a31383; RV64-NEXT: vmul.vx v8, v8, a41384; RV64-NEXT: li a0, 561385; RV64-NEXT: vsrl.vx v8, v8, a01386; RV64-NEXT: ret1387 %v = call <16 x i64> @llvm.vp.ctpop.v16i64(<16 x i64> %va, <16 x i1> splat (i1 true), i32 %evl)1388 ret <16 x i64> %v1389}1390 1391define <32 x i64> @vp_ctpop_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {1392; RV32-LABEL: vp_ctpop_v32i64:1393; RV32: # %bb.0:1394; RV32-NEXT: addi sp, sp, -161395; RV32-NEXT: .cfi_def_cfa_offset 161396; RV32-NEXT: csrr a1, vlenb1397; RV32-NEXT: li a2, 481398; RV32-NEXT: mul a1, a1, a21399; RV32-NEXT: sub sp, sp, a11400; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb1401; RV32-NEXT: csrr a1, vlenb1402; RV32-NEXT: li a2, 401403; RV32-NEXT: mul a1, a1, a21404; RV32-NEXT: add a1, sp, a11405; RV32-NEXT: addi a1, a1, 161406; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1407; RV32-NEXT: li a2, 161408; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1409; RV32-NEXT: vslidedown.vi v7, v0, 21410; RV32-NEXT: mv a1, a01411; RV32-NEXT: bltu a0, a2, .LBB34_21412; RV32-NEXT: # %bb.1:1413; RV32-NEXT: li a1, 161414; RV32-NEXT: .LBB34_2:1415; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1416; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t1417; RV32-NEXT: lui a2, 3495251418; RV32-NEXT: addi a2, a2, 13651419; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1420; RV32-NEXT: vmv.v.x v24, a21421; RV32-NEXT: csrr a2, vlenb1422; RV32-NEXT: slli a2, a2, 51423; RV32-NEXT: add a2, sp, a21424; RV32-NEXT: addi a2, a2, 161425; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill1426; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1427; RV32-NEXT: vand.vv v16, v16, v24, v0.t1428; RV32-NEXT: vsub.vv v8, v8, v16, v0.t1429; RV32-NEXT: lui a2, 2097151430; RV32-NEXT: addi a2, a2, 8191431; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1432; RV32-NEXT: vmv.v.x v24, a21433; RV32-NEXT: addi a2, sp, 161434; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill1435; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1436; RV32-NEXT: vand.vv v16, v8, v24, v0.t1437; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t1438; RV32-NEXT: vand.vv v8, v8, v24, v0.t1439; RV32-NEXT: vadd.vv v8, v16, v8, v0.t1440; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t1441; RV32-NEXT: vadd.vv v8, v8, v16, v0.t1442; RV32-NEXT: lui a2, 616811443; RV32-NEXT: addi a2, a2, -2411444; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1445; RV32-NEXT: vmv.v.x v16, a21446; RV32-NEXT: csrr a2, vlenb1447; RV32-NEXT: li a3, 241448; RV32-NEXT: mul a2, a2, a31449; RV32-NEXT: add a2, sp, a21450; RV32-NEXT: addi a2, a2, 161451; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill1452; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1453; RV32-NEXT: vand.vv v8, v8, v16, v0.t1454; RV32-NEXT: lui a2, 41121455; RV32-NEXT: addi a2, a2, 2571456; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1457; RV32-NEXT: vmv.v.x v16, a21458; RV32-NEXT: csrr a2, vlenb1459; RV32-NEXT: slli a2, a2, 31460; RV32-NEXT: add a2, sp, a21461; RV32-NEXT: addi a2, a2, 161462; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill1463; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1464; RV32-NEXT: vmul.vv v8, v8, v16, v0.t1465; RV32-NEXT: li a1, 561466; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1467; RV32-NEXT: csrr a2, vlenb1468; RV32-NEXT: slli a2, a2, 41469; RV32-NEXT: add a2, sp, a21470; RV32-NEXT: addi a2, a2, 161471; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1472; RV32-NEXT: addi a2, a0, -161473; RV32-NEXT: sltu a0, a0, a21474; RV32-NEXT: addi a0, a0, -11475; RV32-NEXT: and a0, a0, a21476; RV32-NEXT: vmv1r.v v0, v71477; RV32-NEXT: csrr a2, vlenb1478; RV32-NEXT: li a3, 401479; RV32-NEXT: mul a2, a2, a31480; RV32-NEXT: add a2, sp, a21481; RV32-NEXT: addi a2, a2, 161482; RV32-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload1483; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1484; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t1485; RV32-NEXT: csrr a0, vlenb1486; RV32-NEXT: slli a0, a0, 51487; RV32-NEXT: add a0, sp, a01488; RV32-NEXT: addi a0, a0, 161489; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1490; RV32-NEXT: vand.vv v8, v24, v8, v0.t1491; RV32-NEXT: vsub.vv v8, v16, v8, v0.t1492; RV32-NEXT: addi a0, sp, 161493; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload1494; RV32-NEXT: vand.vv v16, v8, v24, v0.t1495; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t1496; RV32-NEXT: vand.vv v8, v8, v24, v0.t1497; RV32-NEXT: vadd.vv v8, v16, v8, v0.t1498; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t1499; RV32-NEXT: vadd.vv v8, v8, v16, v0.t1500; RV32-NEXT: csrr a0, vlenb1501; RV32-NEXT: li a2, 241502; RV32-NEXT: mul a0, a0, a21503; RV32-NEXT: add a0, sp, a01504; RV32-NEXT: addi a0, a0, 161505; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1506; RV32-NEXT: vand.vv v8, v8, v16, v0.t1507; RV32-NEXT: csrr a0, vlenb1508; RV32-NEXT: slli a0, a0, 31509; RV32-NEXT: add a0, sp, a01510; RV32-NEXT: addi a0, a0, 161511; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1512; RV32-NEXT: vmul.vv v8, v8, v16, v0.t1513; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t1514; RV32-NEXT: csrr a0, vlenb1515; RV32-NEXT: slli a0, a0, 41516; RV32-NEXT: add a0, sp, a01517; RV32-NEXT: addi a0, a0, 161518; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1519; RV32-NEXT: csrr a0, vlenb1520; RV32-NEXT: li a1, 481521; RV32-NEXT: mul a0, a0, a11522; RV32-NEXT: add sp, sp, a01523; RV32-NEXT: .cfi_def_cfa sp, 161524; RV32-NEXT: addi sp, sp, 161525; RV32-NEXT: .cfi_def_cfa_offset 01526; RV32-NEXT: ret1527;1528; RV64-LABEL: vp_ctpop_v32i64:1529; RV64: # %bb.0:1530; RV64-NEXT: li a2, 161531; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1532; RV64-NEXT: vslidedown.vi v7, v0, 21533; RV64-NEXT: mv a1, a01534; RV64-NEXT: bltu a0, a2, .LBB34_21535; RV64-NEXT: # %bb.1:1536; RV64-NEXT: li a1, 161537; RV64-NEXT: .LBB34_2:1538; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1539; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t1540; RV64-NEXT: lui a1, 3495251541; RV64-NEXT: lui a2, 2097151542; RV64-NEXT: lui a3, 616811543; RV64-NEXT: lui a4, 41121544; RV64-NEXT: addi a1, a1, 13651545; RV64-NEXT: addi a2, a2, 8191546; RV64-NEXT: addi a3, a3, -2411547; RV64-NEXT: addi a4, a4, 2571548; RV64-NEXT: slli a5, a1, 321549; RV64-NEXT: add a1, a1, a51550; RV64-NEXT: slli a5, a2, 321551; RV64-NEXT: add a2, a2, a51552; RV64-NEXT: slli a5, a3, 321553; RV64-NEXT: add a3, a3, a51554; RV64-NEXT: slli a5, a4, 321555; RV64-NEXT: add a4, a4, a51556; RV64-NEXT: addi a5, a0, -161557; RV64-NEXT: sltu a0, a0, a51558; RV64-NEXT: addi a0, a0, -11559; RV64-NEXT: and a0, a0, a51560; RV64-NEXT: li a5, 561561; RV64-NEXT: vand.vx v24, v24, a1, v0.t1562; RV64-NEXT: vsub.vv v8, v8, v24, v0.t1563; RV64-NEXT: vand.vx v24, v8, a2, v0.t1564; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1565; RV64-NEXT: vand.vx v8, v8, a2, v0.t1566; RV64-NEXT: vadd.vv v8, v24, v8, v0.t1567; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t1568; RV64-NEXT: vadd.vv v8, v8, v24, v0.t1569; RV64-NEXT: vand.vx v8, v8, a3, v0.t1570; RV64-NEXT: vmul.vx v8, v8, a4, v0.t1571; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t1572; RV64-NEXT: vmv1r.v v0, v71573; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1574; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t1575; RV64-NEXT: vand.vx v24, v24, a1, v0.t1576; RV64-NEXT: vsub.vv v16, v16, v24, v0.t1577; RV64-NEXT: vand.vx v24, v16, a2, v0.t1578; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t1579; RV64-NEXT: vand.vx v16, v16, a2, v0.t1580; RV64-NEXT: vadd.vv v16, v24, v16, v0.t1581; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t1582; RV64-NEXT: vadd.vv v16, v16, v24, v0.t1583; RV64-NEXT: vand.vx v16, v16, a3, v0.t1584; RV64-NEXT: vmul.vx v16, v16, a4, v0.t1585; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t1586; RV64-NEXT: ret1587 %v = call <32 x i64> @llvm.vp.ctpop.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl)1588 ret <32 x i64> %v1589}1590 1591define <32 x i64> @vp_ctpop_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {1592; RV32-LABEL: vp_ctpop_v32i64_unmasked:1593; RV32: # %bb.0:1594; RV32-NEXT: li a2, 161595; RV32-NEXT: mv a1, a01596; RV32-NEXT: bltu a0, a2, .LBB35_21597; RV32-NEXT: # %bb.1:1598; RV32-NEXT: li a1, 161599; RV32-NEXT: .LBB35_2:1600; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1601; RV32-NEXT: vsrl.vi v24, v8, 11602; RV32-NEXT: lui a2, 3495251603; RV32-NEXT: addi a2, a2, 13651604; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1605; RV32-NEXT: vmv.v.x v0, a21606; RV32-NEXT: addi a2, a0, -161607; RV32-NEXT: sltu a0, a0, a21608; RV32-NEXT: addi a0, a0, -11609; RV32-NEXT: and a0, a0, a21610; RV32-NEXT: lui a2, 2097151611; RV32-NEXT: addi a2, a2, 8191612; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1613; RV32-NEXT: vand.vv v24, v24, v01614; RV32-NEXT: vsub.vv v8, v8, v241615; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1616; RV32-NEXT: vsrl.vi v24, v16, 11617; RV32-NEXT: vand.vv v24, v24, v01618; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1619; RV32-NEXT: vmv.v.x v0, a21620; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1621; RV32-NEXT: vsub.vv v16, v16, v241622; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1623; RV32-NEXT: vand.vv v24, v8, v01624; RV32-NEXT: vsrl.vi v8, v8, 21625; RV32-NEXT: vand.vv v8, v8, v01626; RV32-NEXT: vadd.vv v8, v24, v81627; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1628; RV32-NEXT: vand.vv v24, v16, v01629; RV32-NEXT: vsrl.vi v16, v16, 21630; RV32-NEXT: vand.vv v16, v16, v01631; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1632; RV32-NEXT: vsrl.vi v0, v8, 41633; RV32-NEXT: vadd.vv v8, v8, v01634; RV32-NEXT: lui a2, 616811635; RV32-NEXT: addi a2, a2, -2411636; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1637; RV32-NEXT: vadd.vv v16, v24, v161638; RV32-NEXT: vsrl.vi v24, v16, 41639; RV32-NEXT: vadd.vv v16, v16, v241640; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1641; RV32-NEXT: vmv.v.x v24, a21642; RV32-NEXT: lui a2, 41121643; RV32-NEXT: addi a2, a2, 2571644; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1645; RV32-NEXT: vand.vv v8, v8, v241646; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1647; RV32-NEXT: vand.vv v16, v16, v241648; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1649; RV32-NEXT: vmv.v.x v24, a21650; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1651; RV32-NEXT: vmul.vv v8, v8, v241652; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1653; RV32-NEXT: vmul.vv v16, v16, v241654; RV32-NEXT: li a2, 561655; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1656; RV32-NEXT: vsrl.vx v8, v8, a21657; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1658; RV32-NEXT: vsrl.vx v16, v16, a21659; RV32-NEXT: ret1660;1661; RV64-LABEL: vp_ctpop_v32i64_unmasked:1662; RV64: # %bb.0:1663; RV64-NEXT: li a2, 161664; RV64-NEXT: mv a1, a01665; RV64-NEXT: bltu a0, a2, .LBB35_21666; RV64-NEXT: # %bb.1:1667; RV64-NEXT: li a1, 161668; RV64-NEXT: .LBB35_2:1669; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1670; RV64-NEXT: vsrl.vi v24, v8, 11671; RV64-NEXT: lui a2, 3495251672; RV64-NEXT: lui a3, 2097151673; RV64-NEXT: lui a4, 616811674; RV64-NEXT: lui a5, 41121675; RV64-NEXT: addi a2, a2, 13651676; RV64-NEXT: addi a3, a3, 8191677; RV64-NEXT: addi a4, a4, -2411678; RV64-NEXT: addi a5, a5, 2571679; RV64-NEXT: slli a6, a2, 321680; RV64-NEXT: add a2, a2, a61681; RV64-NEXT: slli a6, a3, 321682; RV64-NEXT: add a3, a3, a61683; RV64-NEXT: slli a6, a4, 321684; RV64-NEXT: add a4, a4, a61685; RV64-NEXT: slli a6, a5, 321686; RV64-NEXT: add a5, a5, a61687; RV64-NEXT: addi a6, a0, -161688; RV64-NEXT: sltu a0, a0, a61689; RV64-NEXT: addi a0, a0, -11690; RV64-NEXT: and a0, a0, a61691; RV64-NEXT: li a6, 561692; RV64-NEXT: vand.vx v24, v24, a21693; RV64-NEXT: vsub.vv v8, v8, v241694; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1695; RV64-NEXT: vsrl.vi v24, v16, 11696; RV64-NEXT: vand.vx v24, v24, a21697; RV64-NEXT: vsub.vv v16, v16, v241698; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1699; RV64-NEXT: vand.vx v24, v8, a31700; RV64-NEXT: vsrl.vi v8, v8, 21701; RV64-NEXT: vand.vx v8, v8, a31702; RV64-NEXT: vadd.vv v8, v24, v81703; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1704; RV64-NEXT: vand.vx v24, v16, a31705; RV64-NEXT: vsrl.vi v16, v16, 21706; RV64-NEXT: vand.vx v16, v16, a31707; RV64-NEXT: vadd.vv v16, v24, v161708; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1709; RV64-NEXT: vsrl.vi v24, v8, 41710; RV64-NEXT: vadd.vv v8, v8, v241711; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1712; RV64-NEXT: vsrl.vi v24, v16, 41713; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1714; RV64-NEXT: vand.vx v8, v8, a41715; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1716; RV64-NEXT: vadd.vv v16, v16, v241717; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1718; RV64-NEXT: vmul.vx v8, v8, a51719; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1720; RV64-NEXT: vand.vx v16, v16, a41721; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1722; RV64-NEXT: vsrl.vx v8, v8, a61723; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1724; RV64-NEXT: vmul.vx v16, v16, a51725; RV64-NEXT: vsrl.vx v16, v16, a61726; RV64-NEXT: ret1727 %v = call <32 x i64> @llvm.vp.ctpop.v32i64(<32 x i64> %va, <32 x i1> splat (i1 true), i32 %evl)1728 ret <32 x i64> %v1729}1730