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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB6 7define void @ctpop_v16i8(ptr %x, ptr %y) {8; CHECK-LABEL: ctpop_v16i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma11; CHECK-NEXT: vle8.v v8, (a0)12; CHECK-NEXT: li a1, 8513; CHECK-NEXT: vsrl.vi v9, v8, 114; CHECK-NEXT: vand.vx v9, v9, a115; CHECK-NEXT: li a1, 5116; CHECK-NEXT: vsub.vv v8, v8, v917; CHECK-NEXT: vand.vx v9, v8, a118; CHECK-NEXT: vsrl.vi v8, v8, 219; CHECK-NEXT: vand.vx v8, v8, a120; CHECK-NEXT: vadd.vv v8, v9, v821; CHECK-NEXT: vsrl.vi v9, v8, 422; CHECK-NEXT: vadd.vv v8, v8, v923; CHECK-NEXT: vand.vi v8, v8, 1524; CHECK-NEXT: vse8.v v8, (a0)25; CHECK-NEXT: ret26;27; ZVBB-LABEL: ctpop_v16i8:28; ZVBB: # %bb.0:29; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma30; ZVBB-NEXT: vle8.v v8, (a0)31; ZVBB-NEXT: vcpop.v v8, v832; ZVBB-NEXT: vse8.v v8, (a0)33; ZVBB-NEXT: ret34 %a = load <16 x i8>, ptr %x35 %b = load <16 x i8>, ptr %y36 %c = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %a)37 store <16 x i8> %c, ptr %x38 ret void39}40 41define void @ctpop_v8i16(ptr %x, ptr %y) {42; CHECK-LABEL: ctpop_v8i16:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma45; CHECK-NEXT: vle16.v v8, (a0)46; CHECK-NEXT: lui a1, 547; CHECK-NEXT: addi a1, a1, 136548; CHECK-NEXT: vsrl.vi v9, v8, 149; CHECK-NEXT: vand.vx v9, v9, a150; CHECK-NEXT: lui a1, 351; CHECK-NEXT: addi a1, a1, 81952; CHECK-NEXT: vsub.vv v8, v8, v953; CHECK-NEXT: vand.vx v9, v8, a154; CHECK-NEXT: vsrl.vi v8, v8, 255; CHECK-NEXT: vand.vx v8, v8, a156; CHECK-NEXT: lui a1, 157; CHECK-NEXT: addi a1, a1, -24158; CHECK-NEXT: vadd.vv v8, v9, v859; CHECK-NEXT: vsrl.vi v9, v8, 460; CHECK-NEXT: vadd.vv v8, v8, v961; CHECK-NEXT: vand.vx v8, v8, a162; CHECK-NEXT: li a1, 25763; CHECK-NEXT: vmul.vx v8, v8, a164; CHECK-NEXT: vsrl.vi v8, v8, 865; CHECK-NEXT: vse16.v v8, (a0)66; CHECK-NEXT: ret67;68; ZVBB-LABEL: ctpop_v8i16:69; ZVBB: # %bb.0:70; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma71; ZVBB-NEXT: vle16.v v8, (a0)72; ZVBB-NEXT: vcpop.v v8, v873; ZVBB-NEXT: vse16.v v8, (a0)74; ZVBB-NEXT: ret75 %a = load <8 x i16>, ptr %x76 %b = load <8 x i16>, ptr %y77 %c = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %a)78 store <8 x i16> %c, ptr %x79 ret void80}81 82define void @ctpop_v4i32(ptr %x, ptr %y) {83; CHECK-LABEL: ctpop_v4i32:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma86; CHECK-NEXT: vle32.v v8, (a0)87; CHECK-NEXT: lui a1, 34952588; CHECK-NEXT: addi a1, a1, 136589; CHECK-NEXT: vsrl.vi v9, v8, 190; CHECK-NEXT: vand.vx v9, v9, a191; CHECK-NEXT: lui a1, 20971592; CHECK-NEXT: addi a1, a1, 81993; CHECK-NEXT: vsub.vv v8, v8, v994; CHECK-NEXT: vand.vx v9, v8, a195; CHECK-NEXT: vsrl.vi v8, v8, 296; CHECK-NEXT: vand.vx v8, v8, a197; CHECK-NEXT: lui a1, 6168198; CHECK-NEXT: addi a1, a1, -24199; CHECK-NEXT: vadd.vv v8, v9, v8100; CHECK-NEXT: vsrl.vi v9, v8, 4101; CHECK-NEXT: vadd.vv v8, v8, v9102; CHECK-NEXT: vand.vx v8, v8, a1103; CHECK-NEXT: lui a1, 4112104; CHECK-NEXT: addi a1, a1, 257105; CHECK-NEXT: vmul.vx v8, v8, a1106; CHECK-NEXT: vsrl.vi v8, v8, 24107; CHECK-NEXT: vse32.v v8, (a0)108; CHECK-NEXT: ret109;110; ZVBB-LABEL: ctpop_v4i32:111; ZVBB: # %bb.0:112; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma113; ZVBB-NEXT: vle32.v v8, (a0)114; ZVBB-NEXT: vcpop.v v8, v8115; ZVBB-NEXT: vse32.v v8, (a0)116; ZVBB-NEXT: ret117 %a = load <4 x i32>, ptr %x118 %b = load <4 x i32>, ptr %y119 %c = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %a)120 store <4 x i32> %c, ptr %x121 ret void122}123 124define void @ctpop_v2i64(ptr %x, ptr %y) {125; RV32-LABEL: ctpop_v2i64:126; RV32: # %bb.0:127; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma128; RV32-NEXT: vle64.v v8, (a0)129; RV32-NEXT: lui a1, 349525130; RV32-NEXT: addi a1, a1, 1365131; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma132; RV32-NEXT: vmv.v.x v9, a1133; RV32-NEXT: lui a1, 209715134; RV32-NEXT: addi a1, a1, 819135; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma136; RV32-NEXT: vsrl.vi v10, v8, 1137; RV32-NEXT: vand.vv v9, v10, v9138; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma139; RV32-NEXT: vmv.v.x v10, a1140; RV32-NEXT: lui a1, 61681141; RV32-NEXT: addi a1, a1, -241142; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma143; RV32-NEXT: vsub.vv v8, v8, v9144; RV32-NEXT: vand.vv v9, v8, v10145; RV32-NEXT: vsrl.vi v8, v8, 2146; RV32-NEXT: vand.vv v8, v8, v10147; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma148; RV32-NEXT: vmv.v.x v10, a1149; RV32-NEXT: lui a1, 4112150; RV32-NEXT: addi a1, a1, 257151; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma152; RV32-NEXT: vadd.vv v8, v9, v8153; RV32-NEXT: vsrl.vi v9, v8, 4154; RV32-NEXT: vadd.vv v8, v8, v9155; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma156; RV32-NEXT: vmv.v.x v9, a1157; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma158; RV32-NEXT: vand.vv v8, v8, v10159; RV32-NEXT: vmul.vv v8, v8, v9160; RV32-NEXT: li a1, 56161; RV32-NEXT: vsrl.vx v8, v8, a1162; RV32-NEXT: vse64.v v8, (a0)163; RV32-NEXT: ret164;165; RV64-LABEL: ctpop_v2i64:166; RV64: # %bb.0:167; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma168; RV64-NEXT: vle64.v v8, (a0)169; RV64-NEXT: lui a1, 349525170; RV64-NEXT: lui a2, 209715171; RV64-NEXT: lui a3, 61681172; RV64-NEXT: lui a4, 4112173; RV64-NEXT: addi a1, a1, 1365174; RV64-NEXT: addi a2, a2, 819175; RV64-NEXT: addi a3, a3, -241176; RV64-NEXT: addi a4, a4, 257177; RV64-NEXT: slli a5, a1, 32178; RV64-NEXT: add a1, a1, a5179; RV64-NEXT: slli a5, a2, 32180; RV64-NEXT: add a2, a2, a5181; RV64-NEXT: slli a5, a3, 32182; RV64-NEXT: add a3, a3, a5183; RV64-NEXT: slli a5, a4, 32184; RV64-NEXT: add a4, a4, a5185; RV64-NEXT: vsrl.vi v9, v8, 1186; RV64-NEXT: vand.vx v9, v9, a1187; RV64-NEXT: vsub.vv v8, v8, v9188; RV64-NEXT: vand.vx v9, v8, a2189; RV64-NEXT: vsrl.vi v8, v8, 2190; RV64-NEXT: vand.vx v8, v8, a2191; RV64-NEXT: vadd.vv v8, v9, v8192; RV64-NEXT: vsrl.vi v9, v8, 4193; RV64-NEXT: vadd.vv v8, v8, v9194; RV64-NEXT: vand.vx v8, v8, a3195; RV64-NEXT: vmul.vx v8, v8, a4196; RV64-NEXT: li a1, 56197; RV64-NEXT: vsrl.vx v8, v8, a1198; RV64-NEXT: vse64.v v8, (a0)199; RV64-NEXT: ret200;201; ZVBB-LABEL: ctpop_v2i64:202; ZVBB: # %bb.0:203; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma204; ZVBB-NEXT: vle64.v v8, (a0)205; ZVBB-NEXT: vcpop.v v8, v8206; ZVBB-NEXT: vse64.v v8, (a0)207; ZVBB-NEXT: ret208 %a = load <2 x i64>, ptr %x209 %b = load <2 x i64>, ptr %y210 %c = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)211 store <2 x i64> %c, ptr %x212 ret void213}214 215define void @ctpop_v32i8(ptr %x, ptr %y) {216; CHECK-LABEL: ctpop_v32i8:217; CHECK: # %bb.0:218; CHECK-NEXT: li a1, 32219; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma220; CHECK-NEXT: vle8.v v8, (a0)221; CHECK-NEXT: li a1, 85222; CHECK-NEXT: vsrl.vi v10, v8, 1223; CHECK-NEXT: vand.vx v10, v10, a1224; CHECK-NEXT: li a1, 51225; CHECK-NEXT: vsub.vv v8, v8, v10226; CHECK-NEXT: vand.vx v10, v8, a1227; CHECK-NEXT: vsrl.vi v8, v8, 2228; CHECK-NEXT: vand.vx v8, v8, a1229; CHECK-NEXT: vadd.vv v8, v10, v8230; CHECK-NEXT: vsrl.vi v10, v8, 4231; CHECK-NEXT: vadd.vv v8, v8, v10232; CHECK-NEXT: vand.vi v8, v8, 15233; CHECK-NEXT: vse8.v v8, (a0)234; CHECK-NEXT: ret235;236; ZVBB-LABEL: ctpop_v32i8:237; ZVBB: # %bb.0:238; ZVBB-NEXT: li a1, 32239; ZVBB-NEXT: vsetvli zero, a1, e8, m2, ta, ma240; ZVBB-NEXT: vle8.v v8, (a0)241; ZVBB-NEXT: vcpop.v v8, v8242; ZVBB-NEXT: vse8.v v8, (a0)243; ZVBB-NEXT: ret244 %a = load <32 x i8>, ptr %x245 %b = load <32 x i8>, ptr %y246 %c = call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %a)247 store <32 x i8> %c, ptr %x248 ret void249}250 251define void @ctpop_v16i16(ptr %x, ptr %y) {252; CHECK-LABEL: ctpop_v16i16:253; CHECK: # %bb.0:254; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma255; CHECK-NEXT: vle16.v v8, (a0)256; CHECK-NEXT: lui a1, 5257; CHECK-NEXT: addi a1, a1, 1365258; CHECK-NEXT: vsrl.vi v10, v8, 1259; CHECK-NEXT: vand.vx v10, v10, a1260; CHECK-NEXT: lui a1, 3261; CHECK-NEXT: addi a1, a1, 819262; CHECK-NEXT: vsub.vv v8, v8, v10263; CHECK-NEXT: vand.vx v10, v8, a1264; CHECK-NEXT: vsrl.vi v8, v8, 2265; CHECK-NEXT: vand.vx v8, v8, a1266; CHECK-NEXT: lui a1, 1267; CHECK-NEXT: addi a1, a1, -241268; CHECK-NEXT: vadd.vv v8, v10, v8269; CHECK-NEXT: vsrl.vi v10, v8, 4270; CHECK-NEXT: vadd.vv v8, v8, v10271; CHECK-NEXT: vand.vx v8, v8, a1272; CHECK-NEXT: li a1, 257273; CHECK-NEXT: vmul.vx v8, v8, a1274; CHECK-NEXT: vsrl.vi v8, v8, 8275; CHECK-NEXT: vse16.v v8, (a0)276; CHECK-NEXT: ret277;278; ZVBB-LABEL: ctpop_v16i16:279; ZVBB: # %bb.0:280; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma281; ZVBB-NEXT: vle16.v v8, (a0)282; ZVBB-NEXT: vcpop.v v8, v8283; ZVBB-NEXT: vse16.v v8, (a0)284; ZVBB-NEXT: ret285 %a = load <16 x i16>, ptr %x286 %b = load <16 x i16>, ptr %y287 %c = call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %a)288 store <16 x i16> %c, ptr %x289 ret void290}291 292define void @ctpop_v8i32(ptr %x, ptr %y) {293; CHECK-LABEL: ctpop_v8i32:294; CHECK: # %bb.0:295; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma296; CHECK-NEXT: vle32.v v8, (a0)297; CHECK-NEXT: lui a1, 349525298; CHECK-NEXT: addi a1, a1, 1365299; CHECK-NEXT: vsrl.vi v10, v8, 1300; CHECK-NEXT: vand.vx v10, v10, a1301; CHECK-NEXT: lui a1, 209715302; CHECK-NEXT: addi a1, a1, 819303; CHECK-NEXT: vsub.vv v8, v8, v10304; CHECK-NEXT: vand.vx v10, v8, a1305; CHECK-NEXT: vsrl.vi v8, v8, 2306; CHECK-NEXT: vand.vx v8, v8, a1307; CHECK-NEXT: lui a1, 61681308; CHECK-NEXT: addi a1, a1, -241309; CHECK-NEXT: vadd.vv v8, v10, v8310; CHECK-NEXT: vsrl.vi v10, v8, 4311; CHECK-NEXT: vadd.vv v8, v8, v10312; CHECK-NEXT: vand.vx v8, v8, a1313; CHECK-NEXT: lui a1, 4112314; CHECK-NEXT: addi a1, a1, 257315; CHECK-NEXT: vmul.vx v8, v8, a1316; CHECK-NEXT: vsrl.vi v8, v8, 24317; CHECK-NEXT: vse32.v v8, (a0)318; CHECK-NEXT: ret319;320; ZVBB-LABEL: ctpop_v8i32:321; ZVBB: # %bb.0:322; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma323; ZVBB-NEXT: vle32.v v8, (a0)324; ZVBB-NEXT: vcpop.v v8, v8325; ZVBB-NEXT: vse32.v v8, (a0)326; ZVBB-NEXT: ret327 %a = load <8 x i32>, ptr %x328 %b = load <8 x i32>, ptr %y329 %c = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %a)330 store <8 x i32> %c, ptr %x331 ret void332}333define <8 x i1> @ctpop_v8i32_ult_two(ptr %x, ptr %y) {334; CHECK-LABEL: ctpop_v8i32_ult_two:335; CHECK: # %bb.0:336; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma337; CHECK-NEXT: vle32.v v8, (a0)338; CHECK-NEXT: vadd.vi v10, v8, -1339; CHECK-NEXT: vand.vv v8, v8, v10340; CHECK-NEXT: vmseq.vi v0, v8, 0341; CHECK-NEXT: ret342;343; ZVBB-LABEL: ctpop_v8i32_ult_two:344; ZVBB: # %bb.0:345; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma346; ZVBB-NEXT: vle32.v v8, (a0)347; ZVBB-NEXT: vcpop.v v8, v8348; ZVBB-NEXT: vmsleu.vi v0, v8, 1349; ZVBB-NEXT: ret350 %a = load <8 x i32>, ptr %x351 %b = load <8 x i32>, ptr %y352 %c = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %a)353 %cmp = icmp ult <8 x i32> %c, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>354 ret <8 x i1> %cmp355}356define <8 x i1> @ctpop_v8i32_ugt_one(ptr %x, ptr %y) {357; CHECK-LABEL: ctpop_v8i32_ugt_one:358; CHECK: # %bb.0:359; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma360; CHECK-NEXT: vle32.v v8, (a0)361; CHECK-NEXT: vadd.vi v10, v8, -1362; CHECK-NEXT: vand.vv v8, v8, v10363; CHECK-NEXT: vmsne.vi v0, v8, 0364; CHECK-NEXT: ret365;366; ZVBB-LABEL: ctpop_v8i32_ugt_one:367; ZVBB: # %bb.0:368; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma369; ZVBB-NEXT: vle32.v v8, (a0)370; ZVBB-NEXT: vcpop.v v8, v8371; ZVBB-NEXT: vmsgtu.vi v0, v8, 1372; ZVBB-NEXT: ret373 %a = load <8 x i32>, ptr %x374 %b = load <8 x i32>, ptr %y375 %c = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %a)376 %cmp = icmp ugt <8 x i32> %c, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>377 ret <8 x i1> %cmp378}379define <8 x i1> @ctpop_v8i32_eq_one(ptr %x, ptr %y) {380; CHECK-LABEL: ctpop_v8i32_eq_one:381; CHECK: # %bb.0:382; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma383; CHECK-NEXT: vle32.v v8, (a0)384; CHECK-NEXT: vadd.vi v10, v8, -1385; CHECK-NEXT: vxor.vv v8, v8, v10386; CHECK-NEXT: vmsltu.vv v0, v10, v8387; CHECK-NEXT: ret388;389; ZVBB-LABEL: ctpop_v8i32_eq_one:390; ZVBB: # %bb.0:391; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma392; ZVBB-NEXT: vle32.v v8, (a0)393; ZVBB-NEXT: vcpop.v v8, v8394; ZVBB-NEXT: vmseq.vi v0, v8, 1395; ZVBB-NEXT: ret396 %a = load <8 x i32>, ptr %x397 %b = load <8 x i32>, ptr %y398 %c = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %a)399 %cmp = icmp eq <8 x i32> %c, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>400 ret <8 x i1> %cmp401}402define <8 x i1> @ctpop_v8i32_ne_one(ptr %x, ptr %y) {403; CHECK-LABEL: ctpop_v8i32_ne_one:404; CHECK: # %bb.0:405; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma406; CHECK-NEXT: vle32.v v8, (a0)407; CHECK-NEXT: vadd.vi v10, v8, -1408; CHECK-NEXT: vxor.vv v8, v8, v10409; CHECK-NEXT: vmsleu.vv v0, v8, v10410; CHECK-NEXT: ret411;412; ZVBB-LABEL: ctpop_v8i32_ne_one:413; ZVBB: # %bb.0:414; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma415; ZVBB-NEXT: vle32.v v8, (a0)416; ZVBB-NEXT: vcpop.v v8, v8417; ZVBB-NEXT: vmsne.vi v0, v8, 1418; ZVBB-NEXT: ret419 %a = load <8 x i32>, ptr %x420 %b = load <8 x i32>, ptr %y421 %c = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %a)422 %cmp = icmp ne <8 x i32> %c, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>423 ret <8 x i1> %cmp424}425 426define void @ctpop_v4i64(ptr %x, ptr %y) {427; RV32-LABEL: ctpop_v4i64:428; RV32: # %bb.0:429; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma430; RV32-NEXT: vle64.v v8, (a0)431; RV32-NEXT: lui a1, 349525432; RV32-NEXT: addi a1, a1, 1365433; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma434; RV32-NEXT: vmv.v.x v10, a1435; RV32-NEXT: lui a1, 209715436; RV32-NEXT: addi a1, a1, 819437; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma438; RV32-NEXT: vsrl.vi v12, v8, 1439; RV32-NEXT: vand.vv v10, v12, v10440; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma441; RV32-NEXT: vmv.v.x v12, a1442; RV32-NEXT: lui a1, 61681443; RV32-NEXT: addi a1, a1, -241444; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma445; RV32-NEXT: vsub.vv v8, v8, v10446; RV32-NEXT: vand.vv v10, v8, v12447; RV32-NEXT: vsrl.vi v8, v8, 2448; RV32-NEXT: vand.vv v8, v8, v12449; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma450; RV32-NEXT: vmv.v.x v12, a1451; RV32-NEXT: lui a1, 4112452; RV32-NEXT: addi a1, a1, 257453; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma454; RV32-NEXT: vadd.vv v8, v10, v8455; RV32-NEXT: vsrl.vi v10, v8, 4456; RV32-NEXT: vadd.vv v8, v8, v10457; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma458; RV32-NEXT: vmv.v.x v10, a1459; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma460; RV32-NEXT: vand.vv v8, v8, v12461; RV32-NEXT: vmul.vv v8, v8, v10462; RV32-NEXT: li a1, 56463; RV32-NEXT: vsrl.vx v8, v8, a1464; RV32-NEXT: vse64.v v8, (a0)465; RV32-NEXT: ret466;467; RV64-LABEL: ctpop_v4i64:468; RV64: # %bb.0:469; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma470; RV64-NEXT: vle64.v v8, (a0)471; RV64-NEXT: lui a1, 349525472; RV64-NEXT: lui a2, 209715473; RV64-NEXT: lui a3, 61681474; RV64-NEXT: lui a4, 4112475; RV64-NEXT: addi a1, a1, 1365476; RV64-NEXT: addi a2, a2, 819477; RV64-NEXT: addi a3, a3, -241478; RV64-NEXT: addi a4, a4, 257479; RV64-NEXT: slli a5, a1, 32480; RV64-NEXT: add a1, a1, a5481; RV64-NEXT: slli a5, a2, 32482; RV64-NEXT: add a2, a2, a5483; RV64-NEXT: slli a5, a3, 32484; RV64-NEXT: add a3, a3, a5485; RV64-NEXT: slli a5, a4, 32486; RV64-NEXT: add a4, a4, a5487; RV64-NEXT: vsrl.vi v10, v8, 1488; RV64-NEXT: vand.vx v10, v10, a1489; RV64-NEXT: vsub.vv v8, v8, v10490; RV64-NEXT: vand.vx v10, v8, a2491; RV64-NEXT: vsrl.vi v8, v8, 2492; RV64-NEXT: vand.vx v8, v8, a2493; RV64-NEXT: vadd.vv v8, v10, v8494; RV64-NEXT: vsrl.vi v10, v8, 4495; RV64-NEXT: vadd.vv v8, v8, v10496; RV64-NEXT: vand.vx v8, v8, a3497; RV64-NEXT: vmul.vx v8, v8, a4498; RV64-NEXT: li a1, 56499; RV64-NEXT: vsrl.vx v8, v8, a1500; RV64-NEXT: vse64.v v8, (a0)501; RV64-NEXT: ret502;503; ZVBB-LABEL: ctpop_v4i64:504; ZVBB: # %bb.0:505; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma506; ZVBB-NEXT: vle64.v v8, (a0)507; ZVBB-NEXT: vcpop.v v8, v8508; ZVBB-NEXT: vse64.v v8, (a0)509; ZVBB-NEXT: ret510 %a = load <4 x i64>, ptr %x511 %b = load <4 x i64>, ptr %y512 %c = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %a)513 store <4 x i64> %c, ptr %x514 ret void515}516define <4 x i1> @ctpop_v4i64_ult_two(ptr %x, ptr %y) {517; CHECK-LABEL: ctpop_v4i64_ult_two:518; CHECK: # %bb.0:519; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma520; CHECK-NEXT: vle64.v v8, (a0)521; CHECK-NEXT: vadd.vi v10, v8, -1522; CHECK-NEXT: vand.vv v8, v8, v10523; CHECK-NEXT: vmseq.vi v0, v8, 0524; CHECK-NEXT: ret525;526; ZVBB-LABEL: ctpop_v4i64_ult_two:527; ZVBB: # %bb.0:528; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma529; ZVBB-NEXT: vle64.v v8, (a0)530; ZVBB-NEXT: vcpop.v v8, v8531; ZVBB-NEXT: vmsleu.vi v0, v8, 1532; ZVBB-NEXT: ret533 %a = load <4 x i64>, ptr %x534 %b = load <4 x i64>, ptr %y535 %c = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %a)536 %cmp = icmp ult <4 x i64> %c, <i64 2, i64 2, i64 2, i64 2>537 ret <4 x i1> %cmp538}539define <4 x i1> @ctpop_v4i64_ugt_one(ptr %x, ptr %y) {540; CHECK-LABEL: ctpop_v4i64_ugt_one:541; CHECK: # %bb.0:542; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma543; CHECK-NEXT: vle64.v v8, (a0)544; CHECK-NEXT: vadd.vi v10, v8, -1545; CHECK-NEXT: vand.vv v8, v8, v10546; CHECK-NEXT: vmsne.vi v0, v8, 0547; CHECK-NEXT: ret548;549; ZVBB-LABEL: ctpop_v4i64_ugt_one:550; ZVBB: # %bb.0:551; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma552; ZVBB-NEXT: vle64.v v8, (a0)553; ZVBB-NEXT: vcpop.v v8, v8554; ZVBB-NEXT: vmsgtu.vi v0, v8, 1555; ZVBB-NEXT: ret556 %a = load <4 x i64>, ptr %x557 %b = load <4 x i64>, ptr %y558 %c = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %a)559 %cmp = icmp ugt <4 x i64> %c, <i64 1, i64 1, i64 1, i64 1>560 ret <4 x i1> %cmp561}562define <4 x i1> @ctpop_v4i64_eq_one(ptr %x, ptr %y) {563; CHECK-LABEL: ctpop_v4i64_eq_one:564; CHECK: # %bb.0:565; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma566; CHECK-NEXT: vle64.v v8, (a0)567; CHECK-NEXT: vadd.vi v10, v8, -1568; CHECK-NEXT: vxor.vv v8, v8, v10569; CHECK-NEXT: vmsltu.vv v0, v10, v8570; CHECK-NEXT: ret571;572; ZVBB-LABEL: ctpop_v4i64_eq_one:573; ZVBB: # %bb.0:574; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma575; ZVBB-NEXT: vle64.v v8, (a0)576; ZVBB-NEXT: vcpop.v v8, v8577; ZVBB-NEXT: vmseq.vi v0, v8, 1578; ZVBB-NEXT: ret579 %a = load <4 x i64>, ptr %x580 %b = load <4 x i64>, ptr %y581 %c = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %a)582 %cmp = icmp eq <4 x i64> %c, <i64 1, i64 1, i64 1, i64 1>583 ret <4 x i1> %cmp584}585define <4 x i1> @ctpop_v4i64_ne_one(ptr %x, ptr %y) {586; CHECK-LABEL: ctpop_v4i64_ne_one:587; CHECK: # %bb.0:588; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma589; CHECK-NEXT: vle64.v v8, (a0)590; CHECK-NEXT: vadd.vi v10, v8, -1591; CHECK-NEXT: vxor.vv v8, v8, v10592; CHECK-NEXT: vmsleu.vv v0, v8, v10593; CHECK-NEXT: ret594;595; ZVBB-LABEL: ctpop_v4i64_ne_one:596; ZVBB: # %bb.0:597; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma598; ZVBB-NEXT: vle64.v v8, (a0)599; ZVBB-NEXT: vcpop.v v8, v8600; ZVBB-NEXT: vmsne.vi v0, v8, 1601; ZVBB-NEXT: ret602 %a = load <4 x i64>, ptr %x603 %b = load <4 x i64>, ptr %y604 %c = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %a)605 %cmp = icmp ne <4 x i64> %c, <i64 1, i64 1, i64 1, i64 1>606 ret <4 x i1> %cmp607}608