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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV646 7define <2 x i8> @vp_cttz_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vp_cttz_v2i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t12; CHECK-NEXT: li a0, 8513; CHECK-NEXT: vnot.v v8, v8, v0.t14; CHECK-NEXT: vand.vv v8, v8, v9, v0.t15; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t16; CHECK-NEXT: vand.vx v9, v9, a0, v0.t17; CHECK-NEXT: li a0, 5118; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t19; CHECK-NEXT: vand.vx v9, v8, a0, v0.t20; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t21; CHECK-NEXT: vand.vx v8, v8, a0, v0.t22; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t23; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t24; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t25; CHECK-NEXT: vand.vi v8, v8, 15, v0.t26; CHECK-NEXT: ret27 %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl)28 ret <2 x i8> %v29}30 31define <2 x i8> @vp_cttz_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {32; CHECK-LABEL: vp_cttz_v2i8_unmasked:33; CHECK: # %bb.0:34; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma35; CHECK-NEXT: vadd.vi v9, v8, -136; CHECK-NEXT: vnot.v v8, v837; CHECK-NEXT: li a0, 8538; CHECK-NEXT: vand.vv v8, v8, v939; CHECK-NEXT: vsrl.vi v9, v8, 140; CHECK-NEXT: vand.vx v9, v9, a041; CHECK-NEXT: li a0, 5142; CHECK-NEXT: vsub.vv v8, v8, v943; CHECK-NEXT: vand.vx v9, v8, a044; CHECK-NEXT: vsrl.vi v8, v8, 245; CHECK-NEXT: vand.vx v8, v8, a046; CHECK-NEXT: vadd.vv v8, v9, v847; CHECK-NEXT: vsrl.vi v9, v8, 448; CHECK-NEXT: vadd.vv v8, v8, v949; CHECK-NEXT: vand.vi v8, v8, 1550; CHECK-NEXT: ret51 %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl)52 ret <2 x i8> %v53}54 55define <4 x i8> @vp_cttz_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {56; CHECK-LABEL: vp_cttz_v4i8:57; CHECK: # %bb.0:58; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma59; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t60; CHECK-NEXT: li a0, 8561; CHECK-NEXT: vnot.v v8, v8, v0.t62; CHECK-NEXT: vand.vv v8, v8, v9, v0.t63; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t64; CHECK-NEXT: vand.vx v9, v9, a0, v0.t65; CHECK-NEXT: li a0, 5166; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t67; CHECK-NEXT: vand.vx v9, v8, a0, v0.t68; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t69; CHECK-NEXT: vand.vx v8, v8, a0, v0.t70; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t71; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t72; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t73; CHECK-NEXT: vand.vi v8, v8, 15, v0.t74; CHECK-NEXT: ret75 %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl)76 ret <4 x i8> %v77}78 79define <4 x i8> @vp_cttz_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {80; CHECK-LABEL: vp_cttz_v4i8_unmasked:81; CHECK: # %bb.0:82; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma83; CHECK-NEXT: vadd.vi v9, v8, -184; CHECK-NEXT: vnot.v v8, v885; CHECK-NEXT: li a0, 8586; CHECK-NEXT: vand.vv v8, v8, v987; CHECK-NEXT: vsrl.vi v9, v8, 188; CHECK-NEXT: vand.vx v9, v9, a089; CHECK-NEXT: li a0, 5190; CHECK-NEXT: vsub.vv v8, v8, v991; CHECK-NEXT: vand.vx v9, v8, a092; CHECK-NEXT: vsrl.vi v8, v8, 293; CHECK-NEXT: vand.vx v8, v8, a094; CHECK-NEXT: vadd.vv v8, v9, v895; CHECK-NEXT: vsrl.vi v9, v8, 496; CHECK-NEXT: vadd.vv v8, v8, v997; CHECK-NEXT: vand.vi v8, v8, 1598; CHECK-NEXT: ret99 %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl)100 ret <4 x i8> %v101}102 103define <8 x i8> @vp_cttz_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {104; CHECK-LABEL: vp_cttz_v8i8:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma107; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t108; CHECK-NEXT: li a0, 85109; CHECK-NEXT: vnot.v v8, v8, v0.t110; CHECK-NEXT: vand.vv v8, v8, v9, v0.t111; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t112; CHECK-NEXT: vand.vx v9, v9, a0, v0.t113; CHECK-NEXT: li a0, 51114; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t115; CHECK-NEXT: vand.vx v9, v8, a0, v0.t116; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t117; CHECK-NEXT: vand.vx v8, v8, a0, v0.t118; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t119; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t120; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t121; CHECK-NEXT: vand.vi v8, v8, 15, v0.t122; CHECK-NEXT: ret123 %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl)124 ret <8 x i8> %v125}126 127define <8 x i8> @vp_cttz_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {128; CHECK-LABEL: vp_cttz_v8i8_unmasked:129; CHECK: # %bb.0:130; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma131; CHECK-NEXT: vadd.vi v9, v8, -1132; CHECK-NEXT: vnot.v v8, v8133; CHECK-NEXT: li a0, 85134; CHECK-NEXT: vand.vv v8, v8, v9135; CHECK-NEXT: vsrl.vi v9, v8, 1136; CHECK-NEXT: vand.vx v9, v9, a0137; CHECK-NEXT: li a0, 51138; CHECK-NEXT: vsub.vv v8, v8, v9139; CHECK-NEXT: vand.vx v9, v8, a0140; CHECK-NEXT: vsrl.vi v8, v8, 2141; CHECK-NEXT: vand.vx v8, v8, a0142; CHECK-NEXT: vadd.vv v8, v9, v8143; CHECK-NEXT: vsrl.vi v9, v8, 4144; CHECK-NEXT: vadd.vv v8, v8, v9145; CHECK-NEXT: vand.vi v8, v8, 15146; CHECK-NEXT: ret147 %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl)148 ret <8 x i8> %v149}150 151define <16 x i8> @vp_cttz_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {152; CHECK-LABEL: vp_cttz_v16i8:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma155; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t156; CHECK-NEXT: li a0, 85157; CHECK-NEXT: vnot.v v8, v8, v0.t158; CHECK-NEXT: vand.vv v8, v8, v9, v0.t159; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t160; CHECK-NEXT: vand.vx v9, v9, a0, v0.t161; CHECK-NEXT: li a0, 51162; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t163; CHECK-NEXT: vand.vx v9, v8, a0, v0.t164; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t165; CHECK-NEXT: vand.vx v8, v8, a0, v0.t166; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t167; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t168; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t169; CHECK-NEXT: vand.vi v8, v8, 15, v0.t170; CHECK-NEXT: ret171 %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl)172 ret <16 x i8> %v173}174 175define <16 x i8> @vp_cttz_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {176; CHECK-LABEL: vp_cttz_v16i8_unmasked:177; CHECK: # %bb.0:178; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma179; CHECK-NEXT: vadd.vi v9, v8, -1180; CHECK-NEXT: vnot.v v8, v8181; CHECK-NEXT: li a0, 85182; CHECK-NEXT: vand.vv v8, v8, v9183; CHECK-NEXT: vsrl.vi v9, v8, 1184; CHECK-NEXT: vand.vx v9, v9, a0185; CHECK-NEXT: li a0, 51186; CHECK-NEXT: vsub.vv v8, v8, v9187; CHECK-NEXT: vand.vx v9, v8, a0188; CHECK-NEXT: vsrl.vi v8, v8, 2189; CHECK-NEXT: vand.vx v8, v8, a0190; CHECK-NEXT: vadd.vv v8, v9, v8191; CHECK-NEXT: vsrl.vi v9, v8, 4192; CHECK-NEXT: vadd.vv v8, v8, v9193; CHECK-NEXT: vand.vi v8, v8, 15194; CHECK-NEXT: ret195 %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl)196 ret <16 x i8> %v197}198 199define <2 x i16> @vp_cttz_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {200; CHECK-LABEL: vp_cttz_v2i16:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma203; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t204; CHECK-NEXT: lui a0, 5205; CHECK-NEXT: vnot.v v8, v8, v0.t206; CHECK-NEXT: addi a0, a0, 1365207; CHECK-NEXT: vand.vv v8, v8, v9, v0.t208; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t209; CHECK-NEXT: vand.vx v9, v9, a0, v0.t210; CHECK-NEXT: lui a0, 3211; CHECK-NEXT: addi a0, a0, 819212; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t213; CHECK-NEXT: vand.vx v9, v8, a0, v0.t214; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t215; CHECK-NEXT: vand.vx v8, v8, a0, v0.t216; CHECK-NEXT: lui a0, 1217; CHECK-NEXT: addi a0, a0, -241218; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t219; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t220; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t221; CHECK-NEXT: vand.vx v8, v8, a0, v0.t222; CHECK-NEXT: li a0, 257223; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t224; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t225; CHECK-NEXT: ret226 %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl)227 ret <2 x i16> %v228}229 230define <2 x i16> @vp_cttz_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {231; CHECK-LABEL: vp_cttz_v2i16_unmasked:232; CHECK: # %bb.0:233; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma234; CHECK-NEXT: vadd.vi v9, v8, -1235; CHECK-NEXT: vnot.v v8, v8236; CHECK-NEXT: lui a0, 5237; CHECK-NEXT: vand.vv v8, v8, v9238; CHECK-NEXT: addi a0, a0, 1365239; CHECK-NEXT: vsrl.vi v9, v8, 1240; CHECK-NEXT: vand.vx v9, v9, a0241; CHECK-NEXT: lui a0, 3242; CHECK-NEXT: addi a0, a0, 819243; CHECK-NEXT: vsub.vv v8, v8, v9244; CHECK-NEXT: vand.vx v9, v8, a0245; CHECK-NEXT: vsrl.vi v8, v8, 2246; CHECK-NEXT: vand.vx v8, v8, a0247; CHECK-NEXT: lui a0, 1248; CHECK-NEXT: addi a0, a0, -241249; CHECK-NEXT: vadd.vv v8, v9, v8250; CHECK-NEXT: vsrl.vi v9, v8, 4251; CHECK-NEXT: vadd.vv v8, v8, v9252; CHECK-NEXT: vand.vx v8, v8, a0253; CHECK-NEXT: li a0, 257254; CHECK-NEXT: vmul.vx v8, v8, a0255; CHECK-NEXT: vsrl.vi v8, v8, 8256; CHECK-NEXT: ret257 %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl)258 ret <2 x i16> %v259}260 261define <4 x i16> @vp_cttz_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {262; CHECK-LABEL: vp_cttz_v4i16:263; CHECK: # %bb.0:264; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma265; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t266; CHECK-NEXT: lui a0, 5267; CHECK-NEXT: vnot.v v8, v8, v0.t268; CHECK-NEXT: addi a0, a0, 1365269; CHECK-NEXT: vand.vv v8, v8, v9, v0.t270; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t271; CHECK-NEXT: vand.vx v9, v9, a0, v0.t272; CHECK-NEXT: lui a0, 3273; CHECK-NEXT: addi a0, a0, 819274; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t275; CHECK-NEXT: vand.vx v9, v8, a0, v0.t276; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t277; CHECK-NEXT: vand.vx v8, v8, a0, v0.t278; CHECK-NEXT: lui a0, 1279; CHECK-NEXT: addi a0, a0, -241280; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t281; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t282; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t283; CHECK-NEXT: vand.vx v8, v8, a0, v0.t284; CHECK-NEXT: li a0, 257285; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t286; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t287; CHECK-NEXT: ret288 %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl)289 ret <4 x i16> %v290}291 292define <4 x i16> @vp_cttz_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {293; CHECK-LABEL: vp_cttz_v4i16_unmasked:294; CHECK: # %bb.0:295; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma296; CHECK-NEXT: vadd.vi v9, v8, -1297; CHECK-NEXT: vnot.v v8, v8298; CHECK-NEXT: lui a0, 5299; CHECK-NEXT: vand.vv v8, v8, v9300; CHECK-NEXT: addi a0, a0, 1365301; CHECK-NEXT: vsrl.vi v9, v8, 1302; CHECK-NEXT: vand.vx v9, v9, a0303; CHECK-NEXT: lui a0, 3304; CHECK-NEXT: addi a0, a0, 819305; CHECK-NEXT: vsub.vv v8, v8, v9306; CHECK-NEXT: vand.vx v9, v8, a0307; CHECK-NEXT: vsrl.vi v8, v8, 2308; CHECK-NEXT: vand.vx v8, v8, a0309; CHECK-NEXT: lui a0, 1310; CHECK-NEXT: addi a0, a0, -241311; CHECK-NEXT: vadd.vv v8, v9, v8312; CHECK-NEXT: vsrl.vi v9, v8, 4313; CHECK-NEXT: vadd.vv v8, v8, v9314; CHECK-NEXT: vand.vx v8, v8, a0315; CHECK-NEXT: li a0, 257316; CHECK-NEXT: vmul.vx v8, v8, a0317; CHECK-NEXT: vsrl.vi v8, v8, 8318; CHECK-NEXT: ret319 %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl)320 ret <4 x i16> %v321}322 323define <8 x i16> @vp_cttz_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {324; CHECK-LABEL: vp_cttz_v8i16:325; CHECK: # %bb.0:326; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma327; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t328; CHECK-NEXT: lui a0, 5329; CHECK-NEXT: vnot.v v8, v8, v0.t330; CHECK-NEXT: addi a0, a0, 1365331; CHECK-NEXT: vand.vv v8, v8, v9, v0.t332; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t333; CHECK-NEXT: vand.vx v9, v9, a0, v0.t334; CHECK-NEXT: lui a0, 3335; CHECK-NEXT: addi a0, a0, 819336; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t337; CHECK-NEXT: vand.vx v9, v8, a0, v0.t338; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t339; CHECK-NEXT: vand.vx v8, v8, a0, v0.t340; CHECK-NEXT: lui a0, 1341; CHECK-NEXT: addi a0, a0, -241342; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t343; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t344; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t345; CHECK-NEXT: vand.vx v8, v8, a0, v0.t346; CHECK-NEXT: li a0, 257347; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t348; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t349; CHECK-NEXT: ret350 %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl)351 ret <8 x i16> %v352}353 354define <8 x i16> @vp_cttz_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {355; CHECK-LABEL: vp_cttz_v8i16_unmasked:356; CHECK: # %bb.0:357; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma358; CHECK-NEXT: vadd.vi v9, v8, -1359; CHECK-NEXT: vnot.v v8, v8360; CHECK-NEXT: lui a0, 5361; CHECK-NEXT: vand.vv v8, v8, v9362; CHECK-NEXT: addi a0, a0, 1365363; CHECK-NEXT: vsrl.vi v9, v8, 1364; CHECK-NEXT: vand.vx v9, v9, a0365; CHECK-NEXT: lui a0, 3366; CHECK-NEXT: addi a0, a0, 819367; CHECK-NEXT: vsub.vv v8, v8, v9368; CHECK-NEXT: vand.vx v9, v8, a0369; CHECK-NEXT: vsrl.vi v8, v8, 2370; CHECK-NEXT: vand.vx v8, v8, a0371; CHECK-NEXT: lui a0, 1372; CHECK-NEXT: addi a0, a0, -241373; CHECK-NEXT: vadd.vv v8, v9, v8374; CHECK-NEXT: vsrl.vi v9, v8, 4375; CHECK-NEXT: vadd.vv v8, v8, v9376; CHECK-NEXT: vand.vx v8, v8, a0377; CHECK-NEXT: li a0, 257378; CHECK-NEXT: vmul.vx v8, v8, a0379; CHECK-NEXT: vsrl.vi v8, v8, 8380; CHECK-NEXT: ret381 %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl)382 ret <8 x i16> %v383}384 385define <16 x i16> @vp_cttz_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {386; CHECK-LABEL: vp_cttz_v16i16:387; CHECK: # %bb.0:388; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma389; CHECK-NEXT: vadd.vi v10, v8, -1, v0.t390; CHECK-NEXT: lui a0, 5391; CHECK-NEXT: vnot.v v8, v8, v0.t392; CHECK-NEXT: addi a0, a0, 1365393; CHECK-NEXT: vand.vv v8, v8, v10, v0.t394; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t395; CHECK-NEXT: vand.vx v10, v10, a0, v0.t396; CHECK-NEXT: lui a0, 3397; CHECK-NEXT: addi a0, a0, 819398; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t399; CHECK-NEXT: vand.vx v10, v8, a0, v0.t400; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t401; CHECK-NEXT: vand.vx v8, v8, a0, v0.t402; CHECK-NEXT: lui a0, 1403; CHECK-NEXT: addi a0, a0, -241404; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t405; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t406; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t407; CHECK-NEXT: vand.vx v8, v8, a0, v0.t408; CHECK-NEXT: li a0, 257409; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t410; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t411; CHECK-NEXT: ret412 %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl)413 ret <16 x i16> %v414}415 416define <16 x i16> @vp_cttz_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {417; CHECK-LABEL: vp_cttz_v16i16_unmasked:418; CHECK: # %bb.0:419; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma420; CHECK-NEXT: vadd.vi v10, v8, -1421; CHECK-NEXT: vnot.v v8, v8422; CHECK-NEXT: lui a0, 5423; CHECK-NEXT: vand.vv v8, v8, v10424; CHECK-NEXT: addi a0, a0, 1365425; CHECK-NEXT: vsrl.vi v10, v8, 1426; CHECK-NEXT: vand.vx v10, v10, a0427; CHECK-NEXT: lui a0, 3428; CHECK-NEXT: addi a0, a0, 819429; CHECK-NEXT: vsub.vv v8, v8, v10430; CHECK-NEXT: vand.vx v10, v8, a0431; CHECK-NEXT: vsrl.vi v8, v8, 2432; CHECK-NEXT: vand.vx v8, v8, a0433; CHECK-NEXT: lui a0, 1434; CHECK-NEXT: addi a0, a0, -241435; CHECK-NEXT: vadd.vv v8, v10, v8436; CHECK-NEXT: vsrl.vi v10, v8, 4437; CHECK-NEXT: vadd.vv v8, v8, v10438; CHECK-NEXT: vand.vx v8, v8, a0439; CHECK-NEXT: li a0, 257440; CHECK-NEXT: vmul.vx v8, v8, a0441; CHECK-NEXT: vsrl.vi v8, v8, 8442; CHECK-NEXT: ret443 %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl)444 ret <16 x i16> %v445}446 447define <2 x i32> @vp_cttz_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {448; CHECK-LABEL: vp_cttz_v2i32:449; CHECK: # %bb.0:450; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma451; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t452; CHECK-NEXT: lui a0, 349525453; CHECK-NEXT: vnot.v v8, v8, v0.t454; CHECK-NEXT: addi a0, a0, 1365455; CHECK-NEXT: vand.vv v8, v8, v9, v0.t456; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t457; CHECK-NEXT: vand.vx v9, v9, a0, v0.t458; CHECK-NEXT: lui a0, 209715459; CHECK-NEXT: addi a0, a0, 819460; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t461; CHECK-NEXT: vand.vx v9, v8, a0, v0.t462; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t463; CHECK-NEXT: vand.vx v8, v8, a0, v0.t464; CHECK-NEXT: lui a0, 61681465; CHECK-NEXT: addi a0, a0, -241466; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t467; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t468; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t469; CHECK-NEXT: vand.vx v8, v8, a0, v0.t470; CHECK-NEXT: lui a0, 4112471; CHECK-NEXT: addi a0, a0, 257472; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t473; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t474; CHECK-NEXT: ret475 %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl)476 ret <2 x i32> %v477}478 479define <2 x i32> @vp_cttz_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {480; CHECK-LABEL: vp_cttz_v2i32_unmasked:481; CHECK: # %bb.0:482; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma483; CHECK-NEXT: vadd.vi v9, v8, -1484; CHECK-NEXT: vnot.v v8, v8485; CHECK-NEXT: lui a0, 349525486; CHECK-NEXT: vand.vv v8, v8, v9487; CHECK-NEXT: addi a0, a0, 1365488; CHECK-NEXT: vsrl.vi v9, v8, 1489; CHECK-NEXT: vand.vx v9, v9, a0490; CHECK-NEXT: lui a0, 209715491; CHECK-NEXT: addi a0, a0, 819492; CHECK-NEXT: vsub.vv v8, v8, v9493; CHECK-NEXT: vand.vx v9, v8, a0494; CHECK-NEXT: vsrl.vi v8, v8, 2495; CHECK-NEXT: vand.vx v8, v8, a0496; CHECK-NEXT: lui a0, 61681497; CHECK-NEXT: addi a0, a0, -241498; CHECK-NEXT: vadd.vv v8, v9, v8499; CHECK-NEXT: vsrl.vi v9, v8, 4500; CHECK-NEXT: vadd.vv v8, v8, v9501; CHECK-NEXT: vand.vx v8, v8, a0502; CHECK-NEXT: lui a0, 4112503; CHECK-NEXT: addi a0, a0, 257504; CHECK-NEXT: vmul.vx v8, v8, a0505; CHECK-NEXT: vsrl.vi v8, v8, 24506; CHECK-NEXT: ret507 %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl)508 ret <2 x i32> %v509}510 511define <4 x i32> @vp_cttz_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {512; CHECK-LABEL: vp_cttz_v4i32:513; CHECK: # %bb.0:514; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma515; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t516; CHECK-NEXT: lui a0, 349525517; CHECK-NEXT: vnot.v v8, v8, v0.t518; CHECK-NEXT: addi a0, a0, 1365519; CHECK-NEXT: vand.vv v8, v8, v9, v0.t520; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t521; CHECK-NEXT: vand.vx v9, v9, a0, v0.t522; CHECK-NEXT: lui a0, 209715523; CHECK-NEXT: addi a0, a0, 819524; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t525; CHECK-NEXT: vand.vx v9, v8, a0, v0.t526; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t527; CHECK-NEXT: vand.vx v8, v8, a0, v0.t528; CHECK-NEXT: lui a0, 61681529; CHECK-NEXT: addi a0, a0, -241530; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t531; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t532; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t533; CHECK-NEXT: vand.vx v8, v8, a0, v0.t534; CHECK-NEXT: lui a0, 4112535; CHECK-NEXT: addi a0, a0, 257536; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t537; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t538; CHECK-NEXT: ret539 %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl)540 ret <4 x i32> %v541}542 543define <4 x i32> @vp_cttz_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {544; CHECK-LABEL: vp_cttz_v4i32_unmasked:545; CHECK: # %bb.0:546; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma547; CHECK-NEXT: vadd.vi v9, v8, -1548; CHECK-NEXT: vnot.v v8, v8549; CHECK-NEXT: lui a0, 349525550; CHECK-NEXT: vand.vv v8, v8, v9551; CHECK-NEXT: addi a0, a0, 1365552; CHECK-NEXT: vsrl.vi v9, v8, 1553; CHECK-NEXT: vand.vx v9, v9, a0554; CHECK-NEXT: lui a0, 209715555; CHECK-NEXT: addi a0, a0, 819556; CHECK-NEXT: vsub.vv v8, v8, v9557; CHECK-NEXT: vand.vx v9, v8, a0558; CHECK-NEXT: vsrl.vi v8, v8, 2559; CHECK-NEXT: vand.vx v8, v8, a0560; CHECK-NEXT: lui a0, 61681561; CHECK-NEXT: addi a0, a0, -241562; CHECK-NEXT: vadd.vv v8, v9, v8563; CHECK-NEXT: vsrl.vi v9, v8, 4564; CHECK-NEXT: vadd.vv v8, v8, v9565; CHECK-NEXT: vand.vx v8, v8, a0566; CHECK-NEXT: lui a0, 4112567; CHECK-NEXT: addi a0, a0, 257568; CHECK-NEXT: vmul.vx v8, v8, a0569; CHECK-NEXT: vsrl.vi v8, v8, 24570; CHECK-NEXT: ret571 %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl)572 ret <4 x i32> %v573}574 575define <8 x i32> @vp_cttz_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {576; CHECK-LABEL: vp_cttz_v8i32:577; CHECK: # %bb.0:578; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma579; CHECK-NEXT: vadd.vi v10, v8, -1, v0.t580; CHECK-NEXT: lui a0, 349525581; CHECK-NEXT: vnot.v v8, v8, v0.t582; CHECK-NEXT: addi a0, a0, 1365583; CHECK-NEXT: vand.vv v8, v8, v10, v0.t584; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t585; CHECK-NEXT: vand.vx v10, v10, a0, v0.t586; CHECK-NEXT: lui a0, 209715587; CHECK-NEXT: addi a0, a0, 819588; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t589; CHECK-NEXT: vand.vx v10, v8, a0, v0.t590; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t591; CHECK-NEXT: vand.vx v8, v8, a0, v0.t592; CHECK-NEXT: lui a0, 61681593; CHECK-NEXT: addi a0, a0, -241594; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t595; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t596; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t597; CHECK-NEXT: vand.vx v8, v8, a0, v0.t598; CHECK-NEXT: lui a0, 4112599; CHECK-NEXT: addi a0, a0, 257600; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t601; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t602; CHECK-NEXT: ret603 %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl)604 ret <8 x i32> %v605}606 607define <8 x i32> @vp_cttz_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {608; CHECK-LABEL: vp_cttz_v8i32_unmasked:609; CHECK: # %bb.0:610; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma611; CHECK-NEXT: vadd.vi v10, v8, -1612; CHECK-NEXT: vnot.v v8, v8613; CHECK-NEXT: lui a0, 349525614; CHECK-NEXT: vand.vv v8, v8, v10615; CHECK-NEXT: addi a0, a0, 1365616; CHECK-NEXT: vsrl.vi v10, v8, 1617; CHECK-NEXT: vand.vx v10, v10, a0618; CHECK-NEXT: lui a0, 209715619; CHECK-NEXT: addi a0, a0, 819620; CHECK-NEXT: vsub.vv v8, v8, v10621; CHECK-NEXT: vand.vx v10, v8, a0622; CHECK-NEXT: vsrl.vi v8, v8, 2623; CHECK-NEXT: vand.vx v8, v8, a0624; CHECK-NEXT: lui a0, 61681625; CHECK-NEXT: addi a0, a0, -241626; CHECK-NEXT: vadd.vv v8, v10, v8627; CHECK-NEXT: vsrl.vi v10, v8, 4628; CHECK-NEXT: vadd.vv v8, v8, v10629; CHECK-NEXT: vand.vx v8, v8, a0630; CHECK-NEXT: lui a0, 4112631; CHECK-NEXT: addi a0, a0, 257632; CHECK-NEXT: vmul.vx v8, v8, a0633; CHECK-NEXT: vsrl.vi v8, v8, 24634; CHECK-NEXT: ret635 %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl)636 ret <8 x i32> %v637}638 639define <16 x i32> @vp_cttz_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {640; CHECK-LABEL: vp_cttz_v16i32:641; CHECK: # %bb.0:642; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma643; CHECK-NEXT: vadd.vi v12, v8, -1, v0.t644; CHECK-NEXT: lui a0, 349525645; CHECK-NEXT: vnot.v v8, v8, v0.t646; CHECK-NEXT: addi a0, a0, 1365647; CHECK-NEXT: vand.vv v8, v8, v12, v0.t648; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t649; CHECK-NEXT: vand.vx v12, v12, a0, v0.t650; CHECK-NEXT: lui a0, 209715651; CHECK-NEXT: addi a0, a0, 819652; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t653; CHECK-NEXT: vand.vx v12, v8, a0, v0.t654; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t655; CHECK-NEXT: vand.vx v8, v8, a0, v0.t656; CHECK-NEXT: lui a0, 61681657; CHECK-NEXT: addi a0, a0, -241658; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t659; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t660; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t661; CHECK-NEXT: vand.vx v8, v8, a0, v0.t662; CHECK-NEXT: lui a0, 4112663; CHECK-NEXT: addi a0, a0, 257664; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t665; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t666; CHECK-NEXT: ret667 %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl)668 ret <16 x i32> %v669}670 671define <16 x i32> @vp_cttz_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {672; CHECK-LABEL: vp_cttz_v16i32_unmasked:673; CHECK: # %bb.0:674; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma675; CHECK-NEXT: vadd.vi v12, v8, -1676; CHECK-NEXT: vnot.v v8, v8677; CHECK-NEXT: lui a0, 349525678; CHECK-NEXT: vand.vv v8, v8, v12679; CHECK-NEXT: addi a0, a0, 1365680; CHECK-NEXT: vsrl.vi v12, v8, 1681; CHECK-NEXT: vand.vx v12, v12, a0682; CHECK-NEXT: lui a0, 209715683; CHECK-NEXT: addi a0, a0, 819684; CHECK-NEXT: vsub.vv v8, v8, v12685; CHECK-NEXT: vand.vx v12, v8, a0686; CHECK-NEXT: vsrl.vi v8, v8, 2687; CHECK-NEXT: vand.vx v8, v8, a0688; CHECK-NEXT: lui a0, 61681689; CHECK-NEXT: addi a0, a0, -241690; CHECK-NEXT: vadd.vv v8, v12, v8691; CHECK-NEXT: vsrl.vi v12, v8, 4692; CHECK-NEXT: vadd.vv v8, v8, v12693; CHECK-NEXT: vand.vx v8, v8, a0694; CHECK-NEXT: lui a0, 4112695; CHECK-NEXT: addi a0, a0, 257696; CHECK-NEXT: vmul.vx v8, v8, a0697; CHECK-NEXT: vsrl.vi v8, v8, 24698; CHECK-NEXT: ret699 %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl)700 ret <16 x i32> %v701}702 703define <2 x i64> @vp_cttz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {704; RV32-LABEL: vp_cttz_v2i64:705; RV32: # %bb.0:706; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma707; RV32-NEXT: vadd.vi v9, v8, -1, v0.t708; RV32-NEXT: lui a1, 349525709; RV32-NEXT: addi a1, a1, 1365710; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma711; RV32-NEXT: vmv.v.x v10, a1712; RV32-NEXT: lui a1, 209715713; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma714; RV32-NEXT: vnot.v v8, v8, v0.t715; RV32-NEXT: addi a1, a1, 819716; RV32-NEXT: vand.vv v8, v8, v9, v0.t717; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t718; RV32-NEXT: vand.vv v9, v9, v10, v0.t719; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma720; RV32-NEXT: vmv.v.x v10, a1721; RV32-NEXT: lui a1, 61681722; RV32-NEXT: addi a1, a1, -241723; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma724; RV32-NEXT: vsub.vv v8, v8, v9, v0.t725; RV32-NEXT: vand.vv v9, v8, v10, v0.t726; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t727; RV32-NEXT: vand.vv v8, v8, v10, v0.t728; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma729; RV32-NEXT: vmv.v.x v10, a1730; RV32-NEXT: lui a1, 4112731; RV32-NEXT: addi a1, a1, 257732; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma733; RV32-NEXT: vadd.vv v8, v9, v8, v0.t734; RV32-NEXT: vsrl.vi v9, v8, 4, v0.t735; RV32-NEXT: vadd.vv v8, v8, v9, v0.t736; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma737; RV32-NEXT: vmv.v.x v9, a1738; RV32-NEXT: li a1, 56739; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma740; RV32-NEXT: vand.vv v8, v8, v10, v0.t741; RV32-NEXT: vmul.vv v8, v8, v9, v0.t742; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t743; RV32-NEXT: ret744;745; RV64-LABEL: vp_cttz_v2i64:746; RV64: # %bb.0:747; RV64-NEXT: lui a1, 349525748; RV64-NEXT: lui a2, 209715749; RV64-NEXT: lui a3, 61681750; RV64-NEXT: lui a4, 4112751; RV64-NEXT: addi a1, a1, 1365752; RV64-NEXT: addi a2, a2, 819753; RV64-NEXT: addi a3, a3, -241754; RV64-NEXT: addi a4, a4, 257755; RV64-NEXT: slli a5, a1, 32756; RV64-NEXT: add a1, a1, a5757; RV64-NEXT: slli a5, a2, 32758; RV64-NEXT: add a2, a2, a5759; RV64-NEXT: slli a5, a3, 32760; RV64-NEXT: add a3, a3, a5761; RV64-NEXT: slli a5, a4, 32762; RV64-NEXT: add a4, a4, a5763; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma764; RV64-NEXT: vadd.vi v9, v8, -1, v0.t765; RV64-NEXT: vnot.v v8, v8, v0.t766; RV64-NEXT: vand.vv v8, v8, v9, v0.t767; RV64-NEXT: vsrl.vi v9, v8, 1, v0.t768; RV64-NEXT: vand.vx v9, v9, a1, v0.t769; RV64-NEXT: vsub.vv v8, v8, v9, v0.t770; RV64-NEXT: vand.vx v9, v8, a2, v0.t771; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t772; RV64-NEXT: vand.vx v8, v8, a2, v0.t773; RV64-NEXT: vadd.vv v8, v9, v8, v0.t774; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t775; RV64-NEXT: vadd.vv v8, v8, v9, v0.t776; RV64-NEXT: vand.vx v8, v8, a3, v0.t777; RV64-NEXT: li a0, 56778; RV64-NEXT: vmul.vx v8, v8, a4, v0.t779; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t780; RV64-NEXT: ret781 %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl)782 ret <2 x i64> %v783}784 785define <2 x i64> @vp_cttz_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {786; RV32-LABEL: vp_cttz_v2i64_unmasked:787; RV32: # %bb.0:788; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma789; RV32-NEXT: vadd.vi v9, v8, -1790; RV32-NEXT: vnot.v v8, v8791; RV32-NEXT: lui a1, 349525792; RV32-NEXT: addi a1, a1, 1365793; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma794; RV32-NEXT: vmv.v.x v10, a1795; RV32-NEXT: lui a1, 209715796; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma797; RV32-NEXT: vand.vv v8, v8, v9798; RV32-NEXT: addi a1, a1, 819799; RV32-NEXT: vsrl.vi v9, v8, 1800; RV32-NEXT: vand.vv v9, v9, v10801; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma802; RV32-NEXT: vmv.v.x v10, a1803; RV32-NEXT: lui a1, 61681804; RV32-NEXT: addi a1, a1, -241805; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma806; RV32-NEXT: vsub.vv v8, v8, v9807; RV32-NEXT: vand.vv v9, v8, v10808; RV32-NEXT: vsrl.vi v8, v8, 2809; RV32-NEXT: vand.vv v8, v8, v10810; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma811; RV32-NEXT: vmv.v.x v10, a1812; RV32-NEXT: lui a1, 4112813; RV32-NEXT: addi a1, a1, 257814; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma815; RV32-NEXT: vadd.vv v8, v9, v8816; RV32-NEXT: vsrl.vi v9, v8, 4817; RV32-NEXT: vadd.vv v8, v8, v9818; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma819; RV32-NEXT: vmv.v.x v9, a1820; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma821; RV32-NEXT: vand.vv v8, v8, v10822; RV32-NEXT: vmul.vv v8, v8, v9823; RV32-NEXT: li a0, 56824; RV32-NEXT: vsrl.vx v8, v8, a0825; RV32-NEXT: ret826;827; RV64-LABEL: vp_cttz_v2i64_unmasked:828; RV64: # %bb.0:829; RV64-NEXT: lui a1, 349525830; RV64-NEXT: lui a2, 209715831; RV64-NEXT: lui a3, 61681832; RV64-NEXT: lui a4, 4112833; RV64-NEXT: addi a1, a1, 1365834; RV64-NEXT: addi a2, a2, 819835; RV64-NEXT: addi a3, a3, -241836; RV64-NEXT: addi a4, a4, 257837; RV64-NEXT: slli a5, a1, 32838; RV64-NEXT: add a1, a1, a5839; RV64-NEXT: slli a5, a2, 32840; RV64-NEXT: add a2, a2, a5841; RV64-NEXT: slli a5, a3, 32842; RV64-NEXT: add a3, a3, a5843; RV64-NEXT: slli a5, a4, 32844; RV64-NEXT: add a4, a4, a5845; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma846; RV64-NEXT: vadd.vi v9, v8, -1847; RV64-NEXT: vnot.v v8, v8848; RV64-NEXT: vand.vv v8, v8, v9849; RV64-NEXT: vsrl.vi v9, v8, 1850; RV64-NEXT: vand.vx v9, v9, a1851; RV64-NEXT: vsub.vv v8, v8, v9852; RV64-NEXT: vand.vx v9, v8, a2853; RV64-NEXT: vsrl.vi v8, v8, 2854; RV64-NEXT: vand.vx v8, v8, a2855; RV64-NEXT: vadd.vv v8, v9, v8856; RV64-NEXT: vsrl.vi v9, v8, 4857; RV64-NEXT: vadd.vv v8, v8, v9858; RV64-NEXT: vand.vx v8, v8, a3859; RV64-NEXT: vmul.vx v8, v8, a4860; RV64-NEXT: li a0, 56861; RV64-NEXT: vsrl.vx v8, v8, a0862; RV64-NEXT: ret863 %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl)864 ret <2 x i64> %v865}866 867define <4 x i64> @vp_cttz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {868; RV32-LABEL: vp_cttz_v4i64:869; RV32: # %bb.0:870; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma871; RV32-NEXT: vadd.vi v10, v8, -1, v0.t872; RV32-NEXT: lui a1, 349525873; RV32-NEXT: addi a1, a1, 1365874; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma875; RV32-NEXT: vmv.v.x v12, a1876; RV32-NEXT: lui a1, 209715877; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma878; RV32-NEXT: vnot.v v8, v8, v0.t879; RV32-NEXT: addi a1, a1, 819880; RV32-NEXT: vand.vv v8, v8, v10, v0.t881; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t882; RV32-NEXT: vand.vv v10, v10, v12, v0.t883; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma884; RV32-NEXT: vmv.v.x v12, a1885; RV32-NEXT: lui a1, 61681886; RV32-NEXT: addi a1, a1, -241887; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma888; RV32-NEXT: vsub.vv v8, v8, v10, v0.t889; RV32-NEXT: vand.vv v10, v8, v12, v0.t890; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t891; RV32-NEXT: vand.vv v8, v8, v12, v0.t892; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma893; RV32-NEXT: vmv.v.x v12, a1894; RV32-NEXT: lui a1, 4112895; RV32-NEXT: addi a1, a1, 257896; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma897; RV32-NEXT: vadd.vv v8, v10, v8, v0.t898; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t899; RV32-NEXT: vadd.vv v8, v8, v10, v0.t900; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma901; RV32-NEXT: vmv.v.x v10, a1902; RV32-NEXT: li a1, 56903; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma904; RV32-NEXT: vand.vv v8, v8, v12, v0.t905; RV32-NEXT: vmul.vv v8, v8, v10, v0.t906; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t907; RV32-NEXT: ret908;909; RV64-LABEL: vp_cttz_v4i64:910; RV64: # %bb.0:911; RV64-NEXT: lui a1, 349525912; RV64-NEXT: lui a2, 209715913; RV64-NEXT: lui a3, 61681914; RV64-NEXT: lui a4, 4112915; RV64-NEXT: addi a1, a1, 1365916; RV64-NEXT: addi a2, a2, 819917; RV64-NEXT: addi a3, a3, -241918; RV64-NEXT: addi a4, a4, 257919; RV64-NEXT: slli a5, a1, 32920; RV64-NEXT: add a1, a1, a5921; RV64-NEXT: slli a5, a2, 32922; RV64-NEXT: add a2, a2, a5923; RV64-NEXT: slli a5, a3, 32924; RV64-NEXT: add a3, a3, a5925; RV64-NEXT: slli a5, a4, 32926; RV64-NEXT: add a4, a4, a5927; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma928; RV64-NEXT: vadd.vi v10, v8, -1, v0.t929; RV64-NEXT: vnot.v v8, v8, v0.t930; RV64-NEXT: vand.vv v8, v8, v10, v0.t931; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t932; RV64-NEXT: vand.vx v10, v10, a1, v0.t933; RV64-NEXT: vsub.vv v8, v8, v10, v0.t934; RV64-NEXT: vand.vx v10, v8, a2, v0.t935; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t936; RV64-NEXT: vand.vx v8, v8, a2, v0.t937; RV64-NEXT: vadd.vv v8, v10, v8, v0.t938; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t939; RV64-NEXT: vadd.vv v8, v8, v10, v0.t940; RV64-NEXT: vand.vx v8, v8, a3, v0.t941; RV64-NEXT: li a0, 56942; RV64-NEXT: vmul.vx v8, v8, a4, v0.t943; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t944; RV64-NEXT: ret945 %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl)946 ret <4 x i64> %v947}948 949define <4 x i64> @vp_cttz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {950; RV32-LABEL: vp_cttz_v4i64_unmasked:951; RV32: # %bb.0:952; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma953; RV32-NEXT: vadd.vi v10, v8, -1954; RV32-NEXT: vnot.v v8, v8955; RV32-NEXT: lui a1, 349525956; RV32-NEXT: addi a1, a1, 1365957; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma958; RV32-NEXT: vmv.v.x v12, a1959; RV32-NEXT: lui a1, 209715960; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma961; RV32-NEXT: vand.vv v8, v8, v10962; RV32-NEXT: addi a1, a1, 819963; RV32-NEXT: vsrl.vi v10, v8, 1964; RV32-NEXT: vand.vv v10, v10, v12965; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma966; RV32-NEXT: vmv.v.x v12, a1967; RV32-NEXT: lui a1, 61681968; RV32-NEXT: addi a1, a1, -241969; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma970; RV32-NEXT: vsub.vv v8, v8, v10971; RV32-NEXT: vand.vv v10, v8, v12972; RV32-NEXT: vsrl.vi v8, v8, 2973; RV32-NEXT: vand.vv v8, v8, v12974; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma975; RV32-NEXT: vmv.v.x v12, a1976; RV32-NEXT: lui a1, 4112977; RV32-NEXT: addi a1, a1, 257978; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma979; RV32-NEXT: vadd.vv v8, v10, v8980; RV32-NEXT: vsrl.vi v10, v8, 4981; RV32-NEXT: vadd.vv v8, v8, v10982; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma983; RV32-NEXT: vmv.v.x v10, a1984; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma985; RV32-NEXT: vand.vv v8, v8, v12986; RV32-NEXT: vmul.vv v8, v8, v10987; RV32-NEXT: li a0, 56988; RV32-NEXT: vsrl.vx v8, v8, a0989; RV32-NEXT: ret990;991; RV64-LABEL: vp_cttz_v4i64_unmasked:992; RV64: # %bb.0:993; RV64-NEXT: lui a1, 349525994; RV64-NEXT: lui a2, 209715995; RV64-NEXT: lui a3, 61681996; RV64-NEXT: lui a4, 4112997; RV64-NEXT: addi a1, a1, 1365998; RV64-NEXT: addi a2, a2, 819999; RV64-NEXT: addi a3, a3, -2411000; RV64-NEXT: addi a4, a4, 2571001; RV64-NEXT: slli a5, a1, 321002; RV64-NEXT: add a1, a1, a51003; RV64-NEXT: slli a5, a2, 321004; RV64-NEXT: add a2, a2, a51005; RV64-NEXT: slli a5, a3, 321006; RV64-NEXT: add a3, a3, a51007; RV64-NEXT: slli a5, a4, 321008; RV64-NEXT: add a4, a4, a51009; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma1010; RV64-NEXT: vadd.vi v10, v8, -11011; RV64-NEXT: vnot.v v8, v81012; RV64-NEXT: vand.vv v8, v8, v101013; RV64-NEXT: vsrl.vi v10, v8, 11014; RV64-NEXT: vand.vx v10, v10, a11015; RV64-NEXT: vsub.vv v8, v8, v101016; RV64-NEXT: vand.vx v10, v8, a21017; RV64-NEXT: vsrl.vi v8, v8, 21018; RV64-NEXT: vand.vx v8, v8, a21019; RV64-NEXT: vadd.vv v8, v10, v81020; RV64-NEXT: vsrl.vi v10, v8, 41021; RV64-NEXT: vadd.vv v8, v8, v101022; RV64-NEXT: vand.vx v8, v8, a31023; RV64-NEXT: vmul.vx v8, v8, a41024; RV64-NEXT: li a0, 561025; RV64-NEXT: vsrl.vx v8, v8, a01026; RV64-NEXT: ret1027 %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl)1028 ret <4 x i64> %v1029}1030 1031define <8 x i64> @vp_cttz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {1032; RV32-LABEL: vp_cttz_v8i64:1033; RV32: # %bb.0:1034; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1035; RV32-NEXT: vadd.vi v12, v8, -1, v0.t1036; RV32-NEXT: lui a1, 3495251037; RV32-NEXT: addi a1, a1, 13651038; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1039; RV32-NEXT: vmv.v.x v16, a11040; RV32-NEXT: lui a1, 2097151041; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1042; RV32-NEXT: vnot.v v8, v8, v0.t1043; RV32-NEXT: addi a1, a1, 8191044; RV32-NEXT: vand.vv v12, v8, v12, v0.t1045; RV32-NEXT: vsrl.vi v8, v12, 1, v0.t1046; RV32-NEXT: vand.vv v16, v8, v16, v0.t1047; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1048; RV32-NEXT: vmv.v.x v8, a11049; RV32-NEXT: lui a1, 616811050; RV32-NEXT: addi a1, a1, -2411051; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1052; RV32-NEXT: vsub.vv v12, v12, v16, v0.t1053; RV32-NEXT: vand.vv v16, v12, v8, v0.t1054; RV32-NEXT: vsrl.vi v12, v12, 2, v0.t1055; RV32-NEXT: vand.vv v8, v12, v8, v0.t1056; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1057; RV32-NEXT: vmv.v.x v12, a11058; RV32-NEXT: lui a1, 41121059; RV32-NEXT: addi a1, a1, 2571060; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1061; RV32-NEXT: vadd.vv v8, v16, v8, v0.t1062; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t1063; RV32-NEXT: vadd.vv v8, v8, v16, v0.t1064; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1065; RV32-NEXT: vmv.v.x v16, a11066; RV32-NEXT: li a1, 561067; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1068; RV32-NEXT: vand.vv v8, v8, v12, v0.t1069; RV32-NEXT: vmul.vv v8, v8, v16, v0.t1070; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1071; RV32-NEXT: ret1072;1073; RV64-LABEL: vp_cttz_v8i64:1074; RV64: # %bb.0:1075; RV64-NEXT: lui a1, 3495251076; RV64-NEXT: lui a2, 2097151077; RV64-NEXT: lui a3, 616811078; RV64-NEXT: lui a4, 41121079; RV64-NEXT: addi a1, a1, 13651080; RV64-NEXT: addi a2, a2, 8191081; RV64-NEXT: addi a3, a3, -2411082; RV64-NEXT: addi a4, a4, 2571083; RV64-NEXT: slli a5, a1, 321084; RV64-NEXT: add a1, a1, a51085; RV64-NEXT: slli a5, a2, 321086; RV64-NEXT: add a2, a2, a51087; RV64-NEXT: slli a5, a3, 321088; RV64-NEXT: add a3, a3, a51089; RV64-NEXT: slli a5, a4, 321090; RV64-NEXT: add a4, a4, a51091; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma1092; RV64-NEXT: vadd.vi v12, v8, -1, v0.t1093; RV64-NEXT: vnot.v v8, v8, v0.t1094; RV64-NEXT: vand.vv v8, v8, v12, v0.t1095; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t1096; RV64-NEXT: vand.vx v12, v12, a1, v0.t1097; RV64-NEXT: vsub.vv v8, v8, v12, v0.t1098; RV64-NEXT: vand.vx v12, v8, a2, v0.t1099; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1100; RV64-NEXT: vand.vx v8, v8, a2, v0.t1101; RV64-NEXT: vadd.vv v8, v12, v8, v0.t1102; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t1103; RV64-NEXT: vadd.vv v8, v8, v12, v0.t1104; RV64-NEXT: vand.vx v8, v8, a3, v0.t1105; RV64-NEXT: li a0, 561106; RV64-NEXT: vmul.vx v8, v8, a4, v0.t1107; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1108; RV64-NEXT: ret1109 %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl)1110 ret <8 x i64> %v1111}1112 1113define <8 x i64> @vp_cttz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {1114; RV32-LABEL: vp_cttz_v8i64_unmasked:1115; RV32: # %bb.0:1116; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1117; RV32-NEXT: vadd.vi v12, v8, -11118; RV32-NEXT: vnot.v v8, v81119; RV32-NEXT: lui a1, 3495251120; RV32-NEXT: addi a1, a1, 13651121; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1122; RV32-NEXT: vmv.v.x v16, a11123; RV32-NEXT: lui a1, 2097151124; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1125; RV32-NEXT: vand.vv v8, v8, v121126; RV32-NEXT: addi a1, a1, 8191127; RV32-NEXT: vsrl.vi v12, v8, 11128; RV32-NEXT: vand.vv v12, v12, v161129; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1130; RV32-NEXT: vmv.v.x v16, a11131; RV32-NEXT: lui a1, 616811132; RV32-NEXT: addi a1, a1, -2411133; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1134; RV32-NEXT: vsub.vv v8, v8, v121135; RV32-NEXT: vand.vv v12, v8, v161136; RV32-NEXT: vsrl.vi v8, v8, 21137; RV32-NEXT: vand.vv v8, v8, v161138; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1139; RV32-NEXT: vmv.v.x v16, a11140; RV32-NEXT: lui a1, 41121141; RV32-NEXT: addi a1, a1, 2571142; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1143; RV32-NEXT: vadd.vv v8, v12, v81144; RV32-NEXT: vsrl.vi v12, v8, 41145; RV32-NEXT: vadd.vv v8, v8, v121146; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma1147; RV32-NEXT: vmv.v.x v12, a11148; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1149; RV32-NEXT: vand.vv v8, v8, v161150; RV32-NEXT: vmul.vv v8, v8, v121151; RV32-NEXT: li a0, 561152; RV32-NEXT: vsrl.vx v8, v8, a01153; RV32-NEXT: ret1154;1155; RV64-LABEL: vp_cttz_v8i64_unmasked:1156; RV64: # %bb.0:1157; RV64-NEXT: lui a1, 3495251158; RV64-NEXT: lui a2, 2097151159; RV64-NEXT: lui a3, 616811160; RV64-NEXT: lui a4, 41121161; RV64-NEXT: addi a1, a1, 13651162; RV64-NEXT: addi a2, a2, 8191163; RV64-NEXT: addi a3, a3, -2411164; RV64-NEXT: addi a4, a4, 2571165; RV64-NEXT: slli a5, a1, 321166; RV64-NEXT: add a1, a1, a51167; RV64-NEXT: slli a5, a2, 321168; RV64-NEXT: add a2, a2, a51169; RV64-NEXT: slli a5, a3, 321170; RV64-NEXT: add a3, a3, a51171; RV64-NEXT: slli a5, a4, 321172; RV64-NEXT: add a4, a4, a51173; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma1174; RV64-NEXT: vadd.vi v12, v8, -11175; RV64-NEXT: vnot.v v8, v81176; RV64-NEXT: vand.vv v8, v8, v121177; RV64-NEXT: vsrl.vi v12, v8, 11178; RV64-NEXT: vand.vx v12, v12, a11179; RV64-NEXT: vsub.vv v8, v8, v121180; RV64-NEXT: vand.vx v12, v8, a21181; RV64-NEXT: vsrl.vi v8, v8, 21182; RV64-NEXT: vand.vx v8, v8, a21183; RV64-NEXT: vadd.vv v8, v12, v81184; RV64-NEXT: vsrl.vi v12, v8, 41185; RV64-NEXT: vadd.vv v8, v8, v121186; RV64-NEXT: vand.vx v8, v8, a31187; RV64-NEXT: vmul.vx v8, v8, a41188; RV64-NEXT: li a0, 561189; RV64-NEXT: vsrl.vx v8, v8, a01190; RV64-NEXT: ret1191 %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl)1192 ret <8 x i64> %v1193}1194 1195define <15 x i64> @vp_cttz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {1196; RV32-LABEL: vp_cttz_v15i64:1197; RV32: # %bb.0:1198; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1199; RV32-NEXT: vadd.vi v16, v8, -1, v0.t1200; RV32-NEXT: lui a1, 3495251201; RV32-NEXT: addi a1, a1, 13651202; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1203; RV32-NEXT: vmv.v.x v24, a11204; RV32-NEXT: lui a1, 2097151205; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1206; RV32-NEXT: vnot.v v8, v8, v0.t1207; RV32-NEXT: addi a1, a1, 8191208; RV32-NEXT: vand.vv v16, v8, v16, v0.t1209; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t1210; RV32-NEXT: vand.vv v24, v8, v24, v0.t1211; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1212; RV32-NEXT: vmv.v.x v8, a11213; RV32-NEXT: lui a1, 616811214; RV32-NEXT: addi a1, a1, -2411215; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1216; RV32-NEXT: vsub.vv v24, v16, v24, v0.t1217; RV32-NEXT: vand.vv v16, v24, v8, v0.t1218; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t1219; RV32-NEXT: vand.vv v24, v24, v8, v0.t1220; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1221; RV32-NEXT: vmv.v.x v8, a11222; RV32-NEXT: lui a1, 41121223; RV32-NEXT: addi a1, a1, 2571224; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1225; RV32-NEXT: vadd.vv v16, v16, v24, v0.t1226; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t1227; RV32-NEXT: vadd.vv v16, v16, v24, v0.t1228; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1229; RV32-NEXT: vmv.v.x v24, a11230; RV32-NEXT: li a1, 561231; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1232; RV32-NEXT: vand.vv v8, v16, v8, v0.t1233; RV32-NEXT: vmul.vv v8, v8, v24, v0.t1234; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1235; RV32-NEXT: ret1236;1237; RV64-LABEL: vp_cttz_v15i64:1238; RV64: # %bb.0:1239; RV64-NEXT: lui a1, 3495251240; RV64-NEXT: lui a2, 2097151241; RV64-NEXT: lui a3, 616811242; RV64-NEXT: lui a4, 41121243; RV64-NEXT: addi a1, a1, 13651244; RV64-NEXT: addi a2, a2, 8191245; RV64-NEXT: addi a3, a3, -2411246; RV64-NEXT: addi a4, a4, 2571247; RV64-NEXT: slli a5, a1, 321248; RV64-NEXT: add a1, a1, a51249; RV64-NEXT: slli a5, a2, 321250; RV64-NEXT: add a2, a2, a51251; RV64-NEXT: slli a5, a3, 321252; RV64-NEXT: add a3, a3, a51253; RV64-NEXT: slli a5, a4, 321254; RV64-NEXT: add a4, a4, a51255; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1256; RV64-NEXT: vadd.vi v16, v8, -1, v0.t1257; RV64-NEXT: vnot.v v8, v8, v0.t1258; RV64-NEXT: vand.vv v8, v8, v16, v0.t1259; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t1260; RV64-NEXT: vand.vx v16, v16, a1, v0.t1261; RV64-NEXT: vsub.vv v8, v8, v16, v0.t1262; RV64-NEXT: vand.vx v16, v8, a2, v0.t1263; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1264; RV64-NEXT: vand.vx v8, v8, a2, v0.t1265; RV64-NEXT: vadd.vv v8, v16, v8, v0.t1266; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t1267; RV64-NEXT: vadd.vv v8, v8, v16, v0.t1268; RV64-NEXT: vand.vx v8, v8, a3, v0.t1269; RV64-NEXT: li a0, 561270; RV64-NEXT: vmul.vx v8, v8, a4, v0.t1271; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1272; RV64-NEXT: ret1273 %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl)1274 ret <15 x i64> %v1275}1276 1277define <15 x i64> @vp_cttz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {1278; RV32-LABEL: vp_cttz_v15i64_unmasked:1279; RV32: # %bb.0:1280; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1281; RV32-NEXT: vadd.vi v16, v8, -11282; RV32-NEXT: vnot.v v8, v81283; RV32-NEXT: lui a1, 3495251284; RV32-NEXT: addi a1, a1, 13651285; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1286; RV32-NEXT: vmv.v.x v24, a11287; RV32-NEXT: lui a1, 2097151288; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1289; RV32-NEXT: vand.vv v8, v8, v161290; RV32-NEXT: addi a1, a1, 8191291; RV32-NEXT: vsrl.vi v16, v8, 11292; RV32-NEXT: vand.vv v24, v16, v241293; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1294; RV32-NEXT: vmv.v.x v16, a11295; RV32-NEXT: lui a1, 616811296; RV32-NEXT: addi a1, a1, -2411297; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1298; RV32-NEXT: vsub.vv v8, v8, v241299; RV32-NEXT: vand.vv v24, v8, v161300; RV32-NEXT: vsrl.vi v8, v8, 21301; RV32-NEXT: vand.vv v8, v8, v161302; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1303; RV32-NEXT: vmv.v.x v16, a11304; RV32-NEXT: lui a1, 41121305; RV32-NEXT: addi a1, a1, 2571306; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1307; RV32-NEXT: vadd.vv v8, v24, v81308; RV32-NEXT: vsrl.vi v24, v8, 41309; RV32-NEXT: vadd.vv v8, v8, v241310; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1311; RV32-NEXT: vmv.v.x v24, a11312; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1313; RV32-NEXT: vand.vv v8, v8, v161314; RV32-NEXT: vmul.vv v8, v8, v241315; RV32-NEXT: li a0, 561316; RV32-NEXT: vsrl.vx v8, v8, a01317; RV32-NEXT: ret1318;1319; RV64-LABEL: vp_cttz_v15i64_unmasked:1320; RV64: # %bb.0:1321; RV64-NEXT: lui a1, 3495251322; RV64-NEXT: lui a2, 2097151323; RV64-NEXT: lui a3, 616811324; RV64-NEXT: lui a4, 41121325; RV64-NEXT: addi a1, a1, 13651326; RV64-NEXT: addi a2, a2, 8191327; RV64-NEXT: addi a3, a3, -2411328; RV64-NEXT: addi a4, a4, 2571329; RV64-NEXT: slli a5, a1, 321330; RV64-NEXT: add a1, a1, a51331; RV64-NEXT: slli a5, a2, 321332; RV64-NEXT: add a2, a2, a51333; RV64-NEXT: slli a5, a3, 321334; RV64-NEXT: add a3, a3, a51335; RV64-NEXT: slli a5, a4, 321336; RV64-NEXT: add a4, a4, a51337; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1338; RV64-NEXT: vadd.vi v16, v8, -11339; RV64-NEXT: vnot.v v8, v81340; RV64-NEXT: vand.vv v8, v8, v161341; RV64-NEXT: vsrl.vi v16, v8, 11342; RV64-NEXT: vand.vx v16, v16, a11343; RV64-NEXT: vsub.vv v8, v8, v161344; RV64-NEXT: vand.vx v16, v8, a21345; RV64-NEXT: vsrl.vi v8, v8, 21346; RV64-NEXT: vand.vx v8, v8, a21347; RV64-NEXT: vadd.vv v8, v16, v81348; RV64-NEXT: vsrl.vi v16, v8, 41349; RV64-NEXT: vadd.vv v8, v8, v161350; RV64-NEXT: vand.vx v8, v8, a31351; RV64-NEXT: vmul.vx v8, v8, a41352; RV64-NEXT: li a0, 561353; RV64-NEXT: vsrl.vx v8, v8, a01354; RV64-NEXT: ret1355 %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 false, <15 x i1> splat (i1 true), i32 %evl)1356 ret <15 x i64> %v1357}1358 1359define <16 x i64> @vp_cttz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {1360; RV32-LABEL: vp_cttz_v16i64:1361; RV32: # %bb.0:1362; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1363; RV32-NEXT: vadd.vi v16, v8, -1, v0.t1364; RV32-NEXT: lui a1, 3495251365; RV32-NEXT: addi a1, a1, 13651366; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1367; RV32-NEXT: vmv.v.x v24, a11368; RV32-NEXT: lui a1, 2097151369; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1370; RV32-NEXT: vnot.v v8, v8, v0.t1371; RV32-NEXT: addi a1, a1, 8191372; RV32-NEXT: vand.vv v16, v8, v16, v0.t1373; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t1374; RV32-NEXT: vand.vv v24, v8, v24, v0.t1375; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1376; RV32-NEXT: vmv.v.x v8, a11377; RV32-NEXT: lui a1, 616811378; RV32-NEXT: addi a1, a1, -2411379; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1380; RV32-NEXT: vsub.vv v24, v16, v24, v0.t1381; RV32-NEXT: vand.vv v16, v24, v8, v0.t1382; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t1383; RV32-NEXT: vand.vv v24, v24, v8, v0.t1384; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1385; RV32-NEXT: vmv.v.x v8, a11386; RV32-NEXT: lui a1, 41121387; RV32-NEXT: addi a1, a1, 2571388; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1389; RV32-NEXT: vadd.vv v16, v16, v24, v0.t1390; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t1391; RV32-NEXT: vadd.vv v16, v16, v24, v0.t1392; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1393; RV32-NEXT: vmv.v.x v24, a11394; RV32-NEXT: li a1, 561395; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1396; RV32-NEXT: vand.vv v8, v16, v8, v0.t1397; RV32-NEXT: vmul.vv v8, v8, v24, v0.t1398; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1399; RV32-NEXT: ret1400;1401; RV64-LABEL: vp_cttz_v16i64:1402; RV64: # %bb.0:1403; RV64-NEXT: lui a1, 3495251404; RV64-NEXT: lui a2, 2097151405; RV64-NEXT: lui a3, 616811406; RV64-NEXT: lui a4, 41121407; RV64-NEXT: addi a1, a1, 13651408; RV64-NEXT: addi a2, a2, 8191409; RV64-NEXT: addi a3, a3, -2411410; RV64-NEXT: addi a4, a4, 2571411; RV64-NEXT: slli a5, a1, 321412; RV64-NEXT: add a1, a1, a51413; RV64-NEXT: slli a5, a2, 321414; RV64-NEXT: add a2, a2, a51415; RV64-NEXT: slli a5, a3, 321416; RV64-NEXT: add a3, a3, a51417; RV64-NEXT: slli a5, a4, 321418; RV64-NEXT: add a4, a4, a51419; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1420; RV64-NEXT: vadd.vi v16, v8, -1, v0.t1421; RV64-NEXT: vnot.v v8, v8, v0.t1422; RV64-NEXT: vand.vv v8, v8, v16, v0.t1423; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t1424; RV64-NEXT: vand.vx v16, v16, a1, v0.t1425; RV64-NEXT: vsub.vv v8, v8, v16, v0.t1426; RV64-NEXT: vand.vx v16, v8, a2, v0.t1427; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1428; RV64-NEXT: vand.vx v8, v8, a2, v0.t1429; RV64-NEXT: vadd.vv v8, v16, v8, v0.t1430; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t1431; RV64-NEXT: vadd.vv v8, v8, v16, v0.t1432; RV64-NEXT: vand.vx v8, v8, a3, v0.t1433; RV64-NEXT: li a0, 561434; RV64-NEXT: vmul.vx v8, v8, a4, v0.t1435; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1436; RV64-NEXT: ret1437 %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl)1438 ret <16 x i64> %v1439}1440 1441define <16 x i64> @vp_cttz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {1442; RV32-LABEL: vp_cttz_v16i64_unmasked:1443; RV32: # %bb.0:1444; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1445; RV32-NEXT: vadd.vi v16, v8, -11446; RV32-NEXT: vnot.v v8, v81447; RV32-NEXT: lui a1, 3495251448; RV32-NEXT: addi a1, a1, 13651449; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1450; RV32-NEXT: vmv.v.x v24, a11451; RV32-NEXT: lui a1, 2097151452; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1453; RV32-NEXT: vand.vv v8, v8, v161454; RV32-NEXT: addi a1, a1, 8191455; RV32-NEXT: vsrl.vi v16, v8, 11456; RV32-NEXT: vand.vv v24, v16, v241457; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1458; RV32-NEXT: vmv.v.x v16, a11459; RV32-NEXT: lui a1, 616811460; RV32-NEXT: addi a1, a1, -2411461; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1462; RV32-NEXT: vsub.vv v8, v8, v241463; RV32-NEXT: vand.vv v24, v8, v161464; RV32-NEXT: vsrl.vi v8, v8, 21465; RV32-NEXT: vand.vv v8, v8, v161466; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1467; RV32-NEXT: vmv.v.x v16, a11468; RV32-NEXT: lui a1, 41121469; RV32-NEXT: addi a1, a1, 2571470; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1471; RV32-NEXT: vadd.vv v8, v24, v81472; RV32-NEXT: vsrl.vi v24, v8, 41473; RV32-NEXT: vadd.vv v8, v8, v241474; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1475; RV32-NEXT: vmv.v.x v24, a11476; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1477; RV32-NEXT: vand.vv v8, v8, v161478; RV32-NEXT: vmul.vv v8, v8, v241479; RV32-NEXT: li a0, 561480; RV32-NEXT: vsrl.vx v8, v8, a01481; RV32-NEXT: ret1482;1483; RV64-LABEL: vp_cttz_v16i64_unmasked:1484; RV64: # %bb.0:1485; RV64-NEXT: lui a1, 3495251486; RV64-NEXT: lui a2, 2097151487; RV64-NEXT: lui a3, 616811488; RV64-NEXT: lui a4, 41121489; RV64-NEXT: addi a1, a1, 13651490; RV64-NEXT: addi a2, a2, 8191491; RV64-NEXT: addi a3, a3, -2411492; RV64-NEXT: addi a4, a4, 2571493; RV64-NEXT: slli a5, a1, 321494; RV64-NEXT: add a1, a1, a51495; RV64-NEXT: slli a5, a2, 321496; RV64-NEXT: add a2, a2, a51497; RV64-NEXT: slli a5, a3, 321498; RV64-NEXT: add a3, a3, a51499; RV64-NEXT: slli a5, a4, 321500; RV64-NEXT: add a4, a4, a51501; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1502; RV64-NEXT: vadd.vi v16, v8, -11503; RV64-NEXT: vnot.v v8, v81504; RV64-NEXT: vand.vv v8, v8, v161505; RV64-NEXT: vsrl.vi v16, v8, 11506; RV64-NEXT: vand.vx v16, v16, a11507; RV64-NEXT: vsub.vv v8, v8, v161508; RV64-NEXT: vand.vx v16, v8, a21509; RV64-NEXT: vsrl.vi v8, v8, 21510; RV64-NEXT: vand.vx v8, v8, a21511; RV64-NEXT: vadd.vv v8, v16, v81512; RV64-NEXT: vsrl.vi v16, v8, 41513; RV64-NEXT: vadd.vv v8, v8, v161514; RV64-NEXT: vand.vx v8, v8, a31515; RV64-NEXT: vmul.vx v8, v8, a41516; RV64-NEXT: li a0, 561517; RV64-NEXT: vsrl.vx v8, v8, a01518; RV64-NEXT: ret1519 %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl)1520 ret <16 x i64> %v1521}1522 1523define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {1524; RV32-LABEL: vp_cttz_v32i64:1525; RV32: # %bb.0:1526; RV32-NEXT: addi sp, sp, -161527; RV32-NEXT: .cfi_def_cfa_offset 161528; RV32-NEXT: csrr a1, vlenb1529; RV32-NEXT: li a2, 481530; RV32-NEXT: mul a1, a1, a21531; RV32-NEXT: sub sp, sp, a11532; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb1533; RV32-NEXT: csrr a1, vlenb1534; RV32-NEXT: li a2, 401535; RV32-NEXT: mul a1, a1, a21536; RV32-NEXT: add a1, sp, a11537; RV32-NEXT: addi a1, a1, 161538; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1539; RV32-NEXT: li a2, 161540; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1541; RV32-NEXT: vslidedown.vi v7, v0, 21542; RV32-NEXT: mv a1, a01543; RV32-NEXT: bltu a0, a2, .LBB34_21544; RV32-NEXT: # %bb.1:1545; RV32-NEXT: li a1, 161546; RV32-NEXT: .LBB34_2:1547; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1548; RV32-NEXT: vadd.vi v16, v8, -1, v0.t1549; RV32-NEXT: lui a2, 3495251550; RV32-NEXT: vnot.v v8, v8, v0.t1551; RV32-NEXT: addi a2, a2, 13651552; RV32-NEXT: vand.vv v8, v8, v16, v0.t1553; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1554; RV32-NEXT: vmv.v.x v24, a21555; RV32-NEXT: csrr a2, vlenb1556; RV32-NEXT: slli a2, a2, 51557; RV32-NEXT: add a2, sp, a21558; RV32-NEXT: addi a2, a2, 161559; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill1560; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1561; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t1562; RV32-NEXT: vand.vv v16, v16, v24, v0.t1563; RV32-NEXT: vsub.vv v8, v8, v16, v0.t1564; RV32-NEXT: lui a2, 2097151565; RV32-NEXT: addi a2, a2, 8191566; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1567; RV32-NEXT: vmv.v.x v16, a21568; RV32-NEXT: csrr a2, vlenb1569; RV32-NEXT: slli a2, a2, 41570; RV32-NEXT: add a2, sp, a21571; RV32-NEXT: addi a2, a2, 161572; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill1573; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1574; RV32-NEXT: vand.vv v24, v8, v16, v0.t1575; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t1576; RV32-NEXT: vand.vv v8, v8, v16, v0.t1577; RV32-NEXT: vadd.vv v8, v24, v8, v0.t1578; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t1579; RV32-NEXT: vadd.vv v8, v8, v24, v0.t1580; RV32-NEXT: lui a2, 616811581; RV32-NEXT: addi a2, a2, -2411582; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1583; RV32-NEXT: vmv.v.x v16, a21584; RV32-NEXT: csrr a2, vlenb1585; RV32-NEXT: li a3, 241586; RV32-NEXT: mul a2, a2, a31587; RV32-NEXT: add a2, sp, a21588; RV32-NEXT: addi a2, a2, 161589; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill1590; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1591; RV32-NEXT: vand.vv v8, v8, v16, v0.t1592; RV32-NEXT: lui a2, 41121593; RV32-NEXT: addi a2, a2, 2571594; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1595; RV32-NEXT: vmv.v.x v16, a21596; RV32-NEXT: addi a2, sp, 161597; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill1598; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1599; RV32-NEXT: vmul.vv v8, v8, v16, v0.t1600; RV32-NEXT: li a1, 561601; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t1602; RV32-NEXT: csrr a2, vlenb1603; RV32-NEXT: slli a2, a2, 31604; RV32-NEXT: add a2, sp, a21605; RV32-NEXT: addi a2, a2, 161606; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1607; RV32-NEXT: addi a2, a0, -161608; RV32-NEXT: sltu a0, a0, a21609; RV32-NEXT: addi a0, a0, -11610; RV32-NEXT: and a0, a0, a21611; RV32-NEXT: vmv1r.v v0, v71612; RV32-NEXT: csrr a2, vlenb1613; RV32-NEXT: li a3, 401614; RV32-NEXT: mul a2, a2, a31615; RV32-NEXT: add a2, sp, a21616; RV32-NEXT: addi a2, a2, 161617; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload1618; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1619; RV32-NEXT: vadd.vi v24, v8, -1, v0.t1620; RV32-NEXT: vnot.v v8, v8, v0.t1621; RV32-NEXT: vand.vv v8, v8, v24, v0.t1622; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t1623; RV32-NEXT: csrr a0, vlenb1624; RV32-NEXT: slli a0, a0, 51625; RV32-NEXT: add a0, sp, a01626; RV32-NEXT: addi a0, a0, 161627; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1628; RV32-NEXT: vand.vv v24, v24, v16, v0.t1629; RV32-NEXT: vsub.vv v8, v8, v24, v0.t1630; RV32-NEXT: csrr a0, vlenb1631; RV32-NEXT: slli a0, a0, 41632; RV32-NEXT: add a0, sp, a01633; RV32-NEXT: addi a0, a0, 161634; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1635; RV32-NEXT: vand.vv v24, v8, v16, v0.t1636; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t1637; RV32-NEXT: vand.vv v8, v8, v16, v0.t1638; RV32-NEXT: vadd.vv v8, v24, v8, v0.t1639; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t1640; RV32-NEXT: vadd.vv v8, v8, v16, v0.t1641; RV32-NEXT: csrr a0, vlenb1642; RV32-NEXT: li a2, 241643; RV32-NEXT: mul a0, a0, a21644; RV32-NEXT: add a0, sp, a01645; RV32-NEXT: addi a0, a0, 161646; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1647; RV32-NEXT: vand.vv v8, v8, v16, v0.t1648; RV32-NEXT: addi a0, sp, 161649; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1650; RV32-NEXT: vmul.vv v8, v8, v16, v0.t1651; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t1652; RV32-NEXT: csrr a0, vlenb1653; RV32-NEXT: slli a0, a0, 31654; RV32-NEXT: add a0, sp, a01655; RV32-NEXT: addi a0, a0, 161656; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1657; RV32-NEXT: csrr a0, vlenb1658; RV32-NEXT: li a1, 481659; RV32-NEXT: mul a0, a0, a11660; RV32-NEXT: add sp, sp, a01661; RV32-NEXT: .cfi_def_cfa sp, 161662; RV32-NEXT: addi sp, sp, 161663; RV32-NEXT: .cfi_def_cfa_offset 01664; RV32-NEXT: ret1665;1666; RV64-LABEL: vp_cttz_v32i64:1667; RV64: # %bb.0:1668; RV64-NEXT: li a2, 161669; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1670; RV64-NEXT: vslidedown.vi v7, v0, 21671; RV64-NEXT: mv a1, a01672; RV64-NEXT: bltu a0, a2, .LBB34_21673; RV64-NEXT: # %bb.1:1674; RV64-NEXT: li a1, 161675; RV64-NEXT: .LBB34_2:1676; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1677; RV64-NEXT: vadd.vi v24, v8, -1, v0.t1678; RV64-NEXT: lui a1, 3495251679; RV64-NEXT: lui a2, 2097151680; RV64-NEXT: lui a3, 616811681; RV64-NEXT: lui a4, 41121682; RV64-NEXT: addi a1, a1, 13651683; RV64-NEXT: addi a2, a2, 8191684; RV64-NEXT: addi a5, a3, -2411685; RV64-NEXT: addi a4, a4, 2571686; RV64-NEXT: slli a3, a1, 321687; RV64-NEXT: add a6, a1, a31688; RV64-NEXT: slli a3, a2, 321689; RV64-NEXT: add a3, a2, a31690; RV64-NEXT: slli a1, a5, 321691; RV64-NEXT: add a1, a5, a11692; RV64-NEXT: slli a2, a4, 321693; RV64-NEXT: add a2, a4, a21694; RV64-NEXT: addi a4, a0, -161695; RV64-NEXT: sltu a0, a0, a41696; RV64-NEXT: addi a0, a0, -11697; RV64-NEXT: and a4, a0, a41698; RV64-NEXT: li a0, 561699; RV64-NEXT: vnot.v v8, v8, v0.t1700; RV64-NEXT: vand.vv v8, v8, v24, v0.t1701; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t1702; RV64-NEXT: vand.vx v24, v24, a6, v0.t1703; RV64-NEXT: vsub.vv v8, v8, v24, v0.t1704; RV64-NEXT: vand.vx v24, v8, a3, v0.t1705; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t1706; RV64-NEXT: vand.vx v8, v8, a3, v0.t1707; RV64-NEXT: vadd.vv v8, v24, v8, v0.t1708; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t1709; RV64-NEXT: vadd.vv v8, v8, v24, v0.t1710; RV64-NEXT: vand.vx v8, v8, a1, v0.t1711; RV64-NEXT: vmul.vx v8, v8, a2, v0.t1712; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t1713; RV64-NEXT: vmv1r.v v0, v71714; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma1715; RV64-NEXT: vadd.vi v24, v16, -1, v0.t1716; RV64-NEXT: vnot.v v16, v16, v0.t1717; RV64-NEXT: vand.vv v16, v16, v24, v0.t1718; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t1719; RV64-NEXT: vand.vx v24, v24, a6, v0.t1720; RV64-NEXT: vsub.vv v16, v16, v24, v0.t1721; RV64-NEXT: vand.vx v24, v16, a3, v0.t1722; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t1723; RV64-NEXT: vand.vx v16, v16, a3, v0.t1724; RV64-NEXT: vadd.vv v16, v24, v16, v0.t1725; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t1726; RV64-NEXT: vadd.vv v16, v16, v24, v0.t1727; RV64-NEXT: vand.vx v16, v16, a1, v0.t1728; RV64-NEXT: vmul.vx v16, v16, a2, v0.t1729; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t1730; RV64-NEXT: ret1731 %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)1732 ret <32 x i64> %v1733}1734 1735define <32 x i64> @vp_cttz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {1736; RV32-LABEL: vp_cttz_v32i64_unmasked:1737; RV32: # %bb.0:1738; RV32-NEXT: li a2, 161739; RV32-NEXT: mv a1, a01740; RV32-NEXT: bltu a0, a2, .LBB35_21741; RV32-NEXT: # %bb.1:1742; RV32-NEXT: li a1, 161743; RV32-NEXT: .LBB35_2:1744; RV32-NEXT: addi sp, sp, -161745; RV32-NEXT: .cfi_def_cfa_offset 161746; RV32-NEXT: csrr a2, vlenb1747; RV32-NEXT: slli a2, a2, 41748; RV32-NEXT: sub sp, sp, a21749; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb1750; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1751; RV32-NEXT: vadd.vi v24, v8, -11752; RV32-NEXT: vnot.v v0, v81753; RV32-NEXT: lui a2, 3495251754; RV32-NEXT: addi a2, a2, 13651755; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1756; RV32-NEXT: vmv.v.x v8, a21757; RV32-NEXT: csrr a2, vlenb1758; RV32-NEXT: slli a2, a2, 31759; RV32-NEXT: add a2, sp, a21760; RV32-NEXT: addi a2, a2, 161761; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1762; RV32-NEXT: addi a2, a0, -161763; RV32-NEXT: sltu a0, a0, a21764; RV32-NEXT: addi a0, a0, -11765; RV32-NEXT: and a0, a0, a21766; RV32-NEXT: lui a2, 2097151767; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1768; RV32-NEXT: vand.vv v24, v0, v241769; RV32-NEXT: addi a2, a2, 8191770; RV32-NEXT: vsrl.vi v0, v24, 11771; RV32-NEXT: vand.vv v0, v0, v81772; RV32-NEXT: vsub.vv v24, v24, v01773; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1774; RV32-NEXT: vadd.vi v0, v16, -11775; RV32-NEXT: vnot.v v16, v161776; RV32-NEXT: vand.vv v0, v16, v01777; RV32-NEXT: addi a3, sp, 161778; RV32-NEXT: vs8r.v v0, (a3) # vscale x 64-byte Folded Spill1779; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1780; RV32-NEXT: vmv.v.x v16, a21781; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1782; RV32-NEXT: vand.vv v8, v24, v161783; RV32-NEXT: vsrl.vi v24, v24, 21784; RV32-NEXT: vand.vv v24, v24, v161785; RV32-NEXT: vadd.vv v8, v8, v241786; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1787; RV32-NEXT: vsrl.vi v24, v0, 11788; RV32-NEXT: csrr a2, vlenb1789; RV32-NEXT: slli a2, a2, 31790; RV32-NEXT: add a2, sp, a21791; RV32-NEXT: addi a2, a2, 161792; RV32-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload1793; RV32-NEXT: vand.vv v24, v24, v01794; RV32-NEXT: addi a2, sp, 161795; RV32-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload1796; RV32-NEXT: vsub.vv v24, v0, v241797; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1798; RV32-NEXT: vsrl.vi v0, v8, 41799; RV32-NEXT: vadd.vv v8, v8, v01800; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1801; RV32-NEXT: vand.vv v0, v24, v161802; RV32-NEXT: vsrl.vi v24, v24, 21803; RV32-NEXT: vand.vv v16, v24, v161804; RV32-NEXT: lui a2, 616811805; RV32-NEXT: addi a2, a2, -2411806; RV32-NEXT: vadd.vv v16, v0, v161807; RV32-NEXT: vsrl.vi v24, v16, 41808; RV32-NEXT: vadd.vv v16, v16, v241809; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1810; RV32-NEXT: vmv.v.x v24, a21811; RV32-NEXT: lui a2, 41121812; RV32-NEXT: addi a2, a2, 2571813; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1814; RV32-NEXT: vand.vv v8, v8, v241815; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1816; RV32-NEXT: vand.vv v16, v16, v241817; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1818; RV32-NEXT: vmv.v.x v24, a21819; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1820; RV32-NEXT: vmul.vv v8, v8, v241821; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1822; RV32-NEXT: vmul.vv v16, v16, v241823; RV32-NEXT: li a2, 561824; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1825; RV32-NEXT: vsrl.vx v8, v8, a21826; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1827; RV32-NEXT: vsrl.vx v16, v16, a21828; RV32-NEXT: csrr a0, vlenb1829; RV32-NEXT: slli a0, a0, 41830; RV32-NEXT: add sp, sp, a01831; RV32-NEXT: .cfi_def_cfa sp, 161832; RV32-NEXT: addi sp, sp, 161833; RV32-NEXT: .cfi_def_cfa_offset 01834; RV32-NEXT: ret1835;1836; RV64-LABEL: vp_cttz_v32i64_unmasked:1837; RV64: # %bb.0:1838; RV64-NEXT: li a2, 161839; RV64-NEXT: mv a1, a01840; RV64-NEXT: bltu a0, a2, .LBB35_21841; RV64-NEXT: # %bb.1:1842; RV64-NEXT: li a1, 161843; RV64-NEXT: .LBB35_2:1844; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1845; RV64-NEXT: vadd.vi v24, v8, -11846; RV64-NEXT: vnot.v v8, v81847; RV64-NEXT: lui a2, 3495251848; RV64-NEXT: lui a3, 2097151849; RV64-NEXT: lui a4, 616811850; RV64-NEXT: lui a5, 41121851; RV64-NEXT: addi a2, a2, 13651852; RV64-NEXT: addi a3, a3, 8191853; RV64-NEXT: addi a4, a4, -2411854; RV64-NEXT: addi a5, a5, 2571855; RV64-NEXT: slli a6, a2, 321856; RV64-NEXT: add a2, a2, a61857; RV64-NEXT: slli a6, a3, 321858; RV64-NEXT: add a3, a3, a61859; RV64-NEXT: slli a6, a4, 321860; RV64-NEXT: add a4, a4, a61861; RV64-NEXT: slli a6, a5, 321862; RV64-NEXT: add a5, a5, a61863; RV64-NEXT: addi a6, a0, -161864; RV64-NEXT: sltu a0, a0, a61865; RV64-NEXT: addi a0, a0, -11866; RV64-NEXT: and a0, a0, a61867; RV64-NEXT: li a6, 561868; RV64-NEXT: vand.vv v8, v8, v241869; RV64-NEXT: vsrl.vi v24, v8, 11870; RV64-NEXT: vand.vx v24, v24, a21871; RV64-NEXT: vsub.vv v8, v8, v241872; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1873; RV64-NEXT: vadd.vi v24, v16, -11874; RV64-NEXT: vnot.v v16, v161875; RV64-NEXT: vand.vv v16, v16, v241876; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1877; RV64-NEXT: vand.vx v24, v8, a31878; RV64-NEXT: vsrl.vi v8, v8, 21879; RV64-NEXT: vand.vx v8, v8, a31880; RV64-NEXT: vadd.vv v8, v24, v81881; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1882; RV64-NEXT: vsrl.vi v24, v16, 11883; RV64-NEXT: vand.vx v24, v24, a21884; RV64-NEXT: vsub.vv v16, v16, v241885; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1886; RV64-NEXT: vsrl.vi v24, v8, 41887; RV64-NEXT: vadd.vv v8, v8, v241888; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1889; RV64-NEXT: vand.vx v24, v16, a31890; RV64-NEXT: vsrl.vi v16, v16, 21891; RV64-NEXT: vand.vx v16, v16, a31892; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1893; RV64-NEXT: vand.vx v8, v8, a41894; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1895; RV64-NEXT: vadd.vv v16, v24, v161896; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1897; RV64-NEXT: vmul.vx v8, v8, a51898; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1899; RV64-NEXT: vsrl.vi v24, v16, 41900; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1901; RV64-NEXT: vsrl.vx v8, v8, a61902; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1903; RV64-NEXT: vadd.vv v16, v16, v241904; RV64-NEXT: vand.vx v16, v16, a41905; RV64-NEXT: vmul.vx v16, v16, a51906; RV64-NEXT: vsrl.vx v16, v16, a61907; RV64-NEXT: ret1908 %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 false, <32 x i1> splat (i1 true), i32 %evl)1909 ret <32 x i64> %v1910}1911 1912define <2 x i8> @vp_cttz_zero_undef_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {1913; CHECK-LABEL: vp_cttz_zero_undef_v2i8:1914; CHECK: # %bb.0:1915; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma1916; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t1917; CHECK-NEXT: li a0, 851918; CHECK-NEXT: vnot.v v8, v8, v0.t1919; CHECK-NEXT: vand.vv v8, v8, v9, v0.t1920; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t1921; CHECK-NEXT: vand.vx v9, v9, a0, v0.t1922; CHECK-NEXT: li a0, 511923; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t1924; CHECK-NEXT: vand.vx v9, v8, a0, v0.t1925; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t1926; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1927; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t1928; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t1929; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t1930; CHECK-NEXT: vand.vi v8, v8, 15, v0.t1931; CHECK-NEXT: ret1932 %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, i1 true, <2 x i1> %m, i32 %evl)1933 ret <2 x i8> %v1934}1935 1936define <2 x i8> @vp_cttz_zero_undef_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {1937; CHECK-LABEL: vp_cttz_zero_undef_v2i8_unmasked:1938; CHECK: # %bb.0:1939; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma1940; CHECK-NEXT: vadd.vi v9, v8, -11941; CHECK-NEXT: vnot.v v8, v81942; CHECK-NEXT: li a0, 851943; CHECK-NEXT: vand.vv v8, v8, v91944; CHECK-NEXT: vsrl.vi v9, v8, 11945; CHECK-NEXT: vand.vx v9, v9, a01946; CHECK-NEXT: li a0, 511947; CHECK-NEXT: vsub.vv v8, v8, v91948; CHECK-NEXT: vand.vx v9, v8, a01949; CHECK-NEXT: vsrl.vi v8, v8, 21950; CHECK-NEXT: vand.vx v8, v8, a01951; CHECK-NEXT: vadd.vv v8, v9, v81952; CHECK-NEXT: vsrl.vi v9, v8, 41953; CHECK-NEXT: vadd.vv v8, v8, v91954; CHECK-NEXT: vand.vi v8, v8, 151955; CHECK-NEXT: ret1956 %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl)1957 ret <2 x i8> %v1958}1959 1960define <4 x i8> @vp_cttz_zero_undef_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {1961; CHECK-LABEL: vp_cttz_zero_undef_v4i8:1962; CHECK: # %bb.0:1963; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma1964; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t1965; CHECK-NEXT: li a0, 851966; CHECK-NEXT: vnot.v v8, v8, v0.t1967; CHECK-NEXT: vand.vv v8, v8, v9, v0.t1968; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t1969; CHECK-NEXT: vand.vx v9, v9, a0, v0.t1970; CHECK-NEXT: li a0, 511971; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t1972; CHECK-NEXT: vand.vx v9, v8, a0, v0.t1973; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t1974; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1975; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t1976; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t1977; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t1978; CHECK-NEXT: vand.vi v8, v8, 15, v0.t1979; CHECK-NEXT: ret1980 %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, i1 true, <4 x i1> %m, i32 %evl)1981 ret <4 x i8> %v1982}1983 1984define <4 x i8> @vp_cttz_zero_undef_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {1985; CHECK-LABEL: vp_cttz_zero_undef_v4i8_unmasked:1986; CHECK: # %bb.0:1987; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma1988; CHECK-NEXT: vadd.vi v9, v8, -11989; CHECK-NEXT: vnot.v v8, v81990; CHECK-NEXT: li a0, 851991; CHECK-NEXT: vand.vv v8, v8, v91992; CHECK-NEXT: vsrl.vi v9, v8, 11993; CHECK-NEXT: vand.vx v9, v9, a01994; CHECK-NEXT: li a0, 511995; CHECK-NEXT: vsub.vv v8, v8, v91996; CHECK-NEXT: vand.vx v9, v8, a01997; CHECK-NEXT: vsrl.vi v8, v8, 21998; CHECK-NEXT: vand.vx v8, v8, a01999; CHECK-NEXT: vadd.vv v8, v9, v82000; CHECK-NEXT: vsrl.vi v9, v8, 42001; CHECK-NEXT: vadd.vv v8, v8, v92002; CHECK-NEXT: vand.vi v8, v8, 152003; CHECK-NEXT: ret2004 %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl)2005 ret <4 x i8> %v2006}2007 2008define <8 x i8> @vp_cttz_zero_undef_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {2009; CHECK-LABEL: vp_cttz_zero_undef_v8i8:2010; CHECK: # %bb.0:2011; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma2012; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t2013; CHECK-NEXT: li a0, 852014; CHECK-NEXT: vnot.v v8, v8, v0.t2015; CHECK-NEXT: vand.vv v8, v8, v9, v0.t2016; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2017; CHECK-NEXT: vand.vx v9, v9, a0, v0.t2018; CHECK-NEXT: li a0, 512019; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t2020; CHECK-NEXT: vand.vx v9, v8, a0, v0.t2021; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2022; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2023; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t2024; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2025; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t2026; CHECK-NEXT: vand.vi v8, v8, 15, v0.t2027; CHECK-NEXT: ret2028 %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, i1 true, <8 x i1> %m, i32 %evl)2029 ret <8 x i8> %v2030}2031 2032define <8 x i8> @vp_cttz_zero_undef_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {2033; CHECK-LABEL: vp_cttz_zero_undef_v8i8_unmasked:2034; CHECK: # %bb.0:2035; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma2036; CHECK-NEXT: vadd.vi v9, v8, -12037; CHECK-NEXT: vnot.v v8, v82038; CHECK-NEXT: li a0, 852039; CHECK-NEXT: vand.vv v8, v8, v92040; CHECK-NEXT: vsrl.vi v9, v8, 12041; CHECK-NEXT: vand.vx v9, v9, a02042; CHECK-NEXT: li a0, 512043; CHECK-NEXT: vsub.vv v8, v8, v92044; CHECK-NEXT: vand.vx v9, v8, a02045; CHECK-NEXT: vsrl.vi v8, v8, 22046; CHECK-NEXT: vand.vx v8, v8, a02047; CHECK-NEXT: vadd.vv v8, v9, v82048; CHECK-NEXT: vsrl.vi v9, v8, 42049; CHECK-NEXT: vadd.vv v8, v8, v92050; CHECK-NEXT: vand.vi v8, v8, 152051; CHECK-NEXT: ret2052 %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl)2053 ret <8 x i8> %v2054}2055 2056define <16 x i8> @vp_cttz_zero_undef_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {2057; CHECK-LABEL: vp_cttz_zero_undef_v16i8:2058; CHECK: # %bb.0:2059; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma2060; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t2061; CHECK-NEXT: li a0, 852062; CHECK-NEXT: vnot.v v8, v8, v0.t2063; CHECK-NEXT: vand.vv v8, v8, v9, v0.t2064; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2065; CHECK-NEXT: vand.vx v9, v9, a0, v0.t2066; CHECK-NEXT: li a0, 512067; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t2068; CHECK-NEXT: vand.vx v9, v8, a0, v0.t2069; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2070; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2071; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t2072; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2073; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t2074; CHECK-NEXT: vand.vi v8, v8, 15, v0.t2075; CHECK-NEXT: ret2076 %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, i1 true, <16 x i1> %m, i32 %evl)2077 ret <16 x i8> %v2078}2079 2080define <16 x i8> @vp_cttz_zero_undef_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {2081; CHECK-LABEL: vp_cttz_zero_undef_v16i8_unmasked:2082; CHECK: # %bb.0:2083; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma2084; CHECK-NEXT: vadd.vi v9, v8, -12085; CHECK-NEXT: vnot.v v8, v82086; CHECK-NEXT: li a0, 852087; CHECK-NEXT: vand.vv v8, v8, v92088; CHECK-NEXT: vsrl.vi v9, v8, 12089; CHECK-NEXT: vand.vx v9, v9, a02090; CHECK-NEXT: li a0, 512091; CHECK-NEXT: vsub.vv v8, v8, v92092; CHECK-NEXT: vand.vx v9, v8, a02093; CHECK-NEXT: vsrl.vi v8, v8, 22094; CHECK-NEXT: vand.vx v8, v8, a02095; CHECK-NEXT: vadd.vv v8, v9, v82096; CHECK-NEXT: vsrl.vi v9, v8, 42097; CHECK-NEXT: vadd.vv v8, v8, v92098; CHECK-NEXT: vand.vi v8, v8, 152099; CHECK-NEXT: ret2100 %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl)2101 ret <16 x i8> %v2102}2103 2104define <2 x i16> @vp_cttz_zero_undef_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {2105; CHECK-LABEL: vp_cttz_zero_undef_v2i16:2106; CHECK: # %bb.0:2107; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma2108; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t2109; CHECK-NEXT: lui a0, 52110; CHECK-NEXT: vnot.v v8, v8, v0.t2111; CHECK-NEXT: addi a0, a0, 13652112; CHECK-NEXT: vand.vv v8, v8, v9, v0.t2113; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2114; CHECK-NEXT: vand.vx v9, v9, a0, v0.t2115; CHECK-NEXT: lui a0, 32116; CHECK-NEXT: addi a0, a0, 8192117; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t2118; CHECK-NEXT: vand.vx v9, v8, a0, v0.t2119; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2120; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2121; CHECK-NEXT: lui a0, 12122; CHECK-NEXT: addi a0, a0, -2412123; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t2124; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2125; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t2126; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2127; CHECK-NEXT: li a0, 2572128; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t2129; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t2130; CHECK-NEXT: ret2131 %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, i1 true, <2 x i1> %m, i32 %evl)2132 ret <2 x i16> %v2133}2134 2135define <2 x i16> @vp_cttz_zero_undef_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {2136; CHECK-LABEL: vp_cttz_zero_undef_v2i16_unmasked:2137; CHECK: # %bb.0:2138; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma2139; CHECK-NEXT: vadd.vi v9, v8, -12140; CHECK-NEXT: vnot.v v8, v82141; CHECK-NEXT: lui a0, 52142; CHECK-NEXT: vand.vv v8, v8, v92143; CHECK-NEXT: addi a0, a0, 13652144; CHECK-NEXT: vsrl.vi v9, v8, 12145; CHECK-NEXT: vand.vx v9, v9, a02146; CHECK-NEXT: lui a0, 32147; CHECK-NEXT: addi a0, a0, 8192148; CHECK-NEXT: vsub.vv v8, v8, v92149; CHECK-NEXT: vand.vx v9, v8, a02150; CHECK-NEXT: vsrl.vi v8, v8, 22151; CHECK-NEXT: vand.vx v8, v8, a02152; CHECK-NEXT: lui a0, 12153; CHECK-NEXT: addi a0, a0, -2412154; CHECK-NEXT: vadd.vv v8, v9, v82155; CHECK-NEXT: vsrl.vi v9, v8, 42156; CHECK-NEXT: vadd.vv v8, v8, v92157; CHECK-NEXT: vand.vx v8, v8, a02158; CHECK-NEXT: li a0, 2572159; CHECK-NEXT: vmul.vx v8, v8, a02160; CHECK-NEXT: vsrl.vi v8, v8, 82161; CHECK-NEXT: ret2162 %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl)2163 ret <2 x i16> %v2164}2165 2166define <4 x i16> @vp_cttz_zero_undef_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {2167; CHECK-LABEL: vp_cttz_zero_undef_v4i16:2168; CHECK: # %bb.0:2169; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma2170; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t2171; CHECK-NEXT: lui a0, 52172; CHECK-NEXT: vnot.v v8, v8, v0.t2173; CHECK-NEXT: addi a0, a0, 13652174; CHECK-NEXT: vand.vv v8, v8, v9, v0.t2175; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2176; CHECK-NEXT: vand.vx v9, v9, a0, v0.t2177; CHECK-NEXT: lui a0, 32178; CHECK-NEXT: addi a0, a0, 8192179; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t2180; CHECK-NEXT: vand.vx v9, v8, a0, v0.t2181; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2182; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2183; CHECK-NEXT: lui a0, 12184; CHECK-NEXT: addi a0, a0, -2412185; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t2186; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2187; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t2188; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2189; CHECK-NEXT: li a0, 2572190; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t2191; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t2192; CHECK-NEXT: ret2193 %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, i1 true, <4 x i1> %m, i32 %evl)2194 ret <4 x i16> %v2195}2196 2197define <4 x i16> @vp_cttz_zero_undef_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {2198; CHECK-LABEL: vp_cttz_zero_undef_v4i16_unmasked:2199; CHECK: # %bb.0:2200; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma2201; CHECK-NEXT: vadd.vi v9, v8, -12202; CHECK-NEXT: vnot.v v8, v82203; CHECK-NEXT: lui a0, 52204; CHECK-NEXT: vand.vv v8, v8, v92205; CHECK-NEXT: addi a0, a0, 13652206; CHECK-NEXT: vsrl.vi v9, v8, 12207; CHECK-NEXT: vand.vx v9, v9, a02208; CHECK-NEXT: lui a0, 32209; CHECK-NEXT: addi a0, a0, 8192210; CHECK-NEXT: vsub.vv v8, v8, v92211; CHECK-NEXT: vand.vx v9, v8, a02212; CHECK-NEXT: vsrl.vi v8, v8, 22213; CHECK-NEXT: vand.vx v8, v8, a02214; CHECK-NEXT: lui a0, 12215; CHECK-NEXT: addi a0, a0, -2412216; CHECK-NEXT: vadd.vv v8, v9, v82217; CHECK-NEXT: vsrl.vi v9, v8, 42218; CHECK-NEXT: vadd.vv v8, v8, v92219; CHECK-NEXT: vand.vx v8, v8, a02220; CHECK-NEXT: li a0, 2572221; CHECK-NEXT: vmul.vx v8, v8, a02222; CHECK-NEXT: vsrl.vi v8, v8, 82223; CHECK-NEXT: ret2224 %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl)2225 ret <4 x i16> %v2226}2227 2228define <8 x i16> @vp_cttz_zero_undef_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {2229; CHECK-LABEL: vp_cttz_zero_undef_v8i16:2230; CHECK: # %bb.0:2231; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma2232; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t2233; CHECK-NEXT: lui a0, 52234; CHECK-NEXT: vnot.v v8, v8, v0.t2235; CHECK-NEXT: addi a0, a0, 13652236; CHECK-NEXT: vand.vv v8, v8, v9, v0.t2237; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2238; CHECK-NEXT: vand.vx v9, v9, a0, v0.t2239; CHECK-NEXT: lui a0, 32240; CHECK-NEXT: addi a0, a0, 8192241; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t2242; CHECK-NEXT: vand.vx v9, v8, a0, v0.t2243; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2244; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2245; CHECK-NEXT: lui a0, 12246; CHECK-NEXT: addi a0, a0, -2412247; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t2248; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2249; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t2250; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2251; CHECK-NEXT: li a0, 2572252; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t2253; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t2254; CHECK-NEXT: ret2255 %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, i1 true, <8 x i1> %m, i32 %evl)2256 ret <8 x i16> %v2257}2258 2259define <8 x i16> @vp_cttz_zero_undef_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {2260; CHECK-LABEL: vp_cttz_zero_undef_v8i16_unmasked:2261; CHECK: # %bb.0:2262; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma2263; CHECK-NEXT: vadd.vi v9, v8, -12264; CHECK-NEXT: vnot.v v8, v82265; CHECK-NEXT: lui a0, 52266; CHECK-NEXT: vand.vv v8, v8, v92267; CHECK-NEXT: addi a0, a0, 13652268; CHECK-NEXT: vsrl.vi v9, v8, 12269; CHECK-NEXT: vand.vx v9, v9, a02270; CHECK-NEXT: lui a0, 32271; CHECK-NEXT: addi a0, a0, 8192272; CHECK-NEXT: vsub.vv v8, v8, v92273; CHECK-NEXT: vand.vx v9, v8, a02274; CHECK-NEXT: vsrl.vi v8, v8, 22275; CHECK-NEXT: vand.vx v8, v8, a02276; CHECK-NEXT: lui a0, 12277; CHECK-NEXT: addi a0, a0, -2412278; CHECK-NEXT: vadd.vv v8, v9, v82279; CHECK-NEXT: vsrl.vi v9, v8, 42280; CHECK-NEXT: vadd.vv v8, v8, v92281; CHECK-NEXT: vand.vx v8, v8, a02282; CHECK-NEXT: li a0, 2572283; CHECK-NEXT: vmul.vx v8, v8, a02284; CHECK-NEXT: vsrl.vi v8, v8, 82285; CHECK-NEXT: ret2286 %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl)2287 ret <8 x i16> %v2288}2289 2290define <16 x i16> @vp_cttz_zero_undef_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {2291; CHECK-LABEL: vp_cttz_zero_undef_v16i16:2292; CHECK: # %bb.0:2293; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma2294; CHECK-NEXT: vadd.vi v10, v8, -1, v0.t2295; CHECK-NEXT: lui a0, 52296; CHECK-NEXT: vnot.v v8, v8, v0.t2297; CHECK-NEXT: addi a0, a0, 13652298; CHECK-NEXT: vand.vv v8, v8, v10, v0.t2299; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t2300; CHECK-NEXT: vand.vx v10, v10, a0, v0.t2301; CHECK-NEXT: lui a0, 32302; CHECK-NEXT: addi a0, a0, 8192303; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t2304; CHECK-NEXT: vand.vx v10, v8, a0, v0.t2305; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2306; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2307; CHECK-NEXT: lui a0, 12308; CHECK-NEXT: addi a0, a0, -2412309; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t2310; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t2311; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t2312; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2313; CHECK-NEXT: li a0, 2572314; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t2315; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t2316; CHECK-NEXT: ret2317 %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, i1 true, <16 x i1> %m, i32 %evl)2318 ret <16 x i16> %v2319}2320 2321define <16 x i16> @vp_cttz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {2322; CHECK-LABEL: vp_cttz_zero_undef_v16i16_unmasked:2323; CHECK: # %bb.0:2324; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma2325; CHECK-NEXT: vadd.vi v10, v8, -12326; CHECK-NEXT: vnot.v v8, v82327; CHECK-NEXT: lui a0, 52328; CHECK-NEXT: vand.vv v8, v8, v102329; CHECK-NEXT: addi a0, a0, 13652330; CHECK-NEXT: vsrl.vi v10, v8, 12331; CHECK-NEXT: vand.vx v10, v10, a02332; CHECK-NEXT: lui a0, 32333; CHECK-NEXT: addi a0, a0, 8192334; CHECK-NEXT: vsub.vv v8, v8, v102335; CHECK-NEXT: vand.vx v10, v8, a02336; CHECK-NEXT: vsrl.vi v8, v8, 22337; CHECK-NEXT: vand.vx v8, v8, a02338; CHECK-NEXT: lui a0, 12339; CHECK-NEXT: addi a0, a0, -2412340; CHECK-NEXT: vadd.vv v8, v10, v82341; CHECK-NEXT: vsrl.vi v10, v8, 42342; CHECK-NEXT: vadd.vv v8, v8, v102343; CHECK-NEXT: vand.vx v8, v8, a02344; CHECK-NEXT: li a0, 2572345; CHECK-NEXT: vmul.vx v8, v8, a02346; CHECK-NEXT: vsrl.vi v8, v8, 82347; CHECK-NEXT: ret2348 %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl)2349 ret <16 x i16> %v2350}2351 2352define <2 x i32> @vp_cttz_zero_undef_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {2353; CHECK-LABEL: vp_cttz_zero_undef_v2i32:2354; CHECK: # %bb.0:2355; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma2356; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t2357; CHECK-NEXT: lui a0, 3495252358; CHECK-NEXT: vnot.v v8, v8, v0.t2359; CHECK-NEXT: addi a0, a0, 13652360; CHECK-NEXT: vand.vv v8, v8, v9, v0.t2361; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2362; CHECK-NEXT: vand.vx v9, v9, a0, v0.t2363; CHECK-NEXT: lui a0, 2097152364; CHECK-NEXT: addi a0, a0, 8192365; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t2366; CHECK-NEXT: vand.vx v9, v8, a0, v0.t2367; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2368; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2369; CHECK-NEXT: lui a0, 616812370; CHECK-NEXT: addi a0, a0, -2412371; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t2372; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2373; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t2374; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2375; CHECK-NEXT: lui a0, 41122376; CHECK-NEXT: addi a0, a0, 2572377; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t2378; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t2379; CHECK-NEXT: ret2380 %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, i1 true, <2 x i1> %m, i32 %evl)2381 ret <2 x i32> %v2382}2383 2384define <2 x i32> @vp_cttz_zero_undef_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {2385; CHECK-LABEL: vp_cttz_zero_undef_v2i32_unmasked:2386; CHECK: # %bb.0:2387; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma2388; CHECK-NEXT: vadd.vi v9, v8, -12389; CHECK-NEXT: vnot.v v8, v82390; CHECK-NEXT: lui a0, 3495252391; CHECK-NEXT: vand.vv v8, v8, v92392; CHECK-NEXT: addi a0, a0, 13652393; CHECK-NEXT: vsrl.vi v9, v8, 12394; CHECK-NEXT: vand.vx v9, v9, a02395; CHECK-NEXT: lui a0, 2097152396; CHECK-NEXT: addi a0, a0, 8192397; CHECK-NEXT: vsub.vv v8, v8, v92398; CHECK-NEXT: vand.vx v9, v8, a02399; CHECK-NEXT: vsrl.vi v8, v8, 22400; CHECK-NEXT: vand.vx v8, v8, a02401; CHECK-NEXT: lui a0, 616812402; CHECK-NEXT: addi a0, a0, -2412403; CHECK-NEXT: vadd.vv v8, v9, v82404; CHECK-NEXT: vsrl.vi v9, v8, 42405; CHECK-NEXT: vadd.vv v8, v8, v92406; CHECK-NEXT: vand.vx v8, v8, a02407; CHECK-NEXT: lui a0, 41122408; CHECK-NEXT: addi a0, a0, 2572409; CHECK-NEXT: vmul.vx v8, v8, a02410; CHECK-NEXT: vsrl.vi v8, v8, 242411; CHECK-NEXT: ret2412 %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl)2413 ret <2 x i32> %v2414}2415 2416define <4 x i32> @vp_cttz_zero_undef_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {2417; CHECK-LABEL: vp_cttz_zero_undef_v4i32:2418; CHECK: # %bb.0:2419; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma2420; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t2421; CHECK-NEXT: lui a0, 3495252422; CHECK-NEXT: vnot.v v8, v8, v0.t2423; CHECK-NEXT: addi a0, a0, 13652424; CHECK-NEXT: vand.vv v8, v8, v9, v0.t2425; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t2426; CHECK-NEXT: vand.vx v9, v9, a0, v0.t2427; CHECK-NEXT: lui a0, 2097152428; CHECK-NEXT: addi a0, a0, 8192429; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t2430; CHECK-NEXT: vand.vx v9, v8, a0, v0.t2431; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2432; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2433; CHECK-NEXT: lui a0, 616812434; CHECK-NEXT: addi a0, a0, -2412435; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t2436; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t2437; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t2438; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2439; CHECK-NEXT: lui a0, 41122440; CHECK-NEXT: addi a0, a0, 2572441; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t2442; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t2443; CHECK-NEXT: ret2444 %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, i1 true, <4 x i1> %m, i32 %evl)2445 ret <4 x i32> %v2446}2447 2448define <4 x i32> @vp_cttz_zero_undef_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {2449; CHECK-LABEL: vp_cttz_zero_undef_v4i32_unmasked:2450; CHECK: # %bb.0:2451; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma2452; CHECK-NEXT: vadd.vi v9, v8, -12453; CHECK-NEXT: vnot.v v8, v82454; CHECK-NEXT: lui a0, 3495252455; CHECK-NEXT: vand.vv v8, v8, v92456; CHECK-NEXT: addi a0, a0, 13652457; CHECK-NEXT: vsrl.vi v9, v8, 12458; CHECK-NEXT: vand.vx v9, v9, a02459; CHECK-NEXT: lui a0, 2097152460; CHECK-NEXT: addi a0, a0, 8192461; CHECK-NEXT: vsub.vv v8, v8, v92462; CHECK-NEXT: vand.vx v9, v8, a02463; CHECK-NEXT: vsrl.vi v8, v8, 22464; CHECK-NEXT: vand.vx v8, v8, a02465; CHECK-NEXT: lui a0, 616812466; CHECK-NEXT: addi a0, a0, -2412467; CHECK-NEXT: vadd.vv v8, v9, v82468; CHECK-NEXT: vsrl.vi v9, v8, 42469; CHECK-NEXT: vadd.vv v8, v8, v92470; CHECK-NEXT: vand.vx v8, v8, a02471; CHECK-NEXT: lui a0, 41122472; CHECK-NEXT: addi a0, a0, 2572473; CHECK-NEXT: vmul.vx v8, v8, a02474; CHECK-NEXT: vsrl.vi v8, v8, 242475; CHECK-NEXT: ret2476 %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl)2477 ret <4 x i32> %v2478}2479 2480define <8 x i32> @vp_cttz_zero_undef_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {2481; CHECK-LABEL: vp_cttz_zero_undef_v8i32:2482; CHECK: # %bb.0:2483; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma2484; CHECK-NEXT: vadd.vi v10, v8, -1, v0.t2485; CHECK-NEXT: lui a0, 3495252486; CHECK-NEXT: vnot.v v8, v8, v0.t2487; CHECK-NEXT: addi a0, a0, 13652488; CHECK-NEXT: vand.vv v8, v8, v10, v0.t2489; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t2490; CHECK-NEXT: vand.vx v10, v10, a0, v0.t2491; CHECK-NEXT: lui a0, 2097152492; CHECK-NEXT: addi a0, a0, 8192493; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t2494; CHECK-NEXT: vand.vx v10, v8, a0, v0.t2495; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2496; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2497; CHECK-NEXT: lui a0, 616812498; CHECK-NEXT: addi a0, a0, -2412499; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t2500; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t2501; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t2502; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2503; CHECK-NEXT: lui a0, 41122504; CHECK-NEXT: addi a0, a0, 2572505; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t2506; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t2507; CHECK-NEXT: ret2508 %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, i1 true, <8 x i1> %m, i32 %evl)2509 ret <8 x i32> %v2510}2511 2512define <8 x i32> @vp_cttz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {2513; CHECK-LABEL: vp_cttz_zero_undef_v8i32_unmasked:2514; CHECK: # %bb.0:2515; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma2516; CHECK-NEXT: vadd.vi v10, v8, -12517; CHECK-NEXT: vnot.v v8, v82518; CHECK-NEXT: lui a0, 3495252519; CHECK-NEXT: vand.vv v8, v8, v102520; CHECK-NEXT: addi a0, a0, 13652521; CHECK-NEXT: vsrl.vi v10, v8, 12522; CHECK-NEXT: vand.vx v10, v10, a02523; CHECK-NEXT: lui a0, 2097152524; CHECK-NEXT: addi a0, a0, 8192525; CHECK-NEXT: vsub.vv v8, v8, v102526; CHECK-NEXT: vand.vx v10, v8, a02527; CHECK-NEXT: vsrl.vi v8, v8, 22528; CHECK-NEXT: vand.vx v8, v8, a02529; CHECK-NEXT: lui a0, 616812530; CHECK-NEXT: addi a0, a0, -2412531; CHECK-NEXT: vadd.vv v8, v10, v82532; CHECK-NEXT: vsrl.vi v10, v8, 42533; CHECK-NEXT: vadd.vv v8, v8, v102534; CHECK-NEXT: vand.vx v8, v8, a02535; CHECK-NEXT: lui a0, 41122536; CHECK-NEXT: addi a0, a0, 2572537; CHECK-NEXT: vmul.vx v8, v8, a02538; CHECK-NEXT: vsrl.vi v8, v8, 242539; CHECK-NEXT: ret2540 %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl)2541 ret <8 x i32> %v2542}2543 2544define <16 x i32> @vp_cttz_zero_undef_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {2545; CHECK-LABEL: vp_cttz_zero_undef_v16i32:2546; CHECK: # %bb.0:2547; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma2548; CHECK-NEXT: vadd.vi v12, v8, -1, v0.t2549; CHECK-NEXT: lui a0, 3495252550; CHECK-NEXT: vnot.v v8, v8, v0.t2551; CHECK-NEXT: addi a0, a0, 13652552; CHECK-NEXT: vand.vv v8, v8, v12, v0.t2553; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t2554; CHECK-NEXT: vand.vx v12, v12, a0, v0.t2555; CHECK-NEXT: lui a0, 2097152556; CHECK-NEXT: addi a0, a0, 8192557; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t2558; CHECK-NEXT: vand.vx v12, v8, a0, v0.t2559; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t2560; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2561; CHECK-NEXT: lui a0, 616812562; CHECK-NEXT: addi a0, a0, -2412563; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t2564; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t2565; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t2566; CHECK-NEXT: vand.vx v8, v8, a0, v0.t2567; CHECK-NEXT: lui a0, 41122568; CHECK-NEXT: addi a0, a0, 2572569; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t2570; CHECK-NEXT: vsrl.vi v8, v8, 24, v0.t2571; CHECK-NEXT: ret2572 %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, i1 true, <16 x i1> %m, i32 %evl)2573 ret <16 x i32> %v2574}2575 2576define <16 x i32> @vp_cttz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {2577; CHECK-LABEL: vp_cttz_zero_undef_v16i32_unmasked:2578; CHECK: # %bb.0:2579; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma2580; CHECK-NEXT: vadd.vi v12, v8, -12581; CHECK-NEXT: vnot.v v8, v82582; CHECK-NEXT: lui a0, 3495252583; CHECK-NEXT: vand.vv v8, v8, v122584; CHECK-NEXT: addi a0, a0, 13652585; CHECK-NEXT: vsrl.vi v12, v8, 12586; CHECK-NEXT: vand.vx v12, v12, a02587; CHECK-NEXT: lui a0, 2097152588; CHECK-NEXT: addi a0, a0, 8192589; CHECK-NEXT: vsub.vv v8, v8, v122590; CHECK-NEXT: vand.vx v12, v8, a02591; CHECK-NEXT: vsrl.vi v8, v8, 22592; CHECK-NEXT: vand.vx v8, v8, a02593; CHECK-NEXT: lui a0, 616812594; CHECK-NEXT: addi a0, a0, -2412595; CHECK-NEXT: vadd.vv v8, v12, v82596; CHECK-NEXT: vsrl.vi v12, v8, 42597; CHECK-NEXT: vadd.vv v8, v8, v122598; CHECK-NEXT: vand.vx v8, v8, a02599; CHECK-NEXT: lui a0, 41122600; CHECK-NEXT: addi a0, a0, 2572601; CHECK-NEXT: vmul.vx v8, v8, a02602; CHECK-NEXT: vsrl.vi v8, v8, 242603; CHECK-NEXT: ret2604 %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl)2605 ret <16 x i32> %v2606}2607 2608define <2 x i64> @vp_cttz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {2609; RV32-LABEL: vp_cttz_zero_undef_v2i64:2610; RV32: # %bb.0:2611; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma2612; RV32-NEXT: vadd.vi v9, v8, -1, v0.t2613; RV32-NEXT: lui a1, 3495252614; RV32-NEXT: addi a1, a1, 13652615; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma2616; RV32-NEXT: vmv.v.x v10, a12617; RV32-NEXT: lui a1, 2097152618; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma2619; RV32-NEXT: vnot.v v8, v8, v0.t2620; RV32-NEXT: addi a1, a1, 8192621; RV32-NEXT: vand.vv v8, v8, v9, v0.t2622; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t2623; RV32-NEXT: vand.vv v9, v9, v10, v0.t2624; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma2625; RV32-NEXT: vmv.v.x v10, a12626; RV32-NEXT: lui a1, 616812627; RV32-NEXT: addi a1, a1, -2412628; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma2629; RV32-NEXT: vsub.vv v8, v8, v9, v0.t2630; RV32-NEXT: vand.vv v9, v8, v10, v0.t2631; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t2632; RV32-NEXT: vand.vv v8, v8, v10, v0.t2633; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma2634; RV32-NEXT: vmv.v.x v10, a12635; RV32-NEXT: lui a1, 41122636; RV32-NEXT: addi a1, a1, 2572637; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma2638; RV32-NEXT: vadd.vv v8, v9, v8, v0.t2639; RV32-NEXT: vsrl.vi v9, v8, 4, v0.t2640; RV32-NEXT: vadd.vv v8, v8, v9, v0.t2641; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma2642; RV32-NEXT: vmv.v.x v9, a12643; RV32-NEXT: li a1, 562644; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma2645; RV32-NEXT: vand.vv v8, v8, v10, v0.t2646; RV32-NEXT: vmul.vv v8, v8, v9, v0.t2647; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t2648; RV32-NEXT: ret2649;2650; RV64-LABEL: vp_cttz_zero_undef_v2i64:2651; RV64: # %bb.0:2652; RV64-NEXT: lui a1, 3495252653; RV64-NEXT: lui a2, 2097152654; RV64-NEXT: lui a3, 616812655; RV64-NEXT: lui a4, 41122656; RV64-NEXT: addi a1, a1, 13652657; RV64-NEXT: addi a2, a2, 8192658; RV64-NEXT: addi a3, a3, -2412659; RV64-NEXT: addi a4, a4, 2572660; RV64-NEXT: slli a5, a1, 322661; RV64-NEXT: add a1, a1, a52662; RV64-NEXT: slli a5, a2, 322663; RV64-NEXT: add a2, a2, a52664; RV64-NEXT: slli a5, a3, 322665; RV64-NEXT: add a3, a3, a52666; RV64-NEXT: slli a5, a4, 322667; RV64-NEXT: add a4, a4, a52668; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma2669; RV64-NEXT: vadd.vi v9, v8, -1, v0.t2670; RV64-NEXT: vnot.v v8, v8, v0.t2671; RV64-NEXT: vand.vv v8, v8, v9, v0.t2672; RV64-NEXT: vsrl.vi v9, v8, 1, v0.t2673; RV64-NEXT: vand.vx v9, v9, a1, v0.t2674; RV64-NEXT: vsub.vv v8, v8, v9, v0.t2675; RV64-NEXT: vand.vx v9, v8, a2, v0.t2676; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t2677; RV64-NEXT: vand.vx v8, v8, a2, v0.t2678; RV64-NEXT: vadd.vv v8, v9, v8, v0.t2679; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t2680; RV64-NEXT: vadd.vv v8, v8, v9, v0.t2681; RV64-NEXT: vand.vx v8, v8, a3, v0.t2682; RV64-NEXT: li a0, 562683; RV64-NEXT: vmul.vx v8, v8, a4, v0.t2684; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t2685; RV64-NEXT: ret2686 %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 true, <2 x i1> %m, i32 %evl)2687 ret <2 x i64> %v2688}2689 2690define <2 x i64> @vp_cttz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {2691; RV32-LABEL: vp_cttz_zero_undef_v2i64_unmasked:2692; RV32: # %bb.0:2693; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma2694; RV32-NEXT: vadd.vi v9, v8, -12695; RV32-NEXT: vnot.v v8, v82696; RV32-NEXT: lui a1, 3495252697; RV32-NEXT: addi a1, a1, 13652698; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma2699; RV32-NEXT: vmv.v.x v10, a12700; RV32-NEXT: lui a1, 2097152701; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma2702; RV32-NEXT: vand.vv v8, v8, v92703; RV32-NEXT: addi a1, a1, 8192704; RV32-NEXT: vsrl.vi v9, v8, 12705; RV32-NEXT: vand.vv v9, v9, v102706; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma2707; RV32-NEXT: vmv.v.x v10, a12708; RV32-NEXT: lui a1, 616812709; RV32-NEXT: addi a1, a1, -2412710; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma2711; RV32-NEXT: vsub.vv v8, v8, v92712; RV32-NEXT: vand.vv v9, v8, v102713; RV32-NEXT: vsrl.vi v8, v8, 22714; RV32-NEXT: vand.vv v8, v8, v102715; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma2716; RV32-NEXT: vmv.v.x v10, a12717; RV32-NEXT: lui a1, 41122718; RV32-NEXT: addi a1, a1, 2572719; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma2720; RV32-NEXT: vadd.vv v8, v9, v82721; RV32-NEXT: vsrl.vi v9, v8, 42722; RV32-NEXT: vadd.vv v8, v8, v92723; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma2724; RV32-NEXT: vmv.v.x v9, a12725; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma2726; RV32-NEXT: vand.vv v8, v8, v102727; RV32-NEXT: vmul.vv v8, v8, v92728; RV32-NEXT: li a0, 562729; RV32-NEXT: vsrl.vx v8, v8, a02730; RV32-NEXT: ret2731;2732; RV64-LABEL: vp_cttz_zero_undef_v2i64_unmasked:2733; RV64: # %bb.0:2734; RV64-NEXT: lui a1, 3495252735; RV64-NEXT: lui a2, 2097152736; RV64-NEXT: lui a3, 616812737; RV64-NEXT: lui a4, 41122738; RV64-NEXT: addi a1, a1, 13652739; RV64-NEXT: addi a2, a2, 8192740; RV64-NEXT: addi a3, a3, -2412741; RV64-NEXT: addi a4, a4, 2572742; RV64-NEXT: slli a5, a1, 322743; RV64-NEXT: add a1, a1, a52744; RV64-NEXT: slli a5, a2, 322745; RV64-NEXT: add a2, a2, a52746; RV64-NEXT: slli a5, a3, 322747; RV64-NEXT: add a3, a3, a52748; RV64-NEXT: slli a5, a4, 322749; RV64-NEXT: add a4, a4, a52750; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma2751; RV64-NEXT: vadd.vi v9, v8, -12752; RV64-NEXT: vnot.v v8, v82753; RV64-NEXT: vand.vv v8, v8, v92754; RV64-NEXT: vsrl.vi v9, v8, 12755; RV64-NEXT: vand.vx v9, v9, a12756; RV64-NEXT: vsub.vv v8, v8, v92757; RV64-NEXT: vand.vx v9, v8, a22758; RV64-NEXT: vsrl.vi v8, v8, 22759; RV64-NEXT: vand.vx v8, v8, a22760; RV64-NEXT: vadd.vv v8, v9, v82761; RV64-NEXT: vsrl.vi v9, v8, 42762; RV64-NEXT: vadd.vv v8, v8, v92763; RV64-NEXT: vand.vx v8, v8, a32764; RV64-NEXT: vmul.vx v8, v8, a42765; RV64-NEXT: li a0, 562766; RV64-NEXT: vsrl.vx v8, v8, a02767; RV64-NEXT: ret2768 %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl)2769 ret <2 x i64> %v2770}2771 2772define <4 x i64> @vp_cttz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {2773; RV32-LABEL: vp_cttz_zero_undef_v4i64:2774; RV32: # %bb.0:2775; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma2776; RV32-NEXT: vadd.vi v10, v8, -1, v0.t2777; RV32-NEXT: lui a1, 3495252778; RV32-NEXT: addi a1, a1, 13652779; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma2780; RV32-NEXT: vmv.v.x v12, a12781; RV32-NEXT: lui a1, 2097152782; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma2783; RV32-NEXT: vnot.v v8, v8, v0.t2784; RV32-NEXT: addi a1, a1, 8192785; RV32-NEXT: vand.vv v8, v8, v10, v0.t2786; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t2787; RV32-NEXT: vand.vv v10, v10, v12, v0.t2788; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma2789; RV32-NEXT: vmv.v.x v12, a12790; RV32-NEXT: lui a1, 616812791; RV32-NEXT: addi a1, a1, -2412792; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma2793; RV32-NEXT: vsub.vv v8, v8, v10, v0.t2794; RV32-NEXT: vand.vv v10, v8, v12, v0.t2795; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t2796; RV32-NEXT: vand.vv v8, v8, v12, v0.t2797; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma2798; RV32-NEXT: vmv.v.x v12, a12799; RV32-NEXT: lui a1, 41122800; RV32-NEXT: addi a1, a1, 2572801; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma2802; RV32-NEXT: vadd.vv v8, v10, v8, v0.t2803; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t2804; RV32-NEXT: vadd.vv v8, v8, v10, v0.t2805; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma2806; RV32-NEXT: vmv.v.x v10, a12807; RV32-NEXT: li a1, 562808; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma2809; RV32-NEXT: vand.vv v8, v8, v12, v0.t2810; RV32-NEXT: vmul.vv v8, v8, v10, v0.t2811; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t2812; RV32-NEXT: ret2813;2814; RV64-LABEL: vp_cttz_zero_undef_v4i64:2815; RV64: # %bb.0:2816; RV64-NEXT: lui a1, 3495252817; RV64-NEXT: lui a2, 2097152818; RV64-NEXT: lui a3, 616812819; RV64-NEXT: lui a4, 41122820; RV64-NEXT: addi a1, a1, 13652821; RV64-NEXT: addi a2, a2, 8192822; RV64-NEXT: addi a3, a3, -2412823; RV64-NEXT: addi a4, a4, 2572824; RV64-NEXT: slli a5, a1, 322825; RV64-NEXT: add a1, a1, a52826; RV64-NEXT: slli a5, a2, 322827; RV64-NEXT: add a2, a2, a52828; RV64-NEXT: slli a5, a3, 322829; RV64-NEXT: add a3, a3, a52830; RV64-NEXT: slli a5, a4, 322831; RV64-NEXT: add a4, a4, a52832; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma2833; RV64-NEXT: vadd.vi v10, v8, -1, v0.t2834; RV64-NEXT: vnot.v v8, v8, v0.t2835; RV64-NEXT: vand.vv v8, v8, v10, v0.t2836; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t2837; RV64-NEXT: vand.vx v10, v10, a1, v0.t2838; RV64-NEXT: vsub.vv v8, v8, v10, v0.t2839; RV64-NEXT: vand.vx v10, v8, a2, v0.t2840; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t2841; RV64-NEXT: vand.vx v8, v8, a2, v0.t2842; RV64-NEXT: vadd.vv v8, v10, v8, v0.t2843; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t2844; RV64-NEXT: vadd.vv v8, v8, v10, v0.t2845; RV64-NEXT: vand.vx v8, v8, a3, v0.t2846; RV64-NEXT: li a0, 562847; RV64-NEXT: vmul.vx v8, v8, a4, v0.t2848; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t2849; RV64-NEXT: ret2850 %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 true, <4 x i1> %m, i32 %evl)2851 ret <4 x i64> %v2852}2853 2854define <4 x i64> @vp_cttz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {2855; RV32-LABEL: vp_cttz_zero_undef_v4i64_unmasked:2856; RV32: # %bb.0:2857; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma2858; RV32-NEXT: vadd.vi v10, v8, -12859; RV32-NEXT: vnot.v v8, v82860; RV32-NEXT: lui a1, 3495252861; RV32-NEXT: addi a1, a1, 13652862; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma2863; RV32-NEXT: vmv.v.x v12, a12864; RV32-NEXT: lui a1, 2097152865; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma2866; RV32-NEXT: vand.vv v8, v8, v102867; RV32-NEXT: addi a1, a1, 8192868; RV32-NEXT: vsrl.vi v10, v8, 12869; RV32-NEXT: vand.vv v10, v10, v122870; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma2871; RV32-NEXT: vmv.v.x v12, a12872; RV32-NEXT: lui a1, 616812873; RV32-NEXT: addi a1, a1, -2412874; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma2875; RV32-NEXT: vsub.vv v8, v8, v102876; RV32-NEXT: vand.vv v10, v8, v122877; RV32-NEXT: vsrl.vi v8, v8, 22878; RV32-NEXT: vand.vv v8, v8, v122879; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma2880; RV32-NEXT: vmv.v.x v12, a12881; RV32-NEXT: lui a1, 41122882; RV32-NEXT: addi a1, a1, 2572883; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma2884; RV32-NEXT: vadd.vv v8, v10, v82885; RV32-NEXT: vsrl.vi v10, v8, 42886; RV32-NEXT: vadd.vv v8, v8, v102887; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma2888; RV32-NEXT: vmv.v.x v10, a12889; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma2890; RV32-NEXT: vand.vv v8, v8, v122891; RV32-NEXT: vmul.vv v8, v8, v102892; RV32-NEXT: li a0, 562893; RV32-NEXT: vsrl.vx v8, v8, a02894; RV32-NEXT: ret2895;2896; RV64-LABEL: vp_cttz_zero_undef_v4i64_unmasked:2897; RV64: # %bb.0:2898; RV64-NEXT: lui a1, 3495252899; RV64-NEXT: lui a2, 2097152900; RV64-NEXT: lui a3, 616812901; RV64-NEXT: lui a4, 41122902; RV64-NEXT: addi a1, a1, 13652903; RV64-NEXT: addi a2, a2, 8192904; RV64-NEXT: addi a3, a3, -2412905; RV64-NEXT: addi a4, a4, 2572906; RV64-NEXT: slli a5, a1, 322907; RV64-NEXT: add a1, a1, a52908; RV64-NEXT: slli a5, a2, 322909; RV64-NEXT: add a2, a2, a52910; RV64-NEXT: slli a5, a3, 322911; RV64-NEXT: add a3, a3, a52912; RV64-NEXT: slli a5, a4, 322913; RV64-NEXT: add a4, a4, a52914; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma2915; RV64-NEXT: vadd.vi v10, v8, -12916; RV64-NEXT: vnot.v v8, v82917; RV64-NEXT: vand.vv v8, v8, v102918; RV64-NEXT: vsrl.vi v10, v8, 12919; RV64-NEXT: vand.vx v10, v10, a12920; RV64-NEXT: vsub.vv v8, v8, v102921; RV64-NEXT: vand.vx v10, v8, a22922; RV64-NEXT: vsrl.vi v8, v8, 22923; RV64-NEXT: vand.vx v8, v8, a22924; RV64-NEXT: vadd.vv v8, v10, v82925; RV64-NEXT: vsrl.vi v10, v8, 42926; RV64-NEXT: vadd.vv v8, v8, v102927; RV64-NEXT: vand.vx v8, v8, a32928; RV64-NEXT: vmul.vx v8, v8, a42929; RV64-NEXT: li a0, 562930; RV64-NEXT: vsrl.vx v8, v8, a02931; RV64-NEXT: ret2932 %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl)2933 ret <4 x i64> %v2934}2935 2936define <8 x i64> @vp_cttz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {2937; RV32-LABEL: vp_cttz_zero_undef_v8i64:2938; RV32: # %bb.0:2939; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma2940; RV32-NEXT: vadd.vi v12, v8, -1, v0.t2941; RV32-NEXT: lui a1, 3495252942; RV32-NEXT: addi a1, a1, 13652943; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma2944; RV32-NEXT: vmv.v.x v16, a12945; RV32-NEXT: lui a1, 2097152946; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma2947; RV32-NEXT: vnot.v v8, v8, v0.t2948; RV32-NEXT: addi a1, a1, 8192949; RV32-NEXT: vand.vv v12, v8, v12, v0.t2950; RV32-NEXT: vsrl.vi v8, v12, 1, v0.t2951; RV32-NEXT: vand.vv v16, v8, v16, v0.t2952; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma2953; RV32-NEXT: vmv.v.x v8, a12954; RV32-NEXT: lui a1, 616812955; RV32-NEXT: addi a1, a1, -2412956; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma2957; RV32-NEXT: vsub.vv v12, v12, v16, v0.t2958; RV32-NEXT: vand.vv v16, v12, v8, v0.t2959; RV32-NEXT: vsrl.vi v12, v12, 2, v0.t2960; RV32-NEXT: vand.vv v8, v12, v8, v0.t2961; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma2962; RV32-NEXT: vmv.v.x v12, a12963; RV32-NEXT: lui a1, 41122964; RV32-NEXT: addi a1, a1, 2572965; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma2966; RV32-NEXT: vadd.vv v8, v16, v8, v0.t2967; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t2968; RV32-NEXT: vadd.vv v8, v8, v16, v0.t2969; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma2970; RV32-NEXT: vmv.v.x v16, a12971; RV32-NEXT: li a1, 562972; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma2973; RV32-NEXT: vand.vv v8, v8, v12, v0.t2974; RV32-NEXT: vmul.vv v8, v8, v16, v0.t2975; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t2976; RV32-NEXT: ret2977;2978; RV64-LABEL: vp_cttz_zero_undef_v8i64:2979; RV64: # %bb.0:2980; RV64-NEXT: lui a1, 3495252981; RV64-NEXT: lui a2, 2097152982; RV64-NEXT: lui a3, 616812983; RV64-NEXT: lui a4, 41122984; RV64-NEXT: addi a1, a1, 13652985; RV64-NEXT: addi a2, a2, 8192986; RV64-NEXT: addi a3, a3, -2412987; RV64-NEXT: addi a4, a4, 2572988; RV64-NEXT: slli a5, a1, 322989; RV64-NEXT: add a1, a1, a52990; RV64-NEXT: slli a5, a2, 322991; RV64-NEXT: add a2, a2, a52992; RV64-NEXT: slli a5, a3, 322993; RV64-NEXT: add a3, a3, a52994; RV64-NEXT: slli a5, a4, 322995; RV64-NEXT: add a4, a4, a52996; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma2997; RV64-NEXT: vadd.vi v12, v8, -1, v0.t2998; RV64-NEXT: vnot.v v8, v8, v0.t2999; RV64-NEXT: vand.vv v8, v8, v12, v0.t3000; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t3001; RV64-NEXT: vand.vx v12, v12, a1, v0.t3002; RV64-NEXT: vsub.vv v8, v8, v12, v0.t3003; RV64-NEXT: vand.vx v12, v8, a2, v0.t3004; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t3005; RV64-NEXT: vand.vx v8, v8, a2, v0.t3006; RV64-NEXT: vadd.vv v8, v12, v8, v0.t3007; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t3008; RV64-NEXT: vadd.vv v8, v8, v12, v0.t3009; RV64-NEXT: vand.vx v8, v8, a3, v0.t3010; RV64-NEXT: li a0, 563011; RV64-NEXT: vmul.vx v8, v8, a4, v0.t3012; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t3013; RV64-NEXT: ret3014 %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 true, <8 x i1> %m, i32 %evl)3015 ret <8 x i64> %v3016}3017 3018define <8 x i64> @vp_cttz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {3019; RV32-LABEL: vp_cttz_zero_undef_v8i64_unmasked:3020; RV32: # %bb.0:3021; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma3022; RV32-NEXT: vadd.vi v12, v8, -13023; RV32-NEXT: vnot.v v8, v83024; RV32-NEXT: lui a1, 3495253025; RV32-NEXT: addi a1, a1, 13653026; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma3027; RV32-NEXT: vmv.v.x v16, a13028; RV32-NEXT: lui a1, 2097153029; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma3030; RV32-NEXT: vand.vv v8, v8, v123031; RV32-NEXT: addi a1, a1, 8193032; RV32-NEXT: vsrl.vi v12, v8, 13033; RV32-NEXT: vand.vv v12, v12, v163034; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma3035; RV32-NEXT: vmv.v.x v16, a13036; RV32-NEXT: lui a1, 616813037; RV32-NEXT: addi a1, a1, -2413038; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma3039; RV32-NEXT: vsub.vv v8, v8, v123040; RV32-NEXT: vand.vv v12, v8, v163041; RV32-NEXT: vsrl.vi v8, v8, 23042; RV32-NEXT: vand.vv v8, v8, v163043; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma3044; RV32-NEXT: vmv.v.x v16, a13045; RV32-NEXT: lui a1, 41123046; RV32-NEXT: addi a1, a1, 2573047; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma3048; RV32-NEXT: vadd.vv v8, v12, v83049; RV32-NEXT: vsrl.vi v12, v8, 43050; RV32-NEXT: vadd.vv v8, v8, v123051; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma3052; RV32-NEXT: vmv.v.x v12, a13053; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma3054; RV32-NEXT: vand.vv v8, v8, v163055; RV32-NEXT: vmul.vv v8, v8, v123056; RV32-NEXT: li a0, 563057; RV32-NEXT: vsrl.vx v8, v8, a03058; RV32-NEXT: ret3059;3060; RV64-LABEL: vp_cttz_zero_undef_v8i64_unmasked:3061; RV64: # %bb.0:3062; RV64-NEXT: lui a1, 3495253063; RV64-NEXT: lui a2, 2097153064; RV64-NEXT: lui a3, 616813065; RV64-NEXT: lui a4, 41123066; RV64-NEXT: addi a1, a1, 13653067; RV64-NEXT: addi a2, a2, 8193068; RV64-NEXT: addi a3, a3, -2413069; RV64-NEXT: addi a4, a4, 2573070; RV64-NEXT: slli a5, a1, 323071; RV64-NEXT: add a1, a1, a53072; RV64-NEXT: slli a5, a2, 323073; RV64-NEXT: add a2, a2, a53074; RV64-NEXT: slli a5, a3, 323075; RV64-NEXT: add a3, a3, a53076; RV64-NEXT: slli a5, a4, 323077; RV64-NEXT: add a4, a4, a53078; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma3079; RV64-NEXT: vadd.vi v12, v8, -13080; RV64-NEXT: vnot.v v8, v83081; RV64-NEXT: vand.vv v8, v8, v123082; RV64-NEXT: vsrl.vi v12, v8, 13083; RV64-NEXT: vand.vx v12, v12, a13084; RV64-NEXT: vsub.vv v8, v8, v123085; RV64-NEXT: vand.vx v12, v8, a23086; RV64-NEXT: vsrl.vi v8, v8, 23087; RV64-NEXT: vand.vx v8, v8, a23088; RV64-NEXT: vadd.vv v8, v12, v83089; RV64-NEXT: vsrl.vi v12, v8, 43090; RV64-NEXT: vadd.vv v8, v8, v123091; RV64-NEXT: vand.vx v8, v8, a33092; RV64-NEXT: vmul.vx v8, v8, a43093; RV64-NEXT: li a0, 563094; RV64-NEXT: vsrl.vx v8, v8, a03095; RV64-NEXT: ret3096 %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl)3097 ret <8 x i64> %v3098}3099 3100define <15 x i64> @vp_cttz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {3101; RV32-LABEL: vp_cttz_zero_undef_v15i64:3102; RV32: # %bb.0:3103; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3104; RV32-NEXT: vadd.vi v16, v8, -1, v0.t3105; RV32-NEXT: lui a1, 3495253106; RV32-NEXT: addi a1, a1, 13653107; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3108; RV32-NEXT: vmv.v.x v24, a13109; RV32-NEXT: lui a1, 2097153110; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3111; RV32-NEXT: vnot.v v8, v8, v0.t3112; RV32-NEXT: addi a1, a1, 8193113; RV32-NEXT: vand.vv v16, v8, v16, v0.t3114; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t3115; RV32-NEXT: vand.vv v24, v8, v24, v0.t3116; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3117; RV32-NEXT: vmv.v.x v8, a13118; RV32-NEXT: lui a1, 616813119; RV32-NEXT: addi a1, a1, -2413120; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3121; RV32-NEXT: vsub.vv v24, v16, v24, v0.t3122; RV32-NEXT: vand.vv v16, v24, v8, v0.t3123; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t3124; RV32-NEXT: vand.vv v24, v24, v8, v0.t3125; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3126; RV32-NEXT: vmv.v.x v8, a13127; RV32-NEXT: lui a1, 41123128; RV32-NEXT: addi a1, a1, 2573129; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3130; RV32-NEXT: vadd.vv v16, v16, v24, v0.t3131; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t3132; RV32-NEXT: vadd.vv v16, v16, v24, v0.t3133; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3134; RV32-NEXT: vmv.v.x v24, a13135; RV32-NEXT: li a1, 563136; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3137; RV32-NEXT: vand.vv v8, v16, v8, v0.t3138; RV32-NEXT: vmul.vv v8, v8, v24, v0.t3139; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t3140; RV32-NEXT: ret3141;3142; RV64-LABEL: vp_cttz_zero_undef_v15i64:3143; RV64: # %bb.0:3144; RV64-NEXT: lui a1, 3495253145; RV64-NEXT: lui a2, 2097153146; RV64-NEXT: lui a3, 616813147; RV64-NEXT: lui a4, 41123148; RV64-NEXT: addi a1, a1, 13653149; RV64-NEXT: addi a2, a2, 8193150; RV64-NEXT: addi a3, a3, -2413151; RV64-NEXT: addi a4, a4, 2573152; RV64-NEXT: slli a5, a1, 323153; RV64-NEXT: add a1, a1, a53154; RV64-NEXT: slli a5, a2, 323155; RV64-NEXT: add a2, a2, a53156; RV64-NEXT: slli a5, a3, 323157; RV64-NEXT: add a3, a3, a53158; RV64-NEXT: slli a5, a4, 323159; RV64-NEXT: add a4, a4, a53160; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma3161; RV64-NEXT: vadd.vi v16, v8, -1, v0.t3162; RV64-NEXT: vnot.v v8, v8, v0.t3163; RV64-NEXT: vand.vv v8, v8, v16, v0.t3164; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t3165; RV64-NEXT: vand.vx v16, v16, a1, v0.t3166; RV64-NEXT: vsub.vv v8, v8, v16, v0.t3167; RV64-NEXT: vand.vx v16, v8, a2, v0.t3168; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t3169; RV64-NEXT: vand.vx v8, v8, a2, v0.t3170; RV64-NEXT: vadd.vv v8, v16, v8, v0.t3171; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t3172; RV64-NEXT: vadd.vv v8, v8, v16, v0.t3173; RV64-NEXT: vand.vx v8, v8, a3, v0.t3174; RV64-NEXT: li a0, 563175; RV64-NEXT: vmul.vx v8, v8, a4, v0.t3176; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t3177; RV64-NEXT: ret3178 %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 true, <15 x i1> %m, i32 %evl)3179 ret <15 x i64> %v3180}3181 3182define <15 x i64> @vp_cttz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {3183; RV32-LABEL: vp_cttz_zero_undef_v15i64_unmasked:3184; RV32: # %bb.0:3185; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3186; RV32-NEXT: vadd.vi v16, v8, -13187; RV32-NEXT: vnot.v v8, v83188; RV32-NEXT: lui a1, 3495253189; RV32-NEXT: addi a1, a1, 13653190; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3191; RV32-NEXT: vmv.v.x v24, a13192; RV32-NEXT: lui a1, 2097153193; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3194; RV32-NEXT: vand.vv v8, v8, v163195; RV32-NEXT: addi a1, a1, 8193196; RV32-NEXT: vsrl.vi v16, v8, 13197; RV32-NEXT: vand.vv v24, v16, v243198; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3199; RV32-NEXT: vmv.v.x v16, a13200; RV32-NEXT: lui a1, 616813201; RV32-NEXT: addi a1, a1, -2413202; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3203; RV32-NEXT: vsub.vv v8, v8, v243204; RV32-NEXT: vand.vv v24, v8, v163205; RV32-NEXT: vsrl.vi v8, v8, 23206; RV32-NEXT: vand.vv v8, v8, v163207; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3208; RV32-NEXT: vmv.v.x v16, a13209; RV32-NEXT: lui a1, 41123210; RV32-NEXT: addi a1, a1, 2573211; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3212; RV32-NEXT: vadd.vv v8, v24, v83213; RV32-NEXT: vsrl.vi v24, v8, 43214; RV32-NEXT: vadd.vv v8, v8, v243215; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3216; RV32-NEXT: vmv.v.x v24, a13217; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3218; RV32-NEXT: vand.vv v8, v8, v163219; RV32-NEXT: vmul.vv v8, v8, v243220; RV32-NEXT: li a0, 563221; RV32-NEXT: vsrl.vx v8, v8, a03222; RV32-NEXT: ret3223;3224; RV64-LABEL: vp_cttz_zero_undef_v15i64_unmasked:3225; RV64: # %bb.0:3226; RV64-NEXT: lui a1, 3495253227; RV64-NEXT: lui a2, 2097153228; RV64-NEXT: lui a3, 616813229; RV64-NEXT: lui a4, 41123230; RV64-NEXT: addi a1, a1, 13653231; RV64-NEXT: addi a2, a2, 8193232; RV64-NEXT: addi a3, a3, -2413233; RV64-NEXT: addi a4, a4, 2573234; RV64-NEXT: slli a5, a1, 323235; RV64-NEXT: add a1, a1, a53236; RV64-NEXT: slli a5, a2, 323237; RV64-NEXT: add a2, a2, a53238; RV64-NEXT: slli a5, a3, 323239; RV64-NEXT: add a3, a3, a53240; RV64-NEXT: slli a5, a4, 323241; RV64-NEXT: add a4, a4, a53242; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma3243; RV64-NEXT: vadd.vi v16, v8, -13244; RV64-NEXT: vnot.v v8, v83245; RV64-NEXT: vand.vv v8, v8, v163246; RV64-NEXT: vsrl.vi v16, v8, 13247; RV64-NEXT: vand.vx v16, v16, a13248; RV64-NEXT: vsub.vv v8, v8, v163249; RV64-NEXT: vand.vx v16, v8, a23250; RV64-NEXT: vsrl.vi v8, v8, 23251; RV64-NEXT: vand.vx v8, v8, a23252; RV64-NEXT: vadd.vv v8, v16, v83253; RV64-NEXT: vsrl.vi v16, v8, 43254; RV64-NEXT: vadd.vv v8, v8, v163255; RV64-NEXT: vand.vx v8, v8, a33256; RV64-NEXT: vmul.vx v8, v8, a43257; RV64-NEXT: li a0, 563258; RV64-NEXT: vsrl.vx v8, v8, a03259; RV64-NEXT: ret3260 %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 true, <15 x i1> splat (i1 true), i32 %evl)3261 ret <15 x i64> %v3262}3263 3264define <16 x i64> @vp_cttz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {3265; RV32-LABEL: vp_cttz_zero_undef_v16i64:3266; RV32: # %bb.0:3267; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3268; RV32-NEXT: vadd.vi v16, v8, -1, v0.t3269; RV32-NEXT: lui a1, 3495253270; RV32-NEXT: addi a1, a1, 13653271; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3272; RV32-NEXT: vmv.v.x v24, a13273; RV32-NEXT: lui a1, 2097153274; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3275; RV32-NEXT: vnot.v v8, v8, v0.t3276; RV32-NEXT: addi a1, a1, 8193277; RV32-NEXT: vand.vv v16, v8, v16, v0.t3278; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t3279; RV32-NEXT: vand.vv v24, v8, v24, v0.t3280; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3281; RV32-NEXT: vmv.v.x v8, a13282; RV32-NEXT: lui a1, 616813283; RV32-NEXT: addi a1, a1, -2413284; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3285; RV32-NEXT: vsub.vv v24, v16, v24, v0.t3286; RV32-NEXT: vand.vv v16, v24, v8, v0.t3287; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t3288; RV32-NEXT: vand.vv v24, v24, v8, v0.t3289; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3290; RV32-NEXT: vmv.v.x v8, a13291; RV32-NEXT: lui a1, 41123292; RV32-NEXT: addi a1, a1, 2573293; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3294; RV32-NEXT: vadd.vv v16, v16, v24, v0.t3295; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t3296; RV32-NEXT: vadd.vv v16, v16, v24, v0.t3297; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3298; RV32-NEXT: vmv.v.x v24, a13299; RV32-NEXT: li a1, 563300; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3301; RV32-NEXT: vand.vv v8, v16, v8, v0.t3302; RV32-NEXT: vmul.vv v8, v8, v24, v0.t3303; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t3304; RV32-NEXT: ret3305;3306; RV64-LABEL: vp_cttz_zero_undef_v16i64:3307; RV64: # %bb.0:3308; RV64-NEXT: lui a1, 3495253309; RV64-NEXT: lui a2, 2097153310; RV64-NEXT: lui a3, 616813311; RV64-NEXT: lui a4, 41123312; RV64-NEXT: addi a1, a1, 13653313; RV64-NEXT: addi a2, a2, 8193314; RV64-NEXT: addi a3, a3, -2413315; RV64-NEXT: addi a4, a4, 2573316; RV64-NEXT: slli a5, a1, 323317; RV64-NEXT: add a1, a1, a53318; RV64-NEXT: slli a5, a2, 323319; RV64-NEXT: add a2, a2, a53320; RV64-NEXT: slli a5, a3, 323321; RV64-NEXT: add a3, a3, a53322; RV64-NEXT: slli a5, a4, 323323; RV64-NEXT: add a4, a4, a53324; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma3325; RV64-NEXT: vadd.vi v16, v8, -1, v0.t3326; RV64-NEXT: vnot.v v8, v8, v0.t3327; RV64-NEXT: vand.vv v8, v8, v16, v0.t3328; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t3329; RV64-NEXT: vand.vx v16, v16, a1, v0.t3330; RV64-NEXT: vsub.vv v8, v8, v16, v0.t3331; RV64-NEXT: vand.vx v16, v8, a2, v0.t3332; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t3333; RV64-NEXT: vand.vx v8, v8, a2, v0.t3334; RV64-NEXT: vadd.vv v8, v16, v8, v0.t3335; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t3336; RV64-NEXT: vadd.vv v8, v8, v16, v0.t3337; RV64-NEXT: vand.vx v8, v8, a3, v0.t3338; RV64-NEXT: li a0, 563339; RV64-NEXT: vmul.vx v8, v8, a4, v0.t3340; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t3341; RV64-NEXT: ret3342 %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 true, <16 x i1> %m, i32 %evl)3343 ret <16 x i64> %v3344}3345 3346define <16 x i64> @vp_cttz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {3347; RV32-LABEL: vp_cttz_zero_undef_v16i64_unmasked:3348; RV32: # %bb.0:3349; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3350; RV32-NEXT: vadd.vi v16, v8, -13351; RV32-NEXT: vnot.v v8, v83352; RV32-NEXT: lui a1, 3495253353; RV32-NEXT: addi a1, a1, 13653354; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3355; RV32-NEXT: vmv.v.x v24, a13356; RV32-NEXT: lui a1, 2097153357; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3358; RV32-NEXT: vand.vv v8, v8, v163359; RV32-NEXT: addi a1, a1, 8193360; RV32-NEXT: vsrl.vi v16, v8, 13361; RV32-NEXT: vand.vv v24, v16, v243362; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3363; RV32-NEXT: vmv.v.x v16, a13364; RV32-NEXT: lui a1, 616813365; RV32-NEXT: addi a1, a1, -2413366; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3367; RV32-NEXT: vsub.vv v8, v8, v243368; RV32-NEXT: vand.vv v24, v8, v163369; RV32-NEXT: vsrl.vi v8, v8, 23370; RV32-NEXT: vand.vv v8, v8, v163371; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3372; RV32-NEXT: vmv.v.x v16, a13373; RV32-NEXT: lui a1, 41123374; RV32-NEXT: addi a1, a1, 2573375; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3376; RV32-NEXT: vadd.vv v8, v24, v83377; RV32-NEXT: vsrl.vi v24, v8, 43378; RV32-NEXT: vadd.vv v8, v8, v243379; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma3380; RV32-NEXT: vmv.v.x v24, a13381; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3382; RV32-NEXT: vand.vv v8, v8, v163383; RV32-NEXT: vmul.vv v8, v8, v243384; RV32-NEXT: li a0, 563385; RV32-NEXT: vsrl.vx v8, v8, a03386; RV32-NEXT: ret3387;3388; RV64-LABEL: vp_cttz_zero_undef_v16i64_unmasked:3389; RV64: # %bb.0:3390; RV64-NEXT: lui a1, 3495253391; RV64-NEXT: lui a2, 2097153392; RV64-NEXT: lui a3, 616813393; RV64-NEXT: lui a4, 41123394; RV64-NEXT: addi a1, a1, 13653395; RV64-NEXT: addi a2, a2, 8193396; RV64-NEXT: addi a3, a3, -2413397; RV64-NEXT: addi a4, a4, 2573398; RV64-NEXT: slli a5, a1, 323399; RV64-NEXT: add a1, a1, a53400; RV64-NEXT: slli a5, a2, 323401; RV64-NEXT: add a2, a2, a53402; RV64-NEXT: slli a5, a3, 323403; RV64-NEXT: add a3, a3, a53404; RV64-NEXT: slli a5, a4, 323405; RV64-NEXT: add a4, a4, a53406; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma3407; RV64-NEXT: vadd.vi v16, v8, -13408; RV64-NEXT: vnot.v v8, v83409; RV64-NEXT: vand.vv v8, v8, v163410; RV64-NEXT: vsrl.vi v16, v8, 13411; RV64-NEXT: vand.vx v16, v16, a13412; RV64-NEXT: vsub.vv v8, v8, v163413; RV64-NEXT: vand.vx v16, v8, a23414; RV64-NEXT: vsrl.vi v8, v8, 23415; RV64-NEXT: vand.vx v8, v8, a23416; RV64-NEXT: vadd.vv v8, v16, v83417; RV64-NEXT: vsrl.vi v16, v8, 43418; RV64-NEXT: vadd.vv v8, v8, v163419; RV64-NEXT: vand.vx v8, v8, a33420; RV64-NEXT: vmul.vx v8, v8, a43421; RV64-NEXT: li a0, 563422; RV64-NEXT: vsrl.vx v8, v8, a03423; RV64-NEXT: ret3424 %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl)3425 ret <16 x i64> %v3426}3427 3428define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {3429; RV32-LABEL: vp_cttz_zero_undef_v32i64:3430; RV32: # %bb.0:3431; RV32-NEXT: addi sp, sp, -163432; RV32-NEXT: .cfi_def_cfa_offset 163433; RV32-NEXT: csrr a1, vlenb3434; RV32-NEXT: li a2, 483435; RV32-NEXT: mul a1, a1, a23436; RV32-NEXT: sub sp, sp, a13437; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb3438; RV32-NEXT: csrr a1, vlenb3439; RV32-NEXT: li a2, 403440; RV32-NEXT: mul a1, a1, a23441; RV32-NEXT: add a1, sp, a13442; RV32-NEXT: addi a1, a1, 163443; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill3444; RV32-NEXT: li a2, 163445; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma3446; RV32-NEXT: vslidedown.vi v7, v0, 23447; RV32-NEXT: mv a1, a03448; RV32-NEXT: bltu a0, a2, .LBB70_23449; RV32-NEXT: # %bb.1:3450; RV32-NEXT: li a1, 163451; RV32-NEXT: .LBB70_2:3452; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma3453; RV32-NEXT: vadd.vi v16, v8, -1, v0.t3454; RV32-NEXT: lui a2, 3495253455; RV32-NEXT: vnot.v v8, v8, v0.t3456; RV32-NEXT: addi a2, a2, 13653457; RV32-NEXT: vand.vv v8, v8, v16, v0.t3458; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma3459; RV32-NEXT: vmv.v.x v24, a23460; RV32-NEXT: csrr a2, vlenb3461; RV32-NEXT: slli a2, a2, 53462; RV32-NEXT: add a2, sp, a23463; RV32-NEXT: addi a2, a2, 163464; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill3465; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma3466; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t3467; RV32-NEXT: vand.vv v16, v16, v24, v0.t3468; RV32-NEXT: vsub.vv v8, v8, v16, v0.t3469; RV32-NEXT: lui a2, 2097153470; RV32-NEXT: addi a2, a2, 8193471; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma3472; RV32-NEXT: vmv.v.x v16, a23473; RV32-NEXT: csrr a2, vlenb3474; RV32-NEXT: slli a2, a2, 43475; RV32-NEXT: add a2, sp, a23476; RV32-NEXT: addi a2, a2, 163477; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill3478; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma3479; RV32-NEXT: vand.vv v24, v8, v16, v0.t3480; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t3481; RV32-NEXT: vand.vv v8, v8, v16, v0.t3482; RV32-NEXT: vadd.vv v8, v24, v8, v0.t3483; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t3484; RV32-NEXT: vadd.vv v8, v8, v24, v0.t3485; RV32-NEXT: lui a2, 616813486; RV32-NEXT: addi a2, a2, -2413487; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma3488; RV32-NEXT: vmv.v.x v16, a23489; RV32-NEXT: csrr a2, vlenb3490; RV32-NEXT: li a3, 243491; RV32-NEXT: mul a2, a2, a33492; RV32-NEXT: add a2, sp, a23493; RV32-NEXT: addi a2, a2, 163494; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill3495; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma3496; RV32-NEXT: vand.vv v8, v8, v16, v0.t3497; RV32-NEXT: lui a2, 41123498; RV32-NEXT: addi a2, a2, 2573499; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma3500; RV32-NEXT: vmv.v.x v16, a23501; RV32-NEXT: addi a2, sp, 163502; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill3503; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma3504; RV32-NEXT: vmul.vv v8, v8, v16, v0.t3505; RV32-NEXT: li a1, 563506; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t3507; RV32-NEXT: csrr a2, vlenb3508; RV32-NEXT: slli a2, a2, 33509; RV32-NEXT: add a2, sp, a23510; RV32-NEXT: addi a2, a2, 163511; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill3512; RV32-NEXT: addi a2, a0, -163513; RV32-NEXT: sltu a0, a0, a23514; RV32-NEXT: addi a0, a0, -13515; RV32-NEXT: and a0, a0, a23516; RV32-NEXT: vmv1r.v v0, v73517; RV32-NEXT: csrr a2, vlenb3518; RV32-NEXT: li a3, 403519; RV32-NEXT: mul a2, a2, a33520; RV32-NEXT: add a2, sp, a23521; RV32-NEXT: addi a2, a2, 163522; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload3523; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3524; RV32-NEXT: vadd.vi v24, v8, -1, v0.t3525; RV32-NEXT: vnot.v v8, v8, v0.t3526; RV32-NEXT: vand.vv v8, v8, v24, v0.t3527; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t3528; RV32-NEXT: csrr a0, vlenb3529; RV32-NEXT: slli a0, a0, 53530; RV32-NEXT: add a0, sp, a03531; RV32-NEXT: addi a0, a0, 163532; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload3533; RV32-NEXT: vand.vv v24, v24, v16, v0.t3534; RV32-NEXT: vsub.vv v8, v8, v24, v0.t3535; RV32-NEXT: csrr a0, vlenb3536; RV32-NEXT: slli a0, a0, 43537; RV32-NEXT: add a0, sp, a03538; RV32-NEXT: addi a0, a0, 163539; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload3540; RV32-NEXT: vand.vv v24, v8, v16, v0.t3541; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t3542; RV32-NEXT: vand.vv v8, v8, v16, v0.t3543; RV32-NEXT: vadd.vv v8, v24, v8, v0.t3544; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t3545; RV32-NEXT: vadd.vv v8, v8, v16, v0.t3546; RV32-NEXT: csrr a0, vlenb3547; RV32-NEXT: li a2, 243548; RV32-NEXT: mul a0, a0, a23549; RV32-NEXT: add a0, sp, a03550; RV32-NEXT: addi a0, a0, 163551; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload3552; RV32-NEXT: vand.vv v8, v8, v16, v0.t3553; RV32-NEXT: addi a0, sp, 163554; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload3555; RV32-NEXT: vmul.vv v8, v8, v16, v0.t3556; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t3557; RV32-NEXT: csrr a0, vlenb3558; RV32-NEXT: slli a0, a0, 33559; RV32-NEXT: add a0, sp, a03560; RV32-NEXT: addi a0, a0, 163561; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload3562; RV32-NEXT: csrr a0, vlenb3563; RV32-NEXT: li a1, 483564; RV32-NEXT: mul a0, a0, a13565; RV32-NEXT: add sp, sp, a03566; RV32-NEXT: .cfi_def_cfa sp, 163567; RV32-NEXT: addi sp, sp, 163568; RV32-NEXT: .cfi_def_cfa_offset 03569; RV32-NEXT: ret3570;3571; RV64-LABEL: vp_cttz_zero_undef_v32i64:3572; RV64: # %bb.0:3573; RV64-NEXT: li a2, 163574; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma3575; RV64-NEXT: vslidedown.vi v7, v0, 23576; RV64-NEXT: mv a1, a03577; RV64-NEXT: bltu a0, a2, .LBB70_23578; RV64-NEXT: # %bb.1:3579; RV64-NEXT: li a1, 163580; RV64-NEXT: .LBB70_2:3581; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma3582; RV64-NEXT: vadd.vi v24, v8, -1, v0.t3583; RV64-NEXT: lui a1, 3495253584; RV64-NEXT: lui a2, 2097153585; RV64-NEXT: lui a3, 616813586; RV64-NEXT: lui a4, 41123587; RV64-NEXT: addi a1, a1, 13653588; RV64-NEXT: addi a2, a2, 8193589; RV64-NEXT: addi a5, a3, -2413590; RV64-NEXT: addi a4, a4, 2573591; RV64-NEXT: slli a3, a1, 323592; RV64-NEXT: add a6, a1, a33593; RV64-NEXT: slli a3, a2, 323594; RV64-NEXT: add a3, a2, a33595; RV64-NEXT: slli a1, a5, 323596; RV64-NEXT: add a1, a5, a13597; RV64-NEXT: slli a2, a4, 323598; RV64-NEXT: add a2, a4, a23599; RV64-NEXT: addi a4, a0, -163600; RV64-NEXT: sltu a0, a0, a43601; RV64-NEXT: addi a0, a0, -13602; RV64-NEXT: and a4, a0, a43603; RV64-NEXT: li a0, 563604; RV64-NEXT: vnot.v v8, v8, v0.t3605; RV64-NEXT: vand.vv v8, v8, v24, v0.t3606; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t3607; RV64-NEXT: vand.vx v24, v24, a6, v0.t3608; RV64-NEXT: vsub.vv v8, v8, v24, v0.t3609; RV64-NEXT: vand.vx v24, v8, a3, v0.t3610; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t3611; RV64-NEXT: vand.vx v8, v8, a3, v0.t3612; RV64-NEXT: vadd.vv v8, v24, v8, v0.t3613; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t3614; RV64-NEXT: vadd.vv v8, v8, v24, v0.t3615; RV64-NEXT: vand.vx v8, v8, a1, v0.t3616; RV64-NEXT: vmul.vx v8, v8, a2, v0.t3617; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t3618; RV64-NEXT: vmv1r.v v0, v73619; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma3620; RV64-NEXT: vadd.vi v24, v16, -1, v0.t3621; RV64-NEXT: vnot.v v16, v16, v0.t3622; RV64-NEXT: vand.vv v16, v16, v24, v0.t3623; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t3624; RV64-NEXT: vand.vx v24, v24, a6, v0.t3625; RV64-NEXT: vsub.vv v16, v16, v24, v0.t3626; RV64-NEXT: vand.vx v24, v16, a3, v0.t3627; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t3628; RV64-NEXT: vand.vx v16, v16, a3, v0.t3629; RV64-NEXT: vadd.vv v16, v24, v16, v0.t3630; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t3631; RV64-NEXT: vadd.vv v16, v16, v24, v0.t3632; RV64-NEXT: vand.vx v16, v16, a1, v0.t3633; RV64-NEXT: vmul.vx v16, v16, a2, v0.t3634; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t3635; RV64-NEXT: ret3636 %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl)3637 ret <32 x i64> %v3638}3639 3640define <32 x i64> @vp_cttz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {3641; RV32-LABEL: vp_cttz_zero_undef_v32i64_unmasked:3642; RV32: # %bb.0:3643; RV32-NEXT: li a2, 163644; RV32-NEXT: mv a1, a03645; RV32-NEXT: bltu a0, a2, .LBB71_23646; RV32-NEXT: # %bb.1:3647; RV32-NEXT: li a1, 163648; RV32-NEXT: .LBB71_2:3649; RV32-NEXT: addi sp, sp, -163650; RV32-NEXT: .cfi_def_cfa_offset 163651; RV32-NEXT: csrr a2, vlenb3652; RV32-NEXT: slli a2, a2, 43653; RV32-NEXT: sub sp, sp, a23654; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb3655; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma3656; RV32-NEXT: vadd.vi v24, v8, -13657; RV32-NEXT: vnot.v v0, v83658; RV32-NEXT: lui a2, 3495253659; RV32-NEXT: addi a2, a2, 13653660; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma3661; RV32-NEXT: vmv.v.x v8, a23662; RV32-NEXT: csrr a2, vlenb3663; RV32-NEXT: slli a2, a2, 33664; RV32-NEXT: add a2, sp, a23665; RV32-NEXT: addi a2, a2, 163666; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill3667; RV32-NEXT: addi a2, a0, -163668; RV32-NEXT: sltu a0, a0, a23669; RV32-NEXT: addi a0, a0, -13670; RV32-NEXT: and a0, a0, a23671; RV32-NEXT: lui a2, 2097153672; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma3673; RV32-NEXT: vand.vv v24, v0, v243674; RV32-NEXT: addi a2, a2, 8193675; RV32-NEXT: vsrl.vi v0, v24, 13676; RV32-NEXT: vand.vv v0, v0, v83677; RV32-NEXT: vsub.vv v24, v24, v03678; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3679; RV32-NEXT: vadd.vi v0, v16, -13680; RV32-NEXT: vnot.v v16, v163681; RV32-NEXT: vand.vv v0, v16, v03682; RV32-NEXT: addi a3, sp, 163683; RV32-NEXT: vs8r.v v0, (a3) # vscale x 64-byte Folded Spill3684; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma3685; RV32-NEXT: vmv.v.x v16, a23686; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma3687; RV32-NEXT: vand.vv v8, v24, v163688; RV32-NEXT: vsrl.vi v24, v24, 23689; RV32-NEXT: vand.vv v24, v24, v163690; RV32-NEXT: vadd.vv v8, v8, v243691; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3692; RV32-NEXT: vsrl.vi v24, v0, 13693; RV32-NEXT: csrr a2, vlenb3694; RV32-NEXT: slli a2, a2, 33695; RV32-NEXT: add a2, sp, a23696; RV32-NEXT: addi a2, a2, 163697; RV32-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload3698; RV32-NEXT: vand.vv v24, v24, v03699; RV32-NEXT: addi a2, sp, 163700; RV32-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload3701; RV32-NEXT: vsub.vv v24, v0, v243702; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma3703; RV32-NEXT: vsrl.vi v0, v8, 43704; RV32-NEXT: vadd.vv v8, v8, v03705; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3706; RV32-NEXT: vand.vv v0, v24, v163707; RV32-NEXT: vsrl.vi v24, v24, 23708; RV32-NEXT: vand.vv v16, v24, v163709; RV32-NEXT: lui a2, 616813710; RV32-NEXT: addi a2, a2, -2413711; RV32-NEXT: vadd.vv v16, v0, v163712; RV32-NEXT: vsrl.vi v24, v16, 43713; RV32-NEXT: vadd.vv v16, v16, v243714; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma3715; RV32-NEXT: vmv.v.x v24, a23716; RV32-NEXT: lui a2, 41123717; RV32-NEXT: addi a2, a2, 2573718; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma3719; RV32-NEXT: vand.vv v8, v8, v243720; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3721; RV32-NEXT: vand.vv v16, v16, v243722; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma3723; RV32-NEXT: vmv.v.x v24, a23724; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma3725; RV32-NEXT: vmul.vv v8, v8, v243726; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3727; RV32-NEXT: vmul.vv v16, v16, v243728; RV32-NEXT: li a2, 563729; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma3730; RV32-NEXT: vsrl.vx v8, v8, a23731; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma3732; RV32-NEXT: vsrl.vx v16, v16, a23733; RV32-NEXT: csrr a0, vlenb3734; RV32-NEXT: slli a0, a0, 43735; RV32-NEXT: add sp, sp, a03736; RV32-NEXT: .cfi_def_cfa sp, 163737; RV32-NEXT: addi sp, sp, 163738; RV32-NEXT: .cfi_def_cfa_offset 03739; RV32-NEXT: ret3740;3741; RV64-LABEL: vp_cttz_zero_undef_v32i64_unmasked:3742; RV64: # %bb.0:3743; RV64-NEXT: li a2, 163744; RV64-NEXT: mv a1, a03745; RV64-NEXT: bltu a0, a2, .LBB71_23746; RV64-NEXT: # %bb.1:3747; RV64-NEXT: li a1, 163748; RV64-NEXT: .LBB71_2:3749; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma3750; RV64-NEXT: vadd.vi v24, v8, -13751; RV64-NEXT: vnot.v v8, v83752; RV64-NEXT: lui a2, 3495253753; RV64-NEXT: lui a3, 2097153754; RV64-NEXT: lui a4, 616813755; RV64-NEXT: lui a5, 41123756; RV64-NEXT: addi a2, a2, 13653757; RV64-NEXT: addi a3, a3, 8193758; RV64-NEXT: addi a4, a4, -2413759; RV64-NEXT: addi a5, a5, 2573760; RV64-NEXT: slli a6, a2, 323761; RV64-NEXT: add a2, a2, a63762; RV64-NEXT: slli a6, a3, 323763; RV64-NEXT: add a3, a3, a63764; RV64-NEXT: slli a6, a4, 323765; RV64-NEXT: add a4, a4, a63766; RV64-NEXT: slli a6, a5, 323767; RV64-NEXT: add a5, a5, a63768; RV64-NEXT: addi a6, a0, -163769; RV64-NEXT: sltu a0, a0, a63770; RV64-NEXT: addi a0, a0, -13771; RV64-NEXT: and a0, a0, a63772; RV64-NEXT: li a6, 563773; RV64-NEXT: vand.vv v8, v8, v243774; RV64-NEXT: vsrl.vi v24, v8, 13775; RV64-NEXT: vand.vx v24, v24, a23776; RV64-NEXT: vsub.vv v8, v8, v243777; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma3778; RV64-NEXT: vadd.vi v24, v16, -13779; RV64-NEXT: vnot.v v16, v163780; RV64-NEXT: vand.vv v16, v16, v243781; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma3782; RV64-NEXT: vand.vx v24, v8, a33783; RV64-NEXT: vsrl.vi v8, v8, 23784; RV64-NEXT: vand.vx v8, v8, a33785; RV64-NEXT: vadd.vv v8, v24, v83786; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma3787; RV64-NEXT: vsrl.vi v24, v16, 13788; RV64-NEXT: vand.vx v24, v24, a23789; RV64-NEXT: vsub.vv v16, v16, v243790; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma3791; RV64-NEXT: vsrl.vi v24, v8, 43792; RV64-NEXT: vadd.vv v8, v8, v243793; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma3794; RV64-NEXT: vand.vx v24, v16, a33795; RV64-NEXT: vsrl.vi v16, v16, 23796; RV64-NEXT: vand.vx v16, v16, a33797; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma3798; RV64-NEXT: vand.vx v8, v8, a43799; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma3800; RV64-NEXT: vadd.vv v16, v24, v163801; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma3802; RV64-NEXT: vmul.vx v8, v8, a53803; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma3804; RV64-NEXT: vsrl.vi v24, v16, 43805; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma3806; RV64-NEXT: vsrl.vx v8, v8, a63807; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma3808; RV64-NEXT: vadd.vv v16, v16, v243809; RV64-NEXT: vand.vx v16, v16, a43810; RV64-NEXT: vmul.vx v16, v16, a53811; RV64-NEXT: vsrl.vx v16, v16, a63812; RV64-NEXT: ret3813 %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 true, <32 x i1> splat (i1 true), i32 %evl)3814 ret <32 x i64> %v3815}3816