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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zve32f,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+d,+zve32f,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5; Test that limiting ELEN through zve32 scalarizes elements larger than 32 bits6; and disables some fractional LMULs.7 8; This should use LMUL=1.9define void @add_v4i32(ptr %x, ptr %y) {10; CHECK-LABEL: add_v4i32:11; CHECK: # %bb.0:12; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma13; CHECK-NEXT: vle32.v v8, (a0)14; CHECK-NEXT: vle32.v v9, (a1)15; CHECK-NEXT: vadd.vv v8, v8, v916; CHECK-NEXT: vse32.v v8, (a0)17; CHECK-NEXT: ret18 %a = load <4 x i32>, ptr %x19 %b = load <4 x i32>, ptr %y20 %c = add <4 x i32> %a, %b21 store <4 x i32> %c, ptr %x22 ret void23}24 25; i64 vectors should be scalarized26define void @add_v2i64(ptr %x, ptr %y) {27; RV32-LABEL: add_v2i64:28; RV32: # %bb.0:29; RV32-NEXT: lw a2, 0(a0)30; RV32-NEXT: lw a3, 4(a0)31; RV32-NEXT: lw a4, 8(a0)32; RV32-NEXT: lw a5, 12(a0)33; RV32-NEXT: lw a6, 4(a1)34; RV32-NEXT: lw a7, 0(a1)35; RV32-NEXT: lw t0, 12(a1)36; RV32-NEXT: lw a1, 8(a1)37; RV32-NEXT: add a3, a3, a638; RV32-NEXT: add a7, a2, a739; RV32-NEXT: add a5, a5, t040; RV32-NEXT: add a1, a4, a141; RV32-NEXT: sltu a2, a7, a242; RV32-NEXT: sltu a4, a1, a443; RV32-NEXT: add a2, a3, a244; RV32-NEXT: add a4, a5, a445; RV32-NEXT: sw a7, 0(a0)46; RV32-NEXT: sw a2, 4(a0)47; RV32-NEXT: sw a1, 8(a0)48; RV32-NEXT: sw a4, 12(a0)49; RV32-NEXT: ret50;51; RV64-LABEL: add_v2i64:52; RV64: # %bb.0:53; RV64-NEXT: ld a2, 0(a0)54; RV64-NEXT: ld a3, 8(a0)55; RV64-NEXT: ld a4, 0(a1)56; RV64-NEXT: ld a1, 8(a1)57; RV64-NEXT: add a2, a2, a458; RV64-NEXT: add a1, a3, a159; RV64-NEXT: sd a2, 0(a0)60; RV64-NEXT: sd a1, 8(a0)61; RV64-NEXT: ret62 %a = load <2 x i64>, ptr %x63 %b = load <2 x i64>, ptr %y64 %c = add <2 x i64> %a, %b65 store <2 x i64> %c, ptr %x66 ret void67}68 69; This should use LMUL=1 becuase there are no fractional i32 LMULs with ELEN=3270define void @add_v2i32(ptr %x, ptr %y) {71; CHECK-LABEL: add_v2i32:72; CHECK: # %bb.0:73; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma74; CHECK-NEXT: vle32.v v8, (a0)75; CHECK-NEXT: vle32.v v9, (a1)76; CHECK-NEXT: vadd.vv v8, v8, v977; CHECK-NEXT: vse32.v v8, (a0)78; CHECK-NEXT: ret79 %a = load <2 x i32>, ptr %x80 %b = load <2 x i32>, ptr %y81 %c = add <2 x i32> %a, %b82 store <2 x i32> %c, ptr %x83 ret void84}85 86; i64 vectors should be scalarized87define void @add_v1i64(ptr %x, ptr %y) {88; RV32-LABEL: add_v1i64:89; RV32: # %bb.0:90; RV32-NEXT: lw a2, 0(a0)91; RV32-NEXT: lw a3, 4(a0)92; RV32-NEXT: lw a4, 4(a1)93; RV32-NEXT: lw a1, 0(a1)94; RV32-NEXT: add a3, a3, a495; RV32-NEXT: add a1, a2, a196; RV32-NEXT: sltu a2, a1, a297; RV32-NEXT: add a2, a3, a298; RV32-NEXT: sw a1, 0(a0)99; RV32-NEXT: sw a2, 4(a0)100; RV32-NEXT: ret101;102; RV64-LABEL: add_v1i64:103; RV64: # %bb.0:104; RV64-NEXT: ld a2, 0(a0)105; RV64-NEXT: ld a1, 0(a1)106; RV64-NEXT: add a1, a2, a1107; RV64-NEXT: sd a1, 0(a0)108; RV64-NEXT: ret109 %a = load <1 x i64>, ptr %x110 %b = load <1 x i64>, ptr %y111 %c = add <1 x i64> %a, %b112 store <1 x i64> %c, ptr %x113 ret void114}115 116; This should use LMUL=1.117define void @fadd_v4f32(ptr %x, ptr %y) {118; CHECK-LABEL: fadd_v4f32:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma121; CHECK-NEXT: vle32.v v8, (a0)122; CHECK-NEXT: vle32.v v9, (a1)123; CHECK-NEXT: vfadd.vv v8, v8, v9124; CHECK-NEXT: vse32.v v8, (a0)125; CHECK-NEXT: ret126 %a = load <4 x float>, ptr %x127 %b = load <4 x float>, ptr %y128 %c = fadd <4 x float> %a, %b129 store <4 x float> %c, ptr %x130 ret void131}132 133; double vectors should be scalarized134define void @fadd_v2f64(ptr %x, ptr %y) {135; CHECK-LABEL: fadd_v2f64:136; CHECK: # %bb.0:137; CHECK-NEXT: fld fa5, 0(a0)138; CHECK-NEXT: fld fa4, 8(a0)139; CHECK-NEXT: fld fa3, 0(a1)140; CHECK-NEXT: fld fa2, 8(a1)141; CHECK-NEXT: fadd.d fa5, fa5, fa3142; CHECK-NEXT: fadd.d fa4, fa4, fa2143; CHECK-NEXT: fsd fa5, 0(a0)144; CHECK-NEXT: fsd fa4, 8(a0)145; CHECK-NEXT: ret146 %a = load <2 x double>, ptr %x147 %b = load <2 x double>, ptr %y148 %c = fadd <2 x double> %a, %b149 store <2 x double> %c, ptr %x150 ret void151}152 153; This should use LMUL=1 becuase there are no fractional float LMULs with ELEN=32154define void @fadd_v2f32(ptr %x, ptr %y) {155; CHECK-LABEL: fadd_v2f32:156; CHECK: # %bb.0:157; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma158; CHECK-NEXT: vle32.v v8, (a0)159; CHECK-NEXT: vle32.v v9, (a1)160; CHECK-NEXT: vfadd.vv v8, v8, v9161; CHECK-NEXT: vse32.v v8, (a0)162; CHECK-NEXT: ret163 %a = load <2 x float>, ptr %x164 %b = load <2 x float>, ptr %y165 %c = fadd <2 x float> %a, %b166 store <2 x float> %c, ptr %x167 ret void168}169 170; double vectors should be scalarized171define void @fadd_v1f64(ptr %x, ptr %y) {172; CHECK-LABEL: fadd_v1f64:173; CHECK: # %bb.0:174; CHECK-NEXT: fld fa5, 0(a0)175; CHECK-NEXT: fld fa4, 0(a1)176; CHECK-NEXT: fadd.d fa5, fa5, fa4177; CHECK-NEXT: fsd fa5, 0(a0)178; CHECK-NEXT: ret179 %a = load <1 x double>, ptr %x180 %b = load <1 x double>, ptr %y181 %c = fadd <1 x double> %a, %b182 store <1 x double> %c, ptr %x183 ret void184}185