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1# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2# RUN: llc -mtriple riscv64 -mattr=+v -target-abi=lp64 -start-before=prologepilog -o - \3# RUN: -verify-machineinstrs %s | FileCheck %s4--- |5 target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"6 target triple = "riscv64"7 8 define weak_odr dso_local void @fixedlen_vector_spillslot(ptr %ay) nounwind {9 ; CHECK-LABEL: fixedlen_vector_spillslot:10 ; CHECK: # %bb.0: # %entry11 ; CHECK-NEXT: addi sp, sp, -4812 ; CHECK-NEXT: sd ra, 40(sp) # 8-byte Folded Spill13 ; CHECK-NEXT: sd a0, 32(sp)14 ; CHECK-NEXT: sd a0, 16(sp)15 ; CHECK-NEXT: vsetivli a5, 1, e16, m1, ta, mu16 ; CHECK-NEXT: sd a1, 0(sp) # 8-byte Folded Spill17 ; CHECK-NEXT: addi a1, sp, 2418 ; CHECK-NEXT: vs1r.v v25, (a1) # vscale x 8-byte Folded Spill19 ; CHECK-NEXT: ld a1, 0(sp) # 8-byte Folded Reload20 ; CHECK-NEXT: call fixedlen_vector_spillslot21 ; CHECK-NEXT: ld ra, 40(sp) # 8-byte Folded Reload22 ; CHECK-NEXT: addi sp, sp, 4823 ; CHECK-NEXT: ret24 entry:25 ret void26 }27 28...29---30name: fixedlen_vector_spillslot31alignment: 232tracksRegLiveness: false33fixedStack: []34stack:35 - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8,36 stack-id: default, callee-saved-register: '', callee-saved-restored: true,37 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }38 - { id: 1, name: '', type: spill-slot, offset: 0, size: 2, alignment: 8,39 stack-id: default, callee-saved-register: '', callee-saved-restored: true,40 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }41 - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8,42 stack-id: default, callee-saved-register: '', callee-saved-restored: true,43 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }44body: |45 bb.0.entry:46 liveins: $x1, $x5, $x6, $x7, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x28, $x29, $x30, $x31, $v2547 48 SD $x10, %stack.0, 049 SD $x10, %stack.2, 050 dead renamable $x15 = PseudoVSETIVLI 1, 72, implicit-def $vl, implicit-def $vtype51 VS1R_V killed renamable $v25, %stack.1 :: (store (<vscale x 1 x s64>) into %stack.1, align 8)52 ; This is here just to make all the eligible registers live at this point.53 ; This way when we replace the frame index %stack.1 with its actual address54 ; we have to allocate a virtual register to compute it.55 ; A later run of the the register scavenger won't find an available register56 ; either so it will have to spill one to the emergency spill slot.57 PseudoCALL target-flags(riscv-call) @fixedlen_vector_spillslot, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x3158 PseudoRET59...60