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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV324; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV326 7define <1 x half> @expandload_v1f16(ptr %base, <1 x half> %src0, <1 x i1> %mask) {8; CHECK-LABEL: expandload_v1f16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma11; CHECK-NEXT: vcpop.m a1, v012; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13; CHECK-NEXT: vle16.v v9, (a0)14; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu15; CHECK-NEXT: viota.m v10, v016; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t17; CHECK-NEXT: ret18 %res = call <1 x half> @llvm.masked.expandload.v1f16(ptr align 2 %base, <1 x i1> %mask, <1 x half> %src0)19 ret <1 x half>%res20}21 22define <2 x half> @expandload_v2f16(ptr %base, <2 x half> %src0, <2 x i1> %mask) {23; CHECK-LABEL: expandload_v2f16:24; CHECK: # %bb.0:25; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma26; CHECK-NEXT: vcpop.m a1, v027; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma28; CHECK-NEXT: vle16.v v9, (a0)29; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu30; CHECK-NEXT: viota.m v10, v031; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t32; CHECK-NEXT: ret33 %res = call <2 x half> @llvm.masked.expandload.v2f16(ptr align 2 %base, <2 x i1> %mask, <2 x half> %src0)34 ret <2 x half>%res35}36 37define <4 x half> @expandload_v4f16(ptr %base, <4 x half> %src0, <4 x i1> %mask) {38; CHECK-LABEL: expandload_v4f16:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma41; CHECK-NEXT: vcpop.m a1, v042; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma43; CHECK-NEXT: vle16.v v9, (a0)44; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu45; CHECK-NEXT: viota.m v10, v046; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t47; CHECK-NEXT: ret48 %res = call <4 x half> @llvm.masked.expandload.v4f16(ptr align 2 %base, <4 x i1> %mask, <4 x half> %src0)49 ret <4 x half>%res50}51 52define <8 x half> @expandload_v8f16(ptr %base, <8 x half> %src0, <8 x i1> %mask) {53; CHECK-LABEL: expandload_v8f16:54; CHECK: # %bb.0:55; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma56; CHECK-NEXT: vcpop.m a1, v057; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma58; CHECK-NEXT: vle16.v v9, (a0)59; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu60; CHECK-NEXT: viota.m v10, v061; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t62; CHECK-NEXT: ret63 %res = call <8 x half> @llvm.masked.expandload.v8f16(ptr align 2 %base, <8 x i1> %mask, <8 x half> %src0)64 ret <8 x half>%res65}66 67define <1 x float> @expandload_v1f32(ptr %base, <1 x float> %src0, <1 x i1> %mask) {68; CHECK-LABEL: expandload_v1f32:69; CHECK: # %bb.0:70; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma71; CHECK-NEXT: vcpop.m a1, v072; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma73; CHECK-NEXT: vle32.v v9, (a0)74; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu75; CHECK-NEXT: viota.m v10, v076; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t77; CHECK-NEXT: ret78 %res = call <1 x float> @llvm.masked.expandload.v1f32(ptr align 4 %base, <1 x i1> %mask, <1 x float> %src0)79 ret <1 x float>%res80}81 82define <2 x float> @expandload_v2f32(ptr %base, <2 x float> %src0, <2 x i1> %mask) {83; CHECK-LABEL: expandload_v2f32:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma86; CHECK-NEXT: vcpop.m a1, v087; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma88; CHECK-NEXT: vle32.v v9, (a0)89; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu90; CHECK-NEXT: viota.m v10, v091; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t92; CHECK-NEXT: ret93 %res = call <2 x float> @llvm.masked.expandload.v2f32(ptr align 4 %base, <2 x i1> %mask, <2 x float> %src0)94 ret <2 x float>%res95}96 97define <4 x float> @expandload_v4f32(ptr %base, <4 x float> %src0, <4 x i1> %mask) {98; CHECK-LABEL: expandload_v4f32:99; CHECK: # %bb.0:100; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma101; CHECK-NEXT: vcpop.m a1, v0102; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma103; CHECK-NEXT: vle32.v v9, (a0)104; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu105; CHECK-NEXT: viota.m v10, v0106; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t107; CHECK-NEXT: ret108 %res = call <4 x float> @llvm.masked.expandload.v4f32(ptr align 4 %base, <4 x i1> %mask, <4 x float> %src0)109 ret <4 x float>%res110}111 112define <8 x float> @expandload_v8f32(ptr %base, <8 x float> %src0, <8 x i1> %mask) {113; CHECK-LABEL: expandload_v8f32:114; CHECK: # %bb.0:115; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma116; CHECK-NEXT: vcpop.m a1, v0117; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma118; CHECK-NEXT: vle32.v v10, (a0)119; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu120; CHECK-NEXT: viota.m v12, v0121; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t122; CHECK-NEXT: ret123 %res = call <8 x float> @llvm.masked.expandload.v8f32(ptr align 4 %base, <8 x i1> %mask, <8 x float> %src0)124 ret <8 x float>%res125}126 127define <1 x double> @expandload_v1f64(ptr %base, <1 x double> %src0, <1 x i1> %mask) {128; CHECK-LABEL: expandload_v1f64:129; CHECK: # %bb.0:130; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma131; CHECK-NEXT: vcpop.m a1, v0132; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma133; CHECK-NEXT: vle64.v v9, (a0)134; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu135; CHECK-NEXT: viota.m v10, v0136; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t137; CHECK-NEXT: ret138 %res = call <1 x double> @llvm.masked.expandload.v1f64(ptr align 8 %base, <1 x i1> %mask, <1 x double> %src0)139 ret <1 x double>%res140}141 142define <2 x double> @expandload_v2f64(ptr %base, <2 x double> %src0, <2 x i1> %mask) {143; CHECK-LABEL: expandload_v2f64:144; CHECK: # %bb.0:145; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma146; CHECK-NEXT: vcpop.m a1, v0147; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma148; CHECK-NEXT: vle64.v v9, (a0)149; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu150; CHECK-NEXT: viota.m v10, v0151; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t152; CHECK-NEXT: ret153 %res = call <2 x double> @llvm.masked.expandload.v2f64(ptr align 8 %base, <2 x i1> %mask, <2 x double> %src0)154 ret <2 x double>%res155}156 157define <4 x double> @expandload_v4f64(ptr %base, <4 x double> %src0, <4 x i1> %mask) {158; CHECK-LABEL: expandload_v4f64:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma161; CHECK-NEXT: vcpop.m a1, v0162; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma163; CHECK-NEXT: vle64.v v10, (a0)164; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu165; CHECK-NEXT: viota.m v12, v0166; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t167; CHECK-NEXT: ret168 %res = call <4 x double> @llvm.masked.expandload.v4f64(ptr align 8 %base, <4 x i1> %mask, <4 x double> %src0)169 ret <4 x double>%res170}171 172define <8 x double> @expandload_v8f64(ptr %base, <8 x double> %src0, <8 x i1> %mask) {173; CHECK-LABEL: expandload_v8f64:174; CHECK: # %bb.0:175; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma176; CHECK-NEXT: vcpop.m a1, v0177; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma178; CHECK-NEXT: vle64.v v12, (a0)179; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu180; CHECK-NEXT: viota.m v16, v0181; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t182; CHECK-NEXT: ret183 %res = call <8 x double> @llvm.masked.expandload.v8f64(ptr align 8 %base, <8 x i1> %mask, <8 x double> %src0)184 ret <8 x double>%res185}186;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:187; CHECK-RV32: {{.*}}188