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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define <2 x i16> @sextload_v2i1_v2i16(ptr %x) {6; CHECK-LABEL: sextload_v2i1_v2i16:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma9; CHECK-NEXT: vlm.v v0, (a0)10; CHECK-NEXT: vmv.v.i v8, 011; CHECK-NEXT: vmerge.vim v8, v8, -1, v012; CHECK-NEXT: ret13 %y = load <2 x i1>, ptr %x14 %z = sext <2 x i1> %y to <2 x i16>15 ret <2 x i16> %z16}17 18define <2 x i16> @sextload_v2i8_v2i16(ptr %x) {19; CHECK-LABEL: sextload_v2i8_v2i16:20; CHECK: # %bb.0:21; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma22; CHECK-NEXT: vle8.v v9, (a0)23; CHECK-NEXT: vsext.vf2 v8, v924; CHECK-NEXT: ret25 %y = load <2 x i8>, ptr %x26 %z = sext <2 x i8> %y to <2 x i16>27 ret <2 x i16> %z28}29 30define <2 x i16> @zextload_v2i8_v2i16(ptr %x) {31; CHECK-LABEL: zextload_v2i8_v2i16:32; CHECK: # %bb.0:33; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma34; CHECK-NEXT: vle8.v v9, (a0)35; CHECK-NEXT: vzext.vf2 v8, v936; CHECK-NEXT: ret37 %y = load <2 x i8>, ptr %x38 %z = zext <2 x i8> %y to <2 x i16>39 ret <2 x i16> %z40}41 42define <2 x i32> @sextload_v2i8_v2i32(ptr %x) {43; CHECK-LABEL: sextload_v2i8_v2i32:44; CHECK: # %bb.0:45; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma46; CHECK-NEXT: vle8.v v9, (a0)47; CHECK-NEXT: vsext.vf4 v8, v948; CHECK-NEXT: ret49 %y = load <2 x i8>, ptr %x50 %z = sext <2 x i8> %y to <2 x i32>51 ret <2 x i32> %z52}53 54define <2 x i32> @zextload_v2i8_v2i32(ptr %x) {55; CHECK-LABEL: zextload_v2i8_v2i32:56; CHECK: # %bb.0:57; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma58; CHECK-NEXT: vle8.v v9, (a0)59; CHECK-NEXT: vzext.vf4 v8, v960; CHECK-NEXT: ret61 %y = load <2 x i8>, ptr %x62 %z = zext <2 x i8> %y to <2 x i32>63 ret <2 x i32> %z64}65 66define <2 x i64> @sextload_v2i8_v2i64(ptr %x) {67; CHECK-LABEL: sextload_v2i8_v2i64:68; CHECK: # %bb.0:69; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma70; CHECK-NEXT: vle8.v v9, (a0)71; CHECK-NEXT: vsext.vf8 v8, v972; CHECK-NEXT: ret73 %y = load <2 x i8>, ptr %x74 %z = sext <2 x i8> %y to <2 x i64>75 ret <2 x i64> %z76}77 78define <2 x i64> @zextload_v2i8_v2i64(ptr %x) {79; CHECK-LABEL: zextload_v2i8_v2i64:80; CHECK: # %bb.0:81; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma82; CHECK-NEXT: vle8.v v9, (a0)83; CHECK-NEXT: vzext.vf8 v8, v984; CHECK-NEXT: ret85 %y = load <2 x i8>, ptr %x86 %z = zext <2 x i8> %y to <2 x i64>87 ret <2 x i64> %z88}89 90define <4 x i16> @sextload_v4i8_v4i16(ptr %x) {91; CHECK-LABEL: sextload_v4i8_v4i16:92; CHECK: # %bb.0:93; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma94; CHECK-NEXT: vle8.v v9, (a0)95; CHECK-NEXT: vsext.vf2 v8, v996; CHECK-NEXT: ret97 %y = load <4 x i8>, ptr %x98 %z = sext <4 x i8> %y to <4 x i16>99 ret <4 x i16> %z100}101 102define <4 x i16> @zextload_v4i8_v4i16(ptr %x) {103; CHECK-LABEL: zextload_v4i8_v4i16:104; CHECK: # %bb.0:105; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma106; CHECK-NEXT: vle8.v v9, (a0)107; CHECK-NEXT: vzext.vf2 v8, v9108; CHECK-NEXT: ret109 %y = load <4 x i8>, ptr %x110 %z = zext <4 x i8> %y to <4 x i16>111 ret <4 x i16> %z112}113 114define <4 x i32> @sextload_v4i8_v4i32(ptr %x) {115; CHECK-LABEL: sextload_v4i8_v4i32:116; CHECK: # %bb.0:117; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma118; CHECK-NEXT: vle8.v v9, (a0)119; CHECK-NEXT: vsext.vf4 v8, v9120; CHECK-NEXT: ret121 %y = load <4 x i8>, ptr %x122 %z = sext <4 x i8> %y to <4 x i32>123 ret <4 x i32> %z124}125 126define <4 x i32> @zextload_v4i8_v4i32(ptr %x) {127; CHECK-LABEL: zextload_v4i8_v4i32:128; CHECK: # %bb.0:129; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma130; CHECK-NEXT: vle8.v v9, (a0)131; CHECK-NEXT: vzext.vf4 v8, v9132; CHECK-NEXT: ret133 %y = load <4 x i8>, ptr %x134 %z = zext <4 x i8> %y to <4 x i32>135 ret <4 x i32> %z136}137 138define <4 x i64> @sextload_v4i8_v4i64(ptr %x) {139; CHECK-LABEL: sextload_v4i8_v4i64:140; CHECK: # %bb.0:141; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma142; CHECK-NEXT: vle8.v v10, (a0)143; CHECK-NEXT: vsext.vf8 v8, v10144; CHECK-NEXT: ret145 %y = load <4 x i8>, ptr %x146 %z = sext <4 x i8> %y to <4 x i64>147 ret <4 x i64> %z148}149 150define <4 x i64> @zextload_v4i8_v4i64(ptr %x) {151; CHECK-LABEL: zextload_v4i8_v4i64:152; CHECK: # %bb.0:153; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma154; CHECK-NEXT: vle8.v v10, (a0)155; CHECK-NEXT: vzext.vf8 v8, v10156; CHECK-NEXT: ret157 %y = load <4 x i8>, ptr %x158 %z = zext <4 x i8> %y to <4 x i64>159 ret <4 x i64> %z160}161 162define <8 x i16> @sextload_v8i8_v8i16(ptr %x) {163; CHECK-LABEL: sextload_v8i8_v8i16:164; CHECK: # %bb.0:165; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma166; CHECK-NEXT: vle8.v v9, (a0)167; CHECK-NEXT: vsext.vf2 v8, v9168; CHECK-NEXT: ret169 %y = load <8 x i8>, ptr %x170 %z = sext <8 x i8> %y to <8 x i16>171 ret <8 x i16> %z172}173 174define <8 x i16> @zextload_v8i8_v8i16(ptr %x) {175; CHECK-LABEL: zextload_v8i8_v8i16:176; CHECK: # %bb.0:177; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma178; CHECK-NEXT: vle8.v v9, (a0)179; CHECK-NEXT: vzext.vf2 v8, v9180; CHECK-NEXT: ret181 %y = load <8 x i8>, ptr %x182 %z = zext <8 x i8> %y to <8 x i16>183 ret <8 x i16> %z184}185 186define <8 x i32> @sextload_v8i8_v8i32(ptr %x) {187; CHECK-LABEL: sextload_v8i8_v8i32:188; CHECK: # %bb.0:189; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma190; CHECK-NEXT: vle8.v v10, (a0)191; CHECK-NEXT: vsext.vf4 v8, v10192; CHECK-NEXT: ret193 %y = load <8 x i8>, ptr %x194 %z = sext <8 x i8> %y to <8 x i32>195 ret <8 x i32> %z196}197 198define <8 x i32> @zextload_v8i8_v8i32(ptr %x) {199; CHECK-LABEL: zextload_v8i8_v8i32:200; CHECK: # %bb.0:201; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma202; CHECK-NEXT: vle8.v v10, (a0)203; CHECK-NEXT: vzext.vf4 v8, v10204; CHECK-NEXT: ret205 %y = load <8 x i8>, ptr %x206 %z = zext <8 x i8> %y to <8 x i32>207 ret <8 x i32> %z208}209 210define <8 x i64> @sextload_v8i8_v8i64(ptr %x) {211; CHECK-LABEL: sextload_v8i8_v8i64:212; CHECK: # %bb.0:213; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma214; CHECK-NEXT: vle8.v v12, (a0)215; CHECK-NEXT: vsext.vf8 v8, v12216; CHECK-NEXT: ret217 %y = load <8 x i8>, ptr %x218 %z = sext <8 x i8> %y to <8 x i64>219 ret <8 x i64> %z220}221 222define <8 x i64> @zextload_v8i8_v8i64(ptr %x) {223; CHECK-LABEL: zextload_v8i8_v8i64:224; CHECK: # %bb.0:225; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma226; CHECK-NEXT: vle8.v v12, (a0)227; CHECK-NEXT: vzext.vf8 v8, v12228; CHECK-NEXT: ret229 %y = load <8 x i8>, ptr %x230 %z = zext <8 x i8> %y to <8 x i64>231 ret <8 x i64> %z232}233 234define <16 x i16> @sextload_v16i8_v16i16(ptr %x) {235; CHECK-LABEL: sextload_v16i8_v16i16:236; CHECK: # %bb.0:237; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma238; CHECK-NEXT: vle8.v v10, (a0)239; CHECK-NEXT: vsext.vf2 v8, v10240; CHECK-NEXT: ret241 %y = load <16 x i8>, ptr %x242 %z = sext <16 x i8> %y to <16 x i16>243 ret <16 x i16> %z244}245 246define <16 x i16> @zextload_v16i8_v16i16(ptr %x) {247; CHECK-LABEL: zextload_v16i8_v16i16:248; CHECK: # %bb.0:249; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma250; CHECK-NEXT: vle8.v v10, (a0)251; CHECK-NEXT: vzext.vf2 v8, v10252; CHECK-NEXT: ret253 %y = load <16 x i8>, ptr %x254 %z = zext <16 x i8> %y to <16 x i16>255 ret <16 x i16> %z256}257 258define <16 x i32> @sextload_v16i8_v16i32(ptr %x) {259; CHECK-LABEL: sextload_v16i8_v16i32:260; CHECK: # %bb.0:261; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma262; CHECK-NEXT: vle8.v v12, (a0)263; CHECK-NEXT: vsext.vf4 v8, v12264; CHECK-NEXT: ret265 %y = load <16 x i8>, ptr %x266 %z = sext <16 x i8> %y to <16 x i32>267 ret <16 x i32> %z268}269 270define <16 x i32> @zextload_v16i8_v16i32(ptr %x) {271; CHECK-LABEL: zextload_v16i8_v16i32:272; CHECK: # %bb.0:273; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma274; CHECK-NEXT: vle8.v v12, (a0)275; CHECK-NEXT: vzext.vf4 v8, v12276; CHECK-NEXT: ret277 %y = load <16 x i8>, ptr %x278 %z = zext <16 x i8> %y to <16 x i32>279 ret <16 x i32> %z280}281 282define <16 x i64> @sextload_v16i8_v16i64(ptr %x) {283; CHECK-LABEL: sextload_v16i8_v16i64:284; CHECK: # %bb.0:285; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma286; CHECK-NEXT: vle8.v v16, (a0)287; CHECK-NEXT: vsext.vf8 v8, v16288; CHECK-NEXT: ret289 %y = load <16 x i8>, ptr %x290 %z = sext <16 x i8> %y to <16 x i64>291 ret <16 x i64> %z292}293 294define <16 x i64> @zextload_v16i8_v16i64(ptr %x) {295; CHECK-LABEL: zextload_v16i8_v16i64:296; CHECK: # %bb.0:297; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma298; CHECK-NEXT: vle8.v v16, (a0)299; CHECK-NEXT: vzext.vf8 v8, v16300; CHECK-NEXT: ret301 %y = load <16 x i8>, ptr %x302 %z = zext <16 x i8> %y to <16 x i64>303 ret <16 x i64> %z304}305 306define void @truncstore_v2i8_v2i1(<2 x i8> %x, ptr %z) {307; CHECK-LABEL: truncstore_v2i8_v2i1:308; CHECK: # %bb.0:309; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma310; CHECK-NEXT: vand.vi v8, v8, 1311; CHECK-NEXT: vmsne.vi v0, v8, 0312; CHECK-NEXT: vmv.v.i v8, 0313; CHECK-NEXT: vmerge.vim v8, v8, 1, v0314; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma315; CHECK-NEXT: vmv.v.i v9, 0316; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma317; CHECK-NEXT: vmv.v.v v9, v8318; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma319; CHECK-NEXT: vmsne.vi v8, v9, 0320; CHECK-NEXT: vsm.v v8, (a0)321; CHECK-NEXT: ret322 %y = trunc <2 x i8> %x to <2 x i1>323 store <2 x i1> %y, ptr %z324 ret void325}326 327define void @truncstore_v2i16_v2i8(<2 x i16> %x, ptr %z) {328; CHECK-LABEL: truncstore_v2i16_v2i8:329; CHECK: # %bb.0:330; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma331; CHECK-NEXT: vnsrl.wi v8, v8, 0332; CHECK-NEXT: vse8.v v8, (a0)333; CHECK-NEXT: ret334 %y = trunc <2 x i16> %x to <2 x i8>335 store <2 x i8> %y, ptr %z336 ret void337}338 339define <2 x i32> @sextload_v2i16_v2i32(ptr %x) {340; CHECK-LABEL: sextload_v2i16_v2i32:341; CHECK: # %bb.0:342; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma343; CHECK-NEXT: vle16.v v9, (a0)344; CHECK-NEXT: vsext.vf2 v8, v9345; CHECK-NEXT: ret346 %y = load <2 x i16>, ptr %x347 %z = sext <2 x i16> %y to <2 x i32>348 ret <2 x i32> %z349}350 351define <2 x i32> @zextload_v2i16_v2i32(ptr %x) {352; CHECK-LABEL: zextload_v2i16_v2i32:353; CHECK: # %bb.0:354; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma355; CHECK-NEXT: vle16.v v9, (a0)356; CHECK-NEXT: vzext.vf2 v8, v9357; CHECK-NEXT: ret358 %y = load <2 x i16>, ptr %x359 %z = zext <2 x i16> %y to <2 x i32>360 ret <2 x i32> %z361}362 363define <2 x i64> @sextload_v2i16_v2i64(ptr %x) {364; CHECK-LABEL: sextload_v2i16_v2i64:365; CHECK: # %bb.0:366; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma367; CHECK-NEXT: vle16.v v9, (a0)368; CHECK-NEXT: vsext.vf4 v8, v9369; CHECK-NEXT: ret370 %y = load <2 x i16>, ptr %x371 %z = sext <2 x i16> %y to <2 x i64>372 ret <2 x i64> %z373}374 375define <2 x i64> @zextload_v2i16_v2i64(ptr %x) {376; CHECK-LABEL: zextload_v2i16_v2i64:377; CHECK: # %bb.0:378; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma379; CHECK-NEXT: vle16.v v9, (a0)380; CHECK-NEXT: vzext.vf4 v8, v9381; CHECK-NEXT: ret382 %y = load <2 x i16>, ptr %x383 %z = zext <2 x i16> %y to <2 x i64>384 ret <2 x i64> %z385}386 387define void @truncstore_v4i16_v4i8(<4 x i16> %x, ptr %z) {388; CHECK-LABEL: truncstore_v4i16_v4i8:389; CHECK: # %bb.0:390; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma391; CHECK-NEXT: vnsrl.wi v8, v8, 0392; CHECK-NEXT: vse8.v v8, (a0)393; CHECK-NEXT: ret394 %y = trunc <4 x i16> %x to <4 x i8>395 store <4 x i8> %y, ptr %z396 ret void397}398 399define <4 x i32> @sextload_v4i16_v4i32(ptr %x) {400; CHECK-LABEL: sextload_v4i16_v4i32:401; CHECK: # %bb.0:402; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma403; CHECK-NEXT: vle16.v v9, (a0)404; CHECK-NEXT: vsext.vf2 v8, v9405; CHECK-NEXT: ret406 %y = load <4 x i16>, ptr %x407 %z = sext <4 x i16> %y to <4 x i32>408 ret <4 x i32> %z409}410 411define <4 x i32> @zextload_v4i16_v4i32(ptr %x) {412; CHECK-LABEL: zextload_v4i16_v4i32:413; CHECK: # %bb.0:414; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma415; CHECK-NEXT: vle16.v v9, (a0)416; CHECK-NEXT: vzext.vf2 v8, v9417; CHECK-NEXT: ret418 %y = load <4 x i16>, ptr %x419 %z = zext <4 x i16> %y to <4 x i32>420 ret <4 x i32> %z421}422 423define <4 x i64> @sextload_v4i16_v4i64(ptr %x) {424; CHECK-LABEL: sextload_v4i16_v4i64:425; CHECK: # %bb.0:426; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma427; CHECK-NEXT: vle16.v v10, (a0)428; CHECK-NEXT: vsext.vf4 v8, v10429; CHECK-NEXT: ret430 %y = load <4 x i16>, ptr %x431 %z = sext <4 x i16> %y to <4 x i64>432 ret <4 x i64> %z433}434 435define <4 x i64> @zextload_v4i16_v4i64(ptr %x) {436; CHECK-LABEL: zextload_v4i16_v4i64:437; CHECK: # %bb.0:438; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma439; CHECK-NEXT: vle16.v v10, (a0)440; CHECK-NEXT: vzext.vf4 v8, v10441; CHECK-NEXT: ret442 %y = load <4 x i16>, ptr %x443 %z = zext <4 x i16> %y to <4 x i64>444 ret <4 x i64> %z445}446 447define void @truncstore_v8i16_v8i8(<8 x i16> %x, ptr %z) {448; CHECK-LABEL: truncstore_v8i16_v8i8:449; CHECK: # %bb.0:450; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma451; CHECK-NEXT: vnsrl.wi v8, v8, 0452; CHECK-NEXT: vse8.v v8, (a0)453; CHECK-NEXT: ret454 %y = trunc <8 x i16> %x to <8 x i8>455 store <8 x i8> %y, ptr %z456 ret void457}458 459define <8 x i32> @sextload_v8i16_v8i32(ptr %x) {460; CHECK-LABEL: sextload_v8i16_v8i32:461; CHECK: # %bb.0:462; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma463; CHECK-NEXT: vle16.v v10, (a0)464; CHECK-NEXT: vsext.vf2 v8, v10465; CHECK-NEXT: ret466 %y = load <8 x i16>, ptr %x467 %z = sext <8 x i16> %y to <8 x i32>468 ret <8 x i32> %z469}470 471define <8 x i32> @zextload_v8i16_v8i32(ptr %x) {472; CHECK-LABEL: zextload_v8i16_v8i32:473; CHECK: # %bb.0:474; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma475; CHECK-NEXT: vle16.v v10, (a0)476; CHECK-NEXT: vzext.vf2 v8, v10477; CHECK-NEXT: ret478 %y = load <8 x i16>, ptr %x479 %z = zext <8 x i16> %y to <8 x i32>480 ret <8 x i32> %z481}482 483define <8 x i64> @sextload_v8i16_v8i64(ptr %x) {484; CHECK-LABEL: sextload_v8i16_v8i64:485; CHECK: # %bb.0:486; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma487; CHECK-NEXT: vle16.v v12, (a0)488; CHECK-NEXT: vsext.vf4 v8, v12489; CHECK-NEXT: ret490 %y = load <8 x i16>, ptr %x491 %z = sext <8 x i16> %y to <8 x i64>492 ret <8 x i64> %z493}494 495define <8 x i64> @zextload_v8i16_v8i64(ptr %x) {496; CHECK-LABEL: zextload_v8i16_v8i64:497; CHECK: # %bb.0:498; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma499; CHECK-NEXT: vle16.v v12, (a0)500; CHECK-NEXT: vzext.vf4 v8, v12501; CHECK-NEXT: ret502 %y = load <8 x i16>, ptr %x503 %z = zext <8 x i16> %y to <8 x i64>504 ret <8 x i64> %z505}506 507define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %z) {508; CHECK-LABEL: truncstore_v16i16_v16i8:509; CHECK: # %bb.0:510; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma511; CHECK-NEXT: vnsrl.wi v10, v8, 0512; CHECK-NEXT: vse8.v v10, (a0)513; CHECK-NEXT: ret514 %y = trunc <16 x i16> %x to <16 x i8>515 store <16 x i8> %y, ptr %z516 ret void517}518 519define <16 x i32> @sextload_v16i16_v16i32(ptr %x) {520; CHECK-LABEL: sextload_v16i16_v16i32:521; CHECK: # %bb.0:522; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma523; CHECK-NEXT: vle16.v v12, (a0)524; CHECK-NEXT: vsext.vf2 v8, v12525; CHECK-NEXT: ret526 %y = load <16 x i16>, ptr %x527 %z = sext <16 x i16> %y to <16 x i32>528 ret <16 x i32> %z529}530 531define <16 x i32> @zextload_v16i16_v16i32(ptr %x) {532; CHECK-LABEL: zextload_v16i16_v16i32:533; CHECK: # %bb.0:534; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma535; CHECK-NEXT: vle16.v v12, (a0)536; CHECK-NEXT: vzext.vf2 v8, v12537; CHECK-NEXT: ret538 %y = load <16 x i16>, ptr %x539 %z = zext <16 x i16> %y to <16 x i32>540 ret <16 x i32> %z541}542 543define <16 x i64> @sextload_v16i16_v16i64(ptr %x) {544; CHECK-LABEL: sextload_v16i16_v16i64:545; CHECK: # %bb.0:546; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma547; CHECK-NEXT: vle16.v v16, (a0)548; CHECK-NEXT: vsext.vf4 v8, v16549; CHECK-NEXT: ret550 %y = load <16 x i16>, ptr %x551 %z = sext <16 x i16> %y to <16 x i64>552 ret <16 x i64> %z553}554 555define <16 x i64> @zextload_v16i16_v16i64(ptr %x) {556; CHECK-LABEL: zextload_v16i16_v16i64:557; CHECK: # %bb.0:558; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma559; CHECK-NEXT: vle16.v v16, (a0)560; CHECK-NEXT: vzext.vf4 v8, v16561; CHECK-NEXT: ret562 %y = load <16 x i16>, ptr %x563 %z = zext <16 x i16> %y to <16 x i64>564 ret <16 x i64> %z565}566 567define void @truncstore_v2i32_v2i8(<2 x i32> %x, ptr %z) {568; CHECK-LABEL: truncstore_v2i32_v2i8:569; CHECK: # %bb.0:570; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma571; CHECK-NEXT: vnsrl.wi v8, v8, 0572; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma573; CHECK-NEXT: vnsrl.wi v8, v8, 0574; CHECK-NEXT: vse8.v v8, (a0)575; CHECK-NEXT: ret576 %y = trunc <2 x i32> %x to <2 x i8>577 store <2 x i8> %y, ptr %z578 ret void579}580 581define void @truncstore_v2i32_v2i16(<2 x i32> %x, ptr %z) {582; CHECK-LABEL: truncstore_v2i32_v2i16:583; CHECK: # %bb.0:584; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma585; CHECK-NEXT: vnsrl.wi v8, v8, 0586; CHECK-NEXT: vse16.v v8, (a0)587; CHECK-NEXT: ret588 %y = trunc <2 x i32> %x to <2 x i16>589 store <2 x i16> %y, ptr %z590 ret void591}592 593define <2 x i64> @sextload_v2i32_v2i64(ptr %x) {594; CHECK-LABEL: sextload_v2i32_v2i64:595; CHECK: # %bb.0:596; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma597; CHECK-NEXT: vle32.v v9, (a0)598; CHECK-NEXT: vsext.vf2 v8, v9599; CHECK-NEXT: ret600 %y = load <2 x i32>, ptr %x601 %z = sext <2 x i32> %y to <2 x i64>602 ret <2 x i64> %z603}604 605define <2 x i64> @zextload_v2i32_v2i64(ptr %x) {606; CHECK-LABEL: zextload_v2i32_v2i64:607; CHECK: # %bb.0:608; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma609; CHECK-NEXT: vle32.v v9, (a0)610; CHECK-NEXT: vzext.vf2 v8, v9611; CHECK-NEXT: ret612 %y = load <2 x i32>, ptr %x613 %z = zext <2 x i32> %y to <2 x i64>614 ret <2 x i64> %z615}616 617define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %z) {618; CHECK-LABEL: truncstore_v4i32_v4i8:619; CHECK: # %bb.0:620; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma621; CHECK-NEXT: vnsrl.wi v8, v8, 0622; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma623; CHECK-NEXT: vnsrl.wi v8, v8, 0624; CHECK-NEXT: vse8.v v8, (a0)625; CHECK-NEXT: ret626 %y = trunc <4 x i32> %x to <4 x i8>627 store <4 x i8> %y, ptr %z628 ret void629}630 631define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %z) {632; CHECK-LABEL: truncstore_v4i32_v4i16:633; CHECK: # %bb.0:634; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma635; CHECK-NEXT: vnsrl.wi v8, v8, 0636; CHECK-NEXT: vse16.v v8, (a0)637; CHECK-NEXT: ret638 %y = trunc <4 x i32> %x to <4 x i16>639 store <4 x i16> %y, ptr %z640 ret void641}642 643define <4 x i64> @sextload_v4i32_v4i64(ptr %x) {644; CHECK-LABEL: sextload_v4i32_v4i64:645; CHECK: # %bb.0:646; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma647; CHECK-NEXT: vle32.v v10, (a0)648; CHECK-NEXT: vsext.vf2 v8, v10649; CHECK-NEXT: ret650 %y = load <4 x i32>, ptr %x651 %z = sext <4 x i32> %y to <4 x i64>652 ret <4 x i64> %z653}654 655define <4 x i64> @zextload_v4i32_v4i64(ptr %x) {656; CHECK-LABEL: zextload_v4i32_v4i64:657; CHECK: # %bb.0:658; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma659; CHECK-NEXT: vle32.v v10, (a0)660; CHECK-NEXT: vzext.vf2 v8, v10661; CHECK-NEXT: ret662 %y = load <4 x i32>, ptr %x663 %z = zext <4 x i32> %y to <4 x i64>664 ret <4 x i64> %z665}666 667define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %z) {668; CHECK-LABEL: truncstore_v8i32_v8i8:669; CHECK: # %bb.0:670; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma671; CHECK-NEXT: vnsrl.wi v10, v8, 0672; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma673; CHECK-NEXT: vnsrl.wi v8, v10, 0674; CHECK-NEXT: vse8.v v8, (a0)675; CHECK-NEXT: ret676 %y = trunc <8 x i32> %x to <8 x i8>677 store <8 x i8> %y, ptr %z678 ret void679}680 681define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %z) {682; CHECK-LABEL: truncstore_v8i32_v8i16:683; CHECK: # %bb.0:684; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma685; CHECK-NEXT: vnsrl.wi v10, v8, 0686; CHECK-NEXT: vse16.v v10, (a0)687; CHECK-NEXT: ret688 %y = trunc <8 x i32> %x to <8 x i16>689 store <8 x i16> %y, ptr %z690 ret void691}692 693define <8 x i64> @sextload_v8i32_v8i64(ptr %x) {694; CHECK-LABEL: sextload_v8i32_v8i64:695; CHECK: # %bb.0:696; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma697; CHECK-NEXT: vle32.v v12, (a0)698; CHECK-NEXT: vsext.vf2 v8, v12699; CHECK-NEXT: ret700 %y = load <8 x i32>, ptr %x701 %z = sext <8 x i32> %y to <8 x i64>702 ret <8 x i64> %z703}704 705define <8 x i64> @zextload_v8i32_v8i64(ptr %x) {706; CHECK-LABEL: zextload_v8i32_v8i64:707; CHECK: # %bb.0:708; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma709; CHECK-NEXT: vle32.v v12, (a0)710; CHECK-NEXT: vzext.vf2 v8, v12711; CHECK-NEXT: ret712 %y = load <8 x i32>, ptr %x713 %z = zext <8 x i32> %y to <8 x i64>714 ret <8 x i64> %z715}716 717define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %z) {718; CHECK-LABEL: truncstore_v16i32_v16i8:719; CHECK: # %bb.0:720; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma721; CHECK-NEXT: vnsrl.wi v12, v8, 0722; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma723; CHECK-NEXT: vnsrl.wi v8, v12, 0724; CHECK-NEXT: vse8.v v8, (a0)725; CHECK-NEXT: ret726 %y = trunc <16 x i32> %x to <16 x i8>727 store <16 x i8> %y, ptr %z728 ret void729}730 731define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %z) {732; CHECK-LABEL: truncstore_v16i32_v16i16:733; CHECK: # %bb.0:734; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma735; CHECK-NEXT: vnsrl.wi v12, v8, 0736; CHECK-NEXT: vse16.v v12, (a0)737; CHECK-NEXT: ret738 %y = trunc <16 x i32> %x to <16 x i16>739 store <16 x i16> %y, ptr %z740 ret void741}742 743define <16 x i64> @sextload_v16i32_v16i64(ptr %x) {744; CHECK-LABEL: sextload_v16i32_v16i64:745; CHECK: # %bb.0:746; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma747; CHECK-NEXT: vle32.v v16, (a0)748; CHECK-NEXT: vsext.vf2 v8, v16749; CHECK-NEXT: ret750 %y = load <16 x i32>, ptr %x751 %z = sext <16 x i32> %y to <16 x i64>752 ret <16 x i64> %z753}754 755define <16 x i64> @zextload_v16i32_v16i64(ptr %x) {756; CHECK-LABEL: zextload_v16i32_v16i64:757; CHECK: # %bb.0:758; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma759; CHECK-NEXT: vle32.v v16, (a0)760; CHECK-NEXT: vzext.vf2 v8, v16761; CHECK-NEXT: ret762 %y = load <16 x i32>, ptr %x763 %z = zext <16 x i32> %y to <16 x i64>764 ret <16 x i64> %z765}766 767define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %z) {768; CHECK-LABEL: truncstore_v2i64_v2i8:769; CHECK: # %bb.0:770; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma771; CHECK-NEXT: vnsrl.wi v8, v8, 0772; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma773; CHECK-NEXT: vnsrl.wi v8, v8, 0774; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma775; CHECK-NEXT: vnsrl.wi v8, v8, 0776; CHECK-NEXT: vse8.v v8, (a0)777; CHECK-NEXT: ret778 %y = trunc <2 x i64> %x to <2 x i8>779 store <2 x i8> %y, ptr %z780 ret void781}782 783define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %z) {784; CHECK-LABEL: truncstore_v2i64_v2i16:785; CHECK: # %bb.0:786; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma787; CHECK-NEXT: vnsrl.wi v8, v8, 0788; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma789; CHECK-NEXT: vnsrl.wi v8, v8, 0790; CHECK-NEXT: vse16.v v8, (a0)791; CHECK-NEXT: ret792 %y = trunc <2 x i64> %x to <2 x i16>793 store <2 x i16> %y, ptr %z794 ret void795}796 797define void @truncstore_v2i64_v2i32(<2 x i64> %x, ptr %z) {798; CHECK-LABEL: truncstore_v2i64_v2i32:799; CHECK: # %bb.0:800; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma801; CHECK-NEXT: vnsrl.wi v8, v8, 0802; CHECK-NEXT: vse32.v v8, (a0)803; CHECK-NEXT: ret804 %y = trunc <2 x i64> %x to <2 x i32>805 store <2 x i32> %y, ptr %z806 ret void807}808 809define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %z) {810; CHECK-LABEL: truncstore_v4i64_v4i8:811; CHECK: # %bb.0:812; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma813; CHECK-NEXT: vnsrl.wi v10, v8, 0814; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma815; CHECK-NEXT: vnsrl.wi v8, v10, 0816; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma817; CHECK-NEXT: vnsrl.wi v8, v8, 0818; CHECK-NEXT: vse8.v v8, (a0)819; CHECK-NEXT: ret820 %y = trunc <4 x i64> %x to <4 x i8>821 store <4 x i8> %y, ptr %z822 ret void823}824 825define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %z) {826; CHECK-LABEL: truncstore_v4i64_v4i16:827; CHECK: # %bb.0:828; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma829; CHECK-NEXT: vnsrl.wi v10, v8, 0830; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma831; CHECK-NEXT: vnsrl.wi v8, v10, 0832; CHECK-NEXT: vse16.v v8, (a0)833; CHECK-NEXT: ret834 %y = trunc <4 x i64> %x to <4 x i16>835 store <4 x i16> %y, ptr %z836 ret void837}838 839define void @truncstore_v4i64_v4i32(<4 x i64> %x, ptr %z) {840; CHECK-LABEL: truncstore_v4i64_v4i32:841; CHECK: # %bb.0:842; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma843; CHECK-NEXT: vnsrl.wi v10, v8, 0844; CHECK-NEXT: vse32.v v10, (a0)845; CHECK-NEXT: ret846 %y = trunc <4 x i64> %x to <4 x i32>847 store <4 x i32> %y, ptr %z848 ret void849}850 851define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %z) {852; CHECK-LABEL: truncstore_v8i64_v8i8:853; CHECK: # %bb.0:854; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma855; CHECK-NEXT: vnsrl.wi v12, v8, 0856; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma857; CHECK-NEXT: vnsrl.wi v8, v12, 0858; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma859; CHECK-NEXT: vnsrl.wi v8, v8, 0860; CHECK-NEXT: vse8.v v8, (a0)861; CHECK-NEXT: ret862 %y = trunc <8 x i64> %x to <8 x i8>863 store <8 x i8> %y, ptr %z864 ret void865}866 867define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %z) {868; CHECK-LABEL: truncstore_v8i64_v8i16:869; CHECK: # %bb.0:870; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma871; CHECK-NEXT: vnsrl.wi v12, v8, 0872; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma873; CHECK-NEXT: vnsrl.wi v8, v12, 0874; CHECK-NEXT: vse16.v v8, (a0)875; CHECK-NEXT: ret876 %y = trunc <8 x i64> %x to <8 x i16>877 store <8 x i16> %y, ptr %z878 ret void879}880 881define void @truncstore_v8i64_v8i32(<8 x i64> %x, ptr %z) {882; CHECK-LABEL: truncstore_v8i64_v8i32:883; CHECK: # %bb.0:884; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma885; CHECK-NEXT: vnsrl.wi v12, v8, 0886; CHECK-NEXT: vse32.v v12, (a0)887; CHECK-NEXT: ret888 %y = trunc <8 x i64> %x to <8 x i32>889 store <8 x i32> %y, ptr %z890 ret void891}892 893define void @truncstore_v16i64_v16i8(<16 x i64> %x, ptr %z) {894; CHECK-LABEL: truncstore_v16i64_v16i8:895; CHECK: # %bb.0:896; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma897; CHECK-NEXT: vnsrl.wi v16, v8, 0898; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma899; CHECK-NEXT: vnsrl.wi v8, v16, 0900; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma901; CHECK-NEXT: vnsrl.wi v10, v8, 0902; CHECK-NEXT: vse8.v v10, (a0)903; CHECK-NEXT: ret904 %y = trunc <16 x i64> %x to <16 x i8>905 store <16 x i8> %y, ptr %z906 ret void907}908 909define void @truncstore_v16i64_v16i16(<16 x i64> %x, ptr %z) {910; CHECK-LABEL: truncstore_v16i64_v16i16:911; CHECK: # %bb.0:912; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma913; CHECK-NEXT: vnsrl.wi v16, v8, 0914; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma915; CHECK-NEXT: vnsrl.wi v8, v16, 0916; CHECK-NEXT: vse16.v v8, (a0)917; CHECK-NEXT: ret918 %y = trunc <16 x i64> %x to <16 x i16>919 store <16 x i16> %y, ptr %z920 ret void921}922 923define void @truncstore_v16i64_v16i32(<16 x i64> %x, ptr %z) {924; CHECK-LABEL: truncstore_v16i64_v16i32:925; CHECK: # %bb.0:926; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma927; CHECK-NEXT: vnsrl.wi v16, v8, 0928; CHECK-NEXT: vse32.v v16, (a0)929; CHECK-NEXT: ret930 %y = trunc <16 x i64> %x to <16 x i32>931 store <16 x i32> %y, ptr %z932 ret void933}934