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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zbs -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32ZBS6; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zbs -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64ZBS7 8define i1 @extractelt_v1i1(ptr %x, i64 %idx) nounwind {9; CHECK-LABEL: extractelt_v1i1:10; CHECK: # %bb.0:11; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma12; CHECK-NEXT: vle8.v v8, (a0)13; CHECK-NEXT: vmseq.vi v0, v8, 014; CHECK-NEXT: vmv.s.x v8, zero15; CHECK-NEXT: vmerge.vim v8, v8, 1, v016; CHECK-NEXT: vslidedown.vx v8, v8, a117; CHECK-NEXT: vmv.x.s a0, v818; CHECK-NEXT: ret19 %a = load <1 x i8>, ptr %x20 %b = icmp eq <1 x i8> %a, zeroinitializer21 %c = extractelement <1 x i1> %b, i64 %idx22 ret i1 %c23}24 25define i1 @extractelt_v2i1(ptr %x, i64 %idx) nounwind {26; CHECK-LABEL: extractelt_v2i1:27; CHECK: # %bb.0:28; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma29; CHECK-NEXT: vle8.v v8, (a0)30; CHECK-NEXT: vmseq.vi v0, v8, 031; CHECK-NEXT: vmv.v.i v8, 032; CHECK-NEXT: vmerge.vim v8, v8, 1, v033; CHECK-NEXT: vslidedown.vx v8, v8, a134; CHECK-NEXT: vmv.x.s a0, v835; CHECK-NEXT: ret36 %a = load <2 x i8>, ptr %x37 %b = icmp eq <2 x i8> %a, zeroinitializer38 %c = extractelement <2 x i1> %b, i64 %idx39 ret i1 %c40}41 42define i1 @extractelt_v4i1(ptr %x, i64 %idx) nounwind {43; CHECK-LABEL: extractelt_v4i1:44; CHECK: # %bb.0:45; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma46; CHECK-NEXT: vle8.v v8, (a0)47; CHECK-NEXT: vmseq.vi v0, v8, 048; CHECK-NEXT: vmv.v.i v8, 049; CHECK-NEXT: vmerge.vim v8, v8, 1, v050; CHECK-NEXT: vslidedown.vx v8, v8, a151; CHECK-NEXT: vmv.x.s a0, v852; CHECK-NEXT: ret53 %a = load <4 x i8>, ptr %x54 %b = icmp eq <4 x i8> %a, zeroinitializer55 %c = extractelement <4 x i1> %b, i64 %idx56 ret i1 %c57}58 59define i1 @extractelt_v8i1(ptr %x, i64 %idx) nounwind {60; RV32-LABEL: extractelt_v8i1:61; RV32: # %bb.0:62; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma63; RV32-NEXT: vle8.v v8, (a0)64; RV32-NEXT: vmseq.vi v8, v8, 065; RV32-NEXT: vmv.x.s a0, v866; RV32-NEXT: srl a0, a0, a167; RV32-NEXT: andi a0, a0, 168; RV32-NEXT: ret69;70; RV64-LABEL: extractelt_v8i1:71; RV64: # %bb.0:72; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma73; RV64-NEXT: vle8.v v8, (a0)74; RV64-NEXT: vmseq.vi v8, v8, 075; RV64-NEXT: vmv.x.s a0, v876; RV64-NEXT: srl a0, a0, a177; RV64-NEXT: andi a0, a0, 178; RV64-NEXT: ret79;80; RV32ZBS-LABEL: extractelt_v8i1:81; RV32ZBS: # %bb.0:82; RV32ZBS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma83; RV32ZBS-NEXT: vle8.v v8, (a0)84; RV32ZBS-NEXT: vmseq.vi v8, v8, 085; RV32ZBS-NEXT: vmv.x.s a0, v886; RV32ZBS-NEXT: bext a0, a0, a187; RV32ZBS-NEXT: ret88;89; RV64ZBS-LABEL: extractelt_v8i1:90; RV64ZBS: # %bb.0:91; RV64ZBS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma92; RV64ZBS-NEXT: vle8.v v8, (a0)93; RV64ZBS-NEXT: vmseq.vi v8, v8, 094; RV64ZBS-NEXT: vmv.x.s a0, v895; RV64ZBS-NEXT: bext a0, a0, a196; RV64ZBS-NEXT: ret97 %a = load <8 x i8>, ptr %x98 %b = icmp eq <8 x i8> %a, zeroinitializer99 %c = extractelement <8 x i1> %b, i64 %idx100 ret i1 %c101}102 103define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {104; RV32-LABEL: extractelt_v16i1:105; RV32: # %bb.0:106; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma107; RV32-NEXT: vle8.v v8, (a0)108; RV32-NEXT: vmseq.vi v8, v8, 0109; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma110; RV32-NEXT: vmv.x.s a0, v8111; RV32-NEXT: srl a0, a0, a1112; RV32-NEXT: andi a0, a0, 1113; RV32-NEXT: ret114;115; RV64-LABEL: extractelt_v16i1:116; RV64: # %bb.0:117; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma118; RV64-NEXT: vle8.v v8, (a0)119; RV64-NEXT: vmseq.vi v8, v8, 0120; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma121; RV64-NEXT: vmv.x.s a0, v8122; RV64-NEXT: srl a0, a0, a1123; RV64-NEXT: andi a0, a0, 1124; RV64-NEXT: ret125;126; RV32ZBS-LABEL: extractelt_v16i1:127; RV32ZBS: # %bb.0:128; RV32ZBS-NEXT: vsetivli zero, 16, e8, m1, ta, ma129; RV32ZBS-NEXT: vle8.v v8, (a0)130; RV32ZBS-NEXT: vmseq.vi v8, v8, 0131; RV32ZBS-NEXT: vsetvli zero, zero, e16, m2, ta, ma132; RV32ZBS-NEXT: vmv.x.s a0, v8133; RV32ZBS-NEXT: bext a0, a0, a1134; RV32ZBS-NEXT: ret135;136; RV64ZBS-LABEL: extractelt_v16i1:137; RV64ZBS: # %bb.0:138; RV64ZBS-NEXT: vsetivli zero, 16, e8, m1, ta, ma139; RV64ZBS-NEXT: vle8.v v8, (a0)140; RV64ZBS-NEXT: vmseq.vi v8, v8, 0141; RV64ZBS-NEXT: vsetvli zero, zero, e16, m2, ta, ma142; RV64ZBS-NEXT: vmv.x.s a0, v8143; RV64ZBS-NEXT: bext a0, a0, a1144; RV64ZBS-NEXT: ret145 %a = load <16 x i8>, ptr %x146 %b = icmp eq <16 x i8> %a, zeroinitializer147 %c = extractelement <16 x i1> %b, i64 %idx148 ret i1 %c149}150 151define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {152; RV32-LABEL: extractelt_v32i1:153; RV32: # %bb.0:154; RV32-NEXT: li a2, 32155; RV32-NEXT: vsetvli zero, a2, e8, m2, ta, ma156; RV32-NEXT: vle8.v v8, (a0)157; RV32-NEXT: vmseq.vi v10, v8, 0158; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma159; RV32-NEXT: vmv.x.s a0, v10160; RV32-NEXT: srl a0, a0, a1161; RV32-NEXT: andi a0, a0, 1162; RV32-NEXT: ret163;164; RV64-LABEL: extractelt_v32i1:165; RV64: # %bb.0:166; RV64-NEXT: li a2, 32167; RV64-NEXT: vsetvli zero, a2, e8, m2, ta, ma168; RV64-NEXT: vle8.v v8, (a0)169; RV64-NEXT: vmseq.vi v10, v8, 0170; RV64-NEXT: vsetvli zero, zero, e32, m8, ta, ma171; RV64-NEXT: vmv.x.s a0, v10172; RV64-NEXT: srl a0, a0, a1173; RV64-NEXT: andi a0, a0, 1174; RV64-NEXT: ret175;176; RV32ZBS-LABEL: extractelt_v32i1:177; RV32ZBS: # %bb.0:178; RV32ZBS-NEXT: li a2, 32179; RV32ZBS-NEXT: vsetvli zero, a2, e8, m2, ta, ma180; RV32ZBS-NEXT: vle8.v v8, (a0)181; RV32ZBS-NEXT: vmseq.vi v10, v8, 0182; RV32ZBS-NEXT: vsetvli zero, zero, e32, m8, ta, ma183; RV32ZBS-NEXT: vmv.x.s a0, v10184; RV32ZBS-NEXT: bext a0, a0, a1185; RV32ZBS-NEXT: ret186;187; RV64ZBS-LABEL: extractelt_v32i1:188; RV64ZBS: # %bb.0:189; RV64ZBS-NEXT: li a2, 32190; RV64ZBS-NEXT: vsetvli zero, a2, e8, m2, ta, ma191; RV64ZBS-NEXT: vle8.v v8, (a0)192; RV64ZBS-NEXT: vmseq.vi v10, v8, 0193; RV64ZBS-NEXT: vsetvli zero, zero, e32, m8, ta, ma194; RV64ZBS-NEXT: vmv.x.s a0, v10195; RV64ZBS-NEXT: bext a0, a0, a1196; RV64ZBS-NEXT: ret197 %a = load <32 x i8>, ptr %x198 %b = icmp eq <32 x i8> %a, zeroinitializer199 %c = extractelement <32 x i1> %b, i64 %idx200 ret i1 %c201}202 203define i1 @extractelt_v64i1(ptr %x, i64 %idx) nounwind {204; RV32-LABEL: extractelt_v64i1:205; RV32: # %bb.0:206; RV32-NEXT: li a2, 64207; RV32-NEXT: vsetvli zero, a2, e8, m4, ta, ma208; RV32-NEXT: vle8.v v8, (a0)209; RV32-NEXT: vmseq.vi v12, v8, 0210; RV32-NEXT: srli a0, a1, 5211; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma212; RV32-NEXT: vslidedown.vx v8, v12, a0213; RV32-NEXT: vmv.x.s a0, v8214; RV32-NEXT: srl a0, a0, a1215; RV32-NEXT: andi a0, a0, 1216; RV32-NEXT: ret217;218; RV64-LABEL: extractelt_v64i1:219; RV64: # %bb.0:220; RV64-NEXT: li a2, 64221; RV64-NEXT: vsetvli zero, a2, e8, m4, ta, ma222; RV64-NEXT: vle8.v v8, (a0)223; RV64-NEXT: vmseq.vi v12, v8, 0224; RV64-NEXT: vsetvli zero, a2, e64, m1, ta, ma225; RV64-NEXT: vmv.x.s a0, v12226; RV64-NEXT: srl a0, a0, a1227; RV64-NEXT: andi a0, a0, 1228; RV64-NEXT: ret229;230; RV32ZBS-LABEL: extractelt_v64i1:231; RV32ZBS: # %bb.0:232; RV32ZBS-NEXT: li a2, 64233; RV32ZBS-NEXT: vsetvli zero, a2, e8, m4, ta, ma234; RV32ZBS-NEXT: vle8.v v8, (a0)235; RV32ZBS-NEXT: vmseq.vi v12, v8, 0236; RV32ZBS-NEXT: srli a0, a1, 5237; RV32ZBS-NEXT: vsetivli zero, 1, e32, mf2, ta, ma238; RV32ZBS-NEXT: vslidedown.vx v8, v12, a0239; RV32ZBS-NEXT: vmv.x.s a0, v8240; RV32ZBS-NEXT: bext a0, a0, a1241; RV32ZBS-NEXT: ret242;243; RV64ZBS-LABEL: extractelt_v64i1:244; RV64ZBS: # %bb.0:245; RV64ZBS-NEXT: li a2, 64246; RV64ZBS-NEXT: vsetvli zero, a2, e8, m4, ta, ma247; RV64ZBS-NEXT: vle8.v v8, (a0)248; RV64ZBS-NEXT: vmseq.vi v12, v8, 0249; RV64ZBS-NEXT: vsetvli zero, a2, e64, m1, ta, ma250; RV64ZBS-NEXT: vmv.x.s a0, v12251; RV64ZBS-NEXT: bext a0, a0, a1252; RV64ZBS-NEXT: ret253 %a = load <64 x i8>, ptr %x254 %b = icmp eq <64 x i8> %a, zeroinitializer255 %c = extractelement <64 x i1> %b, i64 %idx256 ret i1 %c257}258 259define i1 @extractelt_v128i1(ptr %x, i64 %idx) nounwind {260; RV32-LABEL: extractelt_v128i1:261; RV32: # %bb.0:262; RV32-NEXT: li a2, 128263; RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma264; RV32-NEXT: vle8.v v8, (a0)265; RV32-NEXT: vmseq.vi v16, v8, 0266; RV32-NEXT: srli a0, a1, 5267; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma268; RV32-NEXT: vslidedown.vx v8, v16, a0269; RV32-NEXT: vmv.x.s a0, v8270; RV32-NEXT: srl a0, a0, a1271; RV32-NEXT: andi a0, a0, 1272; RV32-NEXT: ret273;274; RV64-LABEL: extractelt_v128i1:275; RV64: # %bb.0:276; RV64-NEXT: li a2, 128277; RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma278; RV64-NEXT: vle8.v v8, (a0)279; RV64-NEXT: vmseq.vi v16, v8, 0280; RV64-NEXT: srli a0, a1, 6281; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma282; RV64-NEXT: vslidedown.vx v8, v16, a0283; RV64-NEXT: vmv.x.s a0, v8284; RV64-NEXT: srl a0, a0, a1285; RV64-NEXT: andi a0, a0, 1286; RV64-NEXT: ret287;288; RV32ZBS-LABEL: extractelt_v128i1:289; RV32ZBS: # %bb.0:290; RV32ZBS-NEXT: li a2, 128291; RV32ZBS-NEXT: vsetvli zero, a2, e8, m8, ta, ma292; RV32ZBS-NEXT: vle8.v v8, (a0)293; RV32ZBS-NEXT: vmseq.vi v16, v8, 0294; RV32ZBS-NEXT: srli a0, a1, 5295; RV32ZBS-NEXT: vsetivli zero, 1, e32, m1, ta, ma296; RV32ZBS-NEXT: vslidedown.vx v8, v16, a0297; RV32ZBS-NEXT: vmv.x.s a0, v8298; RV32ZBS-NEXT: bext a0, a0, a1299; RV32ZBS-NEXT: ret300;301; RV64ZBS-LABEL: extractelt_v128i1:302; RV64ZBS: # %bb.0:303; RV64ZBS-NEXT: li a2, 128304; RV64ZBS-NEXT: vsetvli zero, a2, e8, m8, ta, ma305; RV64ZBS-NEXT: vle8.v v8, (a0)306; RV64ZBS-NEXT: vmseq.vi v16, v8, 0307; RV64ZBS-NEXT: srli a0, a1, 6308; RV64ZBS-NEXT: vsetivli zero, 1, e64, m1, ta, ma309; RV64ZBS-NEXT: vslidedown.vx v8, v16, a0310; RV64ZBS-NEXT: vmv.x.s a0, v8311; RV64ZBS-NEXT: bext a0, a0, a1312; RV64ZBS-NEXT: ret313 %a = load <128 x i8>, ptr %x314 %b = icmp eq <128 x i8> %a, zeroinitializer315 %c = extractelement <128 x i1> %b, i64 %idx316 ret i1 %c317}318 319define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {320; RV32-LABEL: extractelt_v256i1:321; RV32: # %bb.0:322; RV32-NEXT: addi sp, sp, -384323; RV32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill324; RV32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill325; RV32-NEXT: addi s0, sp, 384326; RV32-NEXT: andi sp, sp, -128327; RV32-NEXT: li a2, 128328; RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma329; RV32-NEXT: vle8.v v8, (a0)330; RV32-NEXT: addi a0, a0, 128331; RV32-NEXT: vle8.v v16, (a0)332; RV32-NEXT: vmseq.vi v0, v8, 0333; RV32-NEXT: vmv.v.i v8, 0334; RV32-NEXT: vmerge.vim v24, v8, 1, v0335; RV32-NEXT: vmseq.vi v0, v16, 0336; RV32-NEXT: zext.b a0, a1337; RV32-NEXT: mv a1, sp338; RV32-NEXT: add a0, a1, a0339; RV32-NEXT: vse8.v v24, (a1)340; RV32-NEXT: vmerge.vim v8, v8, 1, v0341; RV32-NEXT: addi a1, sp, 128342; RV32-NEXT: vse8.v v8, (a1)343; RV32-NEXT: lbu a0, 0(a0)344; RV32-NEXT: addi sp, s0, -384345; RV32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload346; RV32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload347; RV32-NEXT: addi sp, sp, 384348; RV32-NEXT: ret349;350; RV64-LABEL: extractelt_v256i1:351; RV64: # %bb.0:352; RV64-NEXT: addi sp, sp, -384353; RV64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill354; RV64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill355; RV64-NEXT: addi s0, sp, 384356; RV64-NEXT: andi sp, sp, -128357; RV64-NEXT: li a2, 128358; RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma359; RV64-NEXT: vle8.v v8, (a0)360; RV64-NEXT: addi a0, a0, 128361; RV64-NEXT: vle8.v v16, (a0)362; RV64-NEXT: vmseq.vi v0, v8, 0363; RV64-NEXT: vmv.v.i v8, 0364; RV64-NEXT: vmerge.vim v24, v8, 1, v0365; RV64-NEXT: vmseq.vi v0, v16, 0366; RV64-NEXT: zext.b a0, a1367; RV64-NEXT: mv a1, sp368; RV64-NEXT: add a0, a1, a0369; RV64-NEXT: vse8.v v24, (a1)370; RV64-NEXT: vmerge.vim v8, v8, 1, v0371; RV64-NEXT: addi a1, sp, 128372; RV64-NEXT: vse8.v v8, (a1)373; RV64-NEXT: lbu a0, 0(a0)374; RV64-NEXT: addi sp, s0, -384375; RV64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload376; RV64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload377; RV64-NEXT: addi sp, sp, 384378; RV64-NEXT: ret379;380; RV32ZBS-LABEL: extractelt_v256i1:381; RV32ZBS: # %bb.0:382; RV32ZBS-NEXT: addi sp, sp, -384383; RV32ZBS-NEXT: sw ra, 380(sp) # 4-byte Folded Spill384; RV32ZBS-NEXT: sw s0, 376(sp) # 4-byte Folded Spill385; RV32ZBS-NEXT: addi s0, sp, 384386; RV32ZBS-NEXT: andi sp, sp, -128387; RV32ZBS-NEXT: li a2, 128388; RV32ZBS-NEXT: vsetvli zero, a2, e8, m8, ta, ma389; RV32ZBS-NEXT: vle8.v v8, (a0)390; RV32ZBS-NEXT: addi a0, a0, 128391; RV32ZBS-NEXT: vle8.v v16, (a0)392; RV32ZBS-NEXT: vmseq.vi v0, v8, 0393; RV32ZBS-NEXT: vmv.v.i v8, 0394; RV32ZBS-NEXT: vmerge.vim v24, v8, 1, v0395; RV32ZBS-NEXT: vmseq.vi v0, v16, 0396; RV32ZBS-NEXT: zext.b a0, a1397; RV32ZBS-NEXT: mv a1, sp398; RV32ZBS-NEXT: add a0, a1, a0399; RV32ZBS-NEXT: vse8.v v24, (a1)400; RV32ZBS-NEXT: vmerge.vim v8, v8, 1, v0401; RV32ZBS-NEXT: addi a1, sp, 128402; RV32ZBS-NEXT: vse8.v v8, (a1)403; RV32ZBS-NEXT: lbu a0, 0(a0)404; RV32ZBS-NEXT: addi sp, s0, -384405; RV32ZBS-NEXT: lw ra, 380(sp) # 4-byte Folded Reload406; RV32ZBS-NEXT: lw s0, 376(sp) # 4-byte Folded Reload407; RV32ZBS-NEXT: addi sp, sp, 384408; RV32ZBS-NEXT: ret409;410; RV64ZBS-LABEL: extractelt_v256i1:411; RV64ZBS: # %bb.0:412; RV64ZBS-NEXT: addi sp, sp, -384413; RV64ZBS-NEXT: sd ra, 376(sp) # 8-byte Folded Spill414; RV64ZBS-NEXT: sd s0, 368(sp) # 8-byte Folded Spill415; RV64ZBS-NEXT: addi s0, sp, 384416; RV64ZBS-NEXT: andi sp, sp, -128417; RV64ZBS-NEXT: li a2, 128418; RV64ZBS-NEXT: vsetvli zero, a2, e8, m8, ta, ma419; RV64ZBS-NEXT: vle8.v v8, (a0)420; RV64ZBS-NEXT: addi a0, a0, 128421; RV64ZBS-NEXT: vle8.v v16, (a0)422; RV64ZBS-NEXT: vmseq.vi v0, v8, 0423; RV64ZBS-NEXT: vmv.v.i v8, 0424; RV64ZBS-NEXT: vmerge.vim v24, v8, 1, v0425; RV64ZBS-NEXT: vmseq.vi v0, v16, 0426; RV64ZBS-NEXT: zext.b a0, a1427; RV64ZBS-NEXT: mv a1, sp428; RV64ZBS-NEXT: add a0, a1, a0429; RV64ZBS-NEXT: vse8.v v24, (a1)430; RV64ZBS-NEXT: vmerge.vim v8, v8, 1, v0431; RV64ZBS-NEXT: addi a1, sp, 128432; RV64ZBS-NEXT: vse8.v v8, (a1)433; RV64ZBS-NEXT: lbu a0, 0(a0)434; RV64ZBS-NEXT: addi sp, s0, -384435; RV64ZBS-NEXT: ld ra, 376(sp) # 8-byte Folded Reload436; RV64ZBS-NEXT: ld s0, 368(sp) # 8-byte Folded Reload437; RV64ZBS-NEXT: addi sp, sp, 384438; RV64ZBS-NEXT: ret439 %a = load <256 x i8>, ptr %x440 %b = icmp eq <256 x i8> %a, zeroinitializer441 %c = extractelement <256 x i1> %b, i64 %idx442 ret i1 %c443}444 445define i1 @extractelt_v1i1_idx0(ptr %x) nounwind {446; CHECK-LABEL: extractelt_v1i1_idx0:447; CHECK: # %bb.0:448; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma449; CHECK-NEXT: vle8.v v8, (a0)450; CHECK-NEXT: vmseq.vi v8, v8, 0451; CHECK-NEXT: vfirst.m a0, v8452; CHECK-NEXT: seqz a0, a0453; CHECK-NEXT: ret454 %a = load <1 x i8>, ptr %x455 %b = icmp eq <1 x i8> %a, zeroinitializer456 %c = extractelement <1 x i1> %b, i64 0457 ret i1 %c458}459 460define i1 @extractelt_v2i1_idx0(ptr %x) nounwind {461; CHECK-LABEL: extractelt_v2i1_idx0:462; CHECK: # %bb.0:463; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma464; CHECK-NEXT: vle8.v v8, (a0)465; CHECK-NEXT: vmseq.vi v8, v8, 0466; CHECK-NEXT: vfirst.m a0, v8467; CHECK-NEXT: seqz a0, a0468; CHECK-NEXT: ret469 %a = load <2 x i8>, ptr %x470 %b = icmp eq <2 x i8> %a, zeroinitializer471 %c = extractelement <2 x i1> %b, i64 0472 ret i1 %c473}474 475define i1 @extractelt_v4i1_idx0(ptr %x) nounwind {476; CHECK-LABEL: extractelt_v4i1_idx0:477; CHECK: # %bb.0:478; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma479; CHECK-NEXT: vle8.v v8, (a0)480; CHECK-NEXT: vmseq.vi v8, v8, 0481; CHECK-NEXT: vfirst.m a0, v8482; CHECK-NEXT: seqz a0, a0483; CHECK-NEXT: ret484 %a = load <4 x i8>, ptr %x485 %b = icmp eq <4 x i8> %a, zeroinitializer486 %c = extractelement <4 x i1> %b, i64 0487 ret i1 %c488}489 490define i1 @extractelt_v8i1_idx0(ptr %x) nounwind {491; CHECK-LABEL: extractelt_v8i1_idx0:492; CHECK: # %bb.0:493; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma494; CHECK-NEXT: vle8.v v8, (a0)495; CHECK-NEXT: vmseq.vi v8, v8, 0496; CHECK-NEXT: vfirst.m a0, v8497; CHECK-NEXT: seqz a0, a0498; CHECK-NEXT: ret499 %a = load <8 x i8>, ptr %x500 %b = icmp eq <8 x i8> %a, zeroinitializer501 %c = extractelement <8 x i1> %b, i64 0502 ret i1 %c503}504 505define i1 @extractelt_v16i1_idx0(ptr %x) nounwind {506; CHECK-LABEL: extractelt_v16i1_idx0:507; CHECK: # %bb.0:508; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma509; CHECK-NEXT: vle8.v v8, (a0)510; CHECK-NEXT: vmseq.vi v8, v8, 0511; CHECK-NEXT: vfirst.m a0, v8512; CHECK-NEXT: seqz a0, a0513; CHECK-NEXT: ret514 %a = load <16 x i8>, ptr %x515 %b = icmp eq <16 x i8> %a, zeroinitializer516 %c = extractelement <16 x i1> %b, i64 0517 ret i1 %c518}519 520define i1 @extractelt_v32i1_idx0(ptr %x) nounwind {521; CHECK-LABEL: extractelt_v32i1_idx0:522; CHECK: # %bb.0:523; CHECK-NEXT: li a1, 32524; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma525; CHECK-NEXT: vle8.v v8, (a0)526; CHECK-NEXT: vmseq.vi v10, v8, 0527; CHECK-NEXT: vfirst.m a0, v10528; CHECK-NEXT: seqz a0, a0529; CHECK-NEXT: ret530 %a = load <32 x i8>, ptr %x531 %b = icmp eq <32 x i8> %a, zeroinitializer532 %c = extractelement <32 x i1> %b, i64 0533 ret i1 %c534}535 536define i1 @extractelt_v64i1_idx0(ptr %x) nounwind {537; CHECK-LABEL: extractelt_v64i1_idx0:538; CHECK: # %bb.0:539; CHECK-NEXT: li a1, 64540; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma541; CHECK-NEXT: vle8.v v8, (a0)542; CHECK-NEXT: vmseq.vi v12, v8, 0543; CHECK-NEXT: vfirst.m a0, v12544; CHECK-NEXT: seqz a0, a0545; CHECK-NEXT: ret546 %a = load <64 x i8>, ptr %x547 %b = icmp eq <64 x i8> %a, zeroinitializer548 %c = extractelement <64 x i1> %b, i64 0549 ret i1 %c550}551 552define i1 @extractelt_v128i1_idx0(ptr %x) nounwind {553; CHECK-LABEL: extractelt_v128i1_idx0:554; CHECK: # %bb.0:555; CHECK-NEXT: li a1, 128556; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma557; CHECK-NEXT: vle8.v v8, (a0)558; CHECK-NEXT: vmseq.vi v16, v8, 0559; CHECK-NEXT: vfirst.m a0, v16560; CHECK-NEXT: seqz a0, a0561; CHECK-NEXT: ret562 %a = load <128 x i8>, ptr %x563 %b = icmp eq <128 x i8> %a, zeroinitializer564 %c = extractelement <128 x i1> %b, i64 0565 ret i1 %c566}567 568define i1 @extractelt_v256i1_idx0(ptr %x) nounwind {569; CHECK-LABEL: extractelt_v256i1_idx0:570; CHECK: # %bb.0:571; CHECK-NEXT: li a1, 128572; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma573; CHECK-NEXT: vle8.v v8, (a0)574; CHECK-NEXT: vmseq.vi v16, v8, 0575; CHECK-NEXT: vfirst.m a0, v16576; CHECK-NEXT: seqz a0, a0577; CHECK-NEXT: ret578 %a = load <256 x i8>, ptr %x579 %b = icmp eq <256 x i8> %a, zeroinitializer580 %c = extractelement <256 x i1> %b, i64 0581 ret i1 %c582}583