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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,CHECK323; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,CHECK644; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,CHECK325; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,CHECK646 7; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,CHECK328; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,CHECK649; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,CHECK3210; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,CHECK6411 12; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,VLS,CHECK3213; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,VLS,CHECK6414; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,VLS,CHECK3215; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,VLS,CHECK6416 17define void @extract_v2i8_v4i8_0(ptr %x, ptr %y) {18; CHECK-LABEL: extract_v2i8_v4i8_0:19; CHECK: # %bb.0:20; CHECK-NEXT: lh a0, 0(a0)21; CHECK-NEXT: sh a0, 0(a1)22; CHECK-NEXT: ret23 %a = load <4 x i8>, ptr %x24 %c = call <2 x i8> @llvm.vector.extract.v2i8.v4i8(<4 x i8> %a, i64 0)25 store <2 x i8> %c, ptr %y26 ret void27}28 29define void @extract_v2i8_v4i8_2(ptr %x, ptr %y) {30; CHECK-LABEL: extract_v2i8_v4i8_2:31; CHECK: # %bb.0:32; CHECK-NEXT: lh a0, 2(a0)33; CHECK-NEXT: sh a0, 0(a1)34; CHECK-NEXT: ret35 %a = load <4 x i8>, ptr %x36 %c = call <2 x i8> @llvm.vector.extract.v2i8.v4i8(<4 x i8> %a, i64 2)37 store <2 x i8> %c, ptr %y38 ret void39}40 41define void @extract_v2i8_v8i8_0(ptr %x, ptr %y) {42; CHECK-LABEL: extract_v2i8_v8i8_0:43; CHECK: # %bb.0:44; CHECK-NEXT: lh a0, 0(a0)45; CHECK-NEXT: sh a0, 0(a1)46; CHECK-NEXT: ret47 %a = load <8 x i8>, ptr %x48 %c = call <2 x i8> @llvm.vector.extract.v2i8.v8i8(<8 x i8> %a, i64 0)49 store <2 x i8> %c, ptr %y50 ret void51}52 53define void @extract_v2i8_v8i8_6(ptr %x, ptr %y) {54; CHECK-LABEL: extract_v2i8_v8i8_6:55; CHECK: # %bb.0:56; CHECK-NEXT: lh a0, 6(a0)57; CHECK-NEXT: sh a0, 0(a1)58; CHECK-NEXT: ret59 %a = load <8 x i8>, ptr %x60 %c = call <2 x i8> @llvm.vector.extract.v2i8.v8i8(<8 x i8> %a, i64 6)61 store <2 x i8> %c, ptr %y62 ret void63}64 65define void @extract_v1i32_v8i32_4(ptr %x, ptr %y) {66; CHECK-LABEL: extract_v1i32_v8i32_4:67; CHECK: # %bb.0:68; CHECK-NEXT: lw a0, 16(a0)69; CHECK-NEXT: sw a0, 0(a1)70; CHECK-NEXT: ret71 %a = load <8 x i32>, ptr %x72 %c = call <1 x i32> @llvm.vector.extract.v1i32.v8i32(<8 x i32> %a, i64 4)73 store <1 x i32> %c, ptr %y74 ret void75}76 77define void @extract_v1i32_v8i32_5(ptr %x, ptr %y) {78; CHECK-LABEL: extract_v1i32_v8i32_5:79; CHECK: # %bb.0:80; CHECK-NEXT: lw a0, 20(a0)81; CHECK-NEXT: sw a0, 0(a1)82; CHECK-NEXT: ret83 %a = load <8 x i32>, ptr %x84 %c = call <1 x i32> @llvm.vector.extract.v1i32.v8i32(<8 x i32> %a, i64 5)85 store <1 x i32> %c, ptr %y86 ret void87}88 89define void @extract_v2i32_v8i32_0(ptr %x, ptr %y) {90; CHECK32-LABEL: extract_v2i32_v8i32_0:91; CHECK32: # %bb.0:92; CHECK32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma93; CHECK32-NEXT: vle32.v v8, (a0)94; CHECK32-NEXT: vse32.v v8, (a1)95; CHECK32-NEXT: ret96;97; CHECK64-LABEL: extract_v2i32_v8i32_0:98; CHECK64: # %bb.0:99; CHECK64-NEXT: ld a0, 0(a0)100; CHECK64-NEXT: sd a0, 0(a1)101; CHECK64-NEXT: ret102 %a = load <8 x i32>, ptr %x103 %c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 0)104 store <2 x i32> %c, ptr %y105 ret void106}107 108define void @extract_v2i32_v8i32_2(ptr %x, ptr %y) {109; CHECK32-LABEL: extract_v2i32_v8i32_2:110; CHECK32: # %bb.0:111; CHECK32-NEXT: addi a0, a0, 8112; CHECK32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma113; CHECK32-NEXT: vle32.v v8, (a0)114; CHECK32-NEXT: vse32.v v8, (a1)115; CHECK32-NEXT: ret116;117; CHECK64-LABEL: extract_v2i32_v8i32_2:118; CHECK64: # %bb.0:119; CHECK64-NEXT: ld a0, 8(a0)120; CHECK64-NEXT: sd a0, 0(a1)121; CHECK64-NEXT: ret122 %a = load <8 x i32>, ptr %x123 %c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 2)124 store <2 x i32> %c, ptr %y125 ret void126}127 128define void @extract_v2i32_v8i32_4(ptr %x, ptr %y) {129; CHECK32-LABEL: extract_v2i32_v8i32_4:130; CHECK32: # %bb.0:131; CHECK32-NEXT: addi a0, a0, 16132; CHECK32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma133; CHECK32-NEXT: vle32.v v8, (a0)134; CHECK32-NEXT: vse32.v v8, (a1)135; CHECK32-NEXT: ret136;137; CHECK64-LABEL: extract_v2i32_v8i32_4:138; CHECK64: # %bb.0:139; CHECK64-NEXT: ld a0, 16(a0)140; CHECK64-NEXT: sd a0, 0(a1)141; CHECK64-NEXT: ret142 %a = load <8 x i32>, ptr %x143 %c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 4)144 store <2 x i32> %c, ptr %y145 ret void146}147 148define void @extract_v2i32_v8i32_6(ptr %x, ptr %y) {149; CHECK32-LABEL: extract_v2i32_v8i32_6:150; CHECK32: # %bb.0:151; CHECK32-NEXT: addi a0, a0, 24152; CHECK32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma153; CHECK32-NEXT: vle32.v v8, (a0)154; CHECK32-NEXT: vse32.v v8, (a1)155; CHECK32-NEXT: ret156;157; CHECK64-LABEL: extract_v2i32_v8i32_6:158; CHECK64: # %bb.0:159; CHECK64-NEXT: ld a0, 24(a0)160; CHECK64-NEXT: sd a0, 0(a1)161; CHECK64-NEXT: ret162 %a = load <8 x i32>, ptr %x163 %c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 6)164 store <2 x i32> %c, ptr %y165 ret void166}167 168define void @extract_v2i32_nxv16i32_0(<vscale x 16 x i32> %x, ptr %y) {169; CHECK-LABEL: extract_v2i32_nxv16i32_0:170; CHECK: # %bb.0:171; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma172; CHECK-NEXT: vse32.v v8, (a0)173; CHECK-NEXT: ret174 %c = call <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 0)175 store <2 x i32> %c, ptr %y176 ret void177}178 179define void @extract_v2i32_nxv16i32_2(<vscale x 16 x i32> %x, ptr %y) {180; CHECK-LABEL: extract_v2i32_nxv16i32_2:181; CHECK: # %bb.0:182; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma183; CHECK-NEXT: vslidedown.vi v8, v8, 2184; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma185; CHECK-NEXT: vse32.v v8, (a0)186; CHECK-NEXT: ret187 %c = call <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 2)188 store <2 x i32> %c, ptr %y189 ret void190}191 192define void @extract_v2i32_nxv16i32_4(<vscale x 16 x i32> %x, ptr %y) {193; VLA-LABEL: extract_v2i32_nxv16i32_4:194; VLA: # %bb.0:195; VLA-NEXT: vsetivli zero, 2, e32, m2, ta, ma196; VLA-NEXT: vslidedown.vi v8, v8, 4197; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma198; VLA-NEXT: vse32.v v8, (a0)199; VLA-NEXT: ret200;201; VLS-LABEL: extract_v2i32_nxv16i32_4:202; VLS: # %bb.0:203; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma204; VLS-NEXT: vse32.v v9, (a0)205; VLS-NEXT: ret206 %c = call <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 4)207 store <2 x i32> %c, ptr %y208 ret void209}210 211define void @extract_v2i32_nxv16i32_6(<vscale x 16 x i32> %x, ptr %y) {212; VLA-LABEL: extract_v2i32_nxv16i32_6:213; VLA: # %bb.0:214; VLA-NEXT: vsetivli zero, 2, e32, m2, ta, ma215; VLA-NEXT: vslidedown.vi v8, v8, 6216; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma217; VLA-NEXT: vse32.v v8, (a0)218; VLA-NEXT: ret219;220; VLS-LABEL: extract_v2i32_nxv16i32_6:221; VLS: # %bb.0:222; VLS-NEXT: vsetivli zero, 2, e32, m1, ta, ma223; VLS-NEXT: vslidedown.vi v8, v9, 2224; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma225; VLS-NEXT: vse32.v v8, (a0)226; VLS-NEXT: ret227 %c = call <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 6)228 store <2 x i32> %c, ptr %y229 ret void230}231 232define void @extract_v2i32_nxv16i32_8(<vscale x 16 x i32> %x, ptr %y) {233; VLA-LABEL: extract_v2i32_nxv16i32_8:234; VLA: # %bb.0:235; VLA-NEXT: vsetivli zero, 2, e32, m4, ta, ma236; VLA-NEXT: vslidedown.vi v8, v8, 8237; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma238; VLA-NEXT: vse32.v v8, (a0)239; VLA-NEXT: ret240;241; VLS-LABEL: extract_v2i32_nxv16i32_8:242; VLS: # %bb.0:243; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma244; VLS-NEXT: vse32.v v10, (a0)245; VLS-NEXT: ret246 %c = call <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 8)247 store <2 x i32> %c, ptr %y248 ret void249}250 251define void @extract_v2i8_nxv2i8_0(<vscale x 2 x i8> %x, ptr %y) {252; CHECK-LABEL: extract_v2i8_nxv2i8_0:253; CHECK: # %bb.0:254; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma255; CHECK-NEXT: vse8.v v8, (a0)256; CHECK-NEXT: ret257 %c = call <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %x, i64 0)258 store <2 x i8> %c, ptr %y259 ret void260}261 262define void @extract_v2i8_nxv2i8_2(<vscale x 2 x i8> %x, ptr %y) {263; CHECK-LABEL: extract_v2i8_nxv2i8_2:264; CHECK: # %bb.0:265; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma266; CHECK-NEXT: vslidedown.vi v8, v8, 2267; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma268; CHECK-NEXT: vse8.v v8, (a0)269; CHECK-NEXT: ret270 %c = call <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %x, i64 2)271 store <2 x i8> %c, ptr %y272 ret void273}274 275define void @extract_v2i8_nxv2i8_4(<vscale x 2 x i8> %x, ptr %y) {276; CHECK-LABEL: extract_v2i8_nxv2i8_4:277; CHECK: # %bb.0:278; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma279; CHECK-NEXT: vslidedown.vi v8, v8, 4280; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma281; CHECK-NEXT: vse8.v v8, (a0)282; CHECK-NEXT: ret283 %c = call <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %x, i64 4)284 store <2 x i8> %c, ptr %y285 ret void286}287 288define void @extract_v2i8_nxv2i8_6(<vscale x 2 x i8> %x, ptr %y) {289; CHECK-LABEL: extract_v2i8_nxv2i8_6:290; CHECK: # %bb.0:291; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma292; CHECK-NEXT: vslidedown.vi v8, v8, 6293; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma294; CHECK-NEXT: vse8.v v8, (a0)295; CHECK-NEXT: ret296 %c = call <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %x, i64 6)297 store <2 x i8> %c, ptr %y298 ret void299}300 301define void @extract_v8i32_nxv16i32_8(<vscale x 16 x i32> %x, ptr %y) {302; VLA-LABEL: extract_v8i32_nxv16i32_8:303; VLA: # %bb.0:304; VLA-NEXT: vsetivli zero, 8, e32, m4, ta, ma305; VLA-NEXT: vslidedown.vi v8, v8, 8306; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma307; VLA-NEXT: vse32.v v8, (a0)308; VLA-NEXT: ret309;310; VLS-LABEL: extract_v8i32_nxv16i32_8:311; VLS: # %bb.0:312; VLS-NEXT: vs2r.v v10, (a0)313; VLS-NEXT: ret314 %c = call <8 x i32> @llvm.vector.extract.v8i32.nxv16i32(<vscale x 16 x i32> %x, i64 8)315 store <8 x i32> %c, ptr %y316 ret void317}318 319define void @extract_v8i1_v64i1_0(ptr %x, ptr %y) {320; CHECK-LABEL: extract_v8i1_v64i1_0:321; CHECK: # %bb.0:322; CHECK-NEXT: lbu a0, 0(a0)323; CHECK-NEXT: sb a0, 0(a1)324; CHECK-NEXT: ret325 %a = load <64 x i1>, ptr %x326 %c = call <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 0)327 store <8 x i1> %c, ptr %y328 ret void329}330 331define void @extract_v8i1_v64i1_8(ptr %x, ptr %y) {332; CHECK-LABEL: extract_v8i1_v64i1_8:333; CHECK: # %bb.0:334; CHECK-NEXT: lbu a0, 1(a0)335; CHECK-NEXT: sb a0, 0(a1)336; CHECK-NEXT: ret337 %a = load <64 x i1>, ptr %x338 %c = call <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 8)339 store <8 x i1> %c, ptr %y340 ret void341}342 343define void @extract_v8i1_v64i1_48(ptr %x, ptr %y) {344; CHECK-LABEL: extract_v8i1_v64i1_48:345; CHECK: # %bb.0:346; CHECK-NEXT: lbu a0, 6(a0)347; CHECK-NEXT: sb a0, 0(a1)348; CHECK-NEXT: ret349 %a = load <64 x i1>, ptr %x350 %c = call <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 48)351 store <8 x i1> %c, ptr %y352 ret void353}354 355define void @extract_v8i1_nxv2i1_0(<vscale x 2 x i1> %x, ptr %y) {356; CHECK-LABEL: extract_v8i1_nxv2i1_0:357; CHECK: # %bb.0:358; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma359; CHECK-NEXT: vsm.v v0, (a0)360; CHECK-NEXT: ret361 %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv2i1(<vscale x 2 x i1> %x, i64 0)362 store <8 x i1> %c, ptr %y363 ret void364}365 366define void @extract_v8i1_nxv64i1_0(<vscale x 64 x i1> %x, ptr %y) {367; CHECK-LABEL: extract_v8i1_nxv64i1_0:368; CHECK: # %bb.0:369; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma370; CHECK-NEXT: vsm.v v0, (a0)371; CHECK-NEXT: ret372 %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 0)373 store <8 x i1> %c, ptr %y374 ret void375}376 377define void @extract_v8i1_nxv64i1_8(<vscale x 64 x i1> %x, ptr %y) {378; CHECK-LABEL: extract_v8i1_nxv64i1_8:379; CHECK: # %bb.0:380; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma381; CHECK-NEXT: vslidedown.vi v8, v0, 1382; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma383; CHECK-NEXT: vsm.v v8, (a0)384; CHECK-NEXT: ret385 %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 8)386 store <8 x i1> %c, ptr %y387 ret void388}389 390define void @extract_v8i1_nxv64i1_48(<vscale x 64 x i1> %x, ptr %y) {391; CHECK-LABEL: extract_v8i1_nxv64i1_48:392; CHECK: # %bb.0:393; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma394; CHECK-NEXT: vslidedown.vi v8, v0, 6395; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma396; CHECK-NEXT: vsm.v v8, (a0)397; CHECK-NEXT: ret398 %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 48)399 store <8 x i1> %c, ptr %y400 ret void401}402 403define void @extract_v8i1_nxv64i1_128(<vscale x 64 x i1> %x, ptr %y) {404; CHECK-LABEL: extract_v8i1_nxv64i1_128:405; CHECK: # %bb.0:406; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma407; CHECK-NEXT: vslidedown.vi v8, v0, 16408; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma409; CHECK-NEXT: vsm.v v8, (a0)410; CHECK-NEXT: ret411 %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 128)412 store <8 x i1> %c, ptr %y413 ret void414}415 416define void @extract_v8i1_nxv64i1_192(<vscale x 64 x i1> %x, ptr %y) {417; CHECK-LABEL: extract_v8i1_nxv64i1_192:418; CHECK: # %bb.0:419; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma420; CHECK-NEXT: vslidedown.vi v8, v0, 24421; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma422; CHECK-NEXT: vsm.v v8, (a0)423; CHECK-NEXT: ret424 %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 192)425 store <8 x i1> %c, ptr %y426 ret void427}428 429define void @extract_v2i1_v64i1_0(ptr %x, ptr %y) {430; VLA-LABEL: extract_v2i1_v64i1_0:431; VLA: # %bb.0:432; VLA-NEXT: li a2, 64433; VLA-NEXT: vsetvli zero, a2, e8, m4, ta, ma434; VLA-NEXT: vlm.v v0, (a0)435; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma436; VLA-NEXT: vmv.v.i v8, 0437; VLA-NEXT: vmerge.vim v8, v8, 1, v0438; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma439; VLA-NEXT: vmv.v.i v9, 0440; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma441; VLA-NEXT: vmv.v.v v9, v8442; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma443; VLA-NEXT: vmsne.vi v8, v9, 0444; VLA-NEXT: vsm.v v8, (a1)445; VLA-NEXT: ret446;447; VLS-LABEL: extract_v2i1_v64i1_0:448; VLS: # %bb.0:449; VLS-NEXT: vsetvli a2, zero, e8, m4, ta, ma450; VLS-NEXT: vlm.v v0, (a0)451; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma452; VLS-NEXT: vmv.v.i v8, 0453; VLS-NEXT: vmerge.vim v8, v8, 1, v0454; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma455; VLS-NEXT: vmv.v.i v9, 0456; VLS-NEXT: vsetivli zero, 2, e8, mf2, tu, ma457; VLS-NEXT: vmv.v.v v9, v8458; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma459; VLS-NEXT: vmsne.vi v8, v9, 0460; VLS-NEXT: vsm.v v8, (a1)461; VLS-NEXT: ret462 %a = load <64 x i1>, ptr %x463 %c = call <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 0)464 store <2 x i1> %c, ptr %y465 ret void466}467 468define void @extract_v2i1_v64i1_2(ptr %x, ptr %y) {469; VLA-LABEL: extract_v2i1_v64i1_2:470; VLA: # %bb.0:471; VLA-NEXT: li a2, 64472; VLA-NEXT: vsetvli zero, a2, e8, m4, ta, ma473; VLA-NEXT: vlm.v v0, (a0)474; VLA-NEXT: vmv.v.i v8, 0475; VLA-NEXT: vmerge.vim v8, v8, 1, v0476; VLA-NEXT: vsetivli zero, 2, e8, m1, ta, ma477; VLA-NEXT: vslidedown.vi v8, v8, 2478; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma479; VLA-NEXT: vmsne.vi v0, v8, 0480; VLA-NEXT: vmv.v.i v8, 0481; VLA-NEXT: vmerge.vim v8, v8, 1, v0482; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma483; VLA-NEXT: vmv.v.i v9, 0484; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma485; VLA-NEXT: vmv.v.v v9, v8486; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma487; VLA-NEXT: vmsne.vi v8, v9, 0488; VLA-NEXT: vsm.v v8, (a1)489; VLA-NEXT: ret490;491; VLS-LABEL: extract_v2i1_v64i1_2:492; VLS: # %bb.0:493; VLS-NEXT: vsetvli a2, zero, e8, m4, ta, ma494; VLS-NEXT: vlm.v v0, (a0)495; VLS-NEXT: vmv.v.i v8, 0496; VLS-NEXT: vmerge.vim v8, v8, 1, v0497; VLS-NEXT: vsetivli zero, 2, e8, m1, ta, ma498; VLS-NEXT: vslidedown.vi v8, v8, 2499; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma500; VLS-NEXT: vmsne.vi v0, v8, 0501; VLS-NEXT: vmv.v.i v8, 0502; VLS-NEXT: vmerge.vim v8, v8, 1, v0503; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma504; VLS-NEXT: vmv.v.i v9, 0505; VLS-NEXT: vsetivli zero, 2, e8, mf2, tu, ma506; VLS-NEXT: vmv.v.v v9, v8507; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma508; VLS-NEXT: vmsne.vi v8, v9, 0509; VLS-NEXT: vsm.v v8, (a1)510; VLS-NEXT: ret511 %a = load <64 x i1>, ptr %x512 %c = call <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 2)513 store <2 x i1> %c, ptr %y514 ret void515}516 517define void @extract_v2i1_v64i1_42(ptr %x, ptr %y) {518; VLA-LABEL: extract_v2i1_v64i1_42:519; VLA: # %bb.0:520; VLA-NEXT: li a2, 64521; VLA-NEXT: vsetvli zero, a2, e8, m4, ta, ma522; VLA-NEXT: vlm.v v0, (a0)523; VLA-NEXT: li a0, 42524; VLA-NEXT: vmv.v.i v8, 0525; VLA-NEXT: vmerge.vim v8, v8, 1, v0526; VLA-NEXT: vsetivli zero, 2, e8, m4, ta, ma527; VLA-NEXT: vslidedown.vx v8, v8, a0528; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma529; VLA-NEXT: vmsne.vi v0, v8, 0530; VLA-NEXT: vmv.v.i v8, 0531; VLA-NEXT: vmerge.vim v8, v8, 1, v0532; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma533; VLA-NEXT: vmv.v.i v9, 0534; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma535; VLA-NEXT: vmv.v.v v9, v8536; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma537; VLA-NEXT: vmsne.vi v8, v9, 0538; VLA-NEXT: vsm.v v8, (a1)539; VLA-NEXT: ret540;541; VLS-LABEL: extract_v2i1_v64i1_42:542; VLS: # %bb.0:543; VLS-NEXT: vsetvli a2, zero, e8, m4, ta, ma544; VLS-NEXT: vlm.v v0, (a0)545; VLS-NEXT: vmv.v.i v8, 0546; VLS-NEXT: vmerge.vim v8, v8, 1, v0547; VLS-NEXT: vsetivli zero, 2, e8, m1, ta, ma548; VLS-NEXT: vslidedown.vi v8, v10, 10549; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma550; VLS-NEXT: vmsne.vi v0, v8, 0551; VLS-NEXT: vmv.v.i v8, 0552; VLS-NEXT: vmerge.vim v8, v8, 1, v0553; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma554; VLS-NEXT: vmv.v.i v9, 0555; VLS-NEXT: vsetivli zero, 2, e8, mf2, tu, ma556; VLS-NEXT: vmv.v.v v9, v8557; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma558; VLS-NEXT: vmsne.vi v8, v9, 0559; VLS-NEXT: vsm.v v8, (a1)560; VLS-NEXT: ret561 %a = load <64 x i1>, ptr %x562 %c = call <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 42)563 store <2 x i1> %c, ptr %y564 ret void565}566 567define void @extract_v2i1_nxv2i1_0(<vscale x 2 x i1> %x, ptr %y) {568; CHECK-LABEL: extract_v2i1_nxv2i1_0:569; CHECK: # %bb.0:570; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma571; CHECK-NEXT: vmv.v.i v8, 0572; CHECK-NEXT: vmerge.vim v8, v8, 1, v0573; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma574; CHECK-NEXT: vmv.v.i v9, 0575; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma576; CHECK-NEXT: vmv.v.v v9, v8577; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma578; CHECK-NEXT: vmsne.vi v8, v9, 0579; CHECK-NEXT: vsm.v v8, (a0)580; CHECK-NEXT: ret581 %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 0)582 store <2 x i1> %c, ptr %y583 ret void584}585 586define void @extract_v2i1_nxv2i1_2(<vscale x 2 x i1> %x, ptr %y) {587; VLA-LABEL: extract_v2i1_nxv2i1_2:588; VLA: # %bb.0:589; VLA-NEXT: vsetvli a1, zero, e8, mf4, ta, ma590; VLA-NEXT: vmv.v.i v8, 0591; VLA-NEXT: vmerge.vim v8, v8, 1, v0592; VLA-NEXT: vsetivli zero, 2, e8, mf4, ta, ma593; VLA-NEXT: vslidedown.vi v8, v8, 2594; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma595; VLA-NEXT: vmsne.vi v0, v8, 0596; VLA-NEXT: vmv.v.i v8, 0597; VLA-NEXT: vmerge.vim v8, v8, 1, v0598; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma599; VLA-NEXT: vmv.v.i v9, 0600; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma601; VLA-NEXT: vmv.v.v v9, v8602; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma603; VLA-NEXT: vmsne.vi v8, v9, 0604; VLA-NEXT: vsm.v v8, (a0)605; VLA-NEXT: ret606;607; VLS-LABEL: extract_v2i1_nxv2i1_2:608; VLS: # %bb.0:609; VLS-NEXT: vsetivli zero, 4, e8, mf4, ta, ma610; VLS-NEXT: vmv.v.i v8, 0611; VLS-NEXT: vmerge.vim v8, v8, 1, v0612; VLS-NEXT: vsetivli zero, 2, e8, mf4, ta, ma613; VLS-NEXT: vslidedown.vi v8, v8, 2614; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma615; VLS-NEXT: vmsne.vi v0, v8, 0616; VLS-NEXT: vmv.v.i v8, 0617; VLS-NEXT: vmerge.vim v8, v8, 1, v0618; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma619; VLS-NEXT: vmv.v.i v9, 0620; VLS-NEXT: vsetivli zero, 2, e8, mf2, tu, ma621; VLS-NEXT: vmv.v.v v9, v8622; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma623; VLS-NEXT: vmsne.vi v8, v9, 0624; VLS-NEXT: vsm.v v8, (a0)625; VLS-NEXT: ret626 %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 2)627 store <2 x i1> %c, ptr %y628 ret void629}630 631define void @extract_v2i1_nxv64i1_0(<vscale x 64 x i1> %x, ptr %y) {632; CHECK-LABEL: extract_v2i1_nxv64i1_0:633; CHECK: # %bb.0:634; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma635; CHECK-NEXT: vmv.v.i v8, 0636; CHECK-NEXT: vmerge.vim v8, v8, 1, v0637; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma638; CHECK-NEXT: vmv.v.i v9, 0639; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma640; CHECK-NEXT: vmv.v.v v9, v8641; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma642; CHECK-NEXT: vmsne.vi v8, v9, 0643; CHECK-NEXT: vsm.v v8, (a0)644; CHECK-NEXT: ret645 %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 0)646 store <2 x i1> %c, ptr %y647 ret void648}649 650define void @extract_v2i1_nxv64i1_2(<vscale x 64 x i1> %x, ptr %y) {651; CHECK-LABEL: extract_v2i1_nxv64i1_2:652; CHECK: # %bb.0:653; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma654; CHECK-NEXT: vmv.v.i v8, 0655; CHECK-NEXT: vmerge.vim v8, v8, 1, v0656; CHECK-NEXT: vsetivli zero, 2, e8, m1, ta, ma657; CHECK-NEXT: vslidedown.vi v8, v8, 2658; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma659; CHECK-NEXT: vmsne.vi v0, v8, 0660; CHECK-NEXT: vmv.v.i v8, 0661; CHECK-NEXT: vmerge.vim v8, v8, 1, v0662; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma663; CHECK-NEXT: vmv.v.i v9, 0664; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma665; CHECK-NEXT: vmv.v.v v9, v8666; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma667; CHECK-NEXT: vmsne.vi v8, v9, 0668; CHECK-NEXT: vsm.v v8, (a0)669; CHECK-NEXT: ret670 %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 2)671 store <2 x i1> %c, ptr %y672 ret void673}674 675define void @extract_v2i1_nxv64i1_42(<vscale x 64 x i1> %x, ptr %y) {676; VLA-LABEL: extract_v2i1_nxv64i1_42:677; VLA: # %bb.0:678; VLA-NEXT: vsetvli a1, zero, e8, m8, ta, ma679; VLA-NEXT: vmv.v.i v8, 0680; VLA-NEXT: li a1, 42681; VLA-NEXT: vmerge.vim v8, v8, 1, v0682; VLA-NEXT: vsetivli zero, 2, e8, m4, ta, ma683; VLA-NEXT: vslidedown.vx v8, v8, a1684; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma685; VLA-NEXT: vmsne.vi v0, v8, 0686; VLA-NEXT: vmv.v.i v8, 0687; VLA-NEXT: vmerge.vim v8, v8, 1, v0688; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma689; VLA-NEXT: vmv.v.i v9, 0690; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma691; VLA-NEXT: vmv.v.v v9, v8692; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma693; VLA-NEXT: vmsne.vi v8, v9, 0694; VLA-NEXT: vsm.v v8, (a0)695; VLA-NEXT: ret696;697; VLS-LABEL: extract_v2i1_nxv64i1_42:698; VLS: # %bb.0:699; VLS-NEXT: vsetvli a1, zero, e8, m8, ta, ma700; VLS-NEXT: vmv.v.i v8, 0701; VLS-NEXT: vmerge.vim v8, v8, 1, v0702; VLS-NEXT: vsetivli zero, 2, e8, m1, ta, ma703; VLS-NEXT: vslidedown.vi v8, v10, 10704; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma705; VLS-NEXT: vmsne.vi v0, v8, 0706; VLS-NEXT: vmv.v.i v8, 0707; VLS-NEXT: vmerge.vim v8, v8, 1, v0708; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma709; VLS-NEXT: vmv.v.i v9, 0710; VLS-NEXT: vsetivli zero, 2, e8, mf2, tu, ma711; VLS-NEXT: vmv.v.v v9, v8712; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma713; VLS-NEXT: vmsne.vi v8, v9, 0714; VLS-NEXT: vsm.v v8, (a0)715; VLS-NEXT: ret716 %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 42)717 store <2 x i1> %c, ptr %y718 ret void719}720 721define void @extract_v2i1_nxv32i1_26(<vscale x 32 x i1> %x, ptr %y) {722; VLA-LABEL: extract_v2i1_nxv32i1_26:723; VLA: # %bb.0:724; VLA-NEXT: vsetvli a1, zero, e8, m4, ta, ma725; VLA-NEXT: vmv.v.i v8, 0726; VLA-NEXT: vmerge.vim v8, v8, 1, v0727; VLA-NEXT: vsetivli zero, 2, e8, m2, ta, ma728; VLA-NEXT: vslidedown.vi v8, v8, 26729; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma730; VLA-NEXT: vmsne.vi v0, v8, 0731; VLA-NEXT: vmv.v.i v8, 0732; VLA-NEXT: vmerge.vim v8, v8, 1, v0733; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma734; VLA-NEXT: vmv.v.i v9, 0735; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma736; VLA-NEXT: vmv.v.v v9, v8737; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma738; VLA-NEXT: vmsne.vi v8, v9, 0739; VLA-NEXT: vsm.v v8, (a0)740; VLA-NEXT: ret741;742; VLS-LABEL: extract_v2i1_nxv32i1_26:743; VLS: # %bb.0:744; VLS-NEXT: vsetvli a1, zero, e8, m4, ta, ma745; VLS-NEXT: vmv.v.i v8, 0746; VLS-NEXT: vmerge.vim v8, v8, 1, v0747; VLS-NEXT: vsetivli zero, 2, e8, m1, ta, ma748; VLS-NEXT: vslidedown.vi v8, v9, 10749; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma750; VLS-NEXT: vmsne.vi v0, v8, 0751; VLS-NEXT: vmv.v.i v8, 0752; VLS-NEXT: vmerge.vim v8, v8, 1, v0753; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma754; VLS-NEXT: vmv.v.i v9, 0755; VLS-NEXT: vsetivli zero, 2, e8, mf2, tu, ma756; VLS-NEXT: vmv.v.v v9, v8757; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma758; VLS-NEXT: vmsne.vi v8, v9, 0759; VLS-NEXT: vsm.v v8, (a0)760; VLS-NEXT: ret761 %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv32i1(<vscale x 32 x i1> %x, i64 26)762 store <2 x i1> %c, ptr %y763 ret void764}765 766define void @extract_v8i1_nxv32i1_16(<vscale x 32 x i1> %x, ptr %y) {767; CHECK-LABEL: extract_v8i1_nxv32i1_16:768; CHECK: # %bb.0:769; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma770; CHECK-NEXT: vslidedown.vi v8, v0, 2771; CHECK-NEXT: vsm.v v8, (a0)772; CHECK-NEXT: ret773 %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv32i1(<vscale x 32 x i1> %x, i64 16)774 store <8 x i1> %c, ptr %y775 ret void776}777 778define <1 x i64> @extract_v1i64_v2i64_1(<2 x i64> %x) {779; CHECK-LABEL: extract_v1i64_v2i64_1:780; CHECK: # %bb.0:781; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma782; CHECK-NEXT: vslidedown.vi v8, v8, 1783; CHECK-NEXT: ret784 %v = call <1 x i64> @llvm.vector.extract.v1i64.v2i64(<2 x i64> %x, i64 1)785 ret <1 x i64> %v786}787 788define void @extract_v2bf16_v4bf16_0(ptr %x, ptr %y) {789; CHECK-LABEL: extract_v2bf16_v4bf16_0:790; CHECK: # %bb.0:791; CHECK-NEXT: lw a0, 0(a0)792; CHECK-NEXT: sw a0, 0(a1)793; CHECK-NEXT: ret794 %a = load <4 x bfloat>, ptr %x795 %c = call <2 x bfloat> @llvm.vector.extract.v2bf16.v4bf16(<4 x bfloat> %a, i64 0)796 store <2 x bfloat> %c, ptr %y797 ret void798}799 800define void @extract_v2bf16_v4bf16_2(ptr %x, ptr %y) {801; CHECK-LABEL: extract_v2bf16_v4bf16_2:802; CHECK: # %bb.0:803; CHECK-NEXT: lw a0, 4(a0)804; CHECK-NEXT: sw a0, 0(a1)805; CHECK-NEXT: ret806 %a = load <4 x bfloat>, ptr %x807 %c = call <2 x bfloat> @llvm.vector.extract.v2bf16.v4bf16(<4 x bfloat> %a, i64 2)808 store <2 x bfloat> %c, ptr %y809 ret void810}811 812define void @extract_v2f16_v4f16_0(ptr %x, ptr %y) {813; CHECK-LABEL: extract_v2f16_v4f16_0:814; CHECK: # %bb.0:815; CHECK-NEXT: lw a0, 0(a0)816; CHECK-NEXT: sw a0, 0(a1)817; CHECK-NEXT: ret818 %a = load <4 x half>, ptr %x819 %c = call <2 x half> @llvm.vector.extract.v2f16.v4f16(<4 x half> %a, i64 0)820 store <2 x half> %c, ptr %y821 ret void822}823 824define void @extract_v2f16_v4f16_2(ptr %x, ptr %y) {825; CHECK-LABEL: extract_v2f16_v4f16_2:826; CHECK: # %bb.0:827; CHECK-NEXT: lw a0, 4(a0)828; CHECK-NEXT: sw a0, 0(a1)829; CHECK-NEXT: ret830 %a = load <4 x half>, ptr %x831 %c = call <2 x half> @llvm.vector.extract.v2f16.v4f16(<4 x half> %a, i64 2)832 store <2 x half> %c, ptr %y833 ret void834}835 836