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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV32,RV32NOM3; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+zfbfmin,+zvfbfmin,+f,+d,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV32,RV32M4; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV64,RV64NOM5; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+zfbfmin,+zvfbfmin,+f,+d,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV64,RV64M6 7; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+f,+d,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV32,RV32M8; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+f,+d,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV64,RV64M9 10; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+zfbfmin,+zvfbfmin,+f,+d,+m,+experimental-xrivosvisni -verify-machineinstrs < %s | FileCheck %s --check-prefixes=VISNI11 12define i8 @extractelt_v16i8(<16 x i8> %a) nounwind {13; CHECK-LABEL: extractelt_v16i8:14; CHECK: # %bb.0:15; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma16; CHECK-NEXT: vslidedown.vi v8, v8, 717; CHECK-NEXT: vmv.x.s a0, v818; CHECK-NEXT: ret19;20; VISNI-LABEL: extractelt_v16i8:21; VISNI: # %bb.0:22; VISNI-NEXT: vsetivli zero, 1, e8, m1, ta, ma23; VISNI-NEXT: ri.vextract.x.v a0, v8, 724; VISNI-NEXT: ret25 %b = extractelement <16 x i8> %a, i32 726 ret i8 %b27}28 29define i16 @extractelt_v8i16(<8 x i16> %a) nounwind {30; CHECK-LABEL: extractelt_v8i16:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma33; CHECK-NEXT: vslidedown.vi v8, v8, 734; CHECK-NEXT: vmv.x.s a0, v835; CHECK-NEXT: ret36;37; VISNI-LABEL: extractelt_v8i16:38; VISNI: # %bb.0:39; VISNI-NEXT: vsetivli zero, 1, e16, m1, ta, ma40; VISNI-NEXT: ri.vextract.x.v a0, v8, 741; VISNI-NEXT: ret42 %b = extractelement <8 x i16> %a, i32 743 ret i16 %b44}45 46define i32 @extractelt_v4i32(<4 x i32> %a) nounwind {47; CHECK-LABEL: extractelt_v4i32:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma50; CHECK-NEXT: vslidedown.vi v8, v8, 251; CHECK-NEXT: vmv.x.s a0, v852; CHECK-NEXT: ret53;54; VISNI-LABEL: extractelt_v4i32:55; VISNI: # %bb.0:56; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma57; VISNI-NEXT: ri.vextract.x.v a0, v8, 258; VISNI-NEXT: ret59 %b = extractelement <4 x i32> %a, i32 260 ret i32 %b61}62 63define i64 @extractelt_v2i64(<2 x i64> %a) nounwind {64; RV32-LABEL: extractelt_v2i64:65; RV32: # %bb.0:66; RV32-NEXT: li a0, 3267; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma68; RV32-NEXT: vsrl.vx v9, v8, a069; RV32-NEXT: vmv.x.s a1, v970; RV32-NEXT: vmv.x.s a0, v871; RV32-NEXT: ret72;73; RV64-LABEL: extractelt_v2i64:74; RV64: # %bb.0:75; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma76; RV64-NEXT: vmv.x.s a0, v877; RV64-NEXT: ret78;79; VISNI-LABEL: extractelt_v2i64:80; VISNI: # %bb.0:81; VISNI-NEXT: vsetivli zero, 1, e64, m1, ta, ma82; VISNI-NEXT: vmv.x.s a0, v883; VISNI-NEXT: ret84 %b = extractelement <2 x i64> %a, i32 085 ret i64 %b86}87 88define bfloat @extractelt_v8bf16(<8 x bfloat> %a) nounwind {89; CHECK-LABEL: extractelt_v8bf16:90; CHECK: # %bb.0:91; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma92; CHECK-NEXT: vslidedown.vi v8, v8, 793; CHECK-NEXT: vmv.x.s a0, v894; CHECK-NEXT: fmv.h.x fa0, a095; CHECK-NEXT: ret96;97; VISNI-LABEL: extractelt_v8bf16:98; VISNI: # %bb.0:99; VISNI-NEXT: vsetivli zero, 1, e16, m1, ta, ma100; VISNI-NEXT: ri.vextract.x.v a0, v8, 7101; VISNI-NEXT: fmv.h.x fa0, a0102; VISNI-NEXT: ret103 %b = extractelement <8 x bfloat> %a, i32 7104 ret bfloat %b105}106 107define half @extractelt_v8f16(<8 x half> %a) nounwind {108; ZVFH-LABEL: extractelt_v8f16:109; ZVFH: # %bb.0:110; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma111; ZVFH-NEXT: vslidedown.vi v8, v8, 7112; ZVFH-NEXT: vfmv.f.s fa0, v8113; ZVFH-NEXT: ret114;115; ZVFHMIN-LABEL: extractelt_v8f16:116; ZVFHMIN: # %bb.0:117; ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma118; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 7119; ZVFHMIN-NEXT: vmv.x.s a0, v8120; ZVFHMIN-NEXT: fmv.h.x fa0, a0121; ZVFHMIN-NEXT: ret122;123; VISNI-LABEL: extractelt_v8f16:124; VISNI: # %bb.0:125; VISNI-NEXT: vsetivli zero, 1, e16, m1, ta, ma126; VISNI-NEXT: vslidedown.vi v8, v8, 7127; VISNI-NEXT: vfmv.f.s fa0, v8128; VISNI-NEXT: ret129 %b = extractelement <8 x half> %a, i32 7130 ret half %b131}132 133define float @extractelt_v4f32(<4 x float> %a) nounwind {134; CHECK-LABEL: extractelt_v4f32:135; CHECK: # %bb.0:136; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma137; CHECK-NEXT: vslidedown.vi v8, v8, 2138; CHECK-NEXT: vfmv.f.s fa0, v8139; CHECK-NEXT: ret140;141; VISNI-LABEL: extractelt_v4f32:142; VISNI: # %bb.0:143; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma144; VISNI-NEXT: vslidedown.vi v8, v8, 2145; VISNI-NEXT: vfmv.f.s fa0, v8146; VISNI-NEXT: ret147 %b = extractelement <4 x float> %a, i32 2148 ret float %b149}150 151define double @extractelt_v2f64(<2 x double> %a) nounwind {152; CHECK-LABEL: extractelt_v2f64:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma155; CHECK-NEXT: vfmv.f.s fa0, v8156; CHECK-NEXT: ret157;158; VISNI-LABEL: extractelt_v2f64:159; VISNI: # %bb.0:160; VISNI-NEXT: vsetivli zero, 1, e64, m1, ta, ma161; VISNI-NEXT: vfmv.f.s fa0, v8162; VISNI-NEXT: ret163 %b = extractelement <2 x double> %a, i32 0164 ret double %b165}166 167define i8 @extractelt_v32i8(<32 x i8> %a) nounwind {168; CHECK-LABEL: extractelt_v32i8:169; CHECK: # %bb.0:170; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma171; CHECK-NEXT: vslidedown.vi v8, v8, 7172; CHECK-NEXT: vmv.x.s a0, v8173; CHECK-NEXT: ret174;175; VISNI-LABEL: extractelt_v32i8:176; VISNI: # %bb.0:177; VISNI-NEXT: vsetivli zero, 1, e8, m1, ta, ma178; VISNI-NEXT: ri.vextract.x.v a0, v8, 7179; VISNI-NEXT: ret180 %b = extractelement <32 x i8> %a, i32 7181 ret i8 %b182}183 184define i16 @extractelt_v16i16(<16 x i16> %a) nounwind {185; CHECK-LABEL: extractelt_v16i16:186; CHECK: # %bb.0:187; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma188; CHECK-NEXT: vslidedown.vi v8, v8, 7189; CHECK-NEXT: vmv.x.s a0, v8190; CHECK-NEXT: ret191;192; VISNI-LABEL: extractelt_v16i16:193; VISNI: # %bb.0:194; VISNI-NEXT: vsetivli zero, 1, e16, m1, ta, ma195; VISNI-NEXT: ri.vextract.x.v a0, v8, 7196; VISNI-NEXT: ret197 %b = extractelement <16 x i16> %a, i32 7198 ret i16 %b199}200 201define i32 @extractelt_v8i32(<8 x i32> %a) nounwind {202; CHECK-LABEL: extractelt_v8i32:203; CHECK: # %bb.0:204; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma205; CHECK-NEXT: vslidedown.vi v8, v8, 6206; CHECK-NEXT: vmv.x.s a0, v8207; CHECK-NEXT: ret208;209; VISNI-LABEL: extractelt_v8i32:210; VISNI: # %bb.0:211; VISNI-NEXT: vsetivli zero, 1, e32, m2, ta, ma212; VISNI-NEXT: ri.vextract.x.v a0, v8, 6213; VISNI-NEXT: ret214 %b = extractelement <8 x i32> %a, i32 6215 ret i32 %b216}217 218define i64 @extractelt_v4i64(<4 x i64> %a) nounwind {219; RV32-LABEL: extractelt_v4i64:220; RV32: # %bb.0:221; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, ma222; RV32-NEXT: vslidedown.vi v8, v8, 3223; RV32-NEXT: li a0, 32224; RV32-NEXT: vsrl.vx v10, v8, a0225; RV32-NEXT: vmv.x.s a1, v10226; RV32-NEXT: vmv.x.s a0, v8227; RV32-NEXT: ret228;229; RV64-LABEL: extractelt_v4i64:230; RV64: # %bb.0:231; RV64-NEXT: vsetivli zero, 1, e64, m2, ta, ma232; RV64-NEXT: vslidedown.vi v8, v8, 3233; RV64-NEXT: vmv.x.s a0, v8234; RV64-NEXT: ret235;236; VISNI-LABEL: extractelt_v4i64:237; VISNI: # %bb.0:238; VISNI-NEXT: vsetivli zero, 1, e64, m2, ta, ma239; VISNI-NEXT: ri.vextract.x.v a0, v8, 3240; VISNI-NEXT: ret241 %b = extractelement <4 x i64> %a, i32 3242 ret i64 %b243}244 245define bfloat @extractelt_v16bf16(<16 x bfloat> %a) nounwind {246; CHECK-LABEL: extractelt_v16bf16:247; CHECK: # %bb.0:248; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma249; CHECK-NEXT: vslidedown.vi v8, v8, 7250; CHECK-NEXT: vmv.x.s a0, v8251; CHECK-NEXT: fmv.h.x fa0, a0252; CHECK-NEXT: ret253;254; VISNI-LABEL: extractelt_v16bf16:255; VISNI: # %bb.0:256; VISNI-NEXT: vsetivli zero, 1, e16, m1, ta, ma257; VISNI-NEXT: ri.vextract.x.v a0, v8, 7258; VISNI-NEXT: fmv.h.x fa0, a0259; VISNI-NEXT: ret260 %b = extractelement <16 x bfloat> %a, i32 7261 ret bfloat %b262}263 264define half @extractelt_v16f16(<16 x half> %a) nounwind {265; ZVFH-LABEL: extractelt_v16f16:266; ZVFH: # %bb.0:267; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma268; ZVFH-NEXT: vslidedown.vi v8, v8, 7269; ZVFH-NEXT: vfmv.f.s fa0, v8270; ZVFH-NEXT: ret271;272; ZVFHMIN-LABEL: extractelt_v16f16:273; ZVFHMIN: # %bb.0:274; ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma275; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 7276; ZVFHMIN-NEXT: vmv.x.s a0, v8277; ZVFHMIN-NEXT: fmv.h.x fa0, a0278; ZVFHMIN-NEXT: ret279;280; VISNI-LABEL: extractelt_v16f16:281; VISNI: # %bb.0:282; VISNI-NEXT: vsetivli zero, 1, e16, m1, ta, ma283; VISNI-NEXT: vslidedown.vi v8, v8, 7284; VISNI-NEXT: vfmv.f.s fa0, v8285; VISNI-NEXT: ret286 %b = extractelement <16 x half> %a, i32 7287 ret half %b288}289 290define float @extractelt_v8f32(<8 x float> %a) nounwind {291; CHECK-LABEL: extractelt_v8f32:292; CHECK: # %bb.0:293; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma294; CHECK-NEXT: vslidedown.vi v8, v8, 2295; CHECK-NEXT: vfmv.f.s fa0, v8296; CHECK-NEXT: ret297;298; VISNI-LABEL: extractelt_v8f32:299; VISNI: # %bb.0:300; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma301; VISNI-NEXT: vslidedown.vi v8, v8, 2302; VISNI-NEXT: vfmv.f.s fa0, v8303; VISNI-NEXT: ret304 %b = extractelement <8 x float> %a, i32 2305 ret float %b306}307 308define double @extractelt_v4f64(<4 x double> %a) nounwind {309; CHECK-LABEL: extractelt_v4f64:310; CHECK: # %bb.0:311; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma312; CHECK-NEXT: vfmv.f.s fa0, v8313; CHECK-NEXT: ret314;315; VISNI-LABEL: extractelt_v4f64:316; VISNI: # %bb.0:317; VISNI-NEXT: vsetivli zero, 1, e64, m1, ta, ma318; VISNI-NEXT: vfmv.f.s fa0, v8319; VISNI-NEXT: ret320 %b = extractelement <4 x double> %a, i32 0321 ret double %b322}323 324; This uses a non-power of 2 type so that it isn't an MVT to catch an325; incorrect use of getSimpleValueType().326; NOTE: Type legalization is bitcasting to vXi32 and doing 2 independent327; slidedowns and extracts.328define i64 @extractelt_v3i64(<3 x i64> %a) nounwind {329; RV32-LABEL: extractelt_v3i64:330; RV32: # %bb.0:331; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma332; RV32-NEXT: vslidedown.vi v10, v8, 4333; RV32-NEXT: vslidedown.vi v8, v8, 5334; RV32-NEXT: vmv.x.s a0, v10335; RV32-NEXT: vmv.x.s a1, v8336; RV32-NEXT: ret337;338; RV64-LABEL: extractelt_v3i64:339; RV64: # %bb.0:340; RV64-NEXT: vsetivli zero, 1, e64, m2, ta, ma341; RV64-NEXT: vslidedown.vi v8, v8, 2342; RV64-NEXT: vmv.x.s a0, v8343; RV64-NEXT: ret344;345; VISNI-LABEL: extractelt_v3i64:346; VISNI: # %bb.0:347; VISNI-NEXT: vsetivli zero, 1, e64, m2, ta, ma348; VISNI-NEXT: ri.vextract.x.v a0, v8, 2349; VISNI-NEXT: ret350 %b = extractelement <3 x i64> %a, i32 2351 ret i64 %b352}353 354; A LMUL8 type355define i32 @extractelt_v32i32(<32 x i32> %a) nounwind {356; RV32-LABEL: extractelt_v32i32:357; RV32: # %bb.0:358; RV32-NEXT: addi sp, sp, -256359; RV32-NEXT: sw ra, 252(sp) # 4-byte Folded Spill360; RV32-NEXT: sw s0, 248(sp) # 4-byte Folded Spill361; RV32-NEXT: addi s0, sp, 256362; RV32-NEXT: andi sp, sp, -128363; RV32-NEXT: li a0, 32364; RV32-NEXT: mv a1, sp365; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma366; RV32-NEXT: vse32.v v8, (a1)367; RV32-NEXT: lw a0, 124(sp)368; RV32-NEXT: addi sp, s0, -256369; RV32-NEXT: lw ra, 252(sp) # 4-byte Folded Reload370; RV32-NEXT: lw s0, 248(sp) # 4-byte Folded Reload371; RV32-NEXT: addi sp, sp, 256372; RV32-NEXT: ret373;374; RV64-LABEL: extractelt_v32i32:375; RV64: # %bb.0:376; RV64-NEXT: addi sp, sp, -256377; RV64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill378; RV64-NEXT: sd s0, 240(sp) # 8-byte Folded Spill379; RV64-NEXT: addi s0, sp, 256380; RV64-NEXT: andi sp, sp, -128381; RV64-NEXT: li a0, 32382; RV64-NEXT: mv a1, sp383; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, ma384; RV64-NEXT: vse32.v v8, (a1)385; RV64-NEXT: lw a0, 124(sp)386; RV64-NEXT: addi sp, s0, -256387; RV64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload388; RV64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload389; RV64-NEXT: addi sp, sp, 256390; RV64-NEXT: ret391;392; VISNI-LABEL: extractelt_v32i32:393; VISNI: # %bb.0:394; VISNI-NEXT: vsetivli zero, 1, e32, m8, ta, ma395; VISNI-NEXT: ri.vextract.x.v a0, v8, 31396; VISNI-NEXT: ret397 %b = extractelement <32 x i32> %a, i32 31398 ret i32 %b399}400 401; Exercise type legalization for type beyond LMUL8402define i32 @extractelt_v64i32(<64 x i32> %a) nounwind {403; RV32-LABEL: extractelt_v64i32:404; RV32: # %bb.0:405; RV32-NEXT: addi sp, sp, -256406; RV32-NEXT: sw ra, 252(sp) # 4-byte Folded Spill407; RV32-NEXT: sw s0, 248(sp) # 4-byte Folded Spill408; RV32-NEXT: addi s0, sp, 256409; RV32-NEXT: andi sp, sp, -128410; RV32-NEXT: li a0, 32411; RV32-NEXT: mv a1, sp412; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma413; RV32-NEXT: vse32.v v16, (a1)414; RV32-NEXT: lw a0, 124(sp)415; RV32-NEXT: addi sp, s0, -256416; RV32-NEXT: lw ra, 252(sp) # 4-byte Folded Reload417; RV32-NEXT: lw s0, 248(sp) # 4-byte Folded Reload418; RV32-NEXT: addi sp, sp, 256419; RV32-NEXT: ret420;421; RV64-LABEL: extractelt_v64i32:422; RV64: # %bb.0:423; RV64-NEXT: addi sp, sp, -256424; RV64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill425; RV64-NEXT: sd s0, 240(sp) # 8-byte Folded Spill426; RV64-NEXT: addi s0, sp, 256427; RV64-NEXT: andi sp, sp, -128428; RV64-NEXT: li a0, 32429; RV64-NEXT: mv a1, sp430; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, ma431; RV64-NEXT: vse32.v v16, (a1)432; RV64-NEXT: lw a0, 124(sp)433; RV64-NEXT: addi sp, s0, -256434; RV64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload435; RV64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload436; RV64-NEXT: addi sp, sp, 256437; RV64-NEXT: ret438;439; VISNI-LABEL: extractelt_v64i32:440; VISNI: # %bb.0:441; VISNI-NEXT: vsetivli zero, 1, e32, m8, ta, ma442; VISNI-NEXT: ri.vextract.x.v a0, v16, 31443; VISNI-NEXT: ret444 %b = extractelement <64 x i32> %a, i32 63445 ret i32 %b446}447 448define i8 @extractelt_v16i8_idx(<16 x i8> %a, i32 zeroext %idx) nounwind {449; CHECK-LABEL: extractelt_v16i8_idx:450; CHECK: # %bb.0:451; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma452; CHECK-NEXT: vslidedown.vx v8, v8, a0453; CHECK-NEXT: vmv.x.s a0, v8454; CHECK-NEXT: ret455;456; VISNI-LABEL: extractelt_v16i8_idx:457; VISNI: # %bb.0:458; VISNI-NEXT: vsetivli zero, 1, e8, m1, ta, ma459; VISNI-NEXT: vslidedown.vx v8, v8, a0460; VISNI-NEXT: vmv.x.s a0, v8461; VISNI-NEXT: ret462 %b = extractelement <16 x i8> %a, i32 %idx463 ret i8 %b464}465 466define i16 @extractelt_v8i16_idx(<8 x i16> %a, i32 zeroext %idx) nounwind {467; CHECK-LABEL: extractelt_v8i16_idx:468; CHECK: # %bb.0:469; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma470; CHECK-NEXT: vslidedown.vx v8, v8, a0471; CHECK-NEXT: vmv.x.s a0, v8472; CHECK-NEXT: ret473;474; VISNI-LABEL: extractelt_v8i16_idx:475; VISNI: # %bb.0:476; VISNI-NEXT: vsetivli zero, 1, e16, m1, ta, ma477; VISNI-NEXT: vslidedown.vx v8, v8, a0478; VISNI-NEXT: vmv.x.s a0, v8479; VISNI-NEXT: ret480 %b = extractelement <8 x i16> %a, i32 %idx481 ret i16 %b482}483 484define i32 @extractelt_v4i32_idx(<4 x i32> %a, i32 zeroext %idx) nounwind {485; CHECK-LABEL: extractelt_v4i32_idx:486; CHECK: # %bb.0:487; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma488; CHECK-NEXT: vadd.vv v8, v8, v8489; CHECK-NEXT: vslidedown.vx v8, v8, a0490; CHECK-NEXT: vmv.x.s a0, v8491; CHECK-NEXT: ret492;493; VISNI-LABEL: extractelt_v4i32_idx:494; VISNI: # %bb.0:495; VISNI-NEXT: vsetivli zero, 4, e32, m1, ta, ma496; VISNI-NEXT: vadd.vv v8, v8, v8497; VISNI-NEXT: vslidedown.vx v8, v8, a0498; VISNI-NEXT: vmv.x.s a0, v8499; VISNI-NEXT: ret500 %b = add <4 x i32> %a, %a501 %c = extractelement <4 x i32> %b, i32 %idx502 ret i32 %c503}504 505define i64 @extractelt_v2i64_idx(<2 x i64> %a, i32 zeroext %idx) nounwind {506; RV32-LABEL: extractelt_v2i64_idx:507; RV32: # %bb.0:508; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma509; RV32-NEXT: vadd.vv v8, v8, v8510; RV32-NEXT: li a1, 32511; RV32-NEXT: vslidedown.vx v8, v8, a0512; RV32-NEXT: vmv.x.s a0, v8513; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma514; RV32-NEXT: vsrl.vx v8, v8, a1515; RV32-NEXT: vmv.x.s a1, v8516; RV32-NEXT: ret517;518; RV64-LABEL: extractelt_v2i64_idx:519; RV64: # %bb.0:520; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma521; RV64-NEXT: vadd.vv v8, v8, v8522; RV64-NEXT: vslidedown.vx v8, v8, a0523; RV64-NEXT: vmv.x.s a0, v8524; RV64-NEXT: ret525;526; VISNI-LABEL: extractelt_v2i64_idx:527; VISNI: # %bb.0:528; VISNI-NEXT: vsetivli zero, 2, e64, m1, ta, ma529; VISNI-NEXT: vadd.vv v8, v8, v8530; VISNI-NEXT: vslidedown.vx v8, v8, a0531; VISNI-NEXT: vmv.x.s a0, v8532; VISNI-NEXT: ret533 %b = add <2 x i64> %a, %a534 %c = extractelement <2 x i64> %b, i32 %idx535 ret i64 %c536}537 538define bfloat @extractelt_v8bf16_idx(<8 x bfloat> %a, i32 zeroext %idx) nounwind {539; CHECK-LABEL: extractelt_v8bf16_idx:540; CHECK: # %bb.0:541; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma542; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8543; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma544; CHECK-NEXT: vfadd.vv v8, v10, v10545; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma546; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8547; CHECK-NEXT: vslidedown.vx v8, v10, a0548; CHECK-NEXT: vmv.x.s a0, v8549; CHECK-NEXT: fmv.h.x fa0, a0550; CHECK-NEXT: ret551;552; VISNI-LABEL: extractelt_v8bf16_idx:553; VISNI: # %bb.0:554; VISNI-NEXT: vsetivli zero, 8, e16, m1, ta, ma555; VISNI-NEXT: vfwcvtbf16.f.f.v v10, v8556; VISNI-NEXT: vsetvli zero, zero, e32, m2, ta, ma557; VISNI-NEXT: vfadd.vv v8, v10, v10558; VISNI-NEXT: vsetvli zero, zero, e16, m1, ta, ma559; VISNI-NEXT: vfncvtbf16.f.f.w v10, v8560; VISNI-NEXT: vslidedown.vx v8, v10, a0561; VISNI-NEXT: vmv.x.s a0, v8562; VISNI-NEXT: fmv.h.x fa0, a0563; VISNI-NEXT: ret564 %b = fadd <8 x bfloat> %a, %a565 %c = extractelement <8 x bfloat> %b, i32 %idx566 ret bfloat %c567}568 569define half @extractelt_v8f16_idx(<8 x half> %a, i32 zeroext %idx) nounwind {570; ZVFH-LABEL: extractelt_v8f16_idx:571; ZVFH: # %bb.0:572; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma573; ZVFH-NEXT: vfadd.vv v8, v8, v8574; ZVFH-NEXT: vslidedown.vx v8, v8, a0575; ZVFH-NEXT: vfmv.f.s fa0, v8576; ZVFH-NEXT: ret577;578; ZVFHMIN-LABEL: extractelt_v8f16_idx:579; ZVFHMIN: # %bb.0:580; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma581; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8582; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma583; ZVFHMIN-NEXT: vfadd.vv v8, v10, v10584; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma585; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8586; ZVFHMIN-NEXT: vslidedown.vx v8, v10, a0587; ZVFHMIN-NEXT: vmv.x.s a0, v8588; ZVFHMIN-NEXT: fmv.h.x fa0, a0589; ZVFHMIN-NEXT: ret590;591; VISNI-LABEL: extractelt_v8f16_idx:592; VISNI: # %bb.0:593; VISNI-NEXT: vsetivli zero, 8, e16, m1, ta, ma594; VISNI-NEXT: vfadd.vv v8, v8, v8595; VISNI-NEXT: vslidedown.vx v8, v8, a0596; VISNI-NEXT: vfmv.f.s fa0, v8597; VISNI-NEXT: ret598 %b = fadd <8 x half> %a, %a599 %c = extractelement <8 x half> %b, i32 %idx600 ret half %c601}602 603define float @extractelt_v4f32_idx(<4 x float> %a, i32 zeroext %idx) nounwind {604; CHECK-LABEL: extractelt_v4f32_idx:605; CHECK: # %bb.0:606; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma607; CHECK-NEXT: vfadd.vv v8, v8, v8608; CHECK-NEXT: vslidedown.vx v8, v8, a0609; CHECK-NEXT: vfmv.f.s fa0, v8610; CHECK-NEXT: ret611;612; VISNI-LABEL: extractelt_v4f32_idx:613; VISNI: # %bb.0:614; VISNI-NEXT: vsetivli zero, 4, e32, m1, ta, ma615; VISNI-NEXT: vfadd.vv v8, v8, v8616; VISNI-NEXT: vslidedown.vx v8, v8, a0617; VISNI-NEXT: vfmv.f.s fa0, v8618; VISNI-NEXT: ret619 %b = fadd <4 x float> %a, %a620 %c = extractelement <4 x float> %b, i32 %idx621 ret float %c622}623 624define double @extractelt_v2f64_idx(<2 x double> %a, i32 zeroext %idx) nounwind {625; CHECK-LABEL: extractelt_v2f64_idx:626; CHECK: # %bb.0:627; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma628; CHECK-NEXT: vfadd.vv v8, v8, v8629; CHECK-NEXT: vslidedown.vx v8, v8, a0630; CHECK-NEXT: vfmv.f.s fa0, v8631; CHECK-NEXT: ret632;633; VISNI-LABEL: extractelt_v2f64_idx:634; VISNI: # %bb.0:635; VISNI-NEXT: vsetivli zero, 2, e64, m1, ta, ma636; VISNI-NEXT: vfadd.vv v8, v8, v8637; VISNI-NEXT: vslidedown.vx v8, v8, a0638; VISNI-NEXT: vfmv.f.s fa0, v8639; VISNI-NEXT: ret640 %b = fadd <2 x double> %a, %a641 %c = extractelement <2 x double> %b, i32 %idx642 ret double %c643}644 645define i8 @extractelt_v32i8_idx(<32 x i8> %a, i32 zeroext %idx) nounwind {646; CHECK-LABEL: extractelt_v32i8_idx:647; CHECK: # %bb.0:648; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, ma649; CHECK-NEXT: vslidedown.vx v8, v8, a0650; CHECK-NEXT: vmv.x.s a0, v8651; CHECK-NEXT: ret652;653; VISNI-LABEL: extractelt_v32i8_idx:654; VISNI: # %bb.0:655; VISNI-NEXT: vsetivli zero, 1, e8, m2, ta, ma656; VISNI-NEXT: vslidedown.vx v8, v8, a0657; VISNI-NEXT: vmv.x.s a0, v8658; VISNI-NEXT: ret659 %b = extractelement <32 x i8> %a, i32 %idx660 ret i8 %b661}662 663define i16 @extractelt_v16i16_idx(<16 x i16> %a, i32 zeroext %idx) nounwind {664; CHECK-LABEL: extractelt_v16i16_idx:665; CHECK: # %bb.0:666; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, ma667; CHECK-NEXT: vslidedown.vx v8, v8, a0668; CHECK-NEXT: vmv.x.s a0, v8669; CHECK-NEXT: ret670;671; VISNI-LABEL: extractelt_v16i16_idx:672; VISNI: # %bb.0:673; VISNI-NEXT: vsetivli zero, 1, e16, m2, ta, ma674; VISNI-NEXT: vslidedown.vx v8, v8, a0675; VISNI-NEXT: vmv.x.s a0, v8676; VISNI-NEXT: ret677 %b = extractelement <16 x i16> %a, i32 %idx678 ret i16 %b679}680 681define i32 @extractelt_v8i32_idx(<8 x i32> %a, i32 zeroext %idx) nounwind {682; CHECK-LABEL: extractelt_v8i32_idx:683; CHECK: # %bb.0:684; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma685; CHECK-NEXT: vadd.vv v8, v8, v8686; CHECK-NEXT: vslidedown.vx v8, v8, a0687; CHECK-NEXT: vmv.x.s a0, v8688; CHECK-NEXT: ret689;690; VISNI-LABEL: extractelt_v8i32_idx:691; VISNI: # %bb.0:692; VISNI-NEXT: vsetivli zero, 8, e32, m2, ta, ma693; VISNI-NEXT: vadd.vv v8, v8, v8694; VISNI-NEXT: vslidedown.vx v8, v8, a0695; VISNI-NEXT: vmv.x.s a0, v8696; VISNI-NEXT: ret697 %b = add <8 x i32> %a, %a698 %c = extractelement <8 x i32> %b, i32 %idx699 ret i32 %c700}701 702define i64 @extractelt_v4i64_idx(<4 x i64> %a, i32 zeroext %idx) nounwind {703; RV32-LABEL: extractelt_v4i64_idx:704; RV32: # %bb.0:705; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma706; RV32-NEXT: vadd.vv v8, v8, v8707; RV32-NEXT: li a1, 32708; RV32-NEXT: vslidedown.vx v8, v8, a0709; RV32-NEXT: vmv.x.s a0, v8710; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, ma711; RV32-NEXT: vsrl.vx v8, v8, a1712; RV32-NEXT: vmv.x.s a1, v8713; RV32-NEXT: ret714;715; RV64-LABEL: extractelt_v4i64_idx:716; RV64: # %bb.0:717; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma718; RV64-NEXT: vadd.vv v8, v8, v8719; RV64-NEXT: vslidedown.vx v8, v8, a0720; RV64-NEXT: vmv.x.s a0, v8721; RV64-NEXT: ret722;723; VISNI-LABEL: extractelt_v4i64_idx:724; VISNI: # %bb.0:725; VISNI-NEXT: vsetivli zero, 4, e64, m2, ta, ma726; VISNI-NEXT: vadd.vv v8, v8, v8727; VISNI-NEXT: vslidedown.vx v8, v8, a0728; VISNI-NEXT: vmv.x.s a0, v8729; VISNI-NEXT: ret730 %b = add <4 x i64> %a, %a731 %c = extractelement <4 x i64> %b, i32 %idx732 ret i64 %c733}734 735define bfloat @extractelt_v16bf16_idx(<16 x bfloat> %a, i32 zeroext %idx) nounwind {736; CHECK-LABEL: extractelt_v16bf16_idx:737; CHECK: # %bb.0:738; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma739; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8740; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma741; CHECK-NEXT: vfadd.vv v8, v12, v12742; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma743; CHECK-NEXT: vfncvtbf16.f.f.w v12, v8744; CHECK-NEXT: vslidedown.vx v8, v12, a0745; CHECK-NEXT: vmv.x.s a0, v8746; CHECK-NEXT: fmv.h.x fa0, a0747; CHECK-NEXT: ret748;749; VISNI-LABEL: extractelt_v16bf16_idx:750; VISNI: # %bb.0:751; VISNI-NEXT: vsetivli zero, 16, e16, m2, ta, ma752; VISNI-NEXT: vfwcvtbf16.f.f.v v12, v8753; VISNI-NEXT: vsetvli zero, zero, e32, m4, ta, ma754; VISNI-NEXT: vfadd.vv v8, v12, v12755; VISNI-NEXT: vsetvli zero, zero, e16, m2, ta, ma756; VISNI-NEXT: vfncvtbf16.f.f.w v12, v8757; VISNI-NEXT: vslidedown.vx v8, v12, a0758; VISNI-NEXT: vmv.x.s a0, v8759; VISNI-NEXT: fmv.h.x fa0, a0760; VISNI-NEXT: ret761 %b = fadd <16 x bfloat> %a, %a762 %c = extractelement <16 x bfloat> %b, i32 %idx763 ret bfloat %c764}765 766define half @extractelt_v16f16_idx(<16 x half> %a, i32 zeroext %idx) nounwind {767; ZVFH-LABEL: extractelt_v16f16_idx:768; ZVFH: # %bb.0:769; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma770; ZVFH-NEXT: vfadd.vv v8, v8, v8771; ZVFH-NEXT: vslidedown.vx v8, v8, a0772; ZVFH-NEXT: vfmv.f.s fa0, v8773; ZVFH-NEXT: ret774;775; ZVFHMIN-LABEL: extractelt_v16f16_idx:776; ZVFHMIN: # %bb.0:777; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma778; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8779; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma780; ZVFHMIN-NEXT: vfadd.vv v8, v12, v12781; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma782; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v8783; ZVFHMIN-NEXT: vslidedown.vx v8, v12, a0784; ZVFHMIN-NEXT: vmv.x.s a0, v8785; ZVFHMIN-NEXT: fmv.h.x fa0, a0786; ZVFHMIN-NEXT: ret787;788; VISNI-LABEL: extractelt_v16f16_idx:789; VISNI: # %bb.0:790; VISNI-NEXT: vsetivli zero, 16, e16, m2, ta, ma791; VISNI-NEXT: vfadd.vv v8, v8, v8792; VISNI-NEXT: vslidedown.vx v8, v8, a0793; VISNI-NEXT: vfmv.f.s fa0, v8794; VISNI-NEXT: ret795 %b = fadd <16 x half> %a, %a796 %c = extractelement <16 x half> %b, i32 %idx797 ret half %c798}799 800define float @extractelt_v8f32_idx(<8 x float> %a, i32 zeroext %idx) nounwind {801; CHECK-LABEL: extractelt_v8f32_idx:802; CHECK: # %bb.0:803; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma804; CHECK-NEXT: vfadd.vv v8, v8, v8805; CHECK-NEXT: vslidedown.vx v8, v8, a0806; CHECK-NEXT: vfmv.f.s fa0, v8807; CHECK-NEXT: ret808;809; VISNI-LABEL: extractelt_v8f32_idx:810; VISNI: # %bb.0:811; VISNI-NEXT: vsetivli zero, 8, e32, m2, ta, ma812; VISNI-NEXT: vfadd.vv v8, v8, v8813; VISNI-NEXT: vslidedown.vx v8, v8, a0814; VISNI-NEXT: vfmv.f.s fa0, v8815; VISNI-NEXT: ret816 %b = fadd <8 x float> %a, %a817 %c = extractelement <8 x float> %b, i32 %idx818 ret float %c819}820 821define double @extractelt_v4f64_idx(<4 x double> %a, i32 zeroext %idx) nounwind {822; CHECK-LABEL: extractelt_v4f64_idx:823; CHECK: # %bb.0:824; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma825; CHECK-NEXT: vfadd.vv v8, v8, v8826; CHECK-NEXT: vslidedown.vx v8, v8, a0827; CHECK-NEXT: vfmv.f.s fa0, v8828; CHECK-NEXT: ret829;830; VISNI-LABEL: extractelt_v4f64_idx:831; VISNI: # %bb.0:832; VISNI-NEXT: vsetivli zero, 4, e64, m2, ta, ma833; VISNI-NEXT: vfadd.vv v8, v8, v8834; VISNI-NEXT: vslidedown.vx v8, v8, a0835; VISNI-NEXT: vfmv.f.s fa0, v8836; VISNI-NEXT: ret837 %b = fadd <4 x double> %a, %a838 %c = extractelement <4 x double> %b, i32 %idx839 ret double %c840}841 842; This uses a non-power of 2 type so that it isn't an MVT to catch an843; incorrect use of getSimpleValueType_idx(, i32 zeroext %idx).844; NOTE: Type legalization is bitcasting to vXi32 and doing 2 independent845; slidedowns and extracts.846define i64 @extractelt_v3i64_idx(<3 x i64> %a, i32 zeroext %idx) nounwind {847; RV32-LABEL: extractelt_v3i64_idx:848; RV32: # %bb.0:849; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma850; RV32-NEXT: vadd.vv v8, v8, v8851; RV32-NEXT: add a0, a0, a0852; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma853; RV32-NEXT: vslidedown.vx v10, v8, a0854; RV32-NEXT: addi a1, a0, 1855; RV32-NEXT: vmv.x.s a0, v10856; RV32-NEXT: vslidedown.vx v8, v8, a1857; RV32-NEXT: vmv.x.s a1, v8858; RV32-NEXT: ret859;860; RV64-LABEL: extractelt_v3i64_idx:861; RV64: # %bb.0:862; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma863; RV64-NEXT: vadd.vv v8, v8, v8864; RV64-NEXT: vslidedown.vx v8, v8, a0865; RV64-NEXT: vmv.x.s a0, v8866; RV64-NEXT: ret867;868; VISNI-LABEL: extractelt_v3i64_idx:869; VISNI: # %bb.0:870; VISNI-NEXT: vsetivli zero, 4, e64, m2, ta, ma871; VISNI-NEXT: vadd.vv v8, v8, v8872; VISNI-NEXT: vslidedown.vx v8, v8, a0873; VISNI-NEXT: vmv.x.s a0, v8874; VISNI-NEXT: ret875 %b = add <3 x i64> %a, %a876 %c = extractelement <3 x i64> %b, i32 %idx877 ret i64 %c878}879 880define i32 @extractelt_v32i32_idx(ptr %x, i32 zeroext %idx) nounwind {881; RV32NOM-LABEL: extractelt_v32i32_idx:882; RV32NOM: # %bb.0:883; RV32NOM-NEXT: addi sp, sp, -256884; RV32NOM-NEXT: sw ra, 252(sp) # 4-byte Folded Spill885; RV32NOM-NEXT: sw s0, 248(sp) # 4-byte Folded Spill886; RV32NOM-NEXT: sw s2, 244(sp) # 4-byte Folded Spill887; RV32NOM-NEXT: addi s0, sp, 256888; RV32NOM-NEXT: andi sp, sp, -128889; RV32NOM-NEXT: mv s2, a0890; RV32NOM-NEXT: andi a0, a1, 31891; RV32NOM-NEXT: li a1, 4892; RV32NOM-NEXT: call __mulsi3893; RV32NOM-NEXT: li a1, 32894; RV32NOM-NEXT: vsetvli zero, a1, e32, m8, ta, ma895; RV32NOM-NEXT: vle32.v v8, (s2)896; RV32NOM-NEXT: mv a1, sp897; RV32NOM-NEXT: add a0, a1, a0898; RV32NOM-NEXT: vadd.vv v8, v8, v8899; RV32NOM-NEXT: vse32.v v8, (a1)900; RV32NOM-NEXT: lw a0, 0(a0)901; RV32NOM-NEXT: addi sp, s0, -256902; RV32NOM-NEXT: lw ra, 252(sp) # 4-byte Folded Reload903; RV32NOM-NEXT: lw s0, 248(sp) # 4-byte Folded Reload904; RV32NOM-NEXT: lw s2, 244(sp) # 4-byte Folded Reload905; RV32NOM-NEXT: addi sp, sp, 256906; RV32NOM-NEXT: ret907;908; RV32M-LABEL: extractelt_v32i32_idx:909; RV32M: # %bb.0:910; RV32M-NEXT: addi sp, sp, -256911; RV32M-NEXT: sw ra, 252(sp) # 4-byte Folded Spill912; RV32M-NEXT: sw s0, 248(sp) # 4-byte Folded Spill913; RV32M-NEXT: addi s0, sp, 256914; RV32M-NEXT: andi sp, sp, -128915; RV32M-NEXT: andi a1, a1, 31916; RV32M-NEXT: li a2, 32917; RV32M-NEXT: vsetvli zero, a2, e32, m8, ta, ma918; RV32M-NEXT: vle32.v v8, (a0)919; RV32M-NEXT: slli a1, a1, 2920; RV32M-NEXT: mv a0, sp921; RV32M-NEXT: or a1, a0, a1922; RV32M-NEXT: vadd.vv v8, v8, v8923; RV32M-NEXT: vse32.v v8, (a0)924; RV32M-NEXT: lw a0, 0(a1)925; RV32M-NEXT: addi sp, s0, -256926; RV32M-NEXT: lw ra, 252(sp) # 4-byte Folded Reload927; RV32M-NEXT: lw s0, 248(sp) # 4-byte Folded Reload928; RV32M-NEXT: addi sp, sp, 256929; RV32M-NEXT: ret930;931; RV64NOM-LABEL: extractelt_v32i32_idx:932; RV64NOM: # %bb.0:933; RV64NOM-NEXT: addi sp, sp, -256934; RV64NOM-NEXT: sd ra, 248(sp) # 8-byte Folded Spill935; RV64NOM-NEXT: sd s0, 240(sp) # 8-byte Folded Spill936; RV64NOM-NEXT: sd s2, 232(sp) # 8-byte Folded Spill937; RV64NOM-NEXT: addi s0, sp, 256938; RV64NOM-NEXT: andi sp, sp, -128939; RV64NOM-NEXT: mv s2, a0940; RV64NOM-NEXT: andi a0, a1, 31941; RV64NOM-NEXT: li a1, 4942; RV64NOM-NEXT: call __muldi3943; RV64NOM-NEXT: li a1, 32944; RV64NOM-NEXT: vsetvli zero, a1, e32, m8, ta, ma945; RV64NOM-NEXT: vle32.v v8, (s2)946; RV64NOM-NEXT: mv a1, sp947; RV64NOM-NEXT: add a0, a1, a0948; RV64NOM-NEXT: vadd.vv v8, v8, v8949; RV64NOM-NEXT: vse32.v v8, (a1)950; RV64NOM-NEXT: lw a0, 0(a0)951; RV64NOM-NEXT: addi sp, s0, -256952; RV64NOM-NEXT: ld ra, 248(sp) # 8-byte Folded Reload953; RV64NOM-NEXT: ld s0, 240(sp) # 8-byte Folded Reload954; RV64NOM-NEXT: ld s2, 232(sp) # 8-byte Folded Reload955; RV64NOM-NEXT: addi sp, sp, 256956; RV64NOM-NEXT: ret957;958; RV64M-LABEL: extractelt_v32i32_idx:959; RV64M: # %bb.0:960; RV64M-NEXT: addi sp, sp, -256961; RV64M-NEXT: sd ra, 248(sp) # 8-byte Folded Spill962; RV64M-NEXT: sd s0, 240(sp) # 8-byte Folded Spill963; RV64M-NEXT: addi s0, sp, 256964; RV64M-NEXT: andi sp, sp, -128965; RV64M-NEXT: andi a1, a1, 31966; RV64M-NEXT: li a2, 32967; RV64M-NEXT: vsetvli zero, a2, e32, m8, ta, ma968; RV64M-NEXT: vle32.v v8, (a0)969; RV64M-NEXT: slli a1, a1, 2970; RV64M-NEXT: mv a0, sp971; RV64M-NEXT: or a1, a0, a1972; RV64M-NEXT: vadd.vv v8, v8, v8973; RV64M-NEXT: vse32.v v8, (a0)974; RV64M-NEXT: lw a0, 0(a1)975; RV64M-NEXT: addi sp, s0, -256976; RV64M-NEXT: ld ra, 248(sp) # 8-byte Folded Reload977; RV64M-NEXT: ld s0, 240(sp) # 8-byte Folded Reload978; RV64M-NEXT: addi sp, sp, 256979; RV64M-NEXT: ret980;981; VISNI-LABEL: extractelt_v32i32_idx:982; VISNI: # %bb.0:983; VISNI-NEXT: addi sp, sp, -256984; VISNI-NEXT: sd ra, 248(sp) # 8-byte Folded Spill985; VISNI-NEXT: sd s0, 240(sp) # 8-byte Folded Spill986; VISNI-NEXT: addi s0, sp, 256987; VISNI-NEXT: andi sp, sp, -128988; VISNI-NEXT: andi a1, a1, 31989; VISNI-NEXT: li a2, 32990; VISNI-NEXT: vsetvli zero, a2, e32, m8, ta, ma991; VISNI-NEXT: vle32.v v8, (a0)992; VISNI-NEXT: slli a1, a1, 2993; VISNI-NEXT: mv a0, sp994; VISNI-NEXT: or a1, a0, a1995; VISNI-NEXT: vadd.vv v8, v8, v8996; VISNI-NEXT: vse32.v v8, (a0)997; VISNI-NEXT: lw a0, 0(a1)998; VISNI-NEXT: addi sp, s0, -256999; VISNI-NEXT: ld ra, 248(sp) # 8-byte Folded Reload1000; VISNI-NEXT: ld s0, 240(sp) # 8-byte Folded Reload1001; VISNI-NEXT: addi sp, sp, 2561002; VISNI-NEXT: ret1003 %a = load <32 x i32>, ptr %x1004 %b = add <32 x i32> %a, %a1005 %c = extractelement <32 x i32> %b, i32 %idx1006 ret i32 %c1007}1008 1009define i32 @extractelt_v64i32_idx(<64 x i32> %a, i32 zeroext %idx) nounwind {1010; RV32-LABEL: extractelt_v64i32_idx:1011; RV32: # %bb.0:1012; RV32-NEXT: addi sp, sp, -3841013; RV32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill1014; RV32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill1015; RV32-NEXT: addi s0, sp, 3841016; RV32-NEXT: andi sp, sp, -1281017; RV32-NEXT: andi a0, a0, 631018; RV32-NEXT: mv a1, sp1019; RV32-NEXT: li a2, 321020; RV32-NEXT: addi a3, sp, 1281021; RV32-NEXT: slli a0, a0, 21022; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma1023; RV32-NEXT: vadd.vv v8, v8, v81024; RV32-NEXT: vadd.vv v16, v16, v161025; RV32-NEXT: add a0, a1, a01026; RV32-NEXT: vse32.v v16, (a3)1027; RV32-NEXT: vse32.v v8, (a1)1028; RV32-NEXT: lw a0, 0(a0)1029; RV32-NEXT: addi sp, s0, -3841030; RV32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload1031; RV32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload1032; RV32-NEXT: addi sp, sp, 3841033; RV32-NEXT: ret1034;1035; RV64-LABEL: extractelt_v64i32_idx:1036; RV64: # %bb.0:1037; RV64-NEXT: addi sp, sp, -3841038; RV64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill1039; RV64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill1040; RV64-NEXT: addi s0, sp, 3841041; RV64-NEXT: andi sp, sp, -1281042; RV64-NEXT: andi a0, a0, 631043; RV64-NEXT: mv a1, sp1044; RV64-NEXT: li a2, 321045; RV64-NEXT: addi a3, sp, 1281046; RV64-NEXT: slli a0, a0, 21047; RV64-NEXT: vsetvli zero, a2, e32, m8, ta, ma1048; RV64-NEXT: vadd.vv v8, v8, v81049; RV64-NEXT: vadd.vv v16, v16, v161050; RV64-NEXT: add a0, a1, a01051; RV64-NEXT: vse32.v v16, (a3)1052; RV64-NEXT: vse32.v v8, (a1)1053; RV64-NEXT: lw a0, 0(a0)1054; RV64-NEXT: addi sp, s0, -3841055; RV64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload1056; RV64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload1057; RV64-NEXT: addi sp, sp, 3841058; RV64-NEXT: ret1059;1060; VISNI-LABEL: extractelt_v64i32_idx:1061; VISNI: # %bb.0:1062; VISNI-NEXT: addi sp, sp, -3841063; VISNI-NEXT: sd ra, 376(sp) # 8-byte Folded Spill1064; VISNI-NEXT: sd s0, 368(sp) # 8-byte Folded Spill1065; VISNI-NEXT: addi s0, sp, 3841066; VISNI-NEXT: andi sp, sp, -1281067; VISNI-NEXT: andi a0, a0, 631068; VISNI-NEXT: mv a1, sp1069; VISNI-NEXT: li a2, 321070; VISNI-NEXT: addi a3, sp, 1281071; VISNI-NEXT: slli a0, a0, 21072; VISNI-NEXT: vsetvli zero, a2, e32, m8, ta, ma1073; VISNI-NEXT: vadd.vv v8, v8, v81074; VISNI-NEXT: vadd.vv v16, v16, v161075; VISNI-NEXT: add a0, a1, a01076; VISNI-NEXT: vse32.v v16, (a3)1077; VISNI-NEXT: vse32.v v8, (a1)1078; VISNI-NEXT: lw a0, 0(a0)1079; VISNI-NEXT: addi sp, s0, -3841080; VISNI-NEXT: ld ra, 376(sp) # 8-byte Folded Reload1081; VISNI-NEXT: ld s0, 368(sp) # 8-byte Folded Reload1082; VISNI-NEXT: addi sp, sp, 3841083; VISNI-NEXT: ret1084 %b = add <64 x i32> %a, %a1085 %c = extractelement <64 x i32> %b, i32 %idx1086 ret i32 %c1087}1088 1089define void @store_extractelt_v16i8(<16 x i8> %a, ptr %p) nounwind {1090; CHECK-LABEL: store_extractelt_v16i8:1091; CHECK: # %bb.0:1092; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma1093; CHECK-NEXT: vslidedown.vi v8, v8, 71094; CHECK-NEXT: vse8.v v8, (a0)1095; CHECK-NEXT: ret1096;1097; VISNI-LABEL: store_extractelt_v16i8:1098; VISNI: # %bb.0:1099; VISNI-NEXT: vsetivli zero, 1, e8, m1, ta, ma1100; VISNI-NEXT: ri.vextract.x.v a1, v8, 71101; VISNI-NEXT: sb a1, 0(a0)1102; VISNI-NEXT: ret1103 %b = extractelement <16 x i8> %a, i32 71104 store i8 %b, ptr %p1105 ret void1106}1107 1108define void @store_extractelt_v8i16(<8 x i16> %a, ptr %p) nounwind {1109; CHECK-LABEL: store_extractelt_v8i16:1110; CHECK: # %bb.0:1111; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma1112; CHECK-NEXT: vslidedown.vi v8, v8, 71113; CHECK-NEXT: vse16.v v8, (a0)1114; CHECK-NEXT: ret1115;1116; VISNI-LABEL: store_extractelt_v8i16:1117; VISNI: # %bb.0:1118; VISNI-NEXT: vsetivli zero, 1, e16, m1, ta, ma1119; VISNI-NEXT: ri.vextract.x.v a1, v8, 71120; VISNI-NEXT: sh a1, 0(a0)1121; VISNI-NEXT: ret1122 %b = extractelement <8 x i16> %a, i32 71123 store i16 %b, ptr %p1124 ret void1125}1126 1127define void @store_extractelt_v4i32(<4 x i32> %a, ptr %p) nounwind {1128; CHECK-LABEL: store_extractelt_v4i32:1129; CHECK: # %bb.0:1130; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma1131; CHECK-NEXT: vslidedown.vi v8, v8, 21132; CHECK-NEXT: vse32.v v8, (a0)1133; CHECK-NEXT: ret1134;1135; VISNI-LABEL: store_extractelt_v4i32:1136; VISNI: # %bb.0:1137; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma1138; VISNI-NEXT: ri.vextract.x.v a1, v8, 21139; VISNI-NEXT: sw a1, 0(a0)1140; VISNI-NEXT: ret1141 %b = extractelement <4 x i32> %a, i32 21142 store i32 %b, ptr %p1143 ret void1144}1145 1146; FIXME: Use vse64.v on RV32 to avoid two scalar extracts and two scalar stores.1147define void @store_extractelt_v2i64(<2 x i64> %a, ptr %p) nounwind {1148; RV32-LABEL: store_extractelt_v2i64:1149; RV32: # %bb.0:1150; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1151; RV32-NEXT: vslidedown.vi v8, v8, 11152; RV32-NEXT: li a1, 321153; RV32-NEXT: vsrl.vx v9, v8, a11154; RV32-NEXT: vmv.x.s a1, v81155; RV32-NEXT: vmv.x.s a2, v91156; RV32-NEXT: sw a1, 0(a0)1157; RV32-NEXT: sw a2, 4(a0)1158; RV32-NEXT: ret1159;1160; RV64-LABEL: store_extractelt_v2i64:1161; RV64: # %bb.0:1162; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1163; RV64-NEXT: vslidedown.vi v8, v8, 11164; RV64-NEXT: vse64.v v8, (a0)1165; RV64-NEXT: ret1166;1167; VISNI-LABEL: store_extractelt_v2i64:1168; VISNI: # %bb.0:1169; VISNI-NEXT: vsetivli zero, 1, e64, m1, ta, ma1170; VISNI-NEXT: ri.vextract.x.v a1, v8, 11171; VISNI-NEXT: sd a1, 0(a0)1172; VISNI-NEXT: ret1173 %b = extractelement <2 x i64> %a, i64 11174 store i64 %b, ptr %p1175 ret void1176}1177 1178define void @store_extractelt_v2f64(<2 x double> %a, ptr %p) nounwind {1179; CHECK-LABEL: store_extractelt_v2f64:1180; CHECK: # %bb.0:1181; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma1182; CHECK-NEXT: vslidedown.vi v8, v8, 11183; CHECK-NEXT: vse64.v v8, (a0)1184; CHECK-NEXT: ret1185;1186; VISNI-LABEL: store_extractelt_v2f64:1187; VISNI: # %bb.0:1188; VISNI-NEXT: vsetivli zero, 1, e64, m1, ta, ma1189; VISNI-NEXT: vslidedown.vi v8, v8, 11190; VISNI-NEXT: vse64.v v8, (a0)1191; VISNI-NEXT: ret1192 %b = extractelement <2 x double> %a, i64 11193 store double %b, ptr %p1194 ret void1195}1196 1197define i32 @extractelt_add_v4i32(<4 x i32> %x) {1198; RV32-LABEL: extractelt_add_v4i32:1199; RV32: # %bb.0:1200; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma1201; RV32-NEXT: vslidedown.vi v8, v8, 21202; RV32-NEXT: vmv.x.s a0, v81203; RV32-NEXT: addi a0, a0, 131204; RV32-NEXT: ret1205;1206; RV64-LABEL: extractelt_add_v4i32:1207; RV64: # %bb.0:1208; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma1209; RV64-NEXT: vslidedown.vi v8, v8, 21210; RV64-NEXT: vmv.x.s a0, v81211; RV64-NEXT: addiw a0, a0, 131212; RV64-NEXT: ret1213;1214; VISNI-LABEL: extractelt_add_v4i32:1215; VISNI: # %bb.0:1216; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma1217; VISNI-NEXT: ri.vextract.x.v a0, v8, 21218; VISNI-NEXT: addiw a0, a0, 131219; VISNI-NEXT: ret1220 %bo = add <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>1221 %ext = extractelement <4 x i32> %bo, i32 21222 ret i32 %ext1223}1224 1225define i32 @extractelt_sub_v4i32(<4 x i32> %x) {1226; RV32-LABEL: extractelt_sub_v4i32:1227; RV32: # %bb.0:1228; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma1229; RV32-NEXT: vslidedown.vi v8, v8, 21230; RV32-NEXT: vmv.x.s a0, v81231; RV32-NEXT: li a1, 131232; RV32-NEXT: sub a0, a1, a01233; RV32-NEXT: ret1234;1235; RV64-LABEL: extractelt_sub_v4i32:1236; RV64: # %bb.0:1237; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma1238; RV64-NEXT: vslidedown.vi v8, v8, 21239; RV64-NEXT: vmv.x.s a0, v81240; RV64-NEXT: li a1, 131241; RV64-NEXT: subw a0, a1, a01242; RV64-NEXT: ret1243;1244; VISNI-LABEL: extractelt_sub_v4i32:1245; VISNI: # %bb.0:1246; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma1247; VISNI-NEXT: ri.vextract.x.v a0, v8, 21248; VISNI-NEXT: li a1, 131249; VISNI-NEXT: subw a0, a1, a01250; VISNI-NEXT: ret1251 %bo = sub <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %x1252 %ext = extractelement <4 x i32> %bo, i32 21253 ret i32 %ext1254}1255 1256define i32 @extractelt_mul_v4i32(<4 x i32> %x) {1257; RV32NOM-LABEL: extractelt_mul_v4i32:1258; RV32NOM: # %bb.0:1259; RV32NOM-NEXT: li a0, 131260; RV32NOM-NEXT: vsetivli zero, 4, e32, m1, ta, ma1261; RV32NOM-NEXT: vmul.vx v8, v8, a01262; RV32NOM-NEXT: vslidedown.vi v8, v8, 21263; RV32NOM-NEXT: vmv.x.s a0, v81264; RV32NOM-NEXT: ret1265;1266; RV32M-LABEL: extractelt_mul_v4i32:1267; RV32M: # %bb.0:1268; RV32M-NEXT: vsetivli zero, 1, e32, m1, ta, ma1269; RV32M-NEXT: vslidedown.vi v8, v8, 21270; RV32M-NEXT: vmv.x.s a0, v81271; RV32M-NEXT: li a1, 131272; RV32M-NEXT: mul a0, a0, a11273; RV32M-NEXT: ret1274;1275; RV64NOM-LABEL: extractelt_mul_v4i32:1276; RV64NOM: # %bb.0:1277; RV64NOM-NEXT: li a0, 131278; RV64NOM-NEXT: vsetivli zero, 4, e32, m1, ta, ma1279; RV64NOM-NEXT: vmul.vx v8, v8, a01280; RV64NOM-NEXT: vslidedown.vi v8, v8, 21281; RV64NOM-NEXT: vmv.x.s a0, v81282; RV64NOM-NEXT: ret1283;1284; RV64M-LABEL: extractelt_mul_v4i32:1285; RV64M: # %bb.0:1286; RV64M-NEXT: vsetivli zero, 1, e32, m1, ta, ma1287; RV64M-NEXT: vslidedown.vi v8, v8, 21288; RV64M-NEXT: vmv.x.s a0, v81289; RV64M-NEXT: li a1, 131290; RV64M-NEXT: mulw a0, a0, a11291; RV64M-NEXT: ret1292;1293; VISNI-LABEL: extractelt_mul_v4i32:1294; VISNI: # %bb.0:1295; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma1296; VISNI-NEXT: ri.vextract.x.v a0, v8, 21297; VISNI-NEXT: li a1, 131298; VISNI-NEXT: mulw a0, a0, a11299; VISNI-NEXT: ret1300 %bo = mul <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>1301 %ext = extractelement <4 x i32> %bo, i32 21302 ret i32 %ext1303}1304 1305define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) {1306; RV32NOM-LABEL: extractelt_sdiv_v4i32:1307; RV32NOM: # %bb.0:1308; RV32NOM-NEXT: lui a0, %hi(.LCPI46_0)1309; RV32NOM-NEXT: addi a0, a0, %lo(.LCPI46_0)1310; RV32NOM-NEXT: vsetivli zero, 4, e32, m1, ta, ma1311; RV32NOM-NEXT: vle32.v v9, (a0)1312; RV32NOM-NEXT: lui a0, 10444801313; RV32NOM-NEXT: vmv.s.x v10, a01314; RV32NOM-NEXT: lui a0, 123201315; RV32NOM-NEXT: addi a0, a0, 2571316; RV32NOM-NEXT: vsext.vf4 v11, v101317; RV32NOM-NEXT: vand.vv v10, v8, v111318; RV32NOM-NEXT: vmulh.vv v8, v8, v91319; RV32NOM-NEXT: vmv.s.x v9, a01320; RV32NOM-NEXT: vsext.vf4 v11, v91321; RV32NOM-NEXT: vadd.vv v8, v8, v101322; RV32NOM-NEXT: vsra.vv v9, v8, v111323; RV32NOM-NEXT: vsrl.vi v8, v8, 311324; RV32NOM-NEXT: vadd.vv v8, v9, v81325; RV32NOM-NEXT: vslidedown.vi v8, v8, 21326; RV32NOM-NEXT: vmv.x.s a0, v81327; RV32NOM-NEXT: ret1328;1329; RV32M-LABEL: extractelt_sdiv_v4i32:1330; RV32M: # %bb.0:1331; RV32M-NEXT: vsetivli zero, 1, e32, m1, ta, ma1332; RV32M-NEXT: vslidedown.vi v8, v8, 21333; RV32M-NEXT: lui a0, 3226391334; RV32M-NEXT: vmv.x.s a1, v81335; RV32M-NEXT: addi a0, a0, -9451336; RV32M-NEXT: mulh a0, a1, a01337; RV32M-NEXT: srli a1, a0, 311338; RV32M-NEXT: srai a0, a0, 21339; RV32M-NEXT: add a0, a0, a11340; RV32M-NEXT: ret1341;1342; RV64NOM-LABEL: extractelt_sdiv_v4i32:1343; RV64NOM: # %bb.0:1344; RV64NOM-NEXT: lui a0, %hi(.LCPI46_0)1345; RV64NOM-NEXT: addi a0, a0, %lo(.LCPI46_0)1346; RV64NOM-NEXT: vsetivli zero, 4, e32, m1, ta, ma1347; RV64NOM-NEXT: vle32.v v9, (a0)1348; RV64NOM-NEXT: lui a0, 10444801349; RV64NOM-NEXT: vmv.s.x v10, a01350; RV64NOM-NEXT: lui a0, 123201351; RV64NOM-NEXT: addi a0, a0, 2571352; RV64NOM-NEXT: vsext.vf4 v11, v101353; RV64NOM-NEXT: vand.vv v10, v8, v111354; RV64NOM-NEXT: vmulh.vv v8, v8, v91355; RV64NOM-NEXT: vmv.s.x v9, a01356; RV64NOM-NEXT: vadd.vv v8, v8, v101357; RV64NOM-NEXT: vsext.vf4 v10, v91358; RV64NOM-NEXT: vsra.vv v8, v8, v101359; RV64NOM-NEXT: vsrl.vi v9, v8, 311360; RV64NOM-NEXT: vadd.vv v8, v8, v91361; RV64NOM-NEXT: vslidedown.vi v8, v8, 21362; RV64NOM-NEXT: vmv.x.s a0, v81363; RV64NOM-NEXT: ret1364;1365; RV64M-LABEL: extractelt_sdiv_v4i32:1366; RV64M: # %bb.0:1367; RV64M-NEXT: vsetivli zero, 1, e32, m1, ta, ma1368; RV64M-NEXT: vslidedown.vi v8, v8, 21369; RV64M-NEXT: lui a0, 3226391370; RV64M-NEXT: vmv.x.s a1, v81371; RV64M-NEXT: addi a0, a0, -9451372; RV64M-NEXT: mul a0, a1, a01373; RV64M-NEXT: srli a1, a0, 631374; RV64M-NEXT: srai a0, a0, 341375; RV64M-NEXT: add a0, a0, a11376; RV64M-NEXT: ret1377;1378; VISNI-LABEL: extractelt_sdiv_v4i32:1379; VISNI: # %bb.0:1380; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma1381; VISNI-NEXT: ri.vextract.x.v a0, v8, 21382; VISNI-NEXT: lui a1, 3226391383; VISNI-NEXT: sext.w a0, a01384; VISNI-NEXT: addi a1, a1, -9451385; VISNI-NEXT: mul a0, a0, a11386; VISNI-NEXT: srli a1, a0, 631387; VISNI-NEXT: srai a0, a0, 341388; VISNI-NEXT: add a0, a0, a11389; VISNI-NEXT: ret1390 %bo = sdiv <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>1391 %ext = extractelement <4 x i32> %bo, i32 21392 ret i32 %ext1393}1394 1395define i32 @extractelt_udiv_v4i32(<4 x i32> %x) {1396; RV32NOM-LABEL: extractelt_udiv_v4i32:1397; RV32NOM: # %bb.0:1398; RV32NOM-NEXT: vsetivli zero, 4, e32, m1, ta, ma1399; RV32NOM-NEXT: vsrl.vi v8, v8, 01400; RV32NOM-NEXT: lui a0, 3226391401; RV32NOM-NEXT: addi a0, a0, -9451402; RV32NOM-NEXT: vmulhu.vx v8, v8, a01403; RV32NOM-NEXT: vslidedown.vi v8, v8, 21404; RV32NOM-NEXT: vmv.x.s a0, v81405; RV32NOM-NEXT: srli a0, a0, 21406; RV32NOM-NEXT: ret1407;1408; RV32M-LABEL: extractelt_udiv_v4i32:1409; RV32M: # %bb.0:1410; RV32M-NEXT: vsetivli zero, 1, e32, m1, ta, ma1411; RV32M-NEXT: vslidedown.vi v8, v8, 21412; RV32M-NEXT: lui a0, 3226391413; RV32M-NEXT: vmv.x.s a1, v81414; RV32M-NEXT: addi a0, a0, -9451415; RV32M-NEXT: mulhu a0, a1, a01416; RV32M-NEXT: srli a0, a0, 21417; RV32M-NEXT: ret1418;1419; RV64NOM-LABEL: extractelt_udiv_v4i32:1420; RV64NOM: # %bb.0:1421; RV64NOM-NEXT: vsetivli zero, 4, e32, m1, ta, ma1422; RV64NOM-NEXT: vsrl.vi v8, v8, 01423; RV64NOM-NEXT: lui a0, 3226391424; RV64NOM-NEXT: addi a0, a0, -9451425; RV64NOM-NEXT: vmulhu.vx v8, v8, a01426; RV64NOM-NEXT: vslidedown.vi v8, v8, 21427; RV64NOM-NEXT: vmv.x.s a0, v81428; RV64NOM-NEXT: slli a0, a0, 331429; RV64NOM-NEXT: srli a0, a0, 351430; RV64NOM-NEXT: ret1431;1432; RV64M-LABEL: extractelt_udiv_v4i32:1433; RV64M: # %bb.0:1434; RV64M-NEXT: lui a0, 3226391435; RV64M-NEXT: vsetivli zero, 1, e32, m1, ta, ma1436; RV64M-NEXT: vslidedown.vi v8, v8, 21437; RV64M-NEXT: addi a0, a0, -9451438; RV64M-NEXT: vmv.x.s a1, v81439; RV64M-NEXT: slli a0, a0, 321440; RV64M-NEXT: slli a1, a1, 321441; RV64M-NEXT: mulhu a0, a1, a01442; RV64M-NEXT: srli a0, a0, 341443; RV64M-NEXT: ret1444;1445; VISNI-LABEL: extractelt_udiv_v4i32:1446; VISNI: # %bb.0:1447; VISNI-NEXT: lui a0, 3226391448; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma1449; VISNI-NEXT: ri.vextract.x.v a1, v8, 21450; VISNI-NEXT: addi a0, a0, -9451451; VISNI-NEXT: slli a0, a0, 321452; VISNI-NEXT: slli a1, a1, 321453; VISNI-NEXT: mulhu a0, a1, a01454; VISNI-NEXT: srli a0, a0, 341455; VISNI-NEXT: ret1456 %bo = udiv <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>1457 %ext = extractelement <4 x i32> %bo, i32 21458 ret i32 %ext1459}1460 1461define float @extractelt_fadd_v4f32(<4 x float> %x) {1462; CHECK-LABEL: extractelt_fadd_v4f32:1463; CHECK: # %bb.0:1464; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma1465; CHECK-NEXT: vslidedown.vi v8, v8, 21466; CHECK-NEXT: lui a0, 2675201467; CHECK-NEXT: vfmv.f.s fa5, v81468; CHECK-NEXT: fmv.w.x fa4, a01469; CHECK-NEXT: fadd.s fa0, fa5, fa41470; CHECK-NEXT: ret1471;1472; VISNI-LABEL: extractelt_fadd_v4f32:1473; VISNI: # %bb.0:1474; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma1475; VISNI-NEXT: vslidedown.vi v8, v8, 21476; VISNI-NEXT: lui a0, 2675201477; VISNI-NEXT: vfmv.f.s fa5, v81478; VISNI-NEXT: fmv.w.x fa4, a01479; VISNI-NEXT: fadd.s fa0, fa5, fa41480; VISNI-NEXT: ret1481 %bo = fadd <4 x float> %x, <float 11.0, float 12.0, float 13.0, float 14.0>1482 %ext = extractelement <4 x float> %bo, i32 21483 ret float %ext1484}1485 1486define float @extractelt_fsub_v4f32(<4 x float> %x) {1487; CHECK-LABEL: extractelt_fsub_v4f32:1488; CHECK: # %bb.0:1489; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma1490; CHECK-NEXT: vslidedown.vi v8, v8, 21491; CHECK-NEXT: lui a0, 2675201492; CHECK-NEXT: vfmv.f.s fa5, v81493; CHECK-NEXT: fmv.w.x fa4, a01494; CHECK-NEXT: fsub.s fa0, fa4, fa51495; CHECK-NEXT: ret1496;1497; VISNI-LABEL: extractelt_fsub_v4f32:1498; VISNI: # %bb.0:1499; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma1500; VISNI-NEXT: vslidedown.vi v8, v8, 21501; VISNI-NEXT: lui a0, 2675201502; VISNI-NEXT: vfmv.f.s fa5, v81503; VISNI-NEXT: fmv.w.x fa4, a01504; VISNI-NEXT: fsub.s fa0, fa4, fa51505; VISNI-NEXT: ret1506 %bo = fsub <4 x float> <float 11.0, float 12.0, float 13.0, float 14.0>, %x1507 %ext = extractelement <4 x float> %bo, i32 21508 ret float %ext1509}1510 1511define float @extractelt_fmul_v4f32(<4 x float> %x) {1512; CHECK-LABEL: extractelt_fmul_v4f32:1513; CHECK: # %bb.0:1514; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma1515; CHECK-NEXT: vslidedown.vi v8, v8, 21516; CHECK-NEXT: lui a0, 2675201517; CHECK-NEXT: vfmv.f.s fa5, v81518; CHECK-NEXT: fmv.w.x fa4, a01519; CHECK-NEXT: fmul.s fa0, fa5, fa41520; CHECK-NEXT: ret1521;1522; VISNI-LABEL: extractelt_fmul_v4f32:1523; VISNI: # %bb.0:1524; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma1525; VISNI-NEXT: vslidedown.vi v8, v8, 21526; VISNI-NEXT: lui a0, 2675201527; VISNI-NEXT: vfmv.f.s fa5, v81528; VISNI-NEXT: fmv.w.x fa4, a01529; VISNI-NEXT: fmul.s fa0, fa5, fa41530; VISNI-NEXT: ret1531 %bo = fmul <4 x float> %x, <float 11.0, float 12.0, float 13.0, float 14.0>1532 %ext = extractelement <4 x float> %bo, i32 21533 ret float %ext1534}1535 1536define float @extractelt_fdiv_v4f32(<4 x float> %x) {1537; CHECK-LABEL: extractelt_fdiv_v4f32:1538; CHECK: # %bb.0:1539; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma1540; CHECK-NEXT: vslidedown.vi v8, v8, 21541; CHECK-NEXT: lui a0, 2675201542; CHECK-NEXT: vfmv.f.s fa5, v81543; CHECK-NEXT: fmv.w.x fa4, a01544; CHECK-NEXT: fdiv.s fa0, fa5, fa41545; CHECK-NEXT: ret1546;1547; VISNI-LABEL: extractelt_fdiv_v4f32:1548; VISNI: # %bb.0:1549; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma1550; VISNI-NEXT: vslidedown.vi v8, v8, 21551; VISNI-NEXT: lui a0, 2675201552; VISNI-NEXT: vfmv.f.s fa5, v81553; VISNI-NEXT: fmv.w.x fa4, a01554; VISNI-NEXT: fdiv.s fa0, fa5, fa41555; VISNI-NEXT: ret1556 %bo = fdiv <4 x float> %x, <float 11.0, float 12.0, float 13.0, float 14.0>1557 %ext = extractelement <4 x float> %bo, i32 21558 ret float %ext1559}1560 1561define i32 @extractelt_v16i32_idx7_exact_vlen(<16 x i32> %a) nounwind vscale_range(2,2) {1562; CHECK-LABEL: extractelt_v16i32_idx7_exact_vlen:1563; CHECK: # %bb.0:1564; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma1565; CHECK-NEXT: vslidedown.vi v8, v9, 31566; CHECK-NEXT: vmv.x.s a0, v81567; CHECK-NEXT: ret1568;1569; VISNI-LABEL: extractelt_v16i32_idx7_exact_vlen:1570; VISNI: # %bb.0:1571; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma1572; VISNI-NEXT: ri.vextract.x.v a0, v9, 31573; VISNI-NEXT: ret1574 %b = extractelement <16 x i32> %a, i32 71575 ret i32 %b1576}1577 1578define i32 @extractelt_v16i32_idx15_exact_vlen(<16 x i32> %a) nounwind vscale_range(2,2) {1579; CHECK-LABEL: extractelt_v16i32_idx15_exact_vlen:1580; CHECK: # %bb.0:1581; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma1582; CHECK-NEXT: vslidedown.vi v8, v11, 31583; CHECK-NEXT: vmv.x.s a0, v81584; CHECK-NEXT: ret1585;1586; VISNI-LABEL: extractelt_v16i32_idx15_exact_vlen:1587; VISNI: # %bb.0:1588; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma1589; VISNI-NEXT: ri.vextract.x.v a0, v11, 31590; VISNI-NEXT: ret1591 %b = extractelement <16 x i32> %a, i32 151592 ret i32 %b1593}1594