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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV32 %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64 %s6 7define <1 x half> @ceil_v1f16(<1 x half> %x) strictfp {8; CHECK-LABEL: ceil_v1f16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu11; CHECK-NEXT: vmfne.vv v0, v8, v812; CHECK-NEXT: li a0, 2513; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t14; CHECK-NEXT: slli a0, a0, 1015; CHECK-NEXT: vfabs.v v9, v816; CHECK-NEXT: fmv.h.x fa5, a017; CHECK-NEXT: vmflt.vf v0, v9, fa518; CHECK-NEXT: fsrmi a0, 319; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma20; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t21; CHECK-NEXT: fsrm a022; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t23; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu24; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t25; CHECK-NEXT: ret26 %a = call <1 x half> @llvm.experimental.constrained.ceil.v1f16(<1 x half> %x, metadata !"fpexcept.strict")27 ret <1 x half> %a28}29 30define <2 x half> @ceil_v2f16(<2 x half> %x) strictfp {31; CHECK-LABEL: ceil_v2f16:32; CHECK: # %bb.0:33; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu34; CHECK-NEXT: vmfne.vv v0, v8, v835; CHECK-NEXT: li a0, 2536; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t37; CHECK-NEXT: slli a0, a0, 1038; CHECK-NEXT: vfabs.v v9, v839; CHECK-NEXT: fmv.h.x fa5, a040; CHECK-NEXT: vmflt.vf v0, v9, fa541; CHECK-NEXT: fsrmi a0, 342; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma43; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t44; CHECK-NEXT: fsrm a045; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t46; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu47; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t48; CHECK-NEXT: ret49 %a = call <2 x half> @llvm.experimental.constrained.ceil.v2f16(<2 x half> %x, metadata !"fpexcept.strict")50 ret <2 x half> %a51}52 53define <4 x half> @ceil_v4f16(<4 x half> %x) strictfp {54; CHECK-LABEL: ceil_v4f16:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu57; CHECK-NEXT: vmfne.vv v0, v8, v858; CHECK-NEXT: li a0, 2559; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t60; CHECK-NEXT: slli a0, a0, 1061; CHECK-NEXT: vfabs.v v9, v862; CHECK-NEXT: fmv.h.x fa5, a063; CHECK-NEXT: vmflt.vf v0, v9, fa564; CHECK-NEXT: fsrmi a0, 365; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma66; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t67; CHECK-NEXT: fsrm a068; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t69; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu70; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t71; CHECK-NEXT: ret72 %a = call <4 x half> @llvm.experimental.constrained.ceil.v4f16(<4 x half> %x, metadata !"fpexcept.strict")73 ret <4 x half> %a74}75 76define <8 x half> @ceil_v8f16(<8 x half> %x) strictfp {77; CHECK-LABEL: ceil_v8f16:78; CHECK: # %bb.0:79; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu80; CHECK-NEXT: vmfne.vv v0, v8, v881; CHECK-NEXT: li a0, 2582; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t83; CHECK-NEXT: slli a0, a0, 1084; CHECK-NEXT: vfabs.v v9, v885; CHECK-NEXT: fmv.h.x fa5, a086; CHECK-NEXT: vmflt.vf v0, v9, fa587; CHECK-NEXT: fsrmi a0, 388; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma89; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t90; CHECK-NEXT: fsrm a091; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t92; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu93; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t94; CHECK-NEXT: ret95 %a = call <8 x half> @llvm.experimental.constrained.ceil.v8f16(<8 x half> %x, metadata !"fpexcept.strict")96 ret <8 x half> %a97}98 99define <16 x half> @ceil_v16f16(<16 x half> %x) strictfp {100; CHECK-LABEL: ceil_v16f16:101; CHECK: # %bb.0:102; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu103; CHECK-NEXT: vmfne.vv v0, v8, v8104; CHECK-NEXT: li a0, 25105; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t106; CHECK-NEXT: slli a0, a0, 10107; CHECK-NEXT: vfabs.v v10, v8108; CHECK-NEXT: fmv.h.x fa5, a0109; CHECK-NEXT: vmflt.vf v0, v10, fa5110; CHECK-NEXT: fsrmi a0, 3111; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma112; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t113; CHECK-NEXT: fsrm a0114; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t115; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu116; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t117; CHECK-NEXT: ret118 %a = call <16 x half> @llvm.experimental.constrained.ceil.v16f16(<16 x half> %x, metadata !"fpexcept.strict")119 ret <16 x half> %a120}121 122define <32 x half> @ceil_v32f16(<32 x half> %x) strictfp {123; CHECK-LABEL: ceil_v32f16:124; CHECK: # %bb.0:125; CHECK-NEXT: li a0, 32126; CHECK-NEXT: li a1, 25127; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu128; CHECK-NEXT: vmfne.vv v0, v8, v8129; CHECK-NEXT: slli a1, a1, 10130; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t131; CHECK-NEXT: fmv.h.x fa5, a1132; CHECK-NEXT: vfabs.v v12, v8133; CHECK-NEXT: vmflt.vf v0, v12, fa5134; CHECK-NEXT: fsrmi a0, 3135; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma136; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t137; CHECK-NEXT: fsrm a0138; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t139; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu140; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t141; CHECK-NEXT: ret142 %a = call <32 x half> @llvm.experimental.constrained.ceil.v32f16(<32 x half> %x, metadata !"fpexcept.strict")143 ret <32 x half> %a144}145 146define <1 x float> @ceil_v1f32(<1 x float> %x) strictfp {147; CHECK-LABEL: ceil_v1f32:148; CHECK: # %bb.0:149; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu150; CHECK-NEXT: vmfne.vv v0, v8, v8151; CHECK-NEXT: lui a0, 307200152; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t153; CHECK-NEXT: fmv.w.x fa5, a0154; CHECK-NEXT: vfabs.v v9, v8155; CHECK-NEXT: vmflt.vf v0, v9, fa5156; CHECK-NEXT: fsrmi a0, 3157; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma158; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t159; CHECK-NEXT: fsrm a0160; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t161; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu162; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t163; CHECK-NEXT: ret164 %a = call <1 x float> @llvm.experimental.constrained.ceil.v1f32(<1 x float> %x, metadata !"fpexcept.strict")165 ret <1 x float> %a166}167 168define <2 x float> @ceil_v2f32(<2 x float> %x) strictfp {169; CHECK-LABEL: ceil_v2f32:170; CHECK: # %bb.0:171; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu172; CHECK-NEXT: vmfne.vv v0, v8, v8173; CHECK-NEXT: lui a0, 307200174; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t175; CHECK-NEXT: fmv.w.x fa5, a0176; CHECK-NEXT: vfabs.v v9, v8177; CHECK-NEXT: vmflt.vf v0, v9, fa5178; CHECK-NEXT: fsrmi a0, 3179; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma180; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t181; CHECK-NEXT: fsrm a0182; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t183; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu184; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t185; CHECK-NEXT: ret186 %a = call <2 x float> @llvm.experimental.constrained.ceil.v2f32(<2 x float> %x, metadata !"fpexcept.strict")187 ret <2 x float> %a188}189 190define <4 x float> @ceil_v4f32(<4 x float> %x) strictfp {191; CHECK-LABEL: ceil_v4f32:192; CHECK: # %bb.0:193; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu194; CHECK-NEXT: vmfne.vv v0, v8, v8195; CHECK-NEXT: lui a0, 307200196; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t197; CHECK-NEXT: fmv.w.x fa5, a0198; CHECK-NEXT: vfabs.v v9, v8199; CHECK-NEXT: vmflt.vf v0, v9, fa5200; CHECK-NEXT: fsrmi a0, 3201; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma202; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t203; CHECK-NEXT: fsrm a0204; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t205; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu206; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t207; CHECK-NEXT: ret208 %a = call <4 x float> @llvm.experimental.constrained.ceil.v4f32(<4 x float> %x, metadata !"fpexcept.strict")209 ret <4 x float> %a210}211 212define <8 x float> @ceil_v8f32(<8 x float> %x) strictfp {213; CHECK-LABEL: ceil_v8f32:214; CHECK: # %bb.0:215; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu216; CHECK-NEXT: vmfne.vv v0, v8, v8217; CHECK-NEXT: lui a0, 307200218; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t219; CHECK-NEXT: fmv.w.x fa5, a0220; CHECK-NEXT: vfabs.v v10, v8221; CHECK-NEXT: vmflt.vf v0, v10, fa5222; CHECK-NEXT: fsrmi a0, 3223; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma224; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t225; CHECK-NEXT: fsrm a0226; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t227; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu228; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t229; CHECK-NEXT: ret230 %a = call <8 x float> @llvm.experimental.constrained.ceil.v8f32(<8 x float> %x, metadata !"fpexcept.strict")231 ret <8 x float> %a232}233 234define <16 x float> @ceil_v16f32(<16 x float> %x) strictfp {235; CHECK-LABEL: ceil_v16f32:236; CHECK: # %bb.0:237; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu238; CHECK-NEXT: vmfne.vv v0, v8, v8239; CHECK-NEXT: lui a0, 307200240; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t241; CHECK-NEXT: fmv.w.x fa5, a0242; CHECK-NEXT: vfabs.v v12, v8243; CHECK-NEXT: vmflt.vf v0, v12, fa5244; CHECK-NEXT: fsrmi a0, 3245; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma246; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t247; CHECK-NEXT: fsrm a0248; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t249; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu250; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t251; CHECK-NEXT: ret252 %a = call <16 x float> @llvm.experimental.constrained.ceil.v16f32(<16 x float> %x, metadata !"fpexcept.strict")253 ret <16 x float> %a254}255 256define <1 x double> @ceil_v1f64(<1 x double> %x) strictfp {257; RV32-LABEL: ceil_v1f64:258; RV32: # %bb.0:259; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu260; RV32-NEXT: vmfne.vv v0, v8, v8261; RV32-NEXT: lui a0, %hi(.LCPI11_0)262; RV32-NEXT: fld fa5, %lo(.LCPI11_0)(a0)263; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t264; RV32-NEXT: vfabs.v v9, v8265; RV32-NEXT: vmflt.vf v0, v9, fa5266; RV32-NEXT: fsrmi a0, 3267; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma268; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t269; RV32-NEXT: fsrm a0270; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t271; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu272; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t273; RV32-NEXT: ret274;275; RV64-LABEL: ceil_v1f64:276; RV64: # %bb.0:277; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu278; RV64-NEXT: vmfne.vv v0, v8, v8279; RV64-NEXT: li a0, 1075280; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t281; RV64-NEXT: slli a0, a0, 52282; RV64-NEXT: vfabs.v v9, v8283; RV64-NEXT: fmv.d.x fa5, a0284; RV64-NEXT: vmflt.vf v0, v9, fa5285; RV64-NEXT: fsrmi a0, 3286; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma287; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t288; RV64-NEXT: fsrm a0289; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t290; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu291; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t292; RV64-NEXT: ret293 %a = call <1 x double> @llvm.experimental.constrained.ceil.v1f64(<1 x double> %x, metadata !"fpexcept.strict")294 ret <1 x double> %a295}296 297define <2 x double> @ceil_v2f64(<2 x double> %x) strictfp {298; RV32-LABEL: ceil_v2f64:299; RV32: # %bb.0:300; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu301; RV32-NEXT: vmfne.vv v0, v8, v8302; RV32-NEXT: lui a0, %hi(.LCPI12_0)303; RV32-NEXT: fld fa5, %lo(.LCPI12_0)(a0)304; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t305; RV32-NEXT: vfabs.v v9, v8306; RV32-NEXT: vmflt.vf v0, v9, fa5307; RV32-NEXT: fsrmi a0, 3308; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma309; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t310; RV32-NEXT: fsrm a0311; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t312; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu313; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t314; RV32-NEXT: ret315;316; RV64-LABEL: ceil_v2f64:317; RV64: # %bb.0:318; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu319; RV64-NEXT: vmfne.vv v0, v8, v8320; RV64-NEXT: li a0, 1075321; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t322; RV64-NEXT: slli a0, a0, 52323; RV64-NEXT: vfabs.v v9, v8324; RV64-NEXT: fmv.d.x fa5, a0325; RV64-NEXT: vmflt.vf v0, v9, fa5326; RV64-NEXT: fsrmi a0, 3327; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma328; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t329; RV64-NEXT: fsrm a0330; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t331; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu332; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t333; RV64-NEXT: ret334 %a = call <2 x double> @llvm.experimental.constrained.ceil.v2f64(<2 x double> %x, metadata !"fpexcept.strict")335 ret <2 x double> %a336}337 338define <4 x double> @ceil_v4f64(<4 x double> %x) strictfp {339; RV32-LABEL: ceil_v4f64:340; RV32: # %bb.0:341; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu342; RV32-NEXT: vmfne.vv v0, v8, v8343; RV32-NEXT: lui a0, %hi(.LCPI13_0)344; RV32-NEXT: fld fa5, %lo(.LCPI13_0)(a0)345; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t346; RV32-NEXT: vfabs.v v10, v8347; RV32-NEXT: vmflt.vf v0, v10, fa5348; RV32-NEXT: fsrmi a0, 3349; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma350; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t351; RV32-NEXT: fsrm a0352; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t353; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu354; RV32-NEXT: vfsgnj.vv v8, v10, v8, v0.t355; RV32-NEXT: ret356;357; RV64-LABEL: ceil_v4f64:358; RV64: # %bb.0:359; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu360; RV64-NEXT: vmfne.vv v0, v8, v8361; RV64-NEXT: li a0, 1075362; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t363; RV64-NEXT: slli a0, a0, 52364; RV64-NEXT: vfabs.v v10, v8365; RV64-NEXT: fmv.d.x fa5, a0366; RV64-NEXT: vmflt.vf v0, v10, fa5367; RV64-NEXT: fsrmi a0, 3368; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma369; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t370; RV64-NEXT: fsrm a0371; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t372; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu373; RV64-NEXT: vfsgnj.vv v8, v10, v8, v0.t374; RV64-NEXT: ret375 %a = call <4 x double> @llvm.experimental.constrained.ceil.v4f64(<4 x double> %x, metadata !"fpexcept.strict")376 ret <4 x double> %a377}378 379define <8 x double> @ceil_v8f64(<8 x double> %x) strictfp {380; RV32-LABEL: ceil_v8f64:381; RV32: # %bb.0:382; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu383; RV32-NEXT: vmfne.vv v0, v8, v8384; RV32-NEXT: lui a0, %hi(.LCPI14_0)385; RV32-NEXT: fld fa5, %lo(.LCPI14_0)(a0)386; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t387; RV32-NEXT: vfabs.v v12, v8388; RV32-NEXT: vmflt.vf v0, v12, fa5389; RV32-NEXT: fsrmi a0, 3390; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma391; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t392; RV32-NEXT: fsrm a0393; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t394; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu395; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t396; RV32-NEXT: ret397;398; RV64-LABEL: ceil_v8f64:399; RV64: # %bb.0:400; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu401; RV64-NEXT: vmfne.vv v0, v8, v8402; RV64-NEXT: li a0, 1075403; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t404; RV64-NEXT: slli a0, a0, 52405; RV64-NEXT: vfabs.v v12, v8406; RV64-NEXT: fmv.d.x fa5, a0407; RV64-NEXT: vmflt.vf v0, v12, fa5408; RV64-NEXT: fsrmi a0, 3409; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma410; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t411; RV64-NEXT: fsrm a0412; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t413; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu414; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t415; RV64-NEXT: ret416 %a = call <8 x double> @llvm.experimental.constrained.ceil.v8f64(<8 x double> %x, metadata !"fpexcept.strict")417 ret <8 x double> %a418}419