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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+m -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+m -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN10 11define <2 x half> @vfmin_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i32 zeroext %evl) {12; ZVFH-LABEL: vfmin_vv_v2f16:13; ZVFH: # %bb.0:14; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma15; ZVFH-NEXT: vmv1r.v v10, v016; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t17; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v018; ZVFH-NEXT: vmv1r.v v0, v1019; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t20; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v021; ZVFH-NEXT: vmv1r.v v0, v1022; ZVFH-NEXT: vfmin.vv v8, v8, v11, v0.t23; ZVFH-NEXT: ret24;25; ZVFHMIN-LABEL: vfmin_vv_v2f16:26; ZVFHMIN: # %bb.0:27; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma28; ZVFHMIN-NEXT: vmv1r.v v10, v029; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t30; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t31; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma32; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9, v0.t33; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v11, v034; ZVFHMIN-NEXT: vmv1r.v v0, v1035; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t36; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v9, v037; ZVFHMIN-NEXT: vmv1r.v v0, v1038; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8, v0.t39; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma40; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t41; ZVFHMIN-NEXT: ret42 %v = call <2 x half> @llvm.vp.minimum.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i32 %evl)43 ret <2 x half> %v44}45 46define <2 x half> @vfmin_vv_v2f16_unmasked(<2 x half> %va, <2 x half> %vb, i32 zeroext %evl) {47; ZVFH-LABEL: vfmin_vv_v2f16_unmasked:48; ZVFH: # %bb.0:49; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma50; ZVFH-NEXT: vmfeq.vv v0, v8, v851; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v052; ZVFH-NEXT: vmfeq.vv v0, v9, v953; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v054; ZVFH-NEXT: vfmin.vv v8, v8, v1055; ZVFH-NEXT: ret56;57; ZVFHMIN-LABEL: vfmin_vv_v2f16_unmasked:58; ZVFHMIN: # %bb.0:59; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma60; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v861; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma62; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v1063; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma64; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v965; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma66; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v067; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v868; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v069; ZVFHMIN-NEXT: vfmin.vv v9, v8, v970; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma71; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v972; ZVFHMIN-NEXT: ret73 %v = call <2 x half> @llvm.vp.minimum.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> splat (i1 true), i32 %evl)74 ret <2 x half> %v75}76 77define <4 x half> @vfmin_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i32 zeroext %evl) {78; ZVFH-LABEL: vfmin_vv_v4f16:79; ZVFH: # %bb.0:80; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma81; ZVFH-NEXT: vmv1r.v v10, v082; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t83; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v084; ZVFH-NEXT: vmv1r.v v0, v1085; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t86; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v087; ZVFH-NEXT: vmv1r.v v0, v1088; ZVFH-NEXT: vfmin.vv v8, v8, v11, v0.t89; ZVFH-NEXT: ret90;91; ZVFHMIN-LABEL: vfmin_vv_v4f16:92; ZVFHMIN: # %bb.0:93; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma94; ZVFHMIN-NEXT: vmv1r.v v10, v095; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t96; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t97; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma98; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9, v0.t99; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v11, v0100; ZVFHMIN-NEXT: vmv1r.v v0, v10101; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t102; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v9, v0103; ZVFHMIN-NEXT: vmv1r.v v0, v10104; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8, v0.t105; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma106; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t107; ZVFHMIN-NEXT: ret108 %v = call <4 x half> @llvm.vp.minimum.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i32 %evl)109 ret <4 x half> %v110}111 112define <4 x half> @vfmin_vv_v4f16_unmasked(<4 x half> %va, <4 x half> %vb, i32 zeroext %evl) {113; ZVFH-LABEL: vfmin_vv_v4f16_unmasked:114; ZVFH: # %bb.0:115; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma116; ZVFH-NEXT: vmfeq.vv v0, v8, v8117; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0118; ZVFH-NEXT: vmfeq.vv v0, v9, v9119; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0120; ZVFH-NEXT: vfmin.vv v8, v8, v10121; ZVFH-NEXT: ret122;123; ZVFHMIN-LABEL: vfmin_vv_v4f16_unmasked:124; ZVFHMIN: # %bb.0:125; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma126; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8127; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma128; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10129; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma130; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9131; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma132; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0133; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8134; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0135; ZVFHMIN-NEXT: vfmin.vv v9, v8, v9136; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma137; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9138; ZVFHMIN-NEXT: ret139 %v = call <4 x half> @llvm.vp.minimum.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> splat (i1 true), i32 %evl)140 ret <4 x half> %v141}142 143define <8 x half> @vfmin_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {144; ZVFH-LABEL: vfmin_vv_v8f16:145; ZVFH: # %bb.0:146; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma147; ZVFH-NEXT: vmv1r.v v10, v0148; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t149; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0150; ZVFH-NEXT: vmv1r.v v0, v10151; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t152; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0153; ZVFH-NEXT: vmv1r.v v0, v10154; ZVFH-NEXT: vfmin.vv v8, v8, v11, v0.t155; ZVFH-NEXT: ret156;157; ZVFHMIN-LABEL: vfmin_vv_v8f16:158; ZVFHMIN: # %bb.0:159; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma160; ZVFHMIN-NEXT: vmv1r.v v10, v0161; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9, v0.t162; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t163; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma164; ZVFHMIN-NEXT: vmfeq.vv v8, v14, v14, v0.t165; ZVFHMIN-NEXT: vmv1r.v v0, v8166; ZVFHMIN-NEXT: vmerge.vvm v16, v14, v12, v0167; ZVFHMIN-NEXT: vmv1r.v v0, v10168; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t169; ZVFHMIN-NEXT: vmv1r.v v0, v8170; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v14, v0171; ZVFHMIN-NEXT: vmv1r.v v0, v10172; ZVFHMIN-NEXT: vfmin.vv v12, v8, v16, v0.t173; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma174; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t175; ZVFHMIN-NEXT: ret176 %v = call <8 x half> @llvm.vp.minimum.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 %evl)177 ret <8 x half> %v178}179 180define <8 x half> @vfmin_vv_v8f16_unmasked(<8 x half> %va, <8 x half> %vb, i32 zeroext %evl) {181; ZVFH-LABEL: vfmin_vv_v8f16_unmasked:182; ZVFH: # %bb.0:183; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma184; ZVFH-NEXT: vmfeq.vv v0, v8, v8185; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0186; ZVFH-NEXT: vmfeq.vv v0, v9, v9187; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0188; ZVFH-NEXT: vfmin.vv v8, v8, v10189; ZVFH-NEXT: ret190;191; ZVFHMIN-LABEL: vfmin_vv_v8f16_unmasked:192; ZVFHMIN: # %bb.0:193; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma194; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8195; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma196; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10197; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma198; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9199; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma200; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0201; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12202; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0203; ZVFHMIN-NEXT: vfmin.vv v10, v10, v8204; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma205; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10206; ZVFHMIN-NEXT: ret207 %v = call <8 x half> @llvm.vp.minimum.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> splat (i1 true), i32 %evl)208 ret <8 x half> %v209}210 211define <16 x half> @vfmin_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 zeroext %evl) {212; ZVFH-LABEL: vfmin_vv_v16f16:213; ZVFH: # %bb.0:214; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma215; ZVFH-NEXT: vmv1r.v v12, v0216; ZVFH-NEXT: vmfeq.vv v13, v8, v8, v0.t217; ZVFH-NEXT: vmv1r.v v0, v13218; ZVFH-NEXT: vmerge.vvm v14, v8, v10, v0219; ZVFH-NEXT: vmv1r.v v0, v12220; ZVFH-NEXT: vmfeq.vv v13, v10, v10, v0.t221; ZVFH-NEXT: vmv1r.v v0, v13222; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0223; ZVFH-NEXT: vmv1r.v v0, v12224; ZVFH-NEXT: vfmin.vv v8, v8, v14, v0.t225; ZVFH-NEXT: ret226;227; ZVFHMIN-LABEL: vfmin_vv_v16f16:228; ZVFHMIN: # %bb.0:229; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma230; ZVFHMIN-NEXT: vmv1r.v v12, v0231; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10, v0.t232; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t233; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma234; ZVFHMIN-NEXT: vmfeq.vv v8, v20, v20, v0.t235; ZVFHMIN-NEXT: vmv1r.v v0, v8236; ZVFHMIN-NEXT: vmerge.vvm v24, v20, v16, v0237; ZVFHMIN-NEXT: vmv1r.v v0, v12238; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t239; ZVFHMIN-NEXT: vmv1r.v v0, v8240; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v20, v0241; ZVFHMIN-NEXT: vmv1r.v v0, v12242; ZVFHMIN-NEXT: vfmin.vv v16, v8, v24, v0.t243; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma244; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t245; ZVFHMIN-NEXT: ret246 %v = call <16 x half> @llvm.vp.minimum.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 %evl)247 ret <16 x half> %v248}249 250define <16 x half> @vfmin_vv_v16f16_unmasked(<16 x half> %va, <16 x half> %vb, i32 zeroext %evl) {251; ZVFH-LABEL: vfmin_vv_v16f16_unmasked:252; ZVFH: # %bb.0:253; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma254; ZVFH-NEXT: vmfeq.vv v0, v8, v8255; ZVFH-NEXT: vmerge.vvm v12, v8, v10, v0256; ZVFH-NEXT: vmfeq.vv v0, v10, v10257; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0258; ZVFH-NEXT: vfmin.vv v8, v8, v12259; ZVFH-NEXT: ret260;261; ZVFHMIN-LABEL: vfmin_vv_v16f16_unmasked:262; ZVFHMIN: # %bb.0:263; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma264; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8265; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma266; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12267; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma268; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10269; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma270; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0271; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16272; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0273; ZVFHMIN-NEXT: vfmin.vv v12, v12, v8274; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma275; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12276; ZVFHMIN-NEXT: ret277 %v = call <16 x half> @llvm.vp.minimum.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> splat (i1 true), i32 %evl)278 ret <16 x half> %v279}280 281define <2 x float> @vfmin_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 zeroext %evl) {282; CHECK-LABEL: vfmin_vv_v2f32:283; CHECK: # %bb.0:284; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma285; CHECK-NEXT: vmv1r.v v10, v0286; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t287; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0288; CHECK-NEXT: vmv1r.v v0, v10289; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t290; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0291; CHECK-NEXT: vmv1r.v v0, v10292; CHECK-NEXT: vfmin.vv v8, v8, v11, v0.t293; CHECK-NEXT: ret294 %v = call <2 x float> @llvm.vp.minimum.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 %evl)295 ret <2 x float> %v296}297 298define <2 x float> @vfmin_vv_v2f32_unmasked(<2 x float> %va, <2 x float> %vb, i32 zeroext %evl) {299; CHECK-LABEL: vfmin_vv_v2f32_unmasked:300; CHECK: # %bb.0:301; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma302; CHECK-NEXT: vmfeq.vv v0, v8, v8303; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0304; CHECK-NEXT: vmfeq.vv v0, v9, v9305; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0306; CHECK-NEXT: vfmin.vv v8, v8, v10307; CHECK-NEXT: ret308 %v = call <2 x float> @llvm.vp.minimum.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> splat (i1 true), i32 %evl)309 ret <2 x float> %v310}311 312define <4 x float> @vfmin_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 zeroext %evl) {313; CHECK-LABEL: vfmin_vv_v4f32:314; CHECK: # %bb.0:315; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma316; CHECK-NEXT: vmv1r.v v10, v0317; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t318; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0319; CHECK-NEXT: vmv1r.v v0, v10320; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t321; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0322; CHECK-NEXT: vmv1r.v v0, v10323; CHECK-NEXT: vfmin.vv v8, v8, v11, v0.t324; CHECK-NEXT: ret325 %v = call <4 x float> @llvm.vp.minimum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl)326 ret <4 x float> %v327}328 329define <4 x float> @vfmin_vv_v4f32_unmasked(<4 x float> %va, <4 x float> %vb, i32 zeroext %evl) {330; CHECK-LABEL: vfmin_vv_v4f32_unmasked:331; CHECK: # %bb.0:332; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma333; CHECK-NEXT: vmfeq.vv v0, v8, v8334; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0335; CHECK-NEXT: vmfeq.vv v0, v9, v9336; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0337; CHECK-NEXT: vfmin.vv v8, v8, v10338; CHECK-NEXT: ret339 %v = call <4 x float> @llvm.vp.minimum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> splat (i1 true), i32 %evl)340 ret <4 x float> %v341}342 343define <8 x float> @vfmin_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 zeroext %evl) {344; CHECK-LABEL: vfmin_vv_v8f32:345; CHECK: # %bb.0:346; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma347; CHECK-NEXT: vmv1r.v v12, v0348; CHECK-NEXT: vmfeq.vv v13, v8, v8, v0.t349; CHECK-NEXT: vmv1r.v v0, v13350; CHECK-NEXT: vmerge.vvm v14, v8, v10, v0351; CHECK-NEXT: vmv1r.v v0, v12352; CHECK-NEXT: vmfeq.vv v13, v10, v10, v0.t353; CHECK-NEXT: vmv1r.v v0, v13354; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0355; CHECK-NEXT: vmv1r.v v0, v12356; CHECK-NEXT: vfmin.vv v8, v8, v14, v0.t357; CHECK-NEXT: ret358 %v = call <8 x float> @llvm.vp.minimum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl)359 ret <8 x float> %v360}361 362define <8 x float> @vfmin_vv_v8f32_unmasked(<8 x float> %va, <8 x float> %vb, i32 zeroext %evl) {363; CHECK-LABEL: vfmin_vv_v8f32_unmasked:364; CHECK: # %bb.0:365; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma366; CHECK-NEXT: vmfeq.vv v0, v8, v8367; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0368; CHECK-NEXT: vmfeq.vv v0, v10, v10369; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0370; CHECK-NEXT: vfmin.vv v8, v8, v12371; CHECK-NEXT: ret372 %v = call <8 x float> @llvm.vp.minimum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> splat (i1 true), i32 %evl)373 ret <8 x float> %v374}375 376define <16 x float> @vfmin_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 zeroext %evl) {377; CHECK-LABEL: vfmin_vv_v16f32:378; CHECK: # %bb.0:379; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma380; CHECK-NEXT: vmv1r.v v16, v0381; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t382; CHECK-NEXT: vmv1r.v v0, v17383; CHECK-NEXT: vmerge.vvm v20, v8, v12, v0384; CHECK-NEXT: vmv1r.v v0, v16385; CHECK-NEXT: vmfeq.vv v17, v12, v12, v0.t386; CHECK-NEXT: vmv1r.v v0, v17387; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0388; CHECK-NEXT: vmv1r.v v0, v16389; CHECK-NEXT: vfmin.vv v8, v8, v20, v0.t390; CHECK-NEXT: ret391 %v = call <16 x float> @llvm.vp.minimum.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 %evl)392 ret <16 x float> %v393}394 395define <16 x float> @vfmin_vv_v16f32_unmasked(<16 x float> %va, <16 x float> %vb, i32 zeroext %evl) {396; CHECK-LABEL: vfmin_vv_v16f32_unmasked:397; CHECK: # %bb.0:398; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma399; CHECK-NEXT: vmfeq.vv v0, v8, v8400; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0401; CHECK-NEXT: vmfeq.vv v0, v12, v12402; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0403; CHECK-NEXT: vfmin.vv v8, v8, v16404; CHECK-NEXT: ret405 %v = call <16 x float> @llvm.vp.minimum.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> splat (i1 true), i32 %evl)406 ret <16 x float> %v407}408 409define <2 x double> @vfmin_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 zeroext %evl) {410; CHECK-LABEL: vfmin_vv_v2f64:411; CHECK: # %bb.0:412; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma413; CHECK-NEXT: vmv1r.v v10, v0414; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t415; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0416; CHECK-NEXT: vmv1r.v v0, v10417; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t418; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0419; CHECK-NEXT: vmv1r.v v0, v10420; CHECK-NEXT: vfmin.vv v8, v8, v11, v0.t421; CHECK-NEXT: ret422 %v = call <2 x double> @llvm.vp.minimum.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 %evl)423 ret <2 x double> %v424}425 426define <2 x double> @vfmin_vv_v2f64_unmasked(<2 x double> %va, <2 x double> %vb, i32 zeroext %evl) {427; CHECK-LABEL: vfmin_vv_v2f64_unmasked:428; CHECK: # %bb.0:429; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma430; CHECK-NEXT: vmfeq.vv v0, v8, v8431; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0432; CHECK-NEXT: vmfeq.vv v0, v9, v9433; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0434; CHECK-NEXT: vfmin.vv v8, v8, v10435; CHECK-NEXT: ret436 %v = call <2 x double> @llvm.vp.minimum.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> splat (i1 true), i32 %evl)437 ret <2 x double> %v438}439 440define <4 x double> @vfmin_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 zeroext %evl) {441; CHECK-LABEL: vfmin_vv_v4f64:442; CHECK: # %bb.0:443; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma444; CHECK-NEXT: vmv1r.v v12, v0445; CHECK-NEXT: vmfeq.vv v13, v8, v8, v0.t446; CHECK-NEXT: vmv1r.v v0, v13447; CHECK-NEXT: vmerge.vvm v14, v8, v10, v0448; CHECK-NEXT: vmv1r.v v0, v12449; CHECK-NEXT: vmfeq.vv v13, v10, v10, v0.t450; CHECK-NEXT: vmv1r.v v0, v13451; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0452; CHECK-NEXT: vmv1r.v v0, v12453; CHECK-NEXT: vfmin.vv v8, v8, v14, v0.t454; CHECK-NEXT: ret455 %v = call <4 x double> @llvm.vp.minimum.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 %evl)456 ret <4 x double> %v457}458 459define <4 x double> @vfmin_vv_v4f64_unmasked(<4 x double> %va, <4 x double> %vb, i32 zeroext %evl) {460; CHECK-LABEL: vfmin_vv_v4f64_unmasked:461; CHECK: # %bb.0:462; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma463; CHECK-NEXT: vmfeq.vv v0, v8, v8464; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0465; CHECK-NEXT: vmfeq.vv v0, v10, v10466; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0467; CHECK-NEXT: vfmin.vv v8, v8, v12468; CHECK-NEXT: ret469 %v = call <4 x double> @llvm.vp.minimum.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> splat (i1 true), i32 %evl)470 ret <4 x double> %v471}472 473define <8 x double> @vfmin_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) {474; CHECK-LABEL: vfmin_vv_v8f64:475; CHECK: # %bb.0:476; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma477; CHECK-NEXT: vmv1r.v v16, v0478; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t479; CHECK-NEXT: vmv1r.v v0, v17480; CHECK-NEXT: vmerge.vvm v20, v8, v12, v0481; CHECK-NEXT: vmv1r.v v0, v16482; CHECK-NEXT: vmfeq.vv v17, v12, v12, v0.t483; CHECK-NEXT: vmv1r.v v0, v17484; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0485; CHECK-NEXT: vmv1r.v v0, v16486; CHECK-NEXT: vfmin.vv v8, v8, v20, v0.t487; CHECK-NEXT: ret488 %v = call <8 x double> @llvm.vp.minimum.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 %evl)489 ret <8 x double> %v490}491 492define <8 x double> @vfmin_vv_v8f64_unmasked(<8 x double> %va, <8 x double> %vb, i32 zeroext %evl) {493; CHECK-LABEL: vfmin_vv_v8f64_unmasked:494; CHECK: # %bb.0:495; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma496; CHECK-NEXT: vmfeq.vv v0, v8, v8497; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0498; CHECK-NEXT: vmfeq.vv v0, v12, v12499; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0500; CHECK-NEXT: vfmin.vv v8, v8, v16501; CHECK-NEXT: ret502 %v = call <8 x double> @llvm.vp.minimum.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> splat (i1 true), i32 %evl)503 ret <8 x double> %v504}505 506define <16 x double> @vfmin_vv_v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 zeroext %evl) {507; CHECK-LABEL: vfmin_vv_v16f64:508; CHECK: # %bb.0:509; CHECK-NEXT: addi sp, sp, -16510; CHECK-NEXT: .cfi_def_cfa_offset 16511; CHECK-NEXT: csrr a1, vlenb512; CHECK-NEXT: slli a1, a1, 3513; CHECK-NEXT: sub sp, sp, a1514; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb515; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma516; CHECK-NEXT: vmv1r.v v7, v0517; CHECK-NEXT: vmfeq.vv v25, v8, v8, v0.t518; CHECK-NEXT: vmv1r.v v0, v25519; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0520; CHECK-NEXT: addi a0, sp, 16521; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill522; CHECK-NEXT: vmv1r.v v0, v7523; CHECK-NEXT: vmfeq.vv v25, v16, v16, v0.t524; CHECK-NEXT: vmv1r.v v0, v25525; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0526; CHECK-NEXT: vmv1r.v v0, v7527; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload528; CHECK-NEXT: vfmin.vv v8, v8, v16, v0.t529; CHECK-NEXT: csrr a0, vlenb530; CHECK-NEXT: slli a0, a0, 3531; CHECK-NEXT: add sp, sp, a0532; CHECK-NEXT: .cfi_def_cfa sp, 16533; CHECK-NEXT: addi sp, sp, 16534; CHECK-NEXT: .cfi_def_cfa_offset 0535; CHECK-NEXT: ret536 %v = call <16 x double> @llvm.vp.minimum.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 %evl)537 ret <16 x double> %v538}539 540define <16 x double> @vfmin_vv_v16f64_unmasked(<16 x double> %va, <16 x double> %vb, i32 zeroext %evl) {541; CHECK-LABEL: vfmin_vv_v16f64_unmasked:542; CHECK: # %bb.0:543; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma544; CHECK-NEXT: vmfeq.vv v0, v8, v8545; CHECK-NEXT: vmfeq.vv v7, v16, v16546; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0547; CHECK-NEXT: vmv1r.v v0, v7548; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0549; CHECK-NEXT: vfmin.vv v8, v8, v24550; CHECK-NEXT: ret551 %v = call <16 x double> @llvm.vp.minimum.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> splat (i1 true), i32 %evl)552 ret <16 x double> %v553}554 555define <32 x double> @vfmin_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) {556; CHECK-LABEL: vfmin_vv_v32f64:557; CHECK: # %bb.0:558; CHECK-NEXT: addi sp, sp, -16559; CHECK-NEXT: .cfi_def_cfa_offset 16560; CHECK-NEXT: csrr a1, vlenb561; CHECK-NEXT: slli a1, a1, 5562; CHECK-NEXT: sub sp, sp, a1563; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb564; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma565; CHECK-NEXT: vmv1r.v v6, v0566; CHECK-NEXT: csrr a1, vlenb567; CHECK-NEXT: li a3, 24568; CHECK-NEXT: mul a1, a1, a3569; CHECK-NEXT: add a1, sp, a1570; CHECK-NEXT: addi a1, a1, 16571; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill572; CHECK-NEXT: addi a1, a0, 128573; CHECK-NEXT: vle64.v v16, (a1)574; CHECK-NEXT: csrr a1, vlenb575; CHECK-NEXT: slli a1, a1, 4576; CHECK-NEXT: add a1, sp, a1577; CHECK-NEXT: addi a1, a1, 16578; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill579; CHECK-NEXT: vle64.v v16, (a0)580; CHECK-NEXT: li a1, 16581; CHECK-NEXT: mv a0, a2582; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma583; CHECK-NEXT: vslidedown.vi v7, v0, 2584; CHECK-NEXT: bltu a2, a1, .LBB24_2585; CHECK-NEXT: # %bb.1:586; CHECK-NEXT: li a0, 16587; CHECK-NEXT: .LBB24_2:588; CHECK-NEXT: vmv1r.v v0, v6589; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma590; CHECK-NEXT: vmfeq.vv v26, v8, v8, v0.t591; CHECK-NEXT: vmv1r.v v0, v26592; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0593; CHECK-NEXT: csrr a0, vlenb594; CHECK-NEXT: slli a0, a0, 3595; CHECK-NEXT: add a0, sp, a0596; CHECK-NEXT: addi a0, a0, 16597; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill598; CHECK-NEXT: vmv1r.v v0, v6599; CHECK-NEXT: vmfeq.vv v26, v16, v16, v0.t600; CHECK-NEXT: vmv1r.v v0, v26601; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0602; CHECK-NEXT: vmv1r.v v0, v6603; CHECK-NEXT: csrr a0, vlenb604; CHECK-NEXT: slli a0, a0, 3605; CHECK-NEXT: add a0, sp, a0606; CHECK-NEXT: addi a0, a0, 16607; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload608; CHECK-NEXT: vfmin.vv v8, v8, v16, v0.t609; CHECK-NEXT: csrr a0, vlenb610; CHECK-NEXT: slli a0, a0, 3611; CHECK-NEXT: add a0, sp, a0612; CHECK-NEXT: addi a0, a0, 16613; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill614; CHECK-NEXT: addi a0, a2, -16615; CHECK-NEXT: sltu a1, a2, a0616; CHECK-NEXT: addi a1, a1, -1617; CHECK-NEXT: and a0, a1, a0618; CHECK-NEXT: vmv1r.v v0, v7619; CHECK-NEXT: csrr a1, vlenb620; CHECK-NEXT: li a2, 24621; CHECK-NEXT: mul a1, a1, a2622; CHECK-NEXT: add a1, sp, a1623; CHECK-NEXT: addi a1, a1, 16624; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload625; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma626; CHECK-NEXT: vmfeq.vv v25, v16, v16, v0.t627; CHECK-NEXT: vmv1r.v v0, v25628; CHECK-NEXT: csrr a0, vlenb629; CHECK-NEXT: slli a0, a0, 4630; CHECK-NEXT: add a0, sp, a0631; CHECK-NEXT: addi a0, a0, 16632; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload633; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0634; CHECK-NEXT: addi a0, sp, 16635; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill636; CHECK-NEXT: vmv1r.v v0, v7637; CHECK-NEXT: vmfeq.vv v25, v8, v8, v0.t638; CHECK-NEXT: vmv1r.v v0, v25639; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0640; CHECK-NEXT: vmv1r.v v0, v7641; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload642; CHECK-NEXT: vfmin.vv v16, v24, v8, v0.t643; CHECK-NEXT: csrr a0, vlenb644; CHECK-NEXT: slli a0, a0, 3645; CHECK-NEXT: add a0, sp, a0646; CHECK-NEXT: addi a0, a0, 16647; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload648; CHECK-NEXT: csrr a0, vlenb649; CHECK-NEXT: slli a0, a0, 5650; CHECK-NEXT: add sp, sp, a0651; CHECK-NEXT: .cfi_def_cfa sp, 16652; CHECK-NEXT: addi sp, sp, 16653; CHECK-NEXT: .cfi_def_cfa_offset 0654; CHECK-NEXT: ret655 %v = call <32 x double> @llvm.vp.minimum.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 %evl)656 ret <32 x double> %v657}658 659define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double> %vb, i32 zeroext %evl) {660; CHECK-LABEL: vfmin_vv_v32f64_unmasked:661; CHECK: # %bb.0:662; CHECK-NEXT: addi sp, sp, -16663; CHECK-NEXT: .cfi_def_cfa_offset 16664; CHECK-NEXT: csrr a1, vlenb665; CHECK-NEXT: li a3, 24666; CHECK-NEXT: mul a1, a1, a3667; CHECK-NEXT: sub sp, sp, a1668; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb669; CHECK-NEXT: csrr a1, vlenb670; CHECK-NEXT: slli a1, a1, 4671; CHECK-NEXT: add a1, sp, a1672; CHECK-NEXT: addi a1, a1, 16673; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill674; CHECK-NEXT: addi a1, a0, 128675; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma676; CHECK-NEXT: vle64.v v16, (a1)677; CHECK-NEXT: csrr a1, vlenb678; CHECK-NEXT: slli a1, a1, 3679; CHECK-NEXT: add a1, sp, a1680; CHECK-NEXT: addi a1, a1, 16681; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill682; CHECK-NEXT: vle64.v v24, (a0)683; CHECK-NEXT: li a1, 16684; CHECK-NEXT: mv a0, a2685; CHECK-NEXT: bltu a2, a1, .LBB25_2686; CHECK-NEXT: # %bb.1:687; CHECK-NEXT: li a0, 16688; CHECK-NEXT: .LBB25_2:689; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma690; CHECK-NEXT: vmfeq.vv v0, v8, v8691; CHECK-NEXT: vmfeq.vv v7, v24, v24692; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0693; CHECK-NEXT: vmv1r.v v0, v7694; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0695; CHECK-NEXT: vfmin.vv v8, v8, v16696; CHECK-NEXT: addi a0, sp, 16697; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill698; CHECK-NEXT: addi a0, a2, -16699; CHECK-NEXT: sltu a1, a2, a0700; CHECK-NEXT: addi a1, a1, -1701; CHECK-NEXT: and a0, a1, a0702; CHECK-NEXT: csrr a1, vlenb703; CHECK-NEXT: slli a1, a1, 4704; CHECK-NEXT: add a1, sp, a1705; CHECK-NEXT: addi a1, a1, 16706; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload707; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma708; CHECK-NEXT: vmfeq.vv v0, v16, v16709; CHECK-NEXT: csrr a0, vlenb710; CHECK-NEXT: slli a0, a0, 3711; CHECK-NEXT: add a0, sp, a0712; CHECK-NEXT: addi a0, a0, 16713; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload714; CHECK-NEXT: vmfeq.vv v7, v8, v8715; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0716; CHECK-NEXT: vmv1r.v v0, v7717; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0718; CHECK-NEXT: vfmin.vv v16, v16, v24719; CHECK-NEXT: addi a0, sp, 16720; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload721; CHECK-NEXT: csrr a0, vlenb722; CHECK-NEXT: li a1, 24723; CHECK-NEXT: mul a0, a0, a1724; CHECK-NEXT: add sp, sp, a0725; CHECK-NEXT: .cfi_def_cfa sp, 16726; CHECK-NEXT: addi sp, sp, 16727; CHECK-NEXT: .cfi_def_cfa_offset 0728; CHECK-NEXT: ret729 %v = call <32 x double> @llvm.vp.minimum.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> splat (i1 true), i32 %evl)730 ret <32 x double> %v731}732