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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN10 11define <2 x half> @vfmin_v2f16_vv(<2 x half> %a, <2 x half> %b) {12; ZVFH-LABEL: vfmin_v2f16_vv:13; ZVFH: # %bb.0:14; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma15; ZVFH-NEXT: vmfeq.vv v0, v8, v816; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v017; ZVFH-NEXT: vmfeq.vv v0, v9, v918; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v019; ZVFH-NEXT: vfmin.vv v8, v8, v1020; ZVFH-NEXT: ret21;22; ZVFHMIN-LABEL: vfmin_v2f16_vv:23; ZVFHMIN: # %bb.0:24; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma25; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v826; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma27; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v1028; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma29; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v930; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma31; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v032; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v833; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v034; ZVFHMIN-NEXT: vfmin.vv v9, v8, v935; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma36; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v937; ZVFHMIN-NEXT: ret38 %v = call <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %b)39 ret <2 x half> %v40}41 42define <4 x half> @vfmin_v4f16_vv(<4 x half> %a, <4 x half> %b) {43; ZVFH-LABEL: vfmin_v4f16_vv:44; ZVFH: # %bb.0:45; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma46; ZVFH-NEXT: vmfeq.vv v0, v8, v847; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v048; ZVFH-NEXT: vmfeq.vv v0, v9, v949; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v050; ZVFH-NEXT: vfmin.vv v8, v8, v1051; ZVFH-NEXT: ret52;53; ZVFHMIN-LABEL: vfmin_v4f16_vv:54; ZVFHMIN: # %bb.0:55; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma56; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v857; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma58; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v1059; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma60; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v961; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma62; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v063; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v864; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v065; ZVFHMIN-NEXT: vfmin.vv v9, v8, v966; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma67; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v968; ZVFHMIN-NEXT: ret69 %v = call <4 x half> @llvm.minimum.v4f16(<4 x half> %a, <4 x half> %b)70 ret <4 x half> %v71}72 73define <8 x half> @vfmin_v8f16_vv(<8 x half> %a, <8 x half> %b) {74; ZVFH-LABEL: vfmin_v8f16_vv:75; ZVFH: # %bb.0:76; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma77; ZVFH-NEXT: vmfeq.vv v0, v8, v878; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v079; ZVFH-NEXT: vmfeq.vv v0, v9, v980; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v081; ZVFH-NEXT: vfmin.vv v8, v8, v1082; ZVFH-NEXT: ret83;84; ZVFHMIN-LABEL: vfmin_v8f16_vv:85; ZVFHMIN: # %bb.0:86; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma87; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v888; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma89; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v1090; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma91; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v992; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma93; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v094; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v1295; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v096; ZVFHMIN-NEXT: vfmin.vv v10, v10, v897; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma98; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v1099; ZVFHMIN-NEXT: ret100 %v = call <8 x half> @llvm.minimum.v8f16(<8 x half> %a, <8 x half> %b)101 ret <8 x half> %v102}103 104define <16 x half> @vfmin_v16f16_vv(<16 x half> %a, <16 x half> %b) {105; ZVFH-LABEL: vfmin_v16f16_vv:106; ZVFH: # %bb.0:107; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma108; ZVFH-NEXT: vmfeq.vv v0, v8, v8109; ZVFH-NEXT: vmerge.vvm v12, v8, v10, v0110; ZVFH-NEXT: vmfeq.vv v0, v10, v10111; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0112; ZVFH-NEXT: vfmin.vv v8, v8, v12113; ZVFH-NEXT: ret114;115; ZVFHMIN-LABEL: vfmin_v16f16_vv:116; ZVFHMIN: # %bb.0:117; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma118; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8119; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma120; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12121; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma122; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10123; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma124; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0125; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16126; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0127; ZVFHMIN-NEXT: vfmin.vv v12, v12, v8128; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma129; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12130; ZVFHMIN-NEXT: ret131 %v = call <16 x half> @llvm.minimum.v16f16(<16 x half> %a, <16 x half> %b)132 ret <16 x half> %v133}134 135define <2 x float> @vfmin_v2f32_vv(<2 x float> %a, <2 x float> %b) {136; CHECK-LABEL: vfmin_v2f32_vv:137; CHECK: # %bb.0:138; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma139; CHECK-NEXT: vmfeq.vv v0, v8, v8140; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0141; CHECK-NEXT: vmfeq.vv v0, v9, v9142; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0143; CHECK-NEXT: vfmin.vv v8, v8, v10144; CHECK-NEXT: ret145 %v = call <2 x float> @llvm.minimum.v2f32(<2 x float> %a, <2 x float> %b)146 ret <2 x float> %v147}148 149define <4 x float> @vfmin_v4f32_vv(<4 x float> %a, <4 x float> %b) {150; CHECK-LABEL: vfmin_v4f32_vv:151; CHECK: # %bb.0:152; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma153; CHECK-NEXT: vmfeq.vv v0, v8, v8154; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0155; CHECK-NEXT: vmfeq.vv v0, v9, v9156; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0157; CHECK-NEXT: vfmin.vv v8, v8, v10158; CHECK-NEXT: ret159 %v = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> %b)160 ret <4 x float> %v161}162 163define <8 x float> @vfmin_v8f32_vv(<8 x float> %a, <8 x float> %b) {164; CHECK-LABEL: vfmin_v8f32_vv:165; CHECK: # %bb.0:166; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma167; CHECK-NEXT: vmfeq.vv v0, v8, v8168; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0169; CHECK-NEXT: vmfeq.vv v0, v10, v10170; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0171; CHECK-NEXT: vfmin.vv v8, v8, v12172; CHECK-NEXT: ret173 %v = call <8 x float> @llvm.minimum.v8f32(<8 x float> %a, <8 x float> %b)174 ret <8 x float> %v175}176 177define <16 x float> @vfmin_v16f32_vv(<16 x float> %a, <16 x float> %b) {178; CHECK-LABEL: vfmin_v16f32_vv:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma181; CHECK-NEXT: vmfeq.vv v0, v8, v8182; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0183; CHECK-NEXT: vmfeq.vv v0, v12, v12184; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0185; CHECK-NEXT: vfmin.vv v8, v8, v16186; CHECK-NEXT: ret187 %v = call <16 x float> @llvm.minimum.v16f32(<16 x float> %a, <16 x float> %b)188 ret <16 x float> %v189}190 191define <2 x double> @vfmin_v2f64_vv(<2 x double> %a, <2 x double> %b) {192; CHECK-LABEL: vfmin_v2f64_vv:193; CHECK: # %bb.0:194; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma195; CHECK-NEXT: vmfeq.vv v0, v8, v8196; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0197; CHECK-NEXT: vmfeq.vv v0, v9, v9198; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0199; CHECK-NEXT: vfmin.vv v8, v8, v10200; CHECK-NEXT: ret201 %v = call <2 x double> @llvm.minimum.v2f64(<2 x double> %a, <2 x double> %b)202 ret <2 x double> %v203}204 205define <4 x double> @vfmin_v4f64_vv(<4 x double> %a, <4 x double> %b) {206; CHECK-LABEL: vfmin_v4f64_vv:207; CHECK: # %bb.0:208; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma209; CHECK-NEXT: vmfeq.vv v0, v8, v8210; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0211; CHECK-NEXT: vmfeq.vv v0, v10, v10212; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0213; CHECK-NEXT: vfmin.vv v8, v8, v12214; CHECK-NEXT: ret215 %v = call <4 x double> @llvm.minimum.v4f64(<4 x double> %a, <4 x double> %b)216 ret <4 x double> %v217}218 219define <8 x double> @vfmin_v8f64_vv(<8 x double> %a, <8 x double> %b) {220; CHECK-LABEL: vfmin_v8f64_vv:221; CHECK: # %bb.0:222; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma223; CHECK-NEXT: vmfeq.vv v0, v8, v8224; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0225; CHECK-NEXT: vmfeq.vv v0, v12, v12226; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0227; CHECK-NEXT: vfmin.vv v8, v8, v16228; CHECK-NEXT: ret229 %v = call <8 x double> @llvm.minimum.v8f64(<8 x double> %a, <8 x double> %b)230 ret <8 x double> %v231}232 233define <16 x double> @vfmin_v16f64_vv(<16 x double> %a, <16 x double> %b) nounwind {234; CHECK-LABEL: vfmin_v16f64_vv:235; CHECK: # %bb.0:236; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma237; CHECK-NEXT: vmfeq.vv v0, v8, v8238; CHECK-NEXT: vmfeq.vv v7, v16, v16239; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0240; CHECK-NEXT: vmv1r.v v0, v7241; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0242; CHECK-NEXT: vfmin.vv v8, v8, v24243; CHECK-NEXT: ret244 %v = call <16 x double> @llvm.minimum.v16f64(<16 x double> %a, <16 x double> %b)245 ret <16 x double> %v246}247 248define <2 x half> @vfmin_v2f16_vv_nnan(<2 x half> %a, <2 x half> %b) {249; ZVFH-LABEL: vfmin_v2f16_vv_nnan:250; ZVFH: # %bb.0:251; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma252; ZVFH-NEXT: vfmin.vv v8, v8, v9253; ZVFH-NEXT: ret254;255; ZVFHMIN-LABEL: vfmin_v2f16_vv_nnan:256; ZVFHMIN: # %bb.0:257; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma258; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9259; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8260; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma261; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10262; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma263; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9264; ZVFHMIN-NEXT: ret265 %v = call nnan <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %b)266 ret <2 x half> %v267}268 269define <2 x half> @vfmin_v2f16_vv_nnana(<2 x half> %a, <2 x half> %b) {270; ZVFH-LABEL: vfmin_v2f16_vv_nnana:271; ZVFH: # %bb.0:272; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, mu273; ZVFH-NEXT: vmfeq.vv v0, v9, v9274; ZVFH-NEXT: vmv1r.v v10, v9275; ZVFH-NEXT: vfadd.vv v10, v8, v8, v0.t276; ZVFH-NEXT: vfmin.vv v8, v10, v9277; ZVFH-NEXT: ret278;279; ZVFHMIN-LABEL: vfmin_v2f16_vv_nnana:280; ZVFHMIN: # %bb.0:281; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma282; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8283; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9284; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma285; ZVFHMIN-NEXT: vfadd.vv v9, v10, v10286; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8287; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma288; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9289; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10290; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma291; ZVFHMIN-NEXT: vmerge.vvm v10, v8, v9, v0292; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9293; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0294; ZVFHMIN-NEXT: vfmin.vv v9, v10, v8295; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma296; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9297; ZVFHMIN-NEXT: ret298 %c = fadd nnan <2 x half> %a, %a299 %v = call <2 x half> @llvm.minimum.v2f16(<2 x half> %c, <2 x half> %b)300 ret <2 x half> %v301}302 303define <2 x half> @vfmin_v2f16_vv_nnanb(<2 x half> %a, <2 x half> %b) {304; ZVFH-LABEL: vfmin_v2f16_vv_nnanb:305; ZVFH: # %bb.0:306; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, mu307; ZVFH-NEXT: vmfeq.vv v0, v8, v8308; ZVFH-NEXT: vmv1r.v v10, v8309; ZVFH-NEXT: vfadd.vv v10, v9, v9, v0.t310; ZVFH-NEXT: vfmin.vv v8, v8, v10311; ZVFH-NEXT: ret312;313; ZVFHMIN-LABEL: vfmin_v2f16_vv_nnanb:314; ZVFHMIN: # %bb.0:315; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma316; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9317; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8318; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma319; ZVFHMIN-NEXT: vfadd.vv v8, v10, v10320; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9321; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma322; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8323; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10324; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma325; ZVFHMIN-NEXT: vmerge.vvm v10, v9, v8, v0326; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8327; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0328; ZVFHMIN-NEXT: vfmin.vv v9, v8, v10329; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma330; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9331; ZVFHMIN-NEXT: ret332 %c = fadd nnan <2 x half> %b, %b333 %v = call <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %c)334 ret <2 x half> %v335}336 337define <4 x half> @vfmin_v2f16_vv_nnan_insert_subvector(<2 x half> %a, <2 x half> %b, <4 x half> %c) {338; ZVFH-LABEL: vfmin_v2f16_vv_nnan_insert_subvector:339; ZVFH: # %bb.0:340; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma341; ZVFH-NEXT: vfadd.vv v8, v8, v8342; ZVFH-NEXT: vfadd.vv v9, v9, v9343; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma344; ZVFH-NEXT: vmfeq.vv v0, v10, v10345; ZVFH-NEXT: vslideup.vi v8, v9, 2346; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0347; ZVFH-NEXT: vfmin.vv v8, v8, v10348; ZVFH-NEXT: ret349;350; ZVFHMIN-LABEL: vfmin_v2f16_vv_nnan_insert_subvector:351; ZVFHMIN: # %bb.0:352; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma353; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8354; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9355; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma356; ZVFHMIN-NEXT: vfadd.vv v9, v11, v11357; ZVFHMIN-NEXT: vfadd.vv v8, v8, v8358; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma359; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v9360; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v8361; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma362; ZVFHMIN-NEXT: vslideup.vi v11, v9, 2363; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11364; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma365; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8366; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma367; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10368; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma369; ZVFHMIN-NEXT: vmerge.vvm v10, v8, v9, v0370; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9371; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0372; ZVFHMIN-NEXT: vfmin.vv v9, v8, v10373; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma374; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9375; ZVFHMIN-NEXT: ret376 %d = fadd nnan <2 x half> %a, %a377 %e = fadd nnan <2 x half> %b, %b378 %f = call <4 x half> @llvm.vector.insert.v2f32.v4f32(<4 x half> poison, <2 x half> %d, i64 0)379 %g = call <4 x half> @llvm.vector.insert.v2f32.v4f32(<4 x half> %f, <2 x half> %e, i64 2)380 %v = call <4 x half> @llvm.minimum.v4f16(<4 x half> %g, <4 x half> %c)381 ret <4 x half> %v382}383