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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s \4; RUN: --check-prefixes=CHECK,RV32-FP5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \6; RUN: -verify-machineinstrs < %s | FileCheck %s \7; RUN: --check-prefixes=CHECK,RV64-FP8 9define i16 @bitcast_v1f16_i16(<1 x half> %a) {10; CHECK-LABEL: bitcast_v1f16_i16:11; CHECK: # %bb.0:12; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma13; CHECK-NEXT: vmv.x.s a0, v814; CHECK-NEXT: ret15 %b = bitcast <1 x half> %a to i1616 ret i16 %b17}18 19define half @bitcast_v1f16_f16(<1 x half> %a) {20; CHECK-LABEL: bitcast_v1f16_f16:21; CHECK: # %bb.0:22; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma23; CHECK-NEXT: vfmv.f.s fa0, v824; CHECK-NEXT: ret25 %b = bitcast <1 x half> %a to half26 ret half %b27}28 29define i32 @bitcast_v2f16_i32(<2 x half> %a) {30; CHECK-LABEL: bitcast_v2f16_i32:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma33; CHECK-NEXT: vmv.x.s a0, v834; CHECK-NEXT: ret35 %b = bitcast <2 x half> %a to i3236 ret i32 %b37}38 39define i32 @bitcast_v1f32_i32(<1 x float> %a) {40; CHECK-LABEL: bitcast_v1f32_i32:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma43; CHECK-NEXT: vmv.x.s a0, v844; CHECK-NEXT: ret45 %b = bitcast <1 x float> %a to i3246 ret i32 %b47}48 49define float @bitcast_v2f16_f32(<2 x half> %a) {50; CHECK-LABEL: bitcast_v2f16_f32:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma53; CHECK-NEXT: vfmv.f.s fa0, v854; CHECK-NEXT: ret55 %b = bitcast <2 x half> %a to float56 ret float %b57}58 59define float @bitcast_v1f32_f32(<1 x float> %a) {60; CHECK-LABEL: bitcast_v1f32_f32:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma63; CHECK-NEXT: vfmv.f.s fa0, v864; CHECK-NEXT: ret65 %b = bitcast <1 x float> %a to float66 ret float %b67}68 69define i64 @bitcast_v4f16_i64(<4 x half> %a) {70; RV32-FP-LABEL: bitcast_v4f16_i64:71; RV32-FP: # %bb.0:72; RV32-FP-NEXT: li a0, 3273; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, ma74; RV32-FP-NEXT: vsrl.vx v9, v8, a075; RV32-FP-NEXT: vmv.x.s a1, v976; RV32-FP-NEXT: vmv.x.s a0, v877; RV32-FP-NEXT: ret78;79; RV64-FP-LABEL: bitcast_v4f16_i64:80; RV64-FP: # %bb.0:81; RV64-FP-NEXT: vsetivli zero, 1, e64, m1, ta, ma82; RV64-FP-NEXT: vmv.x.s a0, v883; RV64-FP-NEXT: ret84 %b = bitcast <4 x half> %a to i6485 ret i64 %b86}87 88define i64 @bitcast_v2f32_i64(<2 x float> %a) {89; RV32-FP-LABEL: bitcast_v2f32_i64:90; RV32-FP: # %bb.0:91; RV32-FP-NEXT: li a0, 3292; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, ma93; RV32-FP-NEXT: vsrl.vx v9, v8, a094; RV32-FP-NEXT: vmv.x.s a1, v995; RV32-FP-NEXT: vmv.x.s a0, v896; RV32-FP-NEXT: ret97;98; RV64-FP-LABEL: bitcast_v2f32_i64:99; RV64-FP: # %bb.0:100; RV64-FP-NEXT: vsetivli zero, 1, e64, m1, ta, ma101; RV64-FP-NEXT: vmv.x.s a0, v8102; RV64-FP-NEXT: ret103 %b = bitcast <2 x float> %a to i64104 ret i64 %b105}106 107define i64 @bitcast_v1f64_i64(<1 x double> %a) {108; RV32-FP-LABEL: bitcast_v1f64_i64:109; RV32-FP: # %bb.0:110; RV32-FP-NEXT: li a0, 32111; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, ma112; RV32-FP-NEXT: vsrl.vx v9, v8, a0113; RV32-FP-NEXT: vmv.x.s a1, v9114; RV32-FP-NEXT: vmv.x.s a0, v8115; RV32-FP-NEXT: ret116;117; RV64-FP-LABEL: bitcast_v1f64_i64:118; RV64-FP: # %bb.0:119; RV64-FP-NEXT: vsetivli zero, 1, e64, m1, ta, ma120; RV64-FP-NEXT: vmv.x.s a0, v8121; RV64-FP-NEXT: ret122 %b = bitcast <1 x double> %a to i64123 ret i64 %b124}125 126define double @bitcast_v4f16_f64(<4 x half> %a) {127; CHECK-LABEL: bitcast_v4f16_f64:128; CHECK: # %bb.0:129; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma130; CHECK-NEXT: vfmv.f.s fa0, v8131; CHECK-NEXT: ret132 %b = bitcast <4 x half> %a to double133 ret double %b134}135 136define double @bitcast_v2f32_f64(<2 x float> %a) {137; CHECK-LABEL: bitcast_v2f32_f64:138; CHECK: # %bb.0:139; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma140; CHECK-NEXT: vfmv.f.s fa0, v8141; CHECK-NEXT: ret142 %b = bitcast <2 x float> %a to double143 ret double %b144}145 146define double @bitcast_v1f64_f64(<1 x double> %a) {147; CHECK-LABEL: bitcast_v1f64_f64:148; CHECK: # %bb.0:149; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma150; CHECK-NEXT: vfmv.f.s fa0, v8151; CHECK-NEXT: ret152 %b = bitcast <1 x double> %a to double153 ret double %b154}155 156define <1 x half> @bitcast_i16_v1f16(i16 %a) {157; CHECK-LABEL: bitcast_i16_v1f16:158; CHECK: # %bb.0:159; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma160; CHECK-NEXT: vmv.s.x v8, a0161; CHECK-NEXT: ret162 %b = bitcast i16 %a to <1 x half>163 ret <1 x half> %b164}165 166define <2 x half> @bitcast_i32_v2f16(i32 %a) {167; CHECK-LABEL: bitcast_i32_v2f16:168; CHECK: # %bb.0:169; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma170; CHECK-NEXT: vmv.s.x v8, a0171; CHECK-NEXT: ret172 %b = bitcast i32 %a to <2 x half>173 ret <2 x half> %b174}175 176define <1 x float> @bitcast_i32_v1f32(i32 %a) {177; CHECK-LABEL: bitcast_i32_v1f32:178; CHECK: # %bb.0:179; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma180; CHECK-NEXT: vmv.s.x v8, a0181; CHECK-NEXT: ret182 %b = bitcast i32 %a to <1 x float>183 ret <1 x float> %b184}185 186define <4 x half> @bitcast_i64_v4f16(i64 %a) {187; RV32-FP-LABEL: bitcast_i64_v4f16:188; RV32-FP: # %bb.0:189; RV32-FP-NEXT: vsetivli zero, 2, e32, m1, ta, ma190; RV32-FP-NEXT: vslide1down.vx v8, v8, a0191; RV32-FP-NEXT: vslide1down.vx v8, v8, a1192; RV32-FP-NEXT: ret193;194; RV64-FP-LABEL: bitcast_i64_v4f16:195; RV64-FP: # %bb.0:196; RV64-FP-NEXT: vsetivli zero, 1, e64, m1, ta, ma197; RV64-FP-NEXT: vmv.s.x v8, a0198; RV64-FP-NEXT: ret199 %b = bitcast i64 %a to <4 x half>200 ret <4 x half> %b201}202 203define <2 x float> @bitcast_i64_v2f32(i64 %a) {204; RV32-FP-LABEL: bitcast_i64_v2f32:205; RV32-FP: # %bb.0:206; RV32-FP-NEXT: vsetivli zero, 2, e32, m1, ta, ma207; RV32-FP-NEXT: vslide1down.vx v8, v8, a0208; RV32-FP-NEXT: vslide1down.vx v8, v8, a1209; RV32-FP-NEXT: ret210;211; RV64-FP-LABEL: bitcast_i64_v2f32:212; RV64-FP: # %bb.0:213; RV64-FP-NEXT: vsetivli zero, 1, e64, m1, ta, ma214; RV64-FP-NEXT: vmv.s.x v8, a0215; RV64-FP-NEXT: ret216 %b = bitcast i64 %a to <2 x float>217 ret <2 x float> %b218}219 220define <1 x double> @bitcast_i64_v1f64(i64 %a) {221; RV32-FP-LABEL: bitcast_i64_v1f64:222; RV32-FP: # %bb.0:223; RV32-FP-NEXT: vsetivli zero, 2, e32, m1, ta, ma224; RV32-FP-NEXT: vslide1down.vx v8, v8, a0225; RV32-FP-NEXT: vslide1down.vx v8, v8, a1226; RV32-FP-NEXT: ret227;228; RV64-FP-LABEL: bitcast_i64_v1f64:229; RV64-FP: # %bb.0:230; RV64-FP-NEXT: vsetivli zero, 1, e64, m1, ta, ma231; RV64-FP-NEXT: vmv.s.x v8, a0232; RV64-FP-NEXT: ret233 %b = bitcast i64 %a to <1 x double>234 ret <1 x double> %b235}236 237define <1 x i16> @bitcast_f16_v1i16(half %a) {238; CHECK-LABEL: bitcast_f16_v1i16:239; CHECK: # %bb.0:240; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma241; CHECK-NEXT: vfmv.s.f v8, fa0242; CHECK-NEXT: ret243 %b = bitcast half %a to <1 x i16>244 ret <1 x i16> %b245}246 247define <1 x half> @bitcast_f16_v1f16(half %a) {248; CHECK-LABEL: bitcast_f16_v1f16:249; CHECK: # %bb.0:250; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma251; CHECK-NEXT: vfmv.s.f v8, fa0252; CHECK-NEXT: ret253 %b = bitcast half %a to <1 x half>254 ret <1 x half> %b255}256 257define <2 x i16> @bitcast_f32_v2i16(float %a) {258; CHECK-LABEL: bitcast_f32_v2i16:259; CHECK: # %bb.0:260; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma261; CHECK-NEXT: vfmv.s.f v8, fa0262; CHECK-NEXT: ret263 %b = bitcast float %a to <2 x i16>264 ret <2 x i16> %b265}266 267define <2 x half> @bitcast_f32_v2f16(float %a) {268; CHECK-LABEL: bitcast_f32_v2f16:269; CHECK: # %bb.0:270; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma271; CHECK-NEXT: vfmv.s.f v8, fa0272; CHECK-NEXT: ret273 %b = bitcast float %a to <2 x half>274 ret <2 x half> %b275}276 277define <1 x i32> @bitcast_f32_v1i32(float %a) {278; CHECK-LABEL: bitcast_f32_v1i32:279; CHECK: # %bb.0:280; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma281; CHECK-NEXT: vfmv.s.f v8, fa0282; CHECK-NEXT: ret283 %b = bitcast float %a to <1 x i32>284 ret <1 x i32> %b285}286 287define <1 x float> @bitcast_f32_v1f32(float %a) {288; CHECK-LABEL: bitcast_f32_v1f32:289; CHECK: # %bb.0:290; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma291; CHECK-NEXT: vfmv.s.f v8, fa0292; CHECK-NEXT: ret293 %b = bitcast float %a to <1 x float>294 ret <1 x float> %b295}296 297define <4 x i16> @bitcast_f64_v4i16(double %a) {298; CHECK-LABEL: bitcast_f64_v4i16:299; CHECK: # %bb.0:300; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma301; CHECK-NEXT: vfmv.s.f v8, fa0302; CHECK-NEXT: ret303 %b = bitcast double %a to <4 x i16>304 ret <4 x i16> %b305}306 307define <4 x half> @bitcast_f64_v4f16(double %a) {308; CHECK-LABEL: bitcast_f64_v4f16:309; CHECK: # %bb.0:310; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma311; CHECK-NEXT: vfmv.s.f v8, fa0312; CHECK-NEXT: ret313 %b = bitcast double %a to <4 x half>314 ret <4 x half> %b315}316 317define <2 x i32> @bitcast_f64_v2i32(double %a) {318; CHECK-LABEL: bitcast_f64_v2i32:319; CHECK: # %bb.0:320; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma321; CHECK-NEXT: vfmv.s.f v8, fa0322; CHECK-NEXT: ret323 %b = bitcast double %a to <2 x i32>324 ret <2 x i32> %b325}326 327define <2 x float> @bitcast_f64_v2f32(double %a) {328; CHECK-LABEL: bitcast_f64_v2f32:329; CHECK: # %bb.0:330; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma331; CHECK-NEXT: vfmv.s.f v8, fa0332; CHECK-NEXT: ret333 %b = bitcast double %a to <2 x float>334 ret <2 x float> %b335}336 337define <1 x i64> @bitcast_f64_v1i64(double %a) {338; CHECK-LABEL: bitcast_f64_v1i64:339; CHECK: # %bb.0:340; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma341; CHECK-NEXT: vfmv.s.f v8, fa0342; CHECK-NEXT: ret343 %b = bitcast double %a to <1 x i64>344 ret <1 x i64> %b345}346 347define <1 x double> @bitcast_f64_v1f64(double %a) {348; CHECK-LABEL: bitcast_f64_v1f64:349; CHECK: # %bb.0:350; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma351; CHECK-NEXT: vfmv.s.f v8, fa0352; CHECK-NEXT: ret353 %b = bitcast double %a to <1 x double>354 ret <1 x double> %b355}356