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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFBFMIN,RV32-NO-ZFBFMIN3; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFBFMIN,RV64-NO-ZFBFMIN4; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFBFMIN,RV32-ZFBFMIN5; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFBFMIN,RV64-ZFBFMIN6 7define <4 x bfloat> @splat_idx_v4bf16(<4 x bfloat> %v, i64 %idx) {8; RV32-NO-ZFBFMIN-LABEL: splat_idx_v4bf16:9; RV32-NO-ZFBFMIN: # %bb.0:10; RV32-NO-ZFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma11; RV32-NO-ZFBFMIN-NEXT: vrgather.vx v9, v8, a012; RV32-NO-ZFBFMIN-NEXT: vmv1r.v v8, v913; RV32-NO-ZFBFMIN-NEXT: ret14;15; RV64-NO-ZFBFMIN-LABEL: splat_idx_v4bf16:16; RV64-NO-ZFBFMIN: # %bb.0:17; RV64-NO-ZFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma18; RV64-NO-ZFBFMIN-NEXT: vrgather.vx v9, v8, a019; RV64-NO-ZFBFMIN-NEXT: vmv1r.v v8, v920; RV64-NO-ZFBFMIN-NEXT: ret21;22; RV32-ZFBFMIN-LABEL: splat_idx_v4bf16:23; RV32-ZFBFMIN: # %bb.0:24; RV32-ZFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma25; RV32-ZFBFMIN-NEXT: vslidedown.vx v8, v8, a026; RV32-ZFBFMIN-NEXT: vmv.x.s a0, v827; RV32-ZFBFMIN-NEXT: vmv.v.x v8, a028; RV32-ZFBFMIN-NEXT: ret29;30; RV64-ZFBFMIN-LABEL: splat_idx_v4bf16:31; RV64-ZFBFMIN: # %bb.0:32; RV64-ZFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma33; RV64-ZFBFMIN-NEXT: vslidedown.vx v8, v8, a034; RV64-ZFBFMIN-NEXT: vmv.x.s a0, v835; RV64-ZFBFMIN-NEXT: vmv.v.x v8, a036; RV64-ZFBFMIN-NEXT: ret37 %x = extractelement <4 x bfloat> %v, i64 %idx38 %ins = insertelement <4 x bfloat> poison, bfloat %x, i32 039 %splat = shufflevector <4 x bfloat> %ins, <4 x bfloat> poison, <4 x i32> zeroinitializer40 ret <4 x bfloat> %splat41}42 43define <2 x bfloat> @buildvec_v2bf16(bfloat %a, bfloat %b) {44; RV32-NO-ZFBFMIN-LABEL: buildvec_v2bf16:45; RV32-NO-ZFBFMIN: # %bb.0:46; RV32-NO-ZFBFMIN-NEXT: fmv.x.w a0, fa147; RV32-NO-ZFBFMIN-NEXT: fmv.x.w a1, fa048; RV32-NO-ZFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma49; RV32-NO-ZFBFMIN-NEXT: vmv.v.x v8, a150; RV32-NO-ZFBFMIN-NEXT: vslide1down.vx v8, v8, a051; RV32-NO-ZFBFMIN-NEXT: ret52;53; RV64-NO-ZFBFMIN-LABEL: buildvec_v2bf16:54; RV64-NO-ZFBFMIN: # %bb.0:55; RV64-NO-ZFBFMIN-NEXT: fmv.x.w a0, fa156; RV64-NO-ZFBFMIN-NEXT: fmv.x.w a1, fa057; RV64-NO-ZFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma58; RV64-NO-ZFBFMIN-NEXT: vmv.v.x v8, a159; RV64-NO-ZFBFMIN-NEXT: vslide1down.vx v8, v8, a060; RV64-NO-ZFBFMIN-NEXT: ret61;62; RV32-ZFBFMIN-LABEL: buildvec_v2bf16:63; RV32-ZFBFMIN: # %bb.0:64; RV32-ZFBFMIN-NEXT: fmv.x.h a0, fa165; RV32-ZFBFMIN-NEXT: fmv.x.h a1, fa066; RV32-ZFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma67; RV32-ZFBFMIN-NEXT: vmv.v.x v8, a168; RV32-ZFBFMIN-NEXT: vslide1down.vx v8, v8, a069; RV32-ZFBFMIN-NEXT: ret70;71; RV64-ZFBFMIN-LABEL: buildvec_v2bf16:72; RV64-ZFBFMIN: # %bb.0:73; RV64-ZFBFMIN-NEXT: fmv.x.h a0, fa174; RV64-ZFBFMIN-NEXT: fmv.x.h a1, fa075; RV64-ZFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma76; RV64-ZFBFMIN-NEXT: vmv.v.x v8, a177; RV64-ZFBFMIN-NEXT: vslide1down.vx v8, v8, a078; RV64-ZFBFMIN-NEXT: ret79 %v1 = insertelement <2 x bfloat> poison, bfloat %a, i64 080 %v2 = insertelement <2 x bfloat> %v1, bfloat %b, i64 181 ret <2 x bfloat> %v282}83 84define <2 x bfloat> @vid_v2bf16() {85; CHECK-LABEL: vid_v2bf16:86; CHECK: # %bb.0:87; CHECK-NEXT: lui a0, 26009688; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma89; CHECK-NEXT: vmv.s.x v8, a090; CHECK-NEXT: ret91 ret <2 x bfloat> <bfloat 0.0, bfloat 1.0>92}93 94define <2 x bfloat> @vid_addend1_v2bf16() {95; CHECK-LABEL: vid_addend1_v2bf16:96; CHECK: # %bb.0:97; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma98; CHECK-NEXT: vid.v v899; CHECK-NEXT: lui a0, 4100; CHECK-NEXT: vsll.vi v8, v8, 7101; CHECK-NEXT: addi a0, a0, -128102; CHECK-NEXT: vadd.vx v8, v8, a0103; CHECK-NEXT: ret104 ret <2 x bfloat> <bfloat 1.0, bfloat 2.0>105}106 107define <2 x bfloat> @vid_denominator2_v2bf16() {108; CHECK-LABEL: vid_denominator2_v2bf16:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma111; CHECK-NEXT: vid.v v8112; CHECK-NEXT: lui a0, 4113; CHECK-NEXT: vsll.vi v8, v8, 7114; CHECK-NEXT: addi a0, a0, -256115; CHECK-NEXT: vadd.vx v8, v8, a0116; CHECK-NEXT: ret117 ret <2 x bfloat> <bfloat 0.5, bfloat 1.0>118}119 120define <2 x bfloat> @vid_step2_v2bf16() {121; CHECK-LABEL: vid_step2_v2bf16:122; CHECK: # %bb.0:123; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma124; CHECK-NEXT: vid.v v8125; CHECK-NEXT: vsll.vi v8, v8, 14126; CHECK-NEXT: ret127 ret <2 x bfloat> <bfloat 0.0, bfloat 2.0>128}129;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:130; RV32: {{.*}}131; RV32ZVFBFMIN: {{.*}}132; RV64: {{.*}}133; RV64ZVFBFMIN: {{.*}}134