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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2 3; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFH4; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+zba,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFH5; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFH,RV64V6; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+rva22u64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFH,RVA22U647; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFHMIN,RV32-NO-ZFHMIN8; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFHMIN,RV64-NO-ZFHMIN9; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfhmin,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFHMIN,RV32-ZFHMIN10; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfhmin,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFHMIN,RV64-ZFHMIN11 12; Tests that a floating-point build_vector doesn't try and generate a VID13; instruction14define void @buildvec_no_vid_v4f32(ptr %x) {15; CHECK-LABEL: buildvec_no_vid_v4f32:16; CHECK: # %bb.0:17; CHECK-NEXT: lui a1, %hi(.LCPI0_0)18; CHECK-NEXT: addi a1, a1, %lo(.LCPI0_0)19; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma20; CHECK-NEXT: vle32.v v8, (a1)21; CHECK-NEXT: vse32.v v8, (a0)22; CHECK-NEXT: ret23 store <4 x float> <float 0.0, float 4.0, float 0.0, float 2.0>, ptr %x24 ret void25}26 27; Not all BUILD_VECTORs are successfully lowered by the backend: some are28; expanded into scalarized stack stores. However, this may result in an29; infinite loop in the DAGCombiner which tries to recombine those stores into a30; BUILD_VECTOR followed by a vector store. The BUILD_VECTOR is then expanded31; and the loop begins.32; Until all BUILD_VECTORs are lowered, we disable store-combining after33; legalization for fixed-length vectors.34; This test uses a trick with a shufflevector which can't be lowered to a35; SHUFFLE_VECTOR node; the mask is shorter than the source vectors and the36; shuffle indices aren't located within the same 4-element subvector, so is37; expanded to 4 EXTRACT_VECTOR_ELTs and a BUILD_VECTOR. This then triggers the38; loop when expanded.39define <4 x float> @hang_when_merging_stores_after_legalization(<8 x float> %x, <8 x float> %y) optsize {40; CHECK-LABEL: hang_when_merging_stores_after_legalization:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma43; CHECK-NEXT: vmv.v.i v0, 444; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu45; CHECK-NEXT: vslidedown.vi v12, v10, 446; CHECK-NEXT: vslideup.vi v12, v10, 2, v0.t47; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma48; CHECK-NEXT: vmv.v.i v0, 249; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu50; CHECK-NEXT: vslidedown.vi v8, v8, 6, v0.t51; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma52; CHECK-NEXT: vmv.v.i v0, 1253; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma54; CHECK-NEXT: vmerge.vvm v8, v8, v12, v055; CHECK-NEXT: ret56 %z = shufflevector <8 x float> %x, <8 x float> %y, <4 x i32> <i32 0, i32 7, i32 8, i32 15>57 ret <4 x float> %z58}59 60define void @buildvec_dominant0_v2f32(ptr %x) {61; CHECK-LABEL: buildvec_dominant0_v2f32:62; CHECK: # %bb.0:63; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma64; CHECK-NEXT: vid.v v865; CHECK-NEXT: vfcvt.f.x.v v8, v866; CHECK-NEXT: vse32.v v8, (a0)67; CHECK-NEXT: ret68 store <2 x float> <float 0.0, float 1.0>, ptr %x69 ret void70}71 72; We don't want to lower this to the insertion of two scalar elements as above,73; as each would require their own load from the constant pool.74 75define void @buildvec_dominant1_v2f32(ptr %x) {76; CHECK-LABEL: buildvec_dominant1_v2f32:77; CHECK: # %bb.0:78; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma79; CHECK-NEXT: vid.v v880; CHECK-NEXT: vadd.vi v8, v8, 181; CHECK-NEXT: vfcvt.f.x.v v8, v882; CHECK-NEXT: vse32.v v8, (a0)83; CHECK-NEXT: ret84 store <2 x float> <float 1.0, float 2.0>, ptr %x85 ret void86}87 88define void @buildvec_dominant0_v4f32(ptr %x) {89; CHECK-LABEL: buildvec_dominant0_v4f32:90; CHECK: # %bb.0:91; CHECK-NEXT: lui a1, 26214492; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma93; CHECK-NEXT: vmv.v.x v8, a194; CHECK-NEXT: vmv.s.x v9, zero95; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma96; CHECK-NEXT: vslideup.vi v8, v9, 297; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma98; CHECK-NEXT: vse32.v v8, (a0)99; CHECK-NEXT: ret100 store <4 x float> <float 2.0, float 2.0, float 0.0, float 2.0>, ptr %x101 ret void102}103 104define void @buildvec_dominant1_v4f32(ptr %x, float %f) {105; CHECK-LABEL: buildvec_dominant1_v4f32:106; CHECK: # %bb.0:107; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma108; CHECK-NEXT: vfmv.v.f v8, fa0109; CHECK-NEXT: vmv.s.x v9, zero110; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma111; CHECK-NEXT: vslideup.vi v8, v9, 1112; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma113; CHECK-NEXT: vse32.v v8, (a0)114; CHECK-NEXT: ret115 %v0 = insertelement <4 x float> poison, float %f, i32 0116 %v1 = insertelement <4 x float> %v0, float 0.0, i32 1117 %v2 = insertelement <4 x float> %v1, float %f, i32 2118 %v3 = insertelement <4 x float> %v2, float %f, i32 3119 store <4 x float> %v3, ptr %x120 ret void121}122 123define void @buildvec_dominant2_v4f32(ptr %x, float %f) {124; CHECK-LABEL: buildvec_dominant2_v4f32:125; CHECK: # %bb.0:126; CHECK-NEXT: lui a1, 262144127; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma128; CHECK-NEXT: vmv.s.x v8, a1129; CHECK-NEXT: vfmv.v.f v9, fa0130; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma131; CHECK-NEXT: vslideup.vi v9, v8, 1132; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma133; CHECK-NEXT: vse32.v v9, (a0)134; CHECK-NEXT: ret135 %v0 = insertelement <4 x float> poison, float %f, i32 0136 %v1 = insertelement <4 x float> %v0, float 2.0, i32 1137 %v2 = insertelement <4 x float> %v1, float %f, i32 2138 %v3 = insertelement <4 x float> %v2, float %f, i32 3139 store <4 x float> %v3, ptr %x140 ret void141}142 143define void @buildvec_merge0_v4f32(ptr %x, float %f) {144; CHECK-LABEL: buildvec_merge0_v4f32:145; CHECK: # %bb.0:146; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma147; CHECK-NEXT: vfmv.v.f v8, fa0148; CHECK-NEXT: vmv.v.i v0, 6149; CHECK-NEXT: lui a1, 262144150; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0151; CHECK-NEXT: vse32.v v8, (a0)152; CHECK-NEXT: ret153 %v0 = insertelement <4 x float> poison, float %f, i32 0154 %v1 = insertelement <4 x float> %v0, float 2.0, i32 1155 %v2 = insertelement <4 x float> %v1, float 2.0, i32 2156 %v3 = insertelement <4 x float> %v2, float %f, i32 3157 store <4 x float> %v3, ptr %x158 ret void159}160 161define <4 x half> @splat_c3_v4f16(<4 x half> %v) {162; CHECK-LABEL: splat_c3_v4f16:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma165; CHECK-NEXT: vrgather.vi v9, v8, 3166; CHECK-NEXT: vmv1r.v v8, v9167; CHECK-NEXT: ret168 %x = extractelement <4 x half> %v, i32 3169 %ins = insertelement <4 x half> poison, half %x, i32 0170 %splat = shufflevector <4 x half> %ins, <4 x half> poison, <4 x i32> zeroinitializer171 ret <4 x half> %splat172}173 174define <4 x half> @splat_idx_v4f16(<4 x half> %v, i64 %idx) {175; RV32ZVFH-LABEL: splat_idx_v4f16:176; RV32ZVFH: # %bb.0:177; RV32ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma178; RV32ZVFH-NEXT: vrgather.vx v9, v8, a0179; RV32ZVFH-NEXT: vmv1r.v v8, v9180; RV32ZVFH-NEXT: ret181;182; RV64ZVFH-LABEL: splat_idx_v4f16:183; RV64ZVFH: # %bb.0:184; RV64ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma185; RV64ZVFH-NEXT: vrgather.vx v9, v8, a0186; RV64ZVFH-NEXT: vmv1r.v v8, v9187; RV64ZVFH-NEXT: ret188;189; RV32-NO-ZFHMIN-LABEL: splat_idx_v4f16:190; RV32-NO-ZFHMIN: # %bb.0:191; RV32-NO-ZFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma192; RV32-NO-ZFHMIN-NEXT: vrgather.vx v9, v8, a0193; RV32-NO-ZFHMIN-NEXT: vmv1r.v v8, v9194; RV32-NO-ZFHMIN-NEXT: ret195;196; RV64-NO-ZFHMIN-LABEL: splat_idx_v4f16:197; RV64-NO-ZFHMIN: # %bb.0:198; RV64-NO-ZFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma199; RV64-NO-ZFHMIN-NEXT: vrgather.vx v9, v8, a0200; RV64-NO-ZFHMIN-NEXT: vmv1r.v v8, v9201; RV64-NO-ZFHMIN-NEXT: ret202;203; RV32-ZFHMIN-LABEL: splat_idx_v4f16:204; RV32-ZFHMIN: # %bb.0:205; RV32-ZFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma206; RV32-ZFHMIN-NEXT: vslidedown.vx v8, v8, a0207; RV32-ZFHMIN-NEXT: vmv.x.s a0, v8208; RV32-ZFHMIN-NEXT: vmv.v.x v8, a0209; RV32-ZFHMIN-NEXT: ret210;211; RV64-ZFHMIN-LABEL: splat_idx_v4f16:212; RV64-ZFHMIN: # %bb.0:213; RV64-ZFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma214; RV64-ZFHMIN-NEXT: vslidedown.vx v8, v8, a0215; RV64-ZFHMIN-NEXT: vmv.x.s a0, v8216; RV64-ZFHMIN-NEXT: vmv.v.x v8, a0217; RV64-ZFHMIN-NEXT: ret218 %x = extractelement <4 x half> %v, i64 %idx219 %ins = insertelement <4 x half> poison, half %x, i32 0220 %splat = shufflevector <4 x half> %ins, <4 x half> poison, <4 x i32> zeroinitializer221 ret <4 x half> %splat222}223 224define <8 x float> @splat_c5_v8f32(<8 x float> %v) {225; CHECK-LABEL: splat_c5_v8f32:226; CHECK: # %bb.0:227; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma228; CHECK-NEXT: vrgather.vi v10, v8, 5229; CHECK-NEXT: vmv.v.v v8, v10230; CHECK-NEXT: ret231 %x = extractelement <8 x float> %v, i32 5232 %ins = insertelement <8 x float> poison, float %x, i32 0233 %splat = shufflevector <8 x float> %ins, <8 x float> poison, <8 x i32> zeroinitializer234 ret <8 x float> %splat235}236 237define <8 x float> @splat_idx_v8f32(<8 x float> %v, i64 %idx) {238;239; CHECK-LABEL: splat_idx_v8f32:240; CHECK: # %bb.0:241; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma242; CHECK-NEXT: vrgather.vx v10, v8, a0243; CHECK-NEXT: vmv.v.v v8, v10244; CHECK-NEXT: ret245 %x = extractelement <8 x float> %v, i64 %idx246 %ins = insertelement <8 x float> poison, float %x, i32 0247 %splat = shufflevector <8 x float> %ins, <8 x float> poison, <8 x i32> zeroinitializer248 ret <8 x float> %splat249}250 251; Test that we pull the vlse of the constant pool out of the loop.252define dso_local void @splat_load_licm(ptr %0) {253; RV32-LABEL: splat_load_licm:254; RV32: # %bb.0:255; RV32-NEXT: lui a1, 1256; RV32-NEXT: lui a2, 263168257; RV32-NEXT: add a1, a0, a1258; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma259; RV32-NEXT: vmv.v.x v8, a2260; RV32-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1261; RV32-NEXT: vse32.v v8, (a0)262; RV32-NEXT: addi a0, a0, 16263; RV32-NEXT: bne a0, a1, .LBB12_1264; RV32-NEXT: # %bb.2:265; RV32-NEXT: ret266;267; RV64V-LABEL: splat_load_licm:268; RV64V: # %bb.0:269; RV64V-NEXT: lui a1, 1270; RV64V-NEXT: lui a2, 263168271; RV64V-NEXT: add a1, a0, a1272; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma273; RV64V-NEXT: vmv.v.x v8, a2274; RV64V-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1275; RV64V-NEXT: vse32.v v8, (a0)276; RV64V-NEXT: addi a0, a0, 16277; RV64V-NEXT: bne a0, a1, .LBB12_1278; RV64V-NEXT: # %bb.2:279; RV64V-NEXT: ret280;281; RVA22U64-LABEL: splat_load_licm:282; RVA22U64: # %bb.0:283; RVA22U64-NEXT: lui a1, 1284; RVA22U64-NEXT: lui a2, 263168285; RVA22U64-NEXT: add a1, a1, a0286; RVA22U64-NEXT: vsetivli zero, 4, e32, m1, ta, ma287; RVA22U64-NEXT: vmv.v.x v8, a2288; RVA22U64-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1289; RVA22U64-NEXT: vse32.v v8, (a0)290; RVA22U64-NEXT: addi a0, a0, 16291; RVA22U64-NEXT: bne a0, a1, .LBB12_1292; RVA22U64-NEXT: # %bb.2:293; RVA22U64-NEXT: ret294;295; RV64ZVFHMIN-LABEL: splat_load_licm:296; RV64ZVFHMIN: # %bb.0:297; RV64ZVFHMIN-NEXT: lui a1, 1298; RV64ZVFHMIN-NEXT: lui a2, 263168299; RV64ZVFHMIN-NEXT: add a1, a0, a1300; RV64ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma301; RV64ZVFHMIN-NEXT: vmv.v.x v8, a2302; RV64ZVFHMIN-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1303; RV64ZVFHMIN-NEXT: vse32.v v8, (a0)304; RV64ZVFHMIN-NEXT: addi a0, a0, 16305; RV64ZVFHMIN-NEXT: bne a0, a1, .LBB12_1306; RV64ZVFHMIN-NEXT: # %bb.2:307; RV64ZVFHMIN-NEXT: ret308 br label %2309 3102: ; preds = %2, %1311 %3 = phi i32 [ 0, %1 ], [ %6, %2 ]312 %4 = getelementptr inbounds float, ptr %0, i32 %3313 %5 = bitcast ptr %4 to ptr314 store <4 x float> <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00>, ptr %5, align 4315 %6 = add nuw i32 %3, 4316 %7 = icmp eq i32 %6, 1024317 br i1 %7, label %8, label %2318 3198: ; preds = %2320 ret void321}322 323define <2 x half> @buildvec_v2f16(half %a, half %b) {324; RV32ZVFH-LABEL: buildvec_v2f16:325; RV32ZVFH: # %bb.0:326; RV32ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma327; RV32ZVFH-NEXT: vfmv.v.f v8, fa0328; RV32ZVFH-NEXT: vfslide1down.vf v8, v8, fa1329; RV32ZVFH-NEXT: ret330;331; RV64ZVFH-LABEL: buildvec_v2f16:332; RV64ZVFH: # %bb.0:333; RV64ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma334; RV64ZVFH-NEXT: vfmv.v.f v8, fa0335; RV64ZVFH-NEXT: vfslide1down.vf v8, v8, fa1336; RV64ZVFH-NEXT: ret337;338; RV32-NO-ZFHMIN-LABEL: buildvec_v2f16:339; RV32-NO-ZFHMIN: # %bb.0:340; RV32-NO-ZFHMIN-NEXT: fmv.x.w a0, fa1341; RV32-NO-ZFHMIN-NEXT: fmv.x.w a1, fa0342; RV32-NO-ZFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma343; RV32-NO-ZFHMIN-NEXT: vmv.v.x v8, a1344; RV32-NO-ZFHMIN-NEXT: vslide1down.vx v8, v8, a0345; RV32-NO-ZFHMIN-NEXT: ret346;347; RV64-NO-ZFHMIN-LABEL: buildvec_v2f16:348; RV64-NO-ZFHMIN: # %bb.0:349; RV64-NO-ZFHMIN-NEXT: fmv.x.w a0, fa1350; RV64-NO-ZFHMIN-NEXT: fmv.x.w a1, fa0351; RV64-NO-ZFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma352; RV64-NO-ZFHMIN-NEXT: vmv.v.x v8, a1353; RV64-NO-ZFHMIN-NEXT: vslide1down.vx v8, v8, a0354; RV64-NO-ZFHMIN-NEXT: ret355;356; RV32-ZFHMIN-LABEL: buildvec_v2f16:357; RV32-ZFHMIN: # %bb.0:358; RV32-ZFHMIN-NEXT: fmv.x.h a0, fa1359; RV32-ZFHMIN-NEXT: fmv.x.h a1, fa0360; RV32-ZFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma361; RV32-ZFHMIN-NEXT: vmv.v.x v8, a1362; RV32-ZFHMIN-NEXT: vslide1down.vx v8, v8, a0363; RV32-ZFHMIN-NEXT: ret364;365; RV64-ZFHMIN-LABEL: buildvec_v2f16:366; RV64-ZFHMIN: # %bb.0:367; RV64-ZFHMIN-NEXT: fmv.x.h a0, fa1368; RV64-ZFHMIN-NEXT: fmv.x.h a1, fa0369; RV64-ZFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma370; RV64-ZFHMIN-NEXT: vmv.v.x v8, a1371; RV64-ZFHMIN-NEXT: vslide1down.vx v8, v8, a0372; RV64-ZFHMIN-NEXT: ret373 %v1 = insertelement <2 x half> poison, half %a, i64 0374 %v2 = insertelement <2 x half> %v1, half %b, i64 1375 ret <2 x half> %v2376}377 378define <2 x float> @buildvec_v2f32(float %a, float %b) {379; CHECK-LABEL: buildvec_v2f32:380; CHECK: # %bb.0:381; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma382; CHECK-NEXT: vfmv.v.f v8, fa0383; CHECK-NEXT: vfslide1down.vf v8, v8, fa1384; CHECK-NEXT: ret385 %v1 = insertelement <2 x float> poison, float %a, i64 0386 %v2 = insertelement <2 x float> %v1, float %b, i64 1387 ret <2 x float> %v2388}389 390define <2 x double> @buildvec_v2f64(double %a, double %b) {391; CHECK-LABEL: buildvec_v2f64:392; CHECK: # %bb.0:393; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma394; CHECK-NEXT: vfmv.v.f v8, fa0395; CHECK-NEXT: vfslide1down.vf v8, v8, fa1396; CHECK-NEXT: ret397 %v1 = insertelement <2 x double> poison, double %a, i64 0398 %v2 = insertelement <2 x double> %v1, double %b, i64 1399 ret <2 x double> %v2400}401 402define <2 x double> @buildvec_v2f64_b(double %a, double %b) {403; CHECK-LABEL: buildvec_v2f64_b:404; CHECK: # %bb.0:405; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma406; CHECK-NEXT: vfmv.v.f v8, fa0407; CHECK-NEXT: vfslide1down.vf v8, v8, fa1408; CHECK-NEXT: ret409 %v1 = insertelement <2 x double> poison, double %b, i64 1410 %v2 = insertelement <2 x double> %v1, double %a, i64 0411 ret <2 x double> %v2412}413 414define <4 x float> @buildvec_v4f32(float %a, float %b, float %c, float %d) {415; CHECK-LABEL: buildvec_v4f32:416; CHECK: # %bb.0:417; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma418; CHECK-NEXT: vfmv.v.f v8, fa0419; CHECK-NEXT: vfslide1down.vf v8, v8, fa1420; CHECK-NEXT: vfslide1down.vf v8, v8, fa2421; CHECK-NEXT: vfslide1down.vf v8, v8, fa3422; CHECK-NEXT: ret423 %v1 = insertelement <4 x float> poison, float %a, i64 0424 %v2 = insertelement <4 x float> %v1, float %b, i64 1425 %v3 = insertelement <4 x float> %v2, float %c, i64 2426 %v4 = insertelement <4 x float> %v3, float %d, i64 3427 ret <4 x float> %v4428}429 430define <8 x float> @buildvec_v8f32(float %e0, float %e1, float %e2, float %e3, float %e4, float %e5, float %e6, float %e7) {431; CHECK-LABEL: buildvec_v8f32:432; CHECK: # %bb.0:433; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma434; CHECK-NEXT: vfmv.v.f v8, fa0435; CHECK-NEXT: vfslide1down.vf v8, v8, fa1436; CHECK-NEXT: vfslide1down.vf v8, v8, fa2437; CHECK-NEXT: vfslide1down.vf v8, v8, fa3438; CHECK-NEXT: vfslide1down.vf v8, v8, fa4439; CHECK-NEXT: vfslide1down.vf v8, v8, fa5440; CHECK-NEXT: vfslide1down.vf v8, v8, fa6441; CHECK-NEXT: vfslide1down.vf v8, v8, fa7442; CHECK-NEXT: ret443 %v0 = insertelement <8 x float> poison, float %e0, i64 0444 %v1 = insertelement <8 x float> %v0, float %e1, i64 1445 %v2 = insertelement <8 x float> %v1, float %e2, i64 2446 %v3 = insertelement <8 x float> %v2, float %e3, i64 3447 %v4 = insertelement <8 x float> %v3, float %e4, i64 4448 %v5 = insertelement <8 x float> %v4, float %e5, i64 5449 %v6 = insertelement <8 x float> %v5, float %e6, i64 6450 %v7 = insertelement <8 x float> %v6, float %e7, i64 7451 ret <8 x float> %v7452}453 454define <16 x float> @buildvec_v16f32(float %e0, float %e1, float %e2, float %e3, float %e4, float %e5, float %e6, float %e7, float %e8, float %e9, float %e10, float %e11, float %e12, float %e13, float %e14, float %e15) {455; RV32-LABEL: buildvec_v16f32:456; RV32: # %bb.0:457; RV32-NEXT: addi sp, sp, -128458; RV32-NEXT: .cfi_def_cfa_offset 128459; RV32-NEXT: sw ra, 124(sp) # 4-byte Folded Spill460; RV32-NEXT: sw s0, 120(sp) # 4-byte Folded Spill461; RV32-NEXT: .cfi_offset ra, -4462; RV32-NEXT: .cfi_offset s0, -8463; RV32-NEXT: addi s0, sp, 128464; RV32-NEXT: .cfi_def_cfa s0, 0465; RV32-NEXT: andi sp, sp, -64466; RV32-NEXT: sw a4, 48(sp)467; RV32-NEXT: sw a5, 52(sp)468; RV32-NEXT: sw a6, 56(sp)469; RV32-NEXT: sw a7, 60(sp)470; RV32-NEXT: sw a0, 32(sp)471; RV32-NEXT: sw a1, 36(sp)472; RV32-NEXT: sw a2, 40(sp)473; RV32-NEXT: sw a3, 44(sp)474; RV32-NEXT: fsw fa4, 16(sp)475; RV32-NEXT: fsw fa5, 20(sp)476; RV32-NEXT: fsw fa6, 24(sp)477; RV32-NEXT: fsw fa7, 28(sp)478; RV32-NEXT: fsw fa0, 0(sp)479; RV32-NEXT: fsw fa1, 4(sp)480; RV32-NEXT: fsw fa2, 8(sp)481; RV32-NEXT: fsw fa3, 12(sp)482; RV32-NEXT: mv a0, sp483; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma484; RV32-NEXT: vle32.v v8, (a0)485; RV32-NEXT: addi sp, s0, -128486; RV32-NEXT: .cfi_def_cfa sp, 128487; RV32-NEXT: lw ra, 124(sp) # 4-byte Folded Reload488; RV32-NEXT: lw s0, 120(sp) # 4-byte Folded Reload489; RV32-NEXT: .cfi_restore ra490; RV32-NEXT: .cfi_restore s0491; RV32-NEXT: addi sp, sp, 128492; RV32-NEXT: .cfi_def_cfa_offset 0493; RV32-NEXT: ret494;495; RV64-LABEL: buildvec_v16f32:496; RV64: # %bb.0:497; RV64-NEXT: addi sp, sp, -128498; RV64-NEXT: .cfi_def_cfa_offset 128499; RV64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill500; RV64-NEXT: sd s0, 112(sp) # 8-byte Folded Spill501; RV64-NEXT: .cfi_offset ra, -8502; RV64-NEXT: .cfi_offset s0, -16503; RV64-NEXT: addi s0, sp, 128504; RV64-NEXT: .cfi_def_cfa s0, 0505; RV64-NEXT: andi sp, sp, -64506; RV64-NEXT: fmv.w.x ft0, a0507; RV64-NEXT: fmv.w.x ft1, a1508; RV64-NEXT: fmv.w.x ft2, a2509; RV64-NEXT: fmv.w.x ft3, a3510; RV64-NEXT: fmv.w.x ft4, a4511; RV64-NEXT: fmv.w.x ft5, a5512; RV64-NEXT: fmv.w.x ft6, a6513; RV64-NEXT: fmv.w.x ft7, a7514; RV64-NEXT: fsw fa4, 16(sp)515; RV64-NEXT: fsw fa5, 20(sp)516; RV64-NEXT: fsw fa6, 24(sp)517; RV64-NEXT: fsw fa7, 28(sp)518; RV64-NEXT: fsw fa0, 0(sp)519; RV64-NEXT: fsw fa1, 4(sp)520; RV64-NEXT: fsw fa2, 8(sp)521; RV64-NEXT: fsw fa3, 12(sp)522; RV64-NEXT: fsw ft4, 48(sp)523; RV64-NEXT: fsw ft5, 52(sp)524; RV64-NEXT: fsw ft6, 56(sp)525; RV64-NEXT: fsw ft7, 60(sp)526; RV64-NEXT: fsw ft0, 32(sp)527; RV64-NEXT: fsw ft1, 36(sp)528; RV64-NEXT: fsw ft2, 40(sp)529; RV64-NEXT: fsw ft3, 44(sp)530; RV64-NEXT: mv a0, sp531; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma532; RV64-NEXT: vle32.v v8, (a0)533; RV64-NEXT: addi sp, s0, -128534; RV64-NEXT: .cfi_def_cfa sp, 128535; RV64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload536; RV64-NEXT: ld s0, 112(sp) # 8-byte Folded Reload537; RV64-NEXT: .cfi_restore ra538; RV64-NEXT: .cfi_restore s0539; RV64-NEXT: addi sp, sp, 128540; RV64-NEXT: .cfi_def_cfa_offset 0541; RV64-NEXT: ret542 %v0 = insertelement <16 x float> poison, float %e0, i64 0543 %v1 = insertelement <16 x float> %v0, float %e1, i64 1544 %v2 = insertelement <16 x float> %v1, float %e2, i64 2545 %v3 = insertelement <16 x float> %v2, float %e3, i64 3546 %v4 = insertelement <16 x float> %v3, float %e4, i64 4547 %v5 = insertelement <16 x float> %v4, float %e5, i64 5548 %v6 = insertelement <16 x float> %v5, float %e6, i64 6549 %v7 = insertelement <16 x float> %v6, float %e7, i64 7550 %v8 = insertelement <16 x float> %v7, float %e8, i64 8551 %v9 = insertelement <16 x float> %v8, float %e9, i64 9552 %v10 = insertelement <16 x float> %v9, float %e10, i64 10553 %v11 = insertelement <16 x float> %v10, float %e11, i64 11554 %v12 = insertelement <16 x float> %v11, float %e12, i64 12555 %v13 = insertelement <16 x float> %v12, float %e13, i64 13556 %v14 = insertelement <16 x float> %v13, float %e14, i64 14557 %v15 = insertelement <16 x float> %v14, float %e15, i64 15558 ret <16 x float> %v15559}560 561define <32 x float> @buildvec_v32f32(float %e0, float %e1, float %e2, float %e3, float %e4, float %e5, float %e6, float %e7, float %e8, float %e9, float %e10, float %e11, float %e12, float %e13, float %e14, float %e15, float %e16, float %e17, float %e18, float %e19, float %e20, float %e21, float %e22, float %e23, float %e24, float %e25, float %e26, float %e27, float %e28, float %e29, float %e30, float %e31) {562; RV32-LABEL: buildvec_v32f32:563; RV32: # %bb.0:564; RV32-NEXT: addi sp, sp, -256565; RV32-NEXT: .cfi_def_cfa_offset 256566; RV32-NEXT: sw ra, 252(sp) # 4-byte Folded Spill567; RV32-NEXT: sw s0, 248(sp) # 4-byte Folded Spill568; RV32-NEXT: fsd fs0, 240(sp) # 8-byte Folded Spill569; RV32-NEXT: fsd fs1, 232(sp) # 8-byte Folded Spill570; RV32-NEXT: fsd fs2, 224(sp) # 8-byte Folded Spill571; RV32-NEXT: fsd fs3, 216(sp) # 8-byte Folded Spill572; RV32-NEXT: .cfi_offset ra, -4573; RV32-NEXT: .cfi_offset s0, -8574; RV32-NEXT: .cfi_offset fs0, -16575; RV32-NEXT: .cfi_offset fs1, -24576; RV32-NEXT: .cfi_offset fs2, -32577; RV32-NEXT: .cfi_offset fs3, -40578; RV32-NEXT: addi s0, sp, 256579; RV32-NEXT: .cfi_def_cfa s0, 0580; RV32-NEXT: andi sp, sp, -128581; RV32-NEXT: flw ft0, 0(s0)582; RV32-NEXT: flw ft1, 4(s0)583; RV32-NEXT: flw ft2, 8(s0)584; RV32-NEXT: flw ft3, 12(s0)585; RV32-NEXT: flw ft4, 16(s0)586; RV32-NEXT: flw ft5, 20(s0)587; RV32-NEXT: flw ft6, 24(s0)588; RV32-NEXT: flw ft7, 28(s0)589; RV32-NEXT: flw ft8, 32(s0)590; RV32-NEXT: flw ft9, 36(s0)591; RV32-NEXT: flw ft10, 40(s0)592; RV32-NEXT: flw ft11, 44(s0)593; RV32-NEXT: flw fs0, 48(s0)594; RV32-NEXT: flw fs1, 52(s0)595; RV32-NEXT: flw fs2, 56(s0)596; RV32-NEXT: flw fs3, 60(s0)597; RV32-NEXT: sw a4, 48(sp)598; RV32-NEXT: sw a5, 52(sp)599; RV32-NEXT: sw a6, 56(sp)600; RV32-NEXT: sw a7, 60(sp)601; RV32-NEXT: sw a0, 32(sp)602; RV32-NEXT: sw a1, 36(sp)603; RV32-NEXT: sw a2, 40(sp)604; RV32-NEXT: sw a3, 44(sp)605; RV32-NEXT: fsw fa4, 16(sp)606; RV32-NEXT: fsw fa5, 20(sp)607; RV32-NEXT: fsw fa6, 24(sp)608; RV32-NEXT: fsw fa7, 28(sp)609; RV32-NEXT: fsw fa0, 0(sp)610; RV32-NEXT: fsw fa1, 4(sp)611; RV32-NEXT: fsw fa2, 8(sp)612; RV32-NEXT: fsw fa3, 12(sp)613; RV32-NEXT: li a0, 32614; RV32-NEXT: fsw fs0, 112(sp)615; RV32-NEXT: fsw fs1, 116(sp)616; RV32-NEXT: fsw fs2, 120(sp)617; RV32-NEXT: fsw fs3, 124(sp)618; RV32-NEXT: fsw ft8, 96(sp)619; RV32-NEXT: fsw ft9, 100(sp)620; RV32-NEXT: fsw ft10, 104(sp)621; RV32-NEXT: fsw ft11, 108(sp)622; RV32-NEXT: fsw ft4, 80(sp)623; RV32-NEXT: fsw ft5, 84(sp)624; RV32-NEXT: fsw ft6, 88(sp)625; RV32-NEXT: fsw ft7, 92(sp)626; RV32-NEXT: fsw ft0, 64(sp)627; RV32-NEXT: fsw ft1, 68(sp)628; RV32-NEXT: fsw ft2, 72(sp)629; RV32-NEXT: fsw ft3, 76(sp)630; RV32-NEXT: mv a1, sp631; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma632; RV32-NEXT: vle32.v v8, (a1)633; RV32-NEXT: addi sp, s0, -256634; RV32-NEXT: .cfi_def_cfa sp, 256635; RV32-NEXT: lw ra, 252(sp) # 4-byte Folded Reload636; RV32-NEXT: lw s0, 248(sp) # 4-byte Folded Reload637; RV32-NEXT: fld fs0, 240(sp) # 8-byte Folded Reload638; RV32-NEXT: fld fs1, 232(sp) # 8-byte Folded Reload639; RV32-NEXT: fld fs2, 224(sp) # 8-byte Folded Reload640; RV32-NEXT: fld fs3, 216(sp) # 8-byte Folded Reload641; RV32-NEXT: .cfi_restore ra642; RV32-NEXT: .cfi_restore s0643; RV32-NEXT: .cfi_restore fs0644; RV32-NEXT: .cfi_restore fs1645; RV32-NEXT: .cfi_restore fs2646; RV32-NEXT: .cfi_restore fs3647; RV32-NEXT: addi sp, sp, 256648; RV32-NEXT: .cfi_def_cfa_offset 0649; RV32-NEXT: ret650;651; RV64-LABEL: buildvec_v32f32:652; RV64: # %bb.0:653; RV64-NEXT: addi sp, sp, -256654; RV64-NEXT: .cfi_def_cfa_offset 256655; RV64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill656; RV64-NEXT: sd s0, 240(sp) # 8-byte Folded Spill657; RV64-NEXT: fsd fs0, 232(sp) # 8-byte Folded Spill658; RV64-NEXT: fsd fs1, 224(sp) # 8-byte Folded Spill659; RV64-NEXT: fsd fs2, 216(sp) # 8-byte Folded Spill660; RV64-NEXT: fsd fs3, 208(sp) # 8-byte Folded Spill661; RV64-NEXT: fsd fs4, 200(sp) # 8-byte Folded Spill662; RV64-NEXT: fsd fs5, 192(sp) # 8-byte Folded Spill663; RV64-NEXT: fsd fs6, 184(sp) # 8-byte Folded Spill664; RV64-NEXT: fsd fs7, 176(sp) # 8-byte Folded Spill665; RV64-NEXT: fsd fs8, 168(sp) # 8-byte Folded Spill666; RV64-NEXT: fsd fs9, 160(sp) # 8-byte Folded Spill667; RV64-NEXT: fsd fs10, 152(sp) # 8-byte Folded Spill668; RV64-NEXT: fsd fs11, 144(sp) # 8-byte Folded Spill669; RV64-NEXT: .cfi_offset ra, -8670; RV64-NEXT: .cfi_offset s0, -16671; RV64-NEXT: .cfi_offset fs0, -24672; RV64-NEXT: .cfi_offset fs1, -32673; RV64-NEXT: .cfi_offset fs2, -40674; RV64-NEXT: .cfi_offset fs3, -48675; RV64-NEXT: .cfi_offset fs4, -56676; RV64-NEXT: .cfi_offset fs5, -64677; RV64-NEXT: .cfi_offset fs6, -72678; RV64-NEXT: .cfi_offset fs7, -80679; RV64-NEXT: .cfi_offset fs8, -88680; RV64-NEXT: .cfi_offset fs9, -96681; RV64-NEXT: .cfi_offset fs10, -104682; RV64-NEXT: .cfi_offset fs11, -112683; RV64-NEXT: addi s0, sp, 256684; RV64-NEXT: .cfi_def_cfa s0, 0685; RV64-NEXT: andi sp, sp, -128686; RV64-NEXT: fmv.w.x ft4, a0687; RV64-NEXT: fmv.w.x ft5, a1688; RV64-NEXT: fmv.w.x ft6, a2689; RV64-NEXT: fmv.w.x ft7, a3690; RV64-NEXT: fmv.w.x fs0, a4691; RV64-NEXT: fmv.w.x fs1, a5692; RV64-NEXT: fmv.w.x fs2, a6693; RV64-NEXT: fmv.w.x fs3, a7694; RV64-NEXT: flw ft0, 0(s0)695; RV64-NEXT: flw ft1, 8(s0)696; RV64-NEXT: flw ft2, 16(s0)697; RV64-NEXT: flw ft3, 24(s0)698; RV64-NEXT: flw ft8, 32(s0)699; RV64-NEXT: flw ft9, 40(s0)700; RV64-NEXT: flw ft10, 48(s0)701; RV64-NEXT: flw ft11, 56(s0)702; RV64-NEXT: flw fs4, 64(s0)703; RV64-NEXT: flw fs5, 72(s0)704; RV64-NEXT: flw fs6, 80(s0)705; RV64-NEXT: flw fs7, 88(s0)706; RV64-NEXT: flw fs8, 96(s0)707; RV64-NEXT: flw fs9, 104(s0)708; RV64-NEXT: flw fs10, 112(s0)709; RV64-NEXT: flw fs11, 120(s0)710; RV64-NEXT: fsw fa4, 16(sp)711; RV64-NEXT: fsw fa5, 20(sp)712; RV64-NEXT: fsw fa6, 24(sp)713; RV64-NEXT: fsw fa7, 28(sp)714; RV64-NEXT: fsw fa0, 0(sp)715; RV64-NEXT: fsw fa1, 4(sp)716; RV64-NEXT: fsw fa2, 8(sp)717; RV64-NEXT: fsw fa3, 12(sp)718; RV64-NEXT: li a0, 32719; RV64-NEXT: fsw fs0, 48(sp)720; RV64-NEXT: fsw fs1, 52(sp)721; RV64-NEXT: fsw fs2, 56(sp)722; RV64-NEXT: fsw fs3, 60(sp)723; RV64-NEXT: fsw ft4, 32(sp)724; RV64-NEXT: fsw ft5, 36(sp)725; RV64-NEXT: fsw ft6, 40(sp)726; RV64-NEXT: fsw ft7, 44(sp)727; RV64-NEXT: fsw fs8, 112(sp)728; RV64-NEXT: fsw fs9, 116(sp)729; RV64-NEXT: fsw fs10, 120(sp)730; RV64-NEXT: fsw fs11, 124(sp)731; RV64-NEXT: fsw fs4, 96(sp)732; RV64-NEXT: fsw fs5, 100(sp)733; RV64-NEXT: fsw fs6, 104(sp)734; RV64-NEXT: fsw fs7, 108(sp)735; RV64-NEXT: fsw ft8, 80(sp)736; RV64-NEXT: fsw ft9, 84(sp)737; RV64-NEXT: fsw ft10, 88(sp)738; RV64-NEXT: fsw ft11, 92(sp)739; RV64-NEXT: fsw ft0, 64(sp)740; RV64-NEXT: fsw ft1, 68(sp)741; RV64-NEXT: fsw ft2, 72(sp)742; RV64-NEXT: fsw ft3, 76(sp)743; RV64-NEXT: mv a1, sp744; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, ma745; RV64-NEXT: vle32.v v8, (a1)746; RV64-NEXT: addi sp, s0, -256747; RV64-NEXT: .cfi_def_cfa sp, 256748; RV64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload749; RV64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload750; RV64-NEXT: fld fs0, 232(sp) # 8-byte Folded Reload751; RV64-NEXT: fld fs1, 224(sp) # 8-byte Folded Reload752; RV64-NEXT: fld fs2, 216(sp) # 8-byte Folded Reload753; RV64-NEXT: fld fs3, 208(sp) # 8-byte Folded Reload754; RV64-NEXT: fld fs4, 200(sp) # 8-byte Folded Reload755; RV64-NEXT: fld fs5, 192(sp) # 8-byte Folded Reload756; RV64-NEXT: fld fs6, 184(sp) # 8-byte Folded Reload757; RV64-NEXT: fld fs7, 176(sp) # 8-byte Folded Reload758; RV64-NEXT: fld fs8, 168(sp) # 8-byte Folded Reload759; RV64-NEXT: fld fs9, 160(sp) # 8-byte Folded Reload760; RV64-NEXT: fld fs10, 152(sp) # 8-byte Folded Reload761; RV64-NEXT: fld fs11, 144(sp) # 8-byte Folded Reload762; RV64-NEXT: .cfi_restore ra763; RV64-NEXT: .cfi_restore s0764; RV64-NEXT: .cfi_restore fs0765; RV64-NEXT: .cfi_restore fs1766; RV64-NEXT: .cfi_restore fs2767; RV64-NEXT: .cfi_restore fs3768; RV64-NEXT: .cfi_restore fs4769; RV64-NEXT: .cfi_restore fs5770; RV64-NEXT: .cfi_restore fs6771; RV64-NEXT: .cfi_restore fs7772; RV64-NEXT: .cfi_restore fs8773; RV64-NEXT: .cfi_restore fs9774; RV64-NEXT: .cfi_restore fs10775; RV64-NEXT: .cfi_restore fs11776; RV64-NEXT: addi sp, sp, 256777; RV64-NEXT: .cfi_def_cfa_offset 0778; RV64-NEXT: ret779 %v0 = insertelement <32 x float> poison, float %e0, i64 0780 %v1 = insertelement <32 x float> %v0, float %e1, i64 1781 %v2 = insertelement <32 x float> %v1, float %e2, i64 2782 %v3 = insertelement <32 x float> %v2, float %e3, i64 3783 %v4 = insertelement <32 x float> %v3, float %e4, i64 4784 %v5 = insertelement <32 x float> %v4, float %e5, i64 5785 %v6 = insertelement <32 x float> %v5, float %e6, i64 6786 %v7 = insertelement <32 x float> %v6, float %e7, i64 7787 %v8 = insertelement <32 x float> %v7, float %e8, i64 8788 %v9 = insertelement <32 x float> %v8, float %e9, i64 9789 %v10 = insertelement <32 x float> %v9, float %e10, i64 10790 %v11 = insertelement <32 x float> %v10, float %e11, i64 11791 %v12 = insertelement <32 x float> %v11, float %e12, i64 12792 %v13 = insertelement <32 x float> %v12, float %e13, i64 13793 %v14 = insertelement <32 x float> %v13, float %e14, i64 14794 %v15 = insertelement <32 x float> %v14, float %e15, i64 15795 %v16 = insertelement <32 x float> %v15, float %e16, i64 16796 %v17 = insertelement <32 x float> %v16, float %e17, i64 17797 %v18 = insertelement <32 x float> %v17, float %e18, i64 18798 %v19 = insertelement <32 x float> %v18, float %e19, i64 19799 %v20 = insertelement <32 x float> %v19, float %e20, i64 20800 %v21 = insertelement <32 x float> %v20, float %e21, i64 21801 %v22 = insertelement <32 x float> %v21, float %e22, i64 22802 %v23 = insertelement <32 x float> %v22, float %e23, i64 23803 %v24 = insertelement <32 x float> %v23, float %e24, i64 24804 %v25 = insertelement <32 x float> %v24, float %e25, i64 25805 %v26 = insertelement <32 x float> %v25, float %e26, i64 26806 %v27 = insertelement <32 x float> %v26, float %e27, i64 27807 %v28 = insertelement <32 x float> %v27, float %e28, i64 28808 %v29 = insertelement <32 x float> %v28, float %e29, i64 29809 %v30 = insertelement <32 x float> %v29, float %e30, i64 30810 %v31 = insertelement <32 x float> %v30, float %e31, i64 31811 ret <32 x float> %v31812}813 814define <8 x double> @buildvec_v8f64(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7) {815; RV32-LABEL: buildvec_v8f64:816; RV32: # %bb.0:817; RV32-NEXT: addi sp, sp, -128818; RV32-NEXT: .cfi_def_cfa_offset 128819; RV32-NEXT: sw ra, 124(sp) # 4-byte Folded Spill820; RV32-NEXT: sw s0, 120(sp) # 4-byte Folded Spill821; RV32-NEXT: .cfi_offset ra, -4822; RV32-NEXT: .cfi_offset s0, -8823; RV32-NEXT: addi s0, sp, 128824; RV32-NEXT: .cfi_def_cfa s0, 0825; RV32-NEXT: andi sp, sp, -64826; RV32-NEXT: fsd fa4, 32(sp)827; RV32-NEXT: fsd fa5, 40(sp)828; RV32-NEXT: fsd fa6, 48(sp)829; RV32-NEXT: fsd fa7, 56(sp)830; RV32-NEXT: fsd fa0, 0(sp)831; RV32-NEXT: fsd fa1, 8(sp)832; RV32-NEXT: fsd fa2, 16(sp)833; RV32-NEXT: fsd fa3, 24(sp)834; RV32-NEXT: mv a0, sp835; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma836; RV32-NEXT: vle64.v v8, (a0)837; RV32-NEXT: addi sp, s0, -128838; RV32-NEXT: .cfi_def_cfa sp, 128839; RV32-NEXT: lw ra, 124(sp) # 4-byte Folded Reload840; RV32-NEXT: lw s0, 120(sp) # 4-byte Folded Reload841; RV32-NEXT: .cfi_restore ra842; RV32-NEXT: .cfi_restore s0843; RV32-NEXT: addi sp, sp, 128844; RV32-NEXT: .cfi_def_cfa_offset 0845; RV32-NEXT: ret846;847; RV64-LABEL: buildvec_v8f64:848; RV64: # %bb.0:849; RV64-NEXT: addi sp, sp, -128850; RV64-NEXT: .cfi_def_cfa_offset 128851; RV64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill852; RV64-NEXT: sd s0, 112(sp) # 8-byte Folded Spill853; RV64-NEXT: .cfi_offset ra, -8854; RV64-NEXT: .cfi_offset s0, -16855; RV64-NEXT: addi s0, sp, 128856; RV64-NEXT: .cfi_def_cfa s0, 0857; RV64-NEXT: andi sp, sp, -64858; RV64-NEXT: fsd fa4, 32(sp)859; RV64-NEXT: fsd fa5, 40(sp)860; RV64-NEXT: fsd fa6, 48(sp)861; RV64-NEXT: fsd fa7, 56(sp)862; RV64-NEXT: fsd fa0, 0(sp)863; RV64-NEXT: fsd fa1, 8(sp)864; RV64-NEXT: fsd fa2, 16(sp)865; RV64-NEXT: fsd fa3, 24(sp)866; RV64-NEXT: mv a0, sp867; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma868; RV64-NEXT: vle64.v v8, (a0)869; RV64-NEXT: addi sp, s0, -128870; RV64-NEXT: .cfi_def_cfa sp, 128871; RV64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload872; RV64-NEXT: ld s0, 112(sp) # 8-byte Folded Reload873; RV64-NEXT: .cfi_restore ra874; RV64-NEXT: .cfi_restore s0875; RV64-NEXT: addi sp, sp, 128876; RV64-NEXT: .cfi_def_cfa_offset 0877; RV64-NEXT: ret878 %v0 = insertelement <8 x double> poison, double %e0, i64 0879 %v1 = insertelement <8 x double> %v0, double %e1, i64 1880 %v2 = insertelement <8 x double> %v1, double %e2, i64 2881 %v3 = insertelement <8 x double> %v2, double %e3, i64 3882 %v4 = insertelement <8 x double> %v3, double %e4, i64 4883 %v5 = insertelement <8 x double> %v4, double %e5, i64 5884 %v6 = insertelement <8 x double> %v5, double %e6, i64 6885 %v7 = insertelement <8 x double> %v6, double %e7, i64 7886 ret <8 x double> %v7887}888 889define <16 x double> @buildvec_v16f64(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7, double %e8, double %e9, double %e10, double %e11, double %e12, double %e13, double %e14, double %e15) {890; RV32-LABEL: buildvec_v16f64:891; RV32: # %bb.0:892; RV32-NEXT: addi sp, sp, -384893; RV32-NEXT: .cfi_def_cfa_offset 384894; RV32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill895; RV32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill896; RV32-NEXT: .cfi_offset ra, -4897; RV32-NEXT: .cfi_offset s0, -8898; RV32-NEXT: addi s0, sp, 384899; RV32-NEXT: .cfi_def_cfa s0, 0900; RV32-NEXT: andi sp, sp, -128901; RV32-NEXT: sw a0, 120(sp)902; RV32-NEXT: sw a1, 124(sp)903; RV32-NEXT: fld ft0, 0(s0)904; RV32-NEXT: fld ft1, 8(s0)905; RV32-NEXT: fld ft2, 16(s0)906; RV32-NEXT: fld ft3, 24(s0)907; RV32-NEXT: fld ft4, 120(sp)908; RV32-NEXT: sw a2, 120(sp)909; RV32-NEXT: sw a3, 124(sp)910; RV32-NEXT: fld ft5, 120(sp)911; RV32-NEXT: sw a4, 120(sp)912; RV32-NEXT: sw a5, 124(sp)913; RV32-NEXT: fld ft6, 120(sp)914; RV32-NEXT: sw a6, 120(sp)915; RV32-NEXT: sw a7, 124(sp)916; RV32-NEXT: fld ft7, 120(sp)917; RV32-NEXT: fsd ft0, 224(sp)918; RV32-NEXT: fsd ft1, 232(sp)919; RV32-NEXT: fsd ft2, 240(sp)920; RV32-NEXT: fsd ft3, 248(sp)921; RV32-NEXT: fsd fa4, 160(sp)922; RV32-NEXT: fsd fa5, 168(sp)923; RV32-NEXT: fsd fa6, 176(sp)924; RV32-NEXT: fsd fa7, 184(sp)925; RV32-NEXT: fsd fa0, 128(sp)926; RV32-NEXT: fsd fa1, 136(sp)927; RV32-NEXT: fsd fa2, 144(sp)928; RV32-NEXT: fsd fa3, 152(sp)929; RV32-NEXT: fsd ft4, 192(sp)930; RV32-NEXT: fsd ft5, 200(sp)931; RV32-NEXT: fsd ft6, 208(sp)932; RV32-NEXT: fsd ft7, 216(sp)933; RV32-NEXT: addi a0, sp, 128934; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma935; RV32-NEXT: vle64.v v8, (a0)936; RV32-NEXT: addi sp, s0, -384937; RV32-NEXT: .cfi_def_cfa sp, 384938; RV32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload939; RV32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload940; RV32-NEXT: .cfi_restore ra941; RV32-NEXT: .cfi_restore s0942; RV32-NEXT: addi sp, sp, 384943; RV32-NEXT: .cfi_def_cfa_offset 0944; RV32-NEXT: ret945;946; RV64-LABEL: buildvec_v16f64:947; RV64: # %bb.0:948; RV64-NEXT: addi sp, sp, -256949; RV64-NEXT: .cfi_def_cfa_offset 256950; RV64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill951; RV64-NEXT: sd s0, 240(sp) # 8-byte Folded Spill952; RV64-NEXT: .cfi_offset ra, -8953; RV64-NEXT: .cfi_offset s0, -16954; RV64-NEXT: addi s0, sp, 256955; RV64-NEXT: .cfi_def_cfa s0, 0956; RV64-NEXT: andi sp, sp, -128957; RV64-NEXT: sd a4, 96(sp)958; RV64-NEXT: sd a5, 104(sp)959; RV64-NEXT: sd a6, 112(sp)960; RV64-NEXT: sd a7, 120(sp)961; RV64-NEXT: sd a0, 64(sp)962; RV64-NEXT: sd a1, 72(sp)963; RV64-NEXT: sd a2, 80(sp)964; RV64-NEXT: sd a3, 88(sp)965; RV64-NEXT: fsd fa4, 32(sp)966; RV64-NEXT: fsd fa5, 40(sp)967; RV64-NEXT: fsd fa6, 48(sp)968; RV64-NEXT: fsd fa7, 56(sp)969; RV64-NEXT: fsd fa0, 0(sp)970; RV64-NEXT: fsd fa1, 8(sp)971; RV64-NEXT: fsd fa2, 16(sp)972; RV64-NEXT: fsd fa3, 24(sp)973; RV64-NEXT: mv a0, sp974; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma975; RV64-NEXT: vle64.v v8, (a0)976; RV64-NEXT: addi sp, s0, -256977; RV64-NEXT: .cfi_def_cfa sp, 256978; RV64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload979; RV64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload980; RV64-NEXT: .cfi_restore ra981; RV64-NEXT: .cfi_restore s0982; RV64-NEXT: addi sp, sp, 256983; RV64-NEXT: .cfi_def_cfa_offset 0984; RV64-NEXT: ret985 %v0 = insertelement <16 x double> poison, double %e0, i64 0986 %v1 = insertelement <16 x double> %v0, double %e1, i64 1987 %v2 = insertelement <16 x double> %v1, double %e2, i64 2988 %v3 = insertelement <16 x double> %v2, double %e3, i64 3989 %v4 = insertelement <16 x double> %v3, double %e4, i64 4990 %v5 = insertelement <16 x double> %v4, double %e5, i64 5991 %v6 = insertelement <16 x double> %v5, double %e6, i64 6992 %v7 = insertelement <16 x double> %v6, double %e7, i64 7993 %v8 = insertelement <16 x double> %v7, double %e8, i64 8994 %v9 = insertelement <16 x double> %v8, double %e9, i64 9995 %v10 = insertelement <16 x double> %v9, double %e10, i64 10996 %v11 = insertelement <16 x double> %v10, double %e11, i64 11997 %v12 = insertelement <16 x double> %v11, double %e12, i64 12998 %v13 = insertelement <16 x double> %v12, double %e13, i64 13999 %v14 = insertelement <16 x double> %v13, double %e14, i64 141000 %v15 = insertelement <16 x double> %v14, double %e15, i64 151001 ret <16 x double> %v151002}1003 1004define <32 x double> @buildvec_v32f64(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7, double %e8, double %e9, double %e10, double %e11, double %e12, double %e13, double %e14, double %e15, double %e16, double %e17, double %e18, double %e19, double %e20, double %e21, double %e22, double %e23, double %e24, double %e25, double %e26, double %e27, double %e28, double %e29, double %e30, double %e31) {1005; RV32-LABEL: buildvec_v32f64:1006; RV32: # %bb.0:1007; RV32-NEXT: addi sp, sp, -5121008; RV32-NEXT: .cfi_def_cfa_offset 5121009; RV32-NEXT: sw ra, 508(sp) # 4-byte Folded Spill1010; RV32-NEXT: sw s0, 504(sp) # 4-byte Folded Spill1011; RV32-NEXT: fsd fs0, 496(sp) # 8-byte Folded Spill1012; RV32-NEXT: fsd fs1, 488(sp) # 8-byte Folded Spill1013; RV32-NEXT: fsd fs2, 480(sp) # 8-byte Folded Spill1014; RV32-NEXT: fsd fs3, 472(sp) # 8-byte Folded Spill1015; RV32-NEXT: fsd fs4, 464(sp) # 8-byte Folded Spill1016; RV32-NEXT: fsd fs5, 456(sp) # 8-byte Folded Spill1017; RV32-NEXT: fsd fs6, 448(sp) # 8-byte Folded Spill1018; RV32-NEXT: fsd fs7, 440(sp) # 8-byte Folded Spill1019; RV32-NEXT: fsd fs8, 432(sp) # 8-byte Folded Spill1020; RV32-NEXT: fsd fs9, 424(sp) # 8-byte Folded Spill1021; RV32-NEXT: fsd fs10, 416(sp) # 8-byte Folded Spill1022; RV32-NEXT: fsd fs11, 408(sp) # 8-byte Folded Spill1023; RV32-NEXT: .cfi_offset ra, -41024; RV32-NEXT: .cfi_offset s0, -81025; RV32-NEXT: .cfi_offset fs0, -161026; RV32-NEXT: .cfi_offset fs1, -241027; RV32-NEXT: .cfi_offset fs2, -321028; RV32-NEXT: .cfi_offset fs3, -401029; RV32-NEXT: .cfi_offset fs4, -481030; RV32-NEXT: .cfi_offset fs5, -561031; RV32-NEXT: .cfi_offset fs6, -641032; RV32-NEXT: .cfi_offset fs7, -721033; RV32-NEXT: .cfi_offset fs8, -801034; RV32-NEXT: .cfi_offset fs9, -881035; RV32-NEXT: .cfi_offset fs10, -961036; RV32-NEXT: .cfi_offset fs11, -1041037; RV32-NEXT: addi s0, sp, 5121038; RV32-NEXT: .cfi_def_cfa s0, 01039; RV32-NEXT: andi sp, sp, -1281040; RV32-NEXT: sw a0, 120(sp)1041; RV32-NEXT: sw a1, 124(sp)1042; RV32-NEXT: fld ft0, 0(s0)1043; RV32-NEXT: fld ft1, 8(s0)1044; RV32-NEXT: fld ft2, 16(s0)1045; RV32-NEXT: fld ft3, 24(s0)1046; RV32-NEXT: fld ft4, 32(s0)1047; RV32-NEXT: fld ft5, 40(s0)1048; RV32-NEXT: fld ft6, 48(s0)1049; RV32-NEXT: fld ft7, 56(s0)1050; RV32-NEXT: fld ft8, 64(s0)1051; RV32-NEXT: fld ft9, 72(s0)1052; RV32-NEXT: fld ft10, 80(s0)1053; RV32-NEXT: fld ft11, 88(s0)1054; RV32-NEXT: fld fs0, 96(s0)1055; RV32-NEXT: fld fs1, 104(s0)1056; RV32-NEXT: fld fs2, 112(s0)1057; RV32-NEXT: fld fs3, 120(s0)1058; RV32-NEXT: fld fs4, 128(s0)1059; RV32-NEXT: fld fs5, 136(s0)1060; RV32-NEXT: fld fs6, 144(s0)1061; RV32-NEXT: fld fs7, 152(s0)1062; RV32-NEXT: addi a0, sp, 1281063; RV32-NEXT: addi a1, sp, 2561064; RV32-NEXT: fld fs8, 120(sp)1065; RV32-NEXT: sw a2, 120(sp)1066; RV32-NEXT: sw a3, 124(sp)1067; RV32-NEXT: fld fs9, 120(sp)1068; RV32-NEXT: sw a4, 120(sp)1069; RV32-NEXT: sw a5, 124(sp)1070; RV32-NEXT: fld fs10, 120(sp)1071; RV32-NEXT: sw a6, 120(sp)1072; RV32-NEXT: sw a7, 124(sp)1073; RV32-NEXT: fld fs11, 120(sp)1074; RV32-NEXT: fsd fs4, 224(sp)1075; RV32-NEXT: fsd fs5, 232(sp)1076; RV32-NEXT: fsd fs6, 240(sp)1077; RV32-NEXT: fsd fs7, 248(sp)1078; RV32-NEXT: fsd fs0, 192(sp)1079; RV32-NEXT: fsd fs1, 200(sp)1080; RV32-NEXT: fsd fs2, 208(sp)1081; RV32-NEXT: fsd fs3, 216(sp)1082; RV32-NEXT: fsd ft8, 160(sp)1083; RV32-NEXT: fsd ft9, 168(sp)1084; RV32-NEXT: fsd ft10, 176(sp)1085; RV32-NEXT: fsd ft11, 184(sp)1086; RV32-NEXT: fsd ft4, 128(sp)1087; RV32-NEXT: fsd ft5, 136(sp)1088; RV32-NEXT: fsd ft6, 144(sp)1089; RV32-NEXT: fsd ft7, 152(sp)1090; RV32-NEXT: fsd ft0, 352(sp)1091; RV32-NEXT: fsd ft1, 360(sp)1092; RV32-NEXT: fsd ft2, 368(sp)1093; RV32-NEXT: fsd ft3, 376(sp)1094; RV32-NEXT: fsd fa4, 288(sp)1095; RV32-NEXT: fsd fa5, 296(sp)1096; RV32-NEXT: fsd fa6, 304(sp)1097; RV32-NEXT: fsd fa7, 312(sp)1098; RV32-NEXT: fsd fa0, 256(sp)1099; RV32-NEXT: fsd fa1, 264(sp)1100; RV32-NEXT: fsd fa2, 272(sp)1101; RV32-NEXT: fsd fa3, 280(sp)1102; RV32-NEXT: fsd fs8, 320(sp)1103; RV32-NEXT: fsd fs9, 328(sp)1104; RV32-NEXT: fsd fs10, 336(sp)1105; RV32-NEXT: fsd fs11, 344(sp)1106; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1107; RV32-NEXT: vle64.v v16, (a0)1108; RV32-NEXT: vle64.v v8, (a1)1109; RV32-NEXT: addi sp, s0, -5121110; RV32-NEXT: .cfi_def_cfa sp, 5121111; RV32-NEXT: lw ra, 508(sp) # 4-byte Folded Reload1112; RV32-NEXT: lw s0, 504(sp) # 4-byte Folded Reload1113; RV32-NEXT: fld fs0, 496(sp) # 8-byte Folded Reload1114; RV32-NEXT: fld fs1, 488(sp) # 8-byte Folded Reload1115; RV32-NEXT: fld fs2, 480(sp) # 8-byte Folded Reload1116; RV32-NEXT: fld fs3, 472(sp) # 8-byte Folded Reload1117; RV32-NEXT: fld fs4, 464(sp) # 8-byte Folded Reload1118; RV32-NEXT: fld fs5, 456(sp) # 8-byte Folded Reload1119; RV32-NEXT: fld fs6, 448(sp) # 8-byte Folded Reload1120; RV32-NEXT: fld fs7, 440(sp) # 8-byte Folded Reload1121; RV32-NEXT: fld fs8, 432(sp) # 8-byte Folded Reload1122; RV32-NEXT: fld fs9, 424(sp) # 8-byte Folded Reload1123; RV32-NEXT: fld fs10, 416(sp) # 8-byte Folded Reload1124; RV32-NEXT: fld fs11, 408(sp) # 8-byte Folded Reload1125; RV32-NEXT: .cfi_restore ra1126; RV32-NEXT: .cfi_restore s01127; RV32-NEXT: .cfi_restore fs01128; RV32-NEXT: .cfi_restore fs11129; RV32-NEXT: .cfi_restore fs21130; RV32-NEXT: .cfi_restore fs31131; RV32-NEXT: .cfi_restore fs41132; RV32-NEXT: .cfi_restore fs51133; RV32-NEXT: .cfi_restore fs61134; RV32-NEXT: .cfi_restore fs71135; RV32-NEXT: .cfi_restore fs81136; RV32-NEXT: .cfi_restore fs91137; RV32-NEXT: .cfi_restore fs101138; RV32-NEXT: .cfi_restore fs111139; RV32-NEXT: addi sp, sp, 5121140; RV32-NEXT: .cfi_def_cfa_offset 01141; RV32-NEXT: ret1142;1143; RV64-LABEL: buildvec_v32f64:1144; RV64: # %bb.0:1145; RV64-NEXT: addi sp, sp, -3841146; RV64-NEXT: .cfi_def_cfa_offset 3841147; RV64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill1148; RV64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill1149; RV64-NEXT: fsd fs0, 360(sp) # 8-byte Folded Spill1150; RV64-NEXT: fsd fs1, 352(sp) # 8-byte Folded Spill1151; RV64-NEXT: fsd fs2, 344(sp) # 8-byte Folded Spill1152; RV64-NEXT: fsd fs3, 336(sp) # 8-byte Folded Spill1153; RV64-NEXT: .cfi_offset ra, -81154; RV64-NEXT: .cfi_offset s0, -161155; RV64-NEXT: .cfi_offset fs0, -241156; RV64-NEXT: .cfi_offset fs1, -321157; RV64-NEXT: .cfi_offset fs2, -401158; RV64-NEXT: .cfi_offset fs3, -481159; RV64-NEXT: addi s0, sp, 3841160; RV64-NEXT: .cfi_def_cfa s0, 01161; RV64-NEXT: andi sp, sp, -1281162; RV64-NEXT: fld ft0, 0(s0)1163; RV64-NEXT: fld ft1, 8(s0)1164; RV64-NEXT: fld ft2, 16(s0)1165; RV64-NEXT: fld ft3, 24(s0)1166; RV64-NEXT: fld ft4, 32(s0)1167; RV64-NEXT: fld ft5, 40(s0)1168; RV64-NEXT: fld ft6, 48(s0)1169; RV64-NEXT: fld ft7, 56(s0)1170; RV64-NEXT: fld ft8, 64(s0)1171; RV64-NEXT: fld ft9, 72(s0)1172; RV64-NEXT: fld ft10, 80(s0)1173; RV64-NEXT: fld ft11, 88(s0)1174; RV64-NEXT: fld fs0, 96(s0)1175; RV64-NEXT: fld fs1, 104(s0)1176; RV64-NEXT: fld fs2, 112(s0)1177; RV64-NEXT: fld fs3, 120(s0)1178; RV64-NEXT: sd a4, 224(sp)1179; RV64-NEXT: sd a5, 232(sp)1180; RV64-NEXT: sd a6, 240(sp)1181; RV64-NEXT: sd a7, 248(sp)1182; RV64-NEXT: sd a0, 192(sp)1183; RV64-NEXT: sd a1, 200(sp)1184; RV64-NEXT: sd a2, 208(sp)1185; RV64-NEXT: sd a3, 216(sp)1186; RV64-NEXT: fsd fa4, 160(sp)1187; RV64-NEXT: fsd fa5, 168(sp)1188; RV64-NEXT: fsd fa6, 176(sp)1189; RV64-NEXT: fsd fa7, 184(sp)1190; RV64-NEXT: fsd fa0, 128(sp)1191; RV64-NEXT: fsd fa1, 136(sp)1192; RV64-NEXT: fsd fa2, 144(sp)1193; RV64-NEXT: fsd fa3, 152(sp)1194; RV64-NEXT: addi a0, sp, 1281195; RV64-NEXT: mv a1, sp1196; RV64-NEXT: fsd fs0, 96(sp)1197; RV64-NEXT: fsd fs1, 104(sp)1198; RV64-NEXT: fsd fs2, 112(sp)1199; RV64-NEXT: fsd fs3, 120(sp)1200; RV64-NEXT: fsd ft8, 64(sp)1201; RV64-NEXT: fsd ft9, 72(sp)1202; RV64-NEXT: fsd ft10, 80(sp)1203; RV64-NEXT: fsd ft11, 88(sp)1204; RV64-NEXT: fsd ft4, 32(sp)1205; RV64-NEXT: fsd ft5, 40(sp)1206; RV64-NEXT: fsd ft6, 48(sp)1207; RV64-NEXT: fsd ft7, 56(sp)1208; RV64-NEXT: fsd ft0, 0(sp)1209; RV64-NEXT: fsd ft1, 8(sp)1210; RV64-NEXT: fsd ft2, 16(sp)1211; RV64-NEXT: fsd ft3, 24(sp)1212; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma1213; RV64-NEXT: vle64.v v8, (a0)1214; RV64-NEXT: vle64.v v16, (a1)1215; RV64-NEXT: addi sp, s0, -3841216; RV64-NEXT: .cfi_def_cfa sp, 3841217; RV64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload1218; RV64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload1219; RV64-NEXT: fld fs0, 360(sp) # 8-byte Folded Reload1220; RV64-NEXT: fld fs1, 352(sp) # 8-byte Folded Reload1221; RV64-NEXT: fld fs2, 344(sp) # 8-byte Folded Reload1222; RV64-NEXT: fld fs3, 336(sp) # 8-byte Folded Reload1223; RV64-NEXT: .cfi_restore ra1224; RV64-NEXT: .cfi_restore s01225; RV64-NEXT: .cfi_restore fs01226; RV64-NEXT: .cfi_restore fs11227; RV64-NEXT: .cfi_restore fs21228; RV64-NEXT: .cfi_restore fs31229; RV64-NEXT: addi sp, sp, 3841230; RV64-NEXT: .cfi_def_cfa_offset 01231; RV64-NEXT: ret1232 %v0 = insertelement <32 x double> poison, double %e0, i64 01233 %v1 = insertelement <32 x double> %v0, double %e1, i64 11234 %v2 = insertelement <32 x double> %v1, double %e2, i64 21235 %v3 = insertelement <32 x double> %v2, double %e3, i64 31236 %v4 = insertelement <32 x double> %v3, double %e4, i64 41237 %v5 = insertelement <32 x double> %v4, double %e5, i64 51238 %v6 = insertelement <32 x double> %v5, double %e6, i64 61239 %v7 = insertelement <32 x double> %v6, double %e7, i64 71240 %v8 = insertelement <32 x double> %v7, double %e8, i64 81241 %v9 = insertelement <32 x double> %v8, double %e9, i64 91242 %v10 = insertelement <32 x double> %v9, double %e10, i64 101243 %v11 = insertelement <32 x double> %v10, double %e11, i64 111244 %v12 = insertelement <32 x double> %v11, double %e12, i64 121245 %v13 = insertelement <32 x double> %v12, double %e13, i64 131246 %v14 = insertelement <32 x double> %v13, double %e14, i64 141247 %v15 = insertelement <32 x double> %v14, double %e15, i64 151248 %v16 = insertelement <32 x double> %v15, double %e16, i64 161249 %v17 = insertelement <32 x double> %v16, double %e17, i64 171250 %v18 = insertelement <32 x double> %v17, double %e18, i64 181251 %v19 = insertelement <32 x double> %v18, double %e19, i64 191252 %v20 = insertelement <32 x double> %v19, double %e20, i64 201253 %v21 = insertelement <32 x double> %v20, double %e21, i64 211254 %v22 = insertelement <32 x double> %v21, double %e22, i64 221255 %v23 = insertelement <32 x double> %v22, double %e23, i64 231256 %v24 = insertelement <32 x double> %v23, double %e24, i64 241257 %v25 = insertelement <32 x double> %v24, double %e25, i64 251258 %v26 = insertelement <32 x double> %v25, double %e26, i64 261259 %v27 = insertelement <32 x double> %v26, double %e27, i64 271260 %v28 = insertelement <32 x double> %v27, double %e28, i64 281261 %v29 = insertelement <32 x double> %v28, double %e29, i64 291262 %v30 = insertelement <32 x double> %v29, double %e30, i64 301263 %v31 = insertelement <32 x double> %v30, double %e31, i64 311264 ret <32 x double> %v311265}1266 1267define <32 x double> @buildvec_v32f64_exact_vlen(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7, double %e8, double %e9, double %e10, double %e11, double %e12, double %e13, double %e14, double %e15, double %e16, double %e17, double %e18, double %e19, double %e20, double %e21, double %e22, double %e23, double %e24, double %e25, double %e26, double %e27, double %e28, double %e29, double %e30, double %e31) vscale_range(2,2) {1268; RV32-LABEL: buildvec_v32f64_exact_vlen:1269; RV32: # %bb.0:1270; RV32-NEXT: addi sp, sp, -961271; RV32-NEXT: .cfi_def_cfa_offset 961272; RV32-NEXT: fsd fs0, 88(sp) # 8-byte Folded Spill1273; RV32-NEXT: fsd fs1, 80(sp) # 8-byte Folded Spill1274; RV32-NEXT: fsd fs2, 72(sp) # 8-byte Folded Spill1275; RV32-NEXT: fsd fs3, 64(sp) # 8-byte Folded Spill1276; RV32-NEXT: fsd fs4, 56(sp) # 8-byte Folded Spill1277; RV32-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill1278; RV32-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill1279; RV32-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill1280; RV32-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill1281; RV32-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill1282; RV32-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill1283; RV32-NEXT: .cfi_offset fs0, -81284; RV32-NEXT: .cfi_offset fs1, -161285; RV32-NEXT: .cfi_offset fs2, -241286; RV32-NEXT: .cfi_offset fs3, -321287; RV32-NEXT: .cfi_offset fs4, -401288; RV32-NEXT: .cfi_offset fs5, -481289; RV32-NEXT: .cfi_offset fs6, -561290; RV32-NEXT: .cfi_offset fs7, -641291; RV32-NEXT: .cfi_offset fs8, -721292; RV32-NEXT: .cfi_offset fs9, -801293; RV32-NEXT: .cfi_offset fs10, -881294; RV32-NEXT: sw a6, 0(sp)1295; RV32-NEXT: sw a7, 4(sp)1296; RV32-NEXT: fld ft0, 248(sp)1297; RV32-NEXT: fld ft1, 240(sp)1298; RV32-NEXT: fld ft2, 232(sp)1299; RV32-NEXT: fld ft3, 224(sp)1300; RV32-NEXT: fld ft6, 216(sp)1301; RV32-NEXT: fld ft8, 208(sp)1302; RV32-NEXT: fld ft10, 200(sp)1303; RV32-NEXT: fld fs1, 192(sp)1304; RV32-NEXT: fld ft11, 184(sp)1305; RV32-NEXT: fld fs4, 176(sp)1306; RV32-NEXT: fld fs2, 168(sp)1307; RV32-NEXT: fld fs5, 160(sp)1308; RV32-NEXT: fld fs3, 136(sp)1309; RV32-NEXT: fld fs6, 128(sp)1310; RV32-NEXT: fld fs7, 152(sp)1311; RV32-NEXT: fld fs8, 144(sp)1312; RV32-NEXT: fld ft4, 120(sp)1313; RV32-NEXT: fld ft5, 112(sp)1314; RV32-NEXT: fld ft7, 104(sp)1315; RV32-NEXT: fld ft9, 96(sp)1316; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma1317; RV32-NEXT: vfmv.v.f v8, fa21318; RV32-NEXT: fld fa2, 0(sp)1319; RV32-NEXT: sw a4, 0(sp)1320; RV32-NEXT: sw a5, 4(sp)1321; RV32-NEXT: fld fs0, 0(sp)1322; RV32-NEXT: sw a2, 0(sp)1323; RV32-NEXT: sw a3, 4(sp)1324; RV32-NEXT: fld fs9, 0(sp)1325; RV32-NEXT: sw a0, 0(sp)1326; RV32-NEXT: sw a1, 4(sp)1327; RV32-NEXT: fld fs10, 0(sp)1328; RV32-NEXT: vfmv.v.f v9, fs81329; RV32-NEXT: vfmv.v.f v10, fs61330; RV32-NEXT: vfmv.v.f v11, fs51331; RV32-NEXT: vfmv.v.f v12, fs41332; RV32-NEXT: vfmv.v.f v13, fs11333; RV32-NEXT: vfslide1down.vf v17, v9, fs71334; RV32-NEXT: vfslide1down.vf v16, v10, fs31335; RV32-NEXT: vfslide1down.vf v18, v11, fs21336; RV32-NEXT: vfmv.v.f v9, fs101337; RV32-NEXT: vfslide1down.vf v19, v12, ft111338; RV32-NEXT: vfslide1down.vf v20, v13, ft101339; RV32-NEXT: vfslide1down.vf v12, v9, fs91340; RV32-NEXT: vfslide1down.vf v9, v8, fa31341; RV32-NEXT: vfmv.v.f v8, ft81342; RV32-NEXT: vfslide1down.vf v21, v8, ft61343; RV32-NEXT: vfmv.v.f v8, fa01344; RV32-NEXT: vfslide1down.vf v8, v8, fa11345; RV32-NEXT: vfmv.v.f v10, ft31346; RV32-NEXT: vfslide1down.vf v22, v10, ft21347; RV32-NEXT: vfmv.v.f v10, fa41348; RV32-NEXT: vfslide1down.vf v10, v10, fa51349; RV32-NEXT: vfmv.v.f v11, fa61350; RV32-NEXT: vfslide1down.vf v11, v11, fa71351; RV32-NEXT: vfmv.v.f v13, fs01352; RV32-NEXT: vfslide1down.vf v13, v13, fa21353; RV32-NEXT: vfmv.v.f v14, ft91354; RV32-NEXT: vfslide1down.vf v14, v14, ft71355; RV32-NEXT: vfmv.v.f v15, ft51356; RV32-NEXT: vfslide1down.vf v15, v15, ft41357; RV32-NEXT: vfmv.v.f v23, ft11358; RV32-NEXT: vfslide1down.vf v23, v23, ft01359; RV32-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload1360; RV32-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload1361; RV32-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload1362; RV32-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload1363; RV32-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload1364; RV32-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload1365; RV32-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload1366; RV32-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload1367; RV32-NEXT: fld fs8, 24(sp) # 8-byte Folded Reload1368; RV32-NEXT: fld fs9, 16(sp) # 8-byte Folded Reload1369; RV32-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload1370; RV32-NEXT: .cfi_restore fs01371; RV32-NEXT: .cfi_restore fs11372; RV32-NEXT: .cfi_restore fs21373; RV32-NEXT: .cfi_restore fs31374; RV32-NEXT: .cfi_restore fs41375; RV32-NEXT: .cfi_restore fs51376; RV32-NEXT: .cfi_restore fs61377; RV32-NEXT: .cfi_restore fs71378; RV32-NEXT: .cfi_restore fs81379; RV32-NEXT: .cfi_restore fs91380; RV32-NEXT: .cfi_restore fs101381; RV32-NEXT: addi sp, sp, 961382; RV32-NEXT: .cfi_def_cfa_offset 01383; RV32-NEXT: ret1384;1385; RV64-LABEL: buildvec_v32f64_exact_vlen:1386; RV64: # %bb.0:1387; RV64-NEXT: addi sp, sp, -641388; RV64-NEXT: .cfi_def_cfa_offset 641389; RV64-NEXT: fsd fs0, 56(sp) # 8-byte Folded Spill1390; RV64-NEXT: fsd fs1, 48(sp) # 8-byte Folded Spill1391; RV64-NEXT: fsd fs2, 40(sp) # 8-byte Folded Spill1392; RV64-NEXT: fsd fs3, 32(sp) # 8-byte Folded Spill1393; RV64-NEXT: fsd fs4, 24(sp) # 8-byte Folded Spill1394; RV64-NEXT: fsd fs5, 16(sp) # 8-byte Folded Spill1395; RV64-NEXT: fsd fs6, 8(sp) # 8-byte Folded Spill1396; RV64-NEXT: fsd fs7, 0(sp) # 8-byte Folded Spill1397; RV64-NEXT: .cfi_offset fs0, -81398; RV64-NEXT: .cfi_offset fs1, -161399; RV64-NEXT: .cfi_offset fs2, -241400; RV64-NEXT: .cfi_offset fs3, -321401; RV64-NEXT: .cfi_offset fs4, -401402; RV64-NEXT: .cfi_offset fs5, -481403; RV64-NEXT: .cfi_offset fs6, -561404; RV64-NEXT: .cfi_offset fs7, -641405; RV64-NEXT: fmv.d.x ft6, a71406; RV64-NEXT: fmv.d.x ft9, a51407; RV64-NEXT: fmv.d.x ft10, a31408; RV64-NEXT: fmv.d.x ft11, a11409; RV64-NEXT: fld ft0, 184(sp)1410; RV64-NEXT: fld ft1, 176(sp)1411; RV64-NEXT: fld ft2, 168(sp)1412; RV64-NEXT: fld ft3, 160(sp)1413; RV64-NEXT: fld ft4, 152(sp)1414; RV64-NEXT: fld ft5, 144(sp)1415; RV64-NEXT: fld ft7, 136(sp)1416; RV64-NEXT: fld ft8, 128(sp)1417; RV64-NEXT: fld fs0, 120(sp)1418; RV64-NEXT: fld fs1, 112(sp)1419; RV64-NEXT: fld fs2, 104(sp)1420; RV64-NEXT: fld fs3, 96(sp)1421; RV64-NEXT: fld fs4, 72(sp)1422; RV64-NEXT: fld fs5, 64(sp)1423; RV64-NEXT: fld fs6, 88(sp)1424; RV64-NEXT: fld fs7, 80(sp)1425; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma1426; RV64-NEXT: vfmv.v.f v8, fa21427; RV64-NEXT: vfmv.v.f v10, fa01428; RV64-NEXT: vfmv.v.f v11, fa41429; RV64-NEXT: vfmv.v.f v12, fa61430; RV64-NEXT: vmv.v.x v13, a01431; RV64-NEXT: vmv.v.x v14, a21432; RV64-NEXT: vfslide1down.vf v9, v8, fa31433; RV64-NEXT: vfslide1down.vf v8, v10, fa11434; RV64-NEXT: vfslide1down.vf v10, v11, fa51435; RV64-NEXT: vfslide1down.vf v11, v12, fa71436; RV64-NEXT: vfmv.v.f v15, fs71437; RV64-NEXT: vfmv.v.f v16, fs51438; RV64-NEXT: vfslide1down.vf v12, v13, ft111439; RV64-NEXT: vfslide1down.vf v13, v14, ft101440; RV64-NEXT: vfslide1down.vf v17, v15, fs61441; RV64-NEXT: vfslide1down.vf v16, v16, fs41442; RV64-NEXT: vmv.v.x v14, a41443; RV64-NEXT: vfslide1down.vf v14, v14, ft91444; RV64-NEXT: vfmv.v.f v15, fs31445; RV64-NEXT: vfslide1down.vf v18, v15, fs21446; RV64-NEXT: vmv.v.x v15, a61447; RV64-NEXT: vfslide1down.vf v15, v15, ft61448; RV64-NEXT: vfmv.v.f v19, fs11449; RV64-NEXT: vfslide1down.vf v19, v19, fs01450; RV64-NEXT: vfmv.v.f v20, ft81451; RV64-NEXT: vfslide1down.vf v20, v20, ft71452; RV64-NEXT: vfmv.v.f v21, ft51453; RV64-NEXT: vfslide1down.vf v21, v21, ft41454; RV64-NEXT: vfmv.v.f v22, ft31455; RV64-NEXT: vfslide1down.vf v22, v22, ft21456; RV64-NEXT: vfmv.v.f v23, ft11457; RV64-NEXT: vfslide1down.vf v23, v23, ft01458; RV64-NEXT: fld fs0, 56(sp) # 8-byte Folded Reload1459; RV64-NEXT: fld fs1, 48(sp) # 8-byte Folded Reload1460; RV64-NEXT: fld fs2, 40(sp) # 8-byte Folded Reload1461; RV64-NEXT: fld fs3, 32(sp) # 8-byte Folded Reload1462; RV64-NEXT: fld fs4, 24(sp) # 8-byte Folded Reload1463; RV64-NEXT: fld fs5, 16(sp) # 8-byte Folded Reload1464; RV64-NEXT: fld fs6, 8(sp) # 8-byte Folded Reload1465; RV64-NEXT: fld fs7, 0(sp) # 8-byte Folded Reload1466; RV64-NEXT: .cfi_restore fs01467; RV64-NEXT: .cfi_restore fs11468; RV64-NEXT: .cfi_restore fs21469; RV64-NEXT: .cfi_restore fs31470; RV64-NEXT: .cfi_restore fs41471; RV64-NEXT: .cfi_restore fs51472; RV64-NEXT: .cfi_restore fs61473; RV64-NEXT: .cfi_restore fs71474; RV64-NEXT: addi sp, sp, 641475; RV64-NEXT: .cfi_def_cfa_offset 01476; RV64-NEXT: ret1477 %v0 = insertelement <32 x double> poison, double %e0, i64 01478 %v1 = insertelement <32 x double> %v0, double %e1, i64 11479 %v2 = insertelement <32 x double> %v1, double %e2, i64 21480 %v3 = insertelement <32 x double> %v2, double %e3, i64 31481 %v4 = insertelement <32 x double> %v3, double %e4, i64 41482 %v5 = insertelement <32 x double> %v4, double %e5, i64 51483 %v6 = insertelement <32 x double> %v5, double %e6, i64 61484 %v7 = insertelement <32 x double> %v6, double %e7, i64 71485 %v8 = insertelement <32 x double> %v7, double %e8, i64 81486 %v9 = insertelement <32 x double> %v8, double %e9, i64 91487 %v10 = insertelement <32 x double> %v9, double %e10, i64 101488 %v11 = insertelement <32 x double> %v10, double %e11, i64 111489 %v12 = insertelement <32 x double> %v11, double %e12, i64 121490 %v13 = insertelement <32 x double> %v12, double %e13, i64 131491 %v14 = insertelement <32 x double> %v13, double %e14, i64 141492 %v15 = insertelement <32 x double> %v14, double %e15, i64 151493 %v16 = insertelement <32 x double> %v15, double %e16, i64 161494 %v17 = insertelement <32 x double> %v16, double %e17, i64 171495 %v18 = insertelement <32 x double> %v17, double %e18, i64 181496 %v19 = insertelement <32 x double> %v18, double %e19, i64 191497 %v20 = insertelement <32 x double> %v19, double %e20, i64 201498 %v21 = insertelement <32 x double> %v20, double %e21, i64 211499 %v22 = insertelement <32 x double> %v21, double %e22, i64 221500 %v23 = insertelement <32 x double> %v22, double %e23, i64 231501 %v24 = insertelement <32 x double> %v23, double %e24, i64 241502 %v25 = insertelement <32 x double> %v24, double %e25, i64 251503 %v26 = insertelement <32 x double> %v25, double %e26, i64 261504 %v27 = insertelement <32 x double> %v26, double %e27, i64 271505 %v28 = insertelement <32 x double> %v27, double %e28, i64 281506 %v29 = insertelement <32 x double> %v28, double %e29, i64 291507 %v30 = insertelement <32 x double> %v29, double %e30, i64 301508 %v31 = insertelement <32 x double> %v30, double %e31, i64 311509 ret <32 x double> %v311510}1511 1512; FIXME: These constants have enough sign bits that we could use vmv.v.x/i and1513; vsext, but we don't support this for FP yet.1514define <2 x float> @signbits() {1515; CHECK-LABEL: signbits:1516; CHECK: # %bb.0: # %entry1517; CHECK-NEXT: lui a0, %hi(.LCPI25_0)1518; CHECK-NEXT: addi a0, a0, %lo(.LCPI25_0)1519; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1520; CHECK-NEXT: vle32.v v8, (a0)1521; CHECK-NEXT: ret1522entry:1523 ret <2 x float> <float 0x36A0000000000000, float 0.000000e+00>1524}1525 1526define <2 x half> @vid_v2f16() {1527; RV32ZVFH-LABEL: vid_v2f16:1528; RV32ZVFH: # %bb.0:1529; RV32ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1530; RV32ZVFH-NEXT: vid.v v81531; RV32ZVFH-NEXT: vfcvt.f.x.v v8, v81532; RV32ZVFH-NEXT: ret1533;1534; RV64ZVFH-LABEL: vid_v2f16:1535; RV64ZVFH: # %bb.0:1536; RV64ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1537; RV64ZVFH-NEXT: vid.v v81538; RV64ZVFH-NEXT: vfcvt.f.x.v v8, v81539; RV64ZVFH-NEXT: ret1540;1541; RV32ZVFHMIN-LABEL: vid_v2f16:1542; RV32ZVFHMIN: # %bb.0:1543; RV32ZVFHMIN-NEXT: lui a0, 2457601544; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma1545; RV32ZVFHMIN-NEXT: vmv.s.x v8, a01546; RV32ZVFHMIN-NEXT: ret1547;1548; RV64ZVFHMIN-LABEL: vid_v2f16:1549; RV64ZVFHMIN: # %bb.0:1550; RV64ZVFHMIN-NEXT: lui a0, 2457601551; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma1552; RV64ZVFHMIN-NEXT: vmv.s.x v8, a01553; RV64ZVFHMIN-NEXT: ret1554 ret <2 x half> <half 0.0, half 1.0>1555}1556 1557define <2 x half> @vid_addend1_v2f16() {1558; RV32ZVFH-LABEL: vid_addend1_v2f16:1559; RV32ZVFH: # %bb.0:1560; RV32ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1561; RV32ZVFH-NEXT: vid.v v81562; RV32ZVFH-NEXT: vadd.vi v8, v8, 11563; RV32ZVFH-NEXT: vfcvt.f.x.v v8, v81564; RV32ZVFH-NEXT: ret1565;1566; RV64ZVFH-LABEL: vid_addend1_v2f16:1567; RV64ZVFH: # %bb.0:1568; RV64ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1569; RV64ZVFH-NEXT: vid.v v81570; RV64ZVFH-NEXT: vadd.vi v8, v8, 11571; RV64ZVFH-NEXT: vfcvt.f.x.v v8, v81572; RV64ZVFH-NEXT: ret1573;1574; RV32ZVFHMIN-LABEL: vid_addend1_v2f16:1575; RV32ZVFHMIN: # %bb.0:1576; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1577; RV32ZVFHMIN-NEXT: vid.v v81578; RV32ZVFHMIN-NEXT: li a0, 151579; RV32ZVFHMIN-NEXT: vsll.vi v8, v8, 101580; RV32ZVFHMIN-NEXT: slli a0, a0, 101581; RV32ZVFHMIN-NEXT: vadd.vx v8, v8, a01582; RV32ZVFHMIN-NEXT: ret1583;1584; RV64ZVFHMIN-LABEL: vid_addend1_v2f16:1585; RV64ZVFHMIN: # %bb.0:1586; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1587; RV64ZVFHMIN-NEXT: vid.v v81588; RV64ZVFHMIN-NEXT: li a0, 151589; RV64ZVFHMIN-NEXT: vsll.vi v8, v8, 101590; RV64ZVFHMIN-NEXT: slli a0, a0, 101591; RV64ZVFHMIN-NEXT: vadd.vx v8, v8, a01592; RV64ZVFHMIN-NEXT: ret1593 ret <2 x half> <half 1.0, half 2.0>1594}1595 1596define <2 x half> @vid_denominator2_v2f16() {1597; RV32ZVFH-LABEL: vid_denominator2_v2f16:1598; RV32ZVFH: # %bb.0:1599; RV32ZVFH-NEXT: lui a0, %hi(.LCPI28_0)1600; RV32ZVFH-NEXT: addi a0, a0, %lo(.LCPI28_0)1601; RV32ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1602; RV32ZVFH-NEXT: vle16.v v8, (a0)1603; RV32ZVFH-NEXT: ret1604;1605; RV64ZVFH-LABEL: vid_denominator2_v2f16:1606; RV64ZVFH: # %bb.0:1607; RV64ZVFH-NEXT: lui a0, %hi(.LCPI28_0)1608; RV64ZVFH-NEXT: addi a0, a0, %lo(.LCPI28_0)1609; RV64ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1610; RV64ZVFH-NEXT: vle16.v v8, (a0)1611; RV64ZVFH-NEXT: ret1612;1613; RV32ZVFHMIN-LABEL: vid_denominator2_v2f16:1614; RV32ZVFHMIN: # %bb.0:1615; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1616; RV32ZVFHMIN-NEXT: vid.v v81617; RV32ZVFHMIN-NEXT: li a0, 71618; RV32ZVFHMIN-NEXT: vsll.vi v8, v8, 101619; RV32ZVFHMIN-NEXT: slli a0, a0, 111620; RV32ZVFHMIN-NEXT: vadd.vx v8, v8, a01621; RV32ZVFHMIN-NEXT: ret1622;1623; RV64ZVFHMIN-LABEL: vid_denominator2_v2f16:1624; RV64ZVFHMIN: # %bb.0:1625; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1626; RV64ZVFHMIN-NEXT: vid.v v81627; RV64ZVFHMIN-NEXT: li a0, 71628; RV64ZVFHMIN-NEXT: vsll.vi v8, v8, 101629; RV64ZVFHMIN-NEXT: slli a0, a0, 111630; RV64ZVFHMIN-NEXT: vadd.vx v8, v8, a01631; RV64ZVFHMIN-NEXT: ret1632 ret <2 x half> <half 0.5, half 1.0>1633}1634 1635define <2 x half> @vid_step2_v2f16() {1636; RV32ZVFH-LABEL: vid_step2_v2f16:1637; RV32ZVFH: # %bb.0:1638; RV32ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1639; RV32ZVFH-NEXT: vid.v v81640; RV32ZVFH-NEXT: vadd.vv v8, v8, v81641; RV32ZVFH-NEXT: vfcvt.f.x.v v8, v81642; RV32ZVFH-NEXT: ret1643;1644; RV64ZVFH-LABEL: vid_step2_v2f16:1645; RV64ZVFH: # %bb.0:1646; RV64ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1647; RV64ZVFH-NEXT: vid.v v81648; RV64ZVFH-NEXT: vadd.vv v8, v8, v81649; RV64ZVFH-NEXT: vfcvt.f.x.v v8, v81650; RV64ZVFH-NEXT: ret1651;1652; RV32ZVFHMIN-LABEL: vid_step2_v2f16:1653; RV32ZVFHMIN: # %bb.0:1654; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1655; RV32ZVFHMIN-NEXT: vid.v v81656; RV32ZVFHMIN-NEXT: vsll.vi v8, v8, 141657; RV32ZVFHMIN-NEXT: ret1658;1659; RV64ZVFHMIN-LABEL: vid_step2_v2f16:1660; RV64ZVFHMIN: # %bb.0:1661; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1662; RV64ZVFHMIN-NEXT: vid.v v81663; RV64ZVFHMIN-NEXT: vsll.vi v8, v8, 141664; RV64ZVFHMIN-NEXT: ret1665 ret <2 x half> <half 0.0, half 2.0>1666}1667 1668define <2 x float> @vid_v2f32() {1669; CHECK-LABEL: vid_v2f32:1670; CHECK: # %bb.0:1671; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1672; CHECK-NEXT: vid.v v81673; CHECK-NEXT: vfcvt.f.x.v v8, v81674; CHECK-NEXT: ret1675 ret <2 x float> <float 0.0, float 1.0>1676}1677 1678define <2 x float> @vid_addend1_v2f32() {1679; CHECK-LABEL: vid_addend1_v2f32:1680; CHECK: # %bb.0:1681; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1682; CHECK-NEXT: vid.v v81683; CHECK-NEXT: vadd.vi v8, v8, 11684; CHECK-NEXT: vfcvt.f.x.v v8, v81685; CHECK-NEXT: ret1686 ret <2 x float> <float 1.0, float 2.0>1687}1688 1689define <2 x float> @vid_denominator2_v2f32() {1690; CHECK-LABEL: vid_denominator2_v2f32:1691; CHECK: # %bb.0:1692; CHECK-NEXT: lui a0, %hi(.LCPI32_0)1693; CHECK-NEXT: addi a0, a0, %lo(.LCPI32_0)1694; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1695; CHECK-NEXT: vle32.v v8, (a0)1696; CHECK-NEXT: ret1697 ret <2 x float> <float 0.5, float 1.0>1698}1699 1700define <2 x float> @vid_step2_v2f32() {1701; CHECK-LABEL: vid_step2_v2f32:1702; CHECK: # %bb.0:1703; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1704; CHECK-NEXT: vid.v v81705; CHECK-NEXT: vadd.vv v8, v8, v81706; CHECK-NEXT: vfcvt.f.x.v v8, v81707; CHECK-NEXT: ret1708 ret <2 x float> <float 0.0, float 2.0>1709}1710 1711define <2 x double> @vid_v2f64() {1712; CHECK-LABEL: vid_v2f64:1713; CHECK: # %bb.0:1714; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma1715; CHECK-NEXT: vid.v v81716; CHECK-NEXT: vfcvt.f.x.v v8, v81717; CHECK-NEXT: ret1718 ret <2 x double> <double 0.0, double 1.0>1719}1720 1721define <2 x double> @vid_addend1_v2f64() {1722; CHECK-LABEL: vid_addend1_v2f64:1723; CHECK: # %bb.0:1724; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma1725; CHECK-NEXT: vid.v v81726; CHECK-NEXT: vadd.vi v8, v8, 11727; CHECK-NEXT: vfcvt.f.x.v v8, v81728; CHECK-NEXT: ret1729 ret <2 x double> <double 1.0, double 2.0>1730}1731 1732define <2 x double> @vid_denominator2_v2f64() {1733; CHECK-LABEL: vid_denominator2_v2f64:1734; CHECK: # %bb.0:1735; CHECK-NEXT: lui a0, %hi(.LCPI36_0)1736; CHECK-NEXT: addi a0, a0, %lo(.LCPI36_0)1737; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma1738; CHECK-NEXT: vle64.v v8, (a0)1739; CHECK-NEXT: ret1740 ret <2 x double> <double 0.5, double 1.0>1741}1742 1743define <2 x double> @vid_step2_v2f64() {1744; CHECK-LABEL: vid_step2_v2f64:1745; CHECK: # %bb.0:1746; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma1747; CHECK-NEXT: vid.v v81748; CHECK-NEXT: vadd.vv v8, v8, v81749; CHECK-NEXT: vfcvt.f.x.v v8, v81750; CHECK-NEXT: ret1751 ret <2 x double> <double 0.0, double 2.0>1752}1753 1754 1755define <8 x float> @buildvec_v8f32_zvl256(float %e0, float %e1, float %e2, float %e3, float %e4, float %e5, float %e6, float %e7) vscale_range(4, 128) {1756; CHECK-LABEL: buildvec_v8f32_zvl256:1757; CHECK: # %bb.0:1758; CHECK-NEXT: vsetivli zero, 8, e32, m1, ta, mu1759; CHECK-NEXT: vfmv.v.f v8, fa41760; CHECK-NEXT: vfmv.v.f v9, fa01761; CHECK-NEXT: vmv.v.i v0, 151762; CHECK-NEXT: vfslide1down.vf v8, v8, fa51763; CHECK-NEXT: vfslide1down.vf v9, v9, fa11764; CHECK-NEXT: vfslide1down.vf v8, v8, fa61765; CHECK-NEXT: vfslide1down.vf v9, v9, fa21766; CHECK-NEXT: vfslide1down.vf v8, v8, fa71767; CHECK-NEXT: vfslide1down.vf v9, v9, fa31768; CHECK-NEXT: vslidedown.vi v8, v9, 4, v0.t1769; CHECK-NEXT: ret1770 %v0 = insertelement <8 x float> poison, float %e0, i64 01771 %v1 = insertelement <8 x float> %v0, float %e1, i64 11772 %v2 = insertelement <8 x float> %v1, float %e2, i64 21773 %v3 = insertelement <8 x float> %v2, float %e3, i64 31774 %v4 = insertelement <8 x float> %v3, float %e4, i64 41775 %v5 = insertelement <8 x float> %v4, float %e5, i64 51776 %v6 = insertelement <8 x float> %v5, float %e6, i64 61777 %v7 = insertelement <8 x float> %v6, float %e7, i64 71778 ret <8 x float> %v71779}1780 1781 1782define <8 x double> @buildvec_v8f64_zvl256(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7) vscale_range(4, 128) {1783; CHECK-LABEL: buildvec_v8f64_zvl256:1784; CHECK: # %bb.0:1785; CHECK-NEXT: vsetivli zero, 8, e64, m2, ta, ma1786; CHECK-NEXT: vfmv.v.f v8, fa01787; CHECK-NEXT: vfslide1down.vf v8, v8, fa11788; CHECK-NEXT: vfslide1down.vf v8, v8, fa21789; CHECK-NEXT: vfslide1down.vf v8, v8, fa31790; CHECK-NEXT: vfslide1down.vf v8, v8, fa41791; CHECK-NEXT: vfslide1down.vf v8, v8, fa51792; CHECK-NEXT: vfslide1down.vf v8, v8, fa61793; CHECK-NEXT: vfslide1down.vf v8, v8, fa71794; CHECK-NEXT: ret1795 %v0 = insertelement <8 x double> poison, double %e0, i64 01796 %v1 = insertelement <8 x double> %v0, double %e1, i64 11797 %v2 = insertelement <8 x double> %v1, double %e2, i64 21798 %v3 = insertelement <8 x double> %v2, double %e3, i64 31799 %v4 = insertelement <8 x double> %v3, double %e4, i64 41800 %v5 = insertelement <8 x double> %v4, double %e5, i64 51801 %v6 = insertelement <8 x double> %v5, double %e6, i64 61802 %v7 = insertelement <8 x double> %v6, double %e7, i64 71803 ret <8 x double> %v71804}1805 1806define <8 x double> @buildvec_v8f64_zvl512(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7) vscale_range(8, 128) {1807; CHECK-LABEL: buildvec_v8f64_zvl512:1808; CHECK: # %bb.0:1809; CHECK-NEXT: vsetivli zero, 8, e64, m1, ta, mu1810; CHECK-NEXT: vfmv.v.f v8, fa41811; CHECK-NEXT: vfmv.v.f v9, fa01812; CHECK-NEXT: vmv.v.i v0, 151813; CHECK-NEXT: vfslide1down.vf v8, v8, fa51814; CHECK-NEXT: vfslide1down.vf v9, v9, fa11815; CHECK-NEXT: vfslide1down.vf v8, v8, fa61816; CHECK-NEXT: vfslide1down.vf v9, v9, fa21817; CHECK-NEXT: vfslide1down.vf v8, v8, fa71818; CHECK-NEXT: vfslide1down.vf v9, v9, fa31819; CHECK-NEXT: vslidedown.vi v8, v9, 4, v0.t1820; CHECK-NEXT: ret1821 %v0 = insertelement <8 x double> poison, double %e0, i64 01822 %v1 = insertelement <8 x double> %v0, double %e1, i64 11823 %v2 = insertelement <8 x double> %v1, double %e2, i64 21824 %v3 = insertelement <8 x double> %v2, double %e3, i64 31825 %v4 = insertelement <8 x double> %v3, double %e4, i64 41826 %v5 = insertelement <8 x double> %v4, double %e5, i64 51827 %v6 = insertelement <8 x double> %v5, double %e6, i64 61828 %v7 = insertelement <8 x double> %v6, double %e7, i64 71829 ret <8 x double> %v71830}1831 1832define <4 x float> @buildvec_vfredusum_slideup(float %start, <8 x float> %arg1, <8 x float> %arg2, <8 x float> %arg3, <8 x float> %arg4) nounwind {1833; CHECK-LABEL: buildvec_vfredusum_slideup:1834; CHECK: # %bb.0:1835; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1836; CHECK-NEXT: vfmv.s.f v16, fa01837; CHECK-NEXT: vfredusum.vs v8, v8, v161838; CHECK-NEXT: vfredusum.vs v9, v10, v161839; CHECK-NEXT: vfredusum.vs v10, v12, v161840; CHECK-NEXT: vfredusum.vs v11, v14, v161841; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma1842; CHECK-NEXT: vslideup.vi v10, v11, 11843; CHECK-NEXT: vslideup.vi v9, v10, 11844; CHECK-NEXT: vslideup.vi v8, v9, 11845; CHECK-NEXT: ret1846 %247 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg1)1847 %248 = insertelement <4 x float> poison, float %247, i64 01848 %250 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg2)1849 %251 = insertelement <4 x float> %248, float %250, i64 11850 %252 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg3)1851 %253 = insertelement <4 x float> %251, float %252, i64 21852 %254 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg4)1853 %255 = insertelement <4 x float> %253, float %254, i64 31854 ret <4 x float> %2551855}1856 1857define <8 x float> @buildvec_vfredusum_slideup_leading_undef(float %start, <8 x float> %arg1, <8 x float> %arg2, <8 x float> %arg3, <8 x float> %arg4) nounwind {1858; CHECK-LABEL: buildvec_vfredusum_slideup_leading_undef:1859; CHECK: # %bb.0:1860; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1861; CHECK-NEXT: vfmv.s.f v17, fa01862; CHECK-NEXT: vfredusum.vs v16, v8, v171863; CHECK-NEXT: vfredusum.vs v8, v10, v171864; CHECK-NEXT: vfredusum.vs v10, v12, v171865; CHECK-NEXT: vfredusum.vs v12, v14, v171866; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, ma1867; CHECK-NEXT: vslideup.vi v10, v12, 11868; CHECK-NEXT: vslideup.vi v8, v10, 11869; CHECK-NEXT: vslideup.vi v16, v8, 11870; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma1871; CHECK-NEXT: vslideup.vi v8, v16, 41872; CHECK-NEXT: ret1873 %252 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg1)1874 %253 = insertelement <8 x float> poison, float %252, i64 41875 %254 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg2)1876 %255 = insertelement <8 x float> %253, float %254, i64 51877 %256 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg3)1878 %257 = insertelement <8 x float> %255, float %256, i64 61879 %258 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg4)1880 %259 = insertelement <8 x float> %257, float %258, i64 71881 ret <8 x float> %2591882}1883 1884define <8 x float> @buildvec_vfredusum_slideup_trailing_undef(float %start, <8 x float> %arg1, <8 x float> %arg2, <8 x float> %arg3, <8 x float> %arg4) nounwind {1885; CHECK-LABEL: buildvec_vfredusum_slideup_trailing_undef:1886; CHECK: # %bb.0:1887; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1888; CHECK-NEXT: vfmv.s.f v16, fa01889; CHECK-NEXT: vfredusum.vs v8, v8, v161890; CHECK-NEXT: vfredusum.vs v10, v10, v161891; CHECK-NEXT: vfredusum.vs v12, v12, v161892; CHECK-NEXT: vfredusum.vs v14, v14, v161893; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, ma1894; CHECK-NEXT: vslideup.vi v12, v14, 11895; CHECK-NEXT: vslideup.vi v10, v12, 11896; CHECK-NEXT: vslideup.vi v8, v10, 11897; CHECK-NEXT: ret1898 %252 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg1)1899 %253 = insertelement <8 x float> poison, float %252, i64 01900 %254 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg2)1901 %255 = insertelement <8 x float> %253, float %254, i64 11902 %256 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg3)1903 %257 = insertelement <8 x float> %255, float %256, i64 21904 %258 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg4)1905 %259 = insertelement <8 x float> %257, float %258, i64 31906 ret <8 x float> %2591907}1908 1909; Negative test case checking if we generate slideup only when all build_vec operands are extraction from the first vector element.1910define <8 x float> @buildvec_vfredusum_slideup_not_extract_first(float %start, <8 x float> %arg1, <8 x float> %arg2, <8 x float> %arg3, <8 x float> %arg4) nounwind {1911; CHECK-LABEL: buildvec_vfredusum_slideup_not_extract_first:1912; CHECK: # %bb.0:1913; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1914; CHECK-NEXT: vfmv.s.f v10, fa01915; CHECK-NEXT: vfredusum.vs v8, v8, v101916; CHECK-NEXT: vfredusum.vs v9, v12, v101917; CHECK-NEXT: vfredusum.vs v10, v14, v101918; CHECK-NEXT: vfmv.f.s fa5, v91919; CHECK-NEXT: vfmv.f.s fa4, v101920; CHECK-NEXT: vrgather.vi v10, v8, 01921; CHECK-NEXT: vfslide1down.vf v8, v10, fa01922; CHECK-NEXT: vfslide1down.vf v8, v8, fa51923; CHECK-NEXT: vfslide1down.vf v8, v8, fa41924; CHECK-NEXT: vslidedown.vi v8, v8, 41925; CHECK-NEXT: ret1926 %252 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg1)1927 %253 = insertelement <8 x float> poison, float %252, i64 01928 %255 = insertelement <8 x float> %253, float %start, i64 11929 %256 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg3)1930 %257 = insertelement <8 x float> %255, float %256, i64 21931 %258 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg4)1932 %259 = insertelement <8 x float> %257, float %258, i64 31933 ret <8 x float> %2591934}1935 1936define <8 x float> @buildvec_vfredusum_slideup_mid_undef(float %start, <8 x float> %arg1, <8 x float> %arg2, <8 x float> %arg3, <8 x float> %arg4) nounwind {1937; CHECK-LABEL: buildvec_vfredusum_slideup_mid_undef:1938; CHECK: # %bb.0:1939; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1940; CHECK-NEXT: vfmv.s.f v16, fa01941; CHECK-NEXT: vfredusum.vs v8, v8, v161942; CHECK-NEXT: vfredusum.vs v10, v10, v161943; CHECK-NEXT: vfredusum.vs v12, v12, v161944; CHECK-NEXT: vfredusum.vs v14, v14, v161945; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, ma1946; CHECK-NEXT: vslideup.vi v12, v14, 11947; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma1948; CHECK-NEXT: vslideup.vi v14, v12, 41949; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, ma1950; CHECK-NEXT: vslideup.vi v10, v14, 11951; CHECK-NEXT: vslideup.vi v8, v10, 11952; CHECK-NEXT: ret1953 %252 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg1)1954 %253 = insertelement <8 x float> poison, float %252, i64 01955 %254 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg2)1956 %255 = insertelement <8 x float> %253, float %254, i64 11957 %256 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg3)1958 %257 = insertelement <8 x float> %255, float %256, i64 61959 %258 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg4)1960 %259 = insertelement <8 x float> %257, float %258, i64 71961 ret <8 x float> %2591962}1963 1964define <4 x float> @buildvec_vfredosum_slideup(float %start, <8 x float> %arg1, <8 x float> %arg2, <8 x float> %arg3, <8 x float> %arg4) nounwind {1965; CHECK-LABEL: buildvec_vfredosum_slideup:1966; CHECK: # %bb.0:1967; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1968; CHECK-NEXT: vfmv.s.f v16, fa01969; CHECK-NEXT: vfredosum.vs v8, v8, v161970; CHECK-NEXT: vfredosum.vs v9, v10, v161971; CHECK-NEXT: vfredosum.vs v10, v12, v161972; CHECK-NEXT: vfredosum.vs v11, v14, v161973; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma1974; CHECK-NEXT: vslideup.vi v10, v11, 11975; CHECK-NEXT: vslideup.vi v9, v10, 11976; CHECK-NEXT: vslideup.vi v8, v9, 11977; CHECK-NEXT: ret1978 %247 = tail call float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg1)1979 %248 = insertelement <4 x float> poison, float %247, i64 01980 %250 = tail call float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg2)1981 %251 = insertelement <4 x float> %248, float %250, i64 11982 %252 = tail call float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg3)1983 %253 = insertelement <4 x float> %251, float %252, i64 21984 %254 = tail call float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg4)1985 %255 = insertelement <4 x float> %253, float %254, i64 31986 ret <4 x float> %2551987}1988