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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV323; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-ZVFH4; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-ZVFHMIN,RV64-ZVFHMIN-NOZFHMIN5; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfhmin,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-ZVFHMIN,RV64_ZVFHMIN-ZFHMIN6 7define void @splat_v8f16(ptr %x, half %y) {8; CHECK-RV32-LABEL: splat_v8f16:9; CHECK-RV32: # %bb.0:10; CHECK-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma11; CHECK-RV32-NEXT: vfmv.v.f v8, fa012; CHECK-RV32-NEXT: vse16.v v8, (a0)13; CHECK-RV32-NEXT: ret14;15; RV64-ZVFH-LABEL: splat_v8f16:16; RV64-ZVFH: # %bb.0:17; RV64-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma18; RV64-ZVFH-NEXT: vfmv.v.f v8, fa019; RV64-ZVFH-NEXT: vse16.v v8, (a0)20; RV64-ZVFH-NEXT: ret21;22; RV64-ZVFHMIN-NOZFHMIN-LABEL: splat_v8f16:23; RV64-ZVFHMIN-NOZFHMIN: # %bb.0:24; RV64-ZVFHMIN-NOZFHMIN-NEXT: fmv.x.w a1, fa025; RV64-ZVFHMIN-NOZFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma26; RV64-ZVFHMIN-NOZFHMIN-NEXT: vmv.v.x v8, a127; RV64-ZVFHMIN-NOZFHMIN-NEXT: vse16.v v8, (a0)28; RV64-ZVFHMIN-NOZFHMIN-NEXT: ret29;30; RV64_ZVFHMIN-ZFHMIN-LABEL: splat_v8f16:31; RV64_ZVFHMIN-ZFHMIN: # %bb.0:32; RV64_ZVFHMIN-ZFHMIN-NEXT: fmv.x.h a1, fa033; RV64_ZVFHMIN-ZFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma34; RV64_ZVFHMIN-ZFHMIN-NEXT: vmv.v.x v8, a135; RV64_ZVFHMIN-ZFHMIN-NEXT: vse16.v v8, (a0)36; RV64_ZVFHMIN-ZFHMIN-NEXT: ret37 %a = insertelement <8 x half> poison, half %y, i32 038 %b = shufflevector <8 x half> %a, <8 x half> poison, <8 x i32> zeroinitializer39 store <8 x half> %b, ptr %x40 ret void41}42 43define void @splat_v4f32(ptr %x, float %y) {44; CHECK-LABEL: splat_v4f32:45; CHECK: # %bb.0:46; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma47; CHECK-NEXT: vfmv.v.f v8, fa048; CHECK-NEXT: vse32.v v8, (a0)49; CHECK-NEXT: ret50 %a = insertelement <4 x float> poison, float %y, i32 051 %b = shufflevector <4 x float> %a, <4 x float> poison, <4 x i32> zeroinitializer52 store <4 x float> %b, ptr %x53 ret void54}55 56define void @splat_v2f64(ptr %x, double %y) {57; CHECK-LABEL: splat_v2f64:58; CHECK: # %bb.0:59; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma60; CHECK-NEXT: vfmv.v.f v8, fa061; CHECK-NEXT: vse64.v v8, (a0)62; CHECK-NEXT: ret63 %a = insertelement <2 x double> poison, double %y, i32 064 %b = shufflevector <2 x double> %a, <2 x double> poison, <2 x i32> zeroinitializer65 store <2 x double> %b, ptr %x66 ret void67}68 69define void @splat_16f16(ptr %x, half %y) {70; CHECK-RV32-LABEL: splat_16f16:71; CHECK-RV32: # %bb.0:72; CHECK-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma73; CHECK-RV32-NEXT: vfmv.v.f v8, fa074; CHECK-RV32-NEXT: vse16.v v8, (a0)75; CHECK-RV32-NEXT: ret76;77; RV64-ZVFH-LABEL: splat_16f16:78; RV64-ZVFH: # %bb.0:79; RV64-ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma80; RV64-ZVFH-NEXT: vfmv.v.f v8, fa081; RV64-ZVFH-NEXT: vse16.v v8, (a0)82; RV64-ZVFH-NEXT: ret83;84; RV64-ZVFHMIN-NOZFHMIN-LABEL: splat_16f16:85; RV64-ZVFHMIN-NOZFHMIN: # %bb.0:86; RV64-ZVFHMIN-NOZFHMIN-NEXT: fmv.x.w a1, fa087; RV64-ZVFHMIN-NOZFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma88; RV64-ZVFHMIN-NOZFHMIN-NEXT: vmv.v.x v8, a189; RV64-ZVFHMIN-NOZFHMIN-NEXT: vse16.v v8, (a0)90; RV64-ZVFHMIN-NOZFHMIN-NEXT: ret91;92; RV64_ZVFHMIN-ZFHMIN-LABEL: splat_16f16:93; RV64_ZVFHMIN-ZFHMIN: # %bb.0:94; RV64_ZVFHMIN-ZFHMIN-NEXT: fmv.x.h a1, fa095; RV64_ZVFHMIN-ZFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma96; RV64_ZVFHMIN-ZFHMIN-NEXT: vmv.v.x v8, a197; RV64_ZVFHMIN-ZFHMIN-NEXT: vse16.v v8, (a0)98; RV64_ZVFHMIN-ZFHMIN-NEXT: ret99 %a = insertelement <16 x half> poison, half %y, i32 0100 %b = shufflevector <16 x half> %a, <16 x half> poison, <16 x i32> zeroinitializer101 store <16 x half> %b, ptr %x102 ret void103}104 105define void @splat_v8f32(ptr %x, float %y) {106; CHECK-LABEL: splat_v8f32:107; CHECK: # %bb.0:108; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma109; CHECK-NEXT: vfmv.v.f v8, fa0110; CHECK-NEXT: vse32.v v8, (a0)111; CHECK-NEXT: ret112 %a = insertelement <8 x float> poison, float %y, i32 0113 %b = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> zeroinitializer114 store <8 x float> %b, ptr %x115 ret void116}117 118define void @splat_v4f64(ptr %x, double %y) {119; CHECK-LABEL: splat_v4f64:120; CHECK: # %bb.0:121; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma122; CHECK-NEXT: vfmv.v.f v8, fa0123; CHECK-NEXT: vse64.v v8, (a0)124; CHECK-NEXT: ret125 %a = insertelement <4 x double> poison, double %y, i32 0126 %b = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> zeroinitializer127 store <4 x double> %b, ptr %x128 ret void129}130 131define void @splat_64f16(ptr %x, half %y) {132; CHECK-RV32-LABEL: splat_64f16:133; CHECK-RV32: # %bb.0:134; CHECK-RV32-NEXT: li a1, 64135; CHECK-RV32-NEXT: vsetvli zero, a1, e16, m8, ta, ma136; CHECK-RV32-NEXT: vfmv.v.f v8, fa0137; CHECK-RV32-NEXT: vse16.v v8, (a0)138; CHECK-RV32-NEXT: ret139;140; RV64-ZVFH-LABEL: splat_64f16:141; RV64-ZVFH: # %bb.0:142; RV64-ZVFH-NEXT: li a1, 64143; RV64-ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma144; RV64-ZVFH-NEXT: vfmv.v.f v8, fa0145; RV64-ZVFH-NEXT: vse16.v v8, (a0)146; RV64-ZVFH-NEXT: ret147;148; RV64-ZVFHMIN-NOZFHMIN-LABEL: splat_64f16:149; RV64-ZVFHMIN-NOZFHMIN: # %bb.0:150; RV64-ZVFHMIN-NOZFHMIN-NEXT: fmv.x.w a1, fa0151; RV64-ZVFHMIN-NOZFHMIN-NEXT: li a2, 64152; RV64-ZVFHMIN-NOZFHMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma153; RV64-ZVFHMIN-NOZFHMIN-NEXT: vmv.v.x v8, a1154; RV64-ZVFHMIN-NOZFHMIN-NEXT: vse16.v v8, (a0)155; RV64-ZVFHMIN-NOZFHMIN-NEXT: ret156;157; RV64_ZVFHMIN-ZFHMIN-LABEL: splat_64f16:158; RV64_ZVFHMIN-ZFHMIN: # %bb.0:159; RV64_ZVFHMIN-ZFHMIN-NEXT: fmv.x.h a1, fa0160; RV64_ZVFHMIN-ZFHMIN-NEXT: li a2, 64161; RV64_ZVFHMIN-ZFHMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma162; RV64_ZVFHMIN-ZFHMIN-NEXT: vmv.v.x v8, a1163; RV64_ZVFHMIN-ZFHMIN-NEXT: vse16.v v8, (a0)164; RV64_ZVFHMIN-ZFHMIN-NEXT: ret165 %a = insertelement <64 x half> poison, half %y, i32 0166 %b = shufflevector <64 x half> %a, <64 x half> poison, <64 x i32> zeroinitializer167 store <64 x half> %b, ptr %x168 ret void169}170 171define void @splat_zero_v8f16(ptr %x) {172; CHECK-LABEL: splat_zero_v8f16:173; CHECK: # %bb.0:174; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma175; CHECK-NEXT: vmv.v.i v8, 0176; CHECK-NEXT: vse16.v v8, (a0)177; CHECK-NEXT: ret178 store <8 x half> splat (half 0.0), ptr %x179 ret void180}181 182define void @splat_zero_v4f32(ptr %x) {183; CHECK-LABEL: splat_zero_v4f32:184; CHECK: # %bb.0:185; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma186; CHECK-NEXT: vmv.v.i v8, 0187; CHECK-NEXT: vse32.v v8, (a0)188; CHECK-NEXT: ret189 store <4 x float> splat (float 0.0), ptr %x190 ret void191}192 193define void @splat_zero_v2f64(ptr %x) {194; CHECK-LABEL: splat_zero_v2f64:195; CHECK: # %bb.0:196; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma197; CHECK-NEXT: vmv.v.i v8, 0198; CHECK-NEXT: vse64.v v8, (a0)199; CHECK-NEXT: ret200 store <2 x double> splat (double 0.0), ptr %x201 ret void202}203 204define void @splat_zero_16f16(ptr %x) {205; CHECK-LABEL: splat_zero_16f16:206; CHECK: # %bb.0:207; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma208; CHECK-NEXT: vmv.v.i v8, 0209; CHECK-NEXT: vse16.v v8, (a0)210; CHECK-NEXT: ret211 store <16 x half> splat (half 0.0), ptr %x212 ret void213}214 215define void @splat_zero_v8f32(ptr %x) {216; CHECK-LABEL: splat_zero_v8f32:217; CHECK: # %bb.0:218; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma219; CHECK-NEXT: vmv.v.i v8, 0220; CHECK-NEXT: vse32.v v8, (a0)221; CHECK-NEXT: ret222 store <8 x float> splat (float 0.0), ptr %x223 ret void224}225 226define void @splat_zero_v4f64(ptr %x) {227; CHECK-LABEL: splat_zero_v4f64:228; CHECK: # %bb.0:229; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma230; CHECK-NEXT: vmv.v.i v8, 0231; CHECK-NEXT: vse64.v v8, (a0)232; CHECK-NEXT: ret233 store <4 x double> splat (double 0.0), ptr %x234 ret void235}236 237define void @splat_negzero_v8f16(ptr %x) {238; CHECK-LABEL: splat_negzero_v8f16:239; CHECK: # %bb.0:240; CHECK-NEXT: lui a1, 1048568241; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma242; CHECK-NEXT: vmv.v.x v8, a1243; CHECK-NEXT: vse16.v v8, (a0)244; CHECK-NEXT: ret245 store <8 x half> splat (half -0.0), ptr %x246 ret void247}248 249define void @splat_negzero_v4f32(ptr %x) {250; CHECK-LABEL: splat_negzero_v4f32:251; CHECK: # %bb.0:252; CHECK-NEXT: lui a1, 524288253; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma254; CHECK-NEXT: vmv.v.x v8, a1255; CHECK-NEXT: vse32.v v8, (a0)256; CHECK-NEXT: ret257 store <4 x float> splat (float -0.0), ptr %x258 ret void259}260 261define void @splat_negzero_v2f64(ptr %x) {262; CHECK-RV32-LABEL: splat_negzero_v2f64:263; CHECK-RV32: # %bb.0:264; CHECK-RV32-NEXT: fcvt.d.w fa5, zero265; CHECK-RV32-NEXT: fneg.d fa5, fa5266; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma267; CHECK-RV32-NEXT: vfmv.v.f v8, fa5268; CHECK-RV32-NEXT: vse64.v v8, (a0)269; CHECK-RV32-NEXT: ret270;271; CHECK-RV64-LABEL: splat_negzero_v2f64:272; CHECK-RV64: # %bb.0:273; CHECK-RV64-NEXT: li a1, -1274; CHECK-RV64-NEXT: slli a1, a1, 63275; CHECK-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma276; CHECK-RV64-NEXT: vmv.v.x v8, a1277; CHECK-RV64-NEXT: vse64.v v8, (a0)278; CHECK-RV64-NEXT: ret279 store <2 x double> splat (double -0.0), ptr %x280 ret void281}282 283define void @splat_negzero_16f16(ptr %x) {284; CHECK-LABEL: splat_negzero_16f16:285; CHECK: # %bb.0:286; CHECK-NEXT: lui a1, 1048568287; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma288; CHECK-NEXT: vmv.v.x v8, a1289; CHECK-NEXT: vse16.v v8, (a0)290; CHECK-NEXT: ret291 store <16 x half> splat (half -0.0), ptr %x292 ret void293}294 295define void @splat_negzero_v8f32(ptr %x) {296; CHECK-LABEL: splat_negzero_v8f32:297; CHECK: # %bb.0:298; CHECK-NEXT: lui a1, 524288299; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma300; CHECK-NEXT: vmv.v.x v8, a1301; CHECK-NEXT: vse32.v v8, (a0)302; CHECK-NEXT: ret303 store <8 x float> splat (float -0.0), ptr %x304 ret void305}306 307define void @splat_negzero_v4f64(ptr %x) {308; CHECK-RV32-LABEL: splat_negzero_v4f64:309; CHECK-RV32: # %bb.0:310; CHECK-RV32-NEXT: fcvt.d.w fa5, zero311; CHECK-RV32-NEXT: fneg.d fa5, fa5312; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma313; CHECK-RV32-NEXT: vfmv.v.f v8, fa5314; CHECK-RV32-NEXT: vse64.v v8, (a0)315; CHECK-RV32-NEXT: ret316;317; CHECK-RV64-LABEL: splat_negzero_v4f64:318; CHECK-RV64: # %bb.0:319; CHECK-RV64-NEXT: li a1, -1320; CHECK-RV64-NEXT: slli a1, a1, 63321; CHECK-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma322; CHECK-RV64-NEXT: vmv.v.x v8, a1323; CHECK-RV64-NEXT: vse64.v v8, (a0)324; CHECK-RV64-NEXT: ret325 store <4 x double> splat (double -0.0), ptr %x326 ret void327}328;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:329; RV64-ZVFHMIN: {{.*}}330