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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV32ZVFH3; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV64ZVFH4; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV32ZVFHMIN5; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV64ZVFHMIN6 7 8define void @fadd_v8bf16(ptr %x, ptr %y) {9; CHECK-LABEL: fadd_v8bf16:10; CHECK: # %bb.0:11; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma12; CHECK-NEXT: vle16.v v10, (a1)13; CHECK-NEXT: vle16.v v12, (a0)14; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v1015; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v1216; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma17; CHECK-NEXT: vfadd.vv v8, v10, v818; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma19; CHECK-NEXT: vfncvtbf16.f.f.w v10, v820; CHECK-NEXT: vse16.v v10, (a0)21; CHECK-NEXT: ret22 %a = load <8 x bfloat>, ptr %x23 %b = load <8 x bfloat>, ptr %y24 %c = fadd <8 x bfloat> %a, %b25 store <8 x bfloat> %c, ptr %x26 ret void27}28 29define void @fadd_v6bf16(ptr %x, ptr %y) {30; CHECK-LABEL: fadd_v6bf16:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma33; CHECK-NEXT: vle16.v v10, (a1)34; CHECK-NEXT: vle16.v v12, (a0)35; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v1036; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v1237; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma38; CHECK-NEXT: vfadd.vv v8, v10, v839; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma40; CHECK-NEXT: vfncvtbf16.f.f.w v10, v841; CHECK-NEXT: vse16.v v10, (a0)42; CHECK-NEXT: ret43 %a = load <6 x bfloat>, ptr %x44 %b = load <6 x bfloat>, ptr %y45 %c = fadd <6 x bfloat> %a, %b46 store <6 x bfloat> %c, ptr %x47 ret void48}49 50define void @fadd_v8f16(ptr %x, ptr %y) {51; ZVFH-LABEL: fadd_v8f16:52; ZVFH: # %bb.0:53; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma54; ZVFH-NEXT: vle16.v v8, (a0)55; ZVFH-NEXT: vle16.v v9, (a1)56; ZVFH-NEXT: vfadd.vv v8, v8, v957; ZVFH-NEXT: vse16.v v8, (a0)58; ZVFH-NEXT: ret59;60; ZVFHMIN-LABEL: fadd_v8f16:61; ZVFHMIN: # %bb.0:62; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma63; ZVFHMIN-NEXT: vle16.v v10, (a1)64; ZVFHMIN-NEXT: vle16.v v12, (a0)65; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v1066; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v1267; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma68; ZVFHMIN-NEXT: vfadd.vv v8, v10, v869; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma70; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v871; ZVFHMIN-NEXT: vse16.v v10, (a0)72; ZVFHMIN-NEXT: ret73 %a = load <8 x half>, ptr %x74 %b = load <8 x half>, ptr %y75 %c = fadd <8 x half> %a, %b76 store <8 x half> %c, ptr %x77 ret void78}79 80define void @fadd_v6f16(ptr %x, ptr %y) {81; ZVFH-LABEL: fadd_v6f16:82; ZVFH: # %bb.0:83; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma84; ZVFH-NEXT: vle16.v v8, (a0)85; ZVFH-NEXT: vle16.v v9, (a1)86; ZVFH-NEXT: vfadd.vv v8, v8, v987; ZVFH-NEXT: vse16.v v8, (a0)88; ZVFH-NEXT: ret89;90; ZVFHMIN-LABEL: fadd_v6f16:91; ZVFHMIN: # %bb.0:92; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma93; ZVFHMIN-NEXT: vle16.v v10, (a1)94; ZVFHMIN-NEXT: vle16.v v12, (a0)95; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v1096; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v1297; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma98; ZVFHMIN-NEXT: vfadd.vv v8, v10, v899; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma100; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8101; ZVFHMIN-NEXT: vse16.v v10, (a0)102; ZVFHMIN-NEXT: ret103 %a = load <6 x half>, ptr %x104 %b = load <6 x half>, ptr %y105 %c = fadd <6 x half> %a, %b106 store <6 x half> %c, ptr %x107 ret void108}109 110define void @fadd_v4f32(ptr %x, ptr %y) {111; CHECK-LABEL: fadd_v4f32:112; CHECK: # %bb.0:113; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma114; CHECK-NEXT: vle32.v v8, (a0)115; CHECK-NEXT: vle32.v v9, (a1)116; CHECK-NEXT: vfadd.vv v8, v8, v9117; CHECK-NEXT: vse32.v v8, (a0)118; CHECK-NEXT: ret119 %a = load <4 x float>, ptr %x120 %b = load <4 x float>, ptr %y121 %c = fadd <4 x float> %a, %b122 store <4 x float> %c, ptr %x123 ret void124}125 126define void @fadd_v2f64(ptr %x, ptr %y) {127; CHECK-LABEL: fadd_v2f64:128; CHECK: # %bb.0:129; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma130; CHECK-NEXT: vle64.v v8, (a0)131; CHECK-NEXT: vle64.v v9, (a1)132; CHECK-NEXT: vfadd.vv v8, v8, v9133; CHECK-NEXT: vse64.v v8, (a0)134; CHECK-NEXT: ret135 %a = load <2 x double>, ptr %x136 %b = load <2 x double>, ptr %y137 %c = fadd <2 x double> %a, %b138 store <2 x double> %c, ptr %x139 ret void140}141 142define void @fsub_v8bf16(ptr %x, ptr %y) {143; CHECK-LABEL: fsub_v8bf16:144; CHECK: # %bb.0:145; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma146; CHECK-NEXT: vle16.v v10, (a1)147; CHECK-NEXT: vle16.v v12, (a0)148; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10149; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12150; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma151; CHECK-NEXT: vfsub.vv v8, v10, v8152; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma153; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8154; CHECK-NEXT: vse16.v v10, (a0)155; CHECK-NEXT: ret156 %a = load <8 x bfloat>, ptr %x157 %b = load <8 x bfloat>, ptr %y158 %c = fsub <8 x bfloat> %a, %b159 store <8 x bfloat> %c, ptr %x160 ret void161}162 163define void @fsub_v6bf16(ptr %x, ptr %y) {164; CHECK-LABEL: fsub_v6bf16:165; CHECK: # %bb.0:166; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma167; CHECK-NEXT: vle16.v v10, (a1)168; CHECK-NEXT: vle16.v v12, (a0)169; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10170; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12171; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma172; CHECK-NEXT: vfsub.vv v8, v10, v8173; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma174; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8175; CHECK-NEXT: vse16.v v10, (a0)176; CHECK-NEXT: ret177 %a = load <6 x bfloat>, ptr %x178 %b = load <6 x bfloat>, ptr %y179 %c = fsub <6 x bfloat> %a, %b180 store <6 x bfloat> %c, ptr %x181 ret void182}183 184define void @fsub_v8f16(ptr %x, ptr %y) {185; ZVFH-LABEL: fsub_v8f16:186; ZVFH: # %bb.0:187; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma188; ZVFH-NEXT: vle16.v v8, (a0)189; ZVFH-NEXT: vle16.v v9, (a1)190; ZVFH-NEXT: vfsub.vv v8, v8, v9191; ZVFH-NEXT: vse16.v v8, (a0)192; ZVFH-NEXT: ret193;194; ZVFHMIN-LABEL: fsub_v8f16:195; ZVFHMIN: # %bb.0:196; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma197; ZVFHMIN-NEXT: vle16.v v10, (a1)198; ZVFHMIN-NEXT: vle16.v v12, (a0)199; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10200; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12201; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma202; ZVFHMIN-NEXT: vfsub.vv v8, v10, v8203; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma204; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8205; ZVFHMIN-NEXT: vse16.v v10, (a0)206; ZVFHMIN-NEXT: ret207 %a = load <8 x half>, ptr %x208 %b = load <8 x half>, ptr %y209 %c = fsub <8 x half> %a, %b210 store <8 x half> %c, ptr %x211 ret void212}213 214define void @fsub_v6f16(ptr %x, ptr %y) {215; ZVFH-LABEL: fsub_v6f16:216; ZVFH: # %bb.0:217; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma218; ZVFH-NEXT: vle16.v v8, (a0)219; ZVFH-NEXT: vle16.v v9, (a1)220; ZVFH-NEXT: vfsub.vv v8, v8, v9221; ZVFH-NEXT: vse16.v v8, (a0)222; ZVFH-NEXT: ret223;224; ZVFHMIN-LABEL: fsub_v6f16:225; ZVFHMIN: # %bb.0:226; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma227; ZVFHMIN-NEXT: vle16.v v10, (a1)228; ZVFHMIN-NEXT: vle16.v v12, (a0)229; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10230; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12231; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma232; ZVFHMIN-NEXT: vfsub.vv v8, v10, v8233; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma234; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8235; ZVFHMIN-NEXT: vse16.v v10, (a0)236; ZVFHMIN-NEXT: ret237 %a = load <6 x half>, ptr %x238 %b = load <6 x half>, ptr %y239 %c = fsub <6 x half> %a, %b240 store <6 x half> %c, ptr %x241 ret void242}243 244define void @fsub_v4f32(ptr %x, ptr %y) {245; CHECK-LABEL: fsub_v4f32:246; CHECK: # %bb.0:247; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma248; CHECK-NEXT: vle32.v v8, (a0)249; CHECK-NEXT: vle32.v v9, (a1)250; CHECK-NEXT: vfsub.vv v8, v8, v9251; CHECK-NEXT: vse32.v v8, (a0)252; CHECK-NEXT: ret253 %a = load <4 x float>, ptr %x254 %b = load <4 x float>, ptr %y255 %c = fsub <4 x float> %a, %b256 store <4 x float> %c, ptr %x257 ret void258}259 260define void @fsub_v2f64(ptr %x, ptr %y) {261; CHECK-LABEL: fsub_v2f64:262; CHECK: # %bb.0:263; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma264; CHECK-NEXT: vle64.v v8, (a0)265; CHECK-NEXT: vle64.v v9, (a1)266; CHECK-NEXT: vfsub.vv v8, v8, v9267; CHECK-NEXT: vse64.v v8, (a0)268; CHECK-NEXT: ret269 %a = load <2 x double>, ptr %x270 %b = load <2 x double>, ptr %y271 %c = fsub <2 x double> %a, %b272 store <2 x double> %c, ptr %x273 ret void274}275 276define void @fmul_v8bf16(ptr %x, ptr %y) {277; CHECK-LABEL: fmul_v8bf16:278; CHECK: # %bb.0:279; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma280; CHECK-NEXT: vle16.v v10, (a1)281; CHECK-NEXT: vle16.v v12, (a0)282; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10283; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12284; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma285; CHECK-NEXT: vfmul.vv v8, v10, v8286; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma287; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8288; CHECK-NEXT: vse16.v v10, (a0)289; CHECK-NEXT: ret290 %a = load <8 x bfloat>, ptr %x291 %b = load <8 x bfloat>, ptr %y292 %c = fmul <8 x bfloat> %a, %b293 store <8 x bfloat> %c, ptr %x294 ret void295}296 297define void @fmul_v6bf16(ptr %x, ptr %y) {298; CHECK-LABEL: fmul_v6bf16:299; CHECK: # %bb.0:300; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma301; CHECK-NEXT: vle16.v v10, (a1)302; CHECK-NEXT: vle16.v v12, (a0)303; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10304; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12305; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma306; CHECK-NEXT: vfmul.vv v8, v10, v8307; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma308; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8309; CHECK-NEXT: vse16.v v10, (a0)310; CHECK-NEXT: ret311 %a = load <6 x bfloat>, ptr %x312 %b = load <6 x bfloat>, ptr %y313 %c = fmul <6 x bfloat> %a, %b314 store <6 x bfloat> %c, ptr %x315 ret void316}317 318define void @fmul_v8f16(ptr %x, ptr %y) {319; ZVFH-LABEL: fmul_v8f16:320; ZVFH: # %bb.0:321; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma322; ZVFH-NEXT: vle16.v v8, (a0)323; ZVFH-NEXT: vle16.v v9, (a1)324; ZVFH-NEXT: vfmul.vv v8, v8, v9325; ZVFH-NEXT: vse16.v v8, (a0)326; ZVFH-NEXT: ret327;328; ZVFHMIN-LABEL: fmul_v8f16:329; ZVFHMIN: # %bb.0:330; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma331; ZVFHMIN-NEXT: vle16.v v10, (a1)332; ZVFHMIN-NEXT: vle16.v v12, (a0)333; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10334; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12335; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma336; ZVFHMIN-NEXT: vfmul.vv v8, v10, v8337; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma338; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8339; ZVFHMIN-NEXT: vse16.v v10, (a0)340; ZVFHMIN-NEXT: ret341 %a = load <8 x half>, ptr %x342 %b = load <8 x half>, ptr %y343 %c = fmul <8 x half> %a, %b344 store <8 x half> %c, ptr %x345 ret void346}347 348define void @fmul_v6f16(ptr %x, ptr %y) {349; ZVFH-LABEL: fmul_v6f16:350; ZVFH: # %bb.0:351; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma352; ZVFH-NEXT: vle16.v v8, (a0)353; ZVFH-NEXT: vle16.v v9, (a1)354; ZVFH-NEXT: vfmul.vv v8, v8, v9355; ZVFH-NEXT: vse16.v v8, (a0)356; ZVFH-NEXT: ret357;358; ZVFHMIN-LABEL: fmul_v6f16:359; ZVFHMIN: # %bb.0:360; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma361; ZVFHMIN-NEXT: vle16.v v10, (a1)362; ZVFHMIN-NEXT: vle16.v v12, (a0)363; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10364; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12365; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma366; ZVFHMIN-NEXT: vfmul.vv v8, v10, v8367; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma368; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8369; ZVFHMIN-NEXT: vse16.v v10, (a0)370; ZVFHMIN-NEXT: ret371 %a = load <6 x half>, ptr %x372 %b = load <6 x half>, ptr %y373 %c = fmul <6 x half> %a, %b374 store <6 x half> %c, ptr %x375 ret void376}377 378define void @fmul_v4f32(ptr %x, ptr %y) {379; CHECK-LABEL: fmul_v4f32:380; CHECK: # %bb.0:381; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma382; CHECK-NEXT: vle32.v v8, (a0)383; CHECK-NEXT: vle32.v v9, (a1)384; CHECK-NEXT: vfmul.vv v8, v8, v9385; CHECK-NEXT: vse32.v v8, (a0)386; CHECK-NEXT: ret387 %a = load <4 x float>, ptr %x388 %b = load <4 x float>, ptr %y389 %c = fmul <4 x float> %a, %b390 store <4 x float> %c, ptr %x391 ret void392}393 394define void @fmul_v2f64(ptr %x, ptr %y) {395; CHECK-LABEL: fmul_v2f64:396; CHECK: # %bb.0:397; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma398; CHECK-NEXT: vle64.v v8, (a0)399; CHECK-NEXT: vle64.v v9, (a1)400; CHECK-NEXT: vfmul.vv v8, v8, v9401; CHECK-NEXT: vse64.v v8, (a0)402; CHECK-NEXT: ret403 %a = load <2 x double>, ptr %x404 %b = load <2 x double>, ptr %y405 %c = fmul <2 x double> %a, %b406 store <2 x double> %c, ptr %x407 ret void408}409 410define void @fdiv_v8bf16(ptr %x, ptr %y) {411; CHECK-LABEL: fdiv_v8bf16:412; CHECK: # %bb.0:413; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma414; CHECK-NEXT: vle16.v v10, (a1)415; CHECK-NEXT: vle16.v v12, (a0)416; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10417; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12418; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma419; CHECK-NEXT: vfdiv.vv v8, v10, v8420; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma421; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8422; CHECK-NEXT: vse16.v v10, (a0)423; CHECK-NEXT: ret424 %a = load <8 x bfloat>, ptr %x425 %b = load <8 x bfloat>, ptr %y426 %c = fdiv <8 x bfloat> %a, %b427 store <8 x bfloat> %c, ptr %x428 ret void429}430 431define void @fdiv_v6bf16(ptr %x, ptr %y) {432; CHECK-LABEL: fdiv_v6bf16:433; CHECK: # %bb.0:434; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma435; CHECK-NEXT: vle16.v v10, (a1)436; CHECK-NEXT: vle16.v v12, (a0)437; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10438; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12439; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma440; CHECK-NEXT: vfdiv.vv v8, v10, v8441; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma442; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8443; CHECK-NEXT: vse16.v v10, (a0)444; CHECK-NEXT: ret445 %a = load <6 x bfloat>, ptr %x446 %b = load <6 x bfloat>, ptr %y447 %c = fdiv <6 x bfloat> %a, %b448 store <6 x bfloat> %c, ptr %x449 ret void450}451 452define void @fdiv_v8f16(ptr %x, ptr %y) {453; ZVFH-LABEL: fdiv_v8f16:454; ZVFH: # %bb.0:455; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma456; ZVFH-NEXT: vle16.v v8, (a0)457; ZVFH-NEXT: vle16.v v9, (a1)458; ZVFH-NEXT: vfdiv.vv v8, v8, v9459; ZVFH-NEXT: vse16.v v8, (a0)460; ZVFH-NEXT: ret461;462; ZVFHMIN-LABEL: fdiv_v8f16:463; ZVFHMIN: # %bb.0:464; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma465; ZVFHMIN-NEXT: vle16.v v10, (a1)466; ZVFHMIN-NEXT: vle16.v v12, (a0)467; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10468; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12469; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma470; ZVFHMIN-NEXT: vfdiv.vv v8, v10, v8471; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma472; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8473; ZVFHMIN-NEXT: vse16.v v10, (a0)474; ZVFHMIN-NEXT: ret475 %a = load <8 x half>, ptr %x476 %b = load <8 x half>, ptr %y477 %c = fdiv <8 x half> %a, %b478 store <8 x half> %c, ptr %x479 ret void480}481 482define void @fdiv_v6f16(ptr %x, ptr %y) {483; ZVFH-LABEL: fdiv_v6f16:484; ZVFH: # %bb.0:485; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma486; ZVFH-NEXT: vle16.v v8, (a0)487; ZVFH-NEXT: vle16.v v9, (a1)488; ZVFH-NEXT: vfdiv.vv v8, v8, v9489; ZVFH-NEXT: vse16.v v8, (a0)490; ZVFH-NEXT: ret491;492; ZVFHMIN-LABEL: fdiv_v6f16:493; ZVFHMIN: # %bb.0:494; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma495; ZVFHMIN-NEXT: vle16.v v10, (a1)496; ZVFHMIN-NEXT: vle16.v v12, (a0)497; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10498; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12499; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma500; ZVFHMIN-NEXT: vfdiv.vv v8, v10, v8501; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma502; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8503; ZVFHMIN-NEXT: vse16.v v10, (a0)504; ZVFHMIN-NEXT: ret505 %a = load <6 x half>, ptr %x506 %b = load <6 x half>, ptr %y507 %c = fdiv <6 x half> %a, %b508 store <6 x half> %c, ptr %x509 ret void510}511 512define void @fdiv_v4f32(ptr %x, ptr %y) {513; CHECK-LABEL: fdiv_v4f32:514; CHECK: # %bb.0:515; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma516; CHECK-NEXT: vle32.v v8, (a0)517; CHECK-NEXT: vle32.v v9, (a1)518; CHECK-NEXT: vfdiv.vv v8, v8, v9519; CHECK-NEXT: vse32.v v8, (a0)520; CHECK-NEXT: ret521 %a = load <4 x float>, ptr %x522 %b = load <4 x float>, ptr %y523 %c = fdiv <4 x float> %a, %b524 store <4 x float> %c, ptr %x525 ret void526}527 528define void @fdiv_v2f64(ptr %x, ptr %y) {529; CHECK-LABEL: fdiv_v2f64:530; CHECK: # %bb.0:531; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma532; CHECK-NEXT: vle64.v v8, (a0)533; CHECK-NEXT: vle64.v v9, (a1)534; CHECK-NEXT: vfdiv.vv v8, v8, v9535; CHECK-NEXT: vse64.v v8, (a0)536; CHECK-NEXT: ret537 %a = load <2 x double>, ptr %x538 %b = load <2 x double>, ptr %y539 %c = fdiv <2 x double> %a, %b540 store <2 x double> %c, ptr %x541 ret void542}543 544define void @fneg_v8bf16(ptr %x) {545; CHECK-LABEL: fneg_v8bf16:546; CHECK: # %bb.0:547; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma548; CHECK-NEXT: vle16.v v8, (a0)549; CHECK-NEXT: lui a1, 8550; CHECK-NEXT: vxor.vx v8, v8, a1551; CHECK-NEXT: vse16.v v8, (a0)552; CHECK-NEXT: ret553 %a = load <8 x bfloat>, ptr %x554 %b = fneg <8 x bfloat> %a555 store <8 x bfloat> %b, ptr %x556 ret void557}558 559define void @fneg_v6bf16(ptr %x) {560; CHECK-LABEL: fneg_v6bf16:561; CHECK: # %bb.0:562; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma563; CHECK-NEXT: vle16.v v8, (a0)564; CHECK-NEXT: lui a1, 8565; CHECK-NEXT: vxor.vx v8, v8, a1566; CHECK-NEXT: vse16.v v8, (a0)567; CHECK-NEXT: ret568 %a = load <6 x bfloat>, ptr %x569 %b = fneg <6 x bfloat> %a570 store <6 x bfloat> %b, ptr %x571 ret void572}573 574define void @fneg_v8f16(ptr %x) {575; ZVFH-LABEL: fneg_v8f16:576; ZVFH: # %bb.0:577; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma578; ZVFH-NEXT: vle16.v v8, (a0)579; ZVFH-NEXT: vfneg.v v8, v8580; ZVFH-NEXT: vse16.v v8, (a0)581; ZVFH-NEXT: ret582;583; ZVFHMIN-LABEL: fneg_v8f16:584; ZVFHMIN: # %bb.0:585; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma586; ZVFHMIN-NEXT: vle16.v v8, (a0)587; ZVFHMIN-NEXT: lui a1, 8588; ZVFHMIN-NEXT: vxor.vx v8, v8, a1589; ZVFHMIN-NEXT: vse16.v v8, (a0)590; ZVFHMIN-NEXT: ret591 %a = load <8 x half>, ptr %x592 %b = fneg <8 x half> %a593 store <8 x half> %b, ptr %x594 ret void595}596 597define void @fneg_v6f16(ptr %x) {598; ZVFH-LABEL: fneg_v6f16:599; ZVFH: # %bb.0:600; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma601; ZVFH-NEXT: vle16.v v8, (a0)602; ZVFH-NEXT: vfneg.v v8, v8603; ZVFH-NEXT: vse16.v v8, (a0)604; ZVFH-NEXT: ret605;606; ZVFHMIN-LABEL: fneg_v6f16:607; ZVFHMIN: # %bb.0:608; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma609; ZVFHMIN-NEXT: vle16.v v8, (a0)610; ZVFHMIN-NEXT: lui a1, 8611; ZVFHMIN-NEXT: vxor.vx v8, v8, a1612; ZVFHMIN-NEXT: vse16.v v8, (a0)613; ZVFHMIN-NEXT: ret614 %a = load <6 x half>, ptr %x615 %b = fneg <6 x half> %a616 store <6 x half> %b, ptr %x617 ret void618}619 620define void @fneg_v4f32(ptr %x) {621; CHECK-LABEL: fneg_v4f32:622; CHECK: # %bb.0:623; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma624; CHECK-NEXT: vle32.v v8, (a0)625; CHECK-NEXT: vfneg.v v8, v8626; CHECK-NEXT: vse32.v v8, (a0)627; CHECK-NEXT: ret628 %a = load <4 x float>, ptr %x629 %b = fneg <4 x float> %a630 store <4 x float> %b, ptr %x631 ret void632}633 634define void @fneg_v2f64(ptr %x) {635; CHECK-LABEL: fneg_v2f64:636; CHECK: # %bb.0:637; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma638; CHECK-NEXT: vle64.v v8, (a0)639; CHECK-NEXT: vfneg.v v8, v8640; CHECK-NEXT: vse64.v v8, (a0)641; CHECK-NEXT: ret642 %a = load <2 x double>, ptr %x643 %b = fneg <2 x double> %a644 store <2 x double> %b, ptr %x645 ret void646}647 648define void @fabs_v8bf16(ptr %x) {649; CHECK-LABEL: fabs_v8bf16:650; CHECK: # %bb.0:651; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma652; CHECK-NEXT: vle16.v v8, (a0)653; CHECK-NEXT: lui a1, 8654; CHECK-NEXT: addi a1, a1, -1655; CHECK-NEXT: vand.vx v8, v8, a1656; CHECK-NEXT: vse16.v v8, (a0)657; CHECK-NEXT: ret658 %a = load <8 x bfloat>, ptr %x659 %b = call <8 x bfloat> @llvm.fabs.v8bf16(<8 x bfloat> %a)660 store <8 x bfloat> %b, ptr %x661 ret void662}663 664define void @fabs_v6bf16(ptr %x) {665; CHECK-LABEL: fabs_v6bf16:666; CHECK: # %bb.0:667; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma668; CHECK-NEXT: vle16.v v8, (a0)669; CHECK-NEXT: lui a1, 8670; CHECK-NEXT: addi a1, a1, -1671; CHECK-NEXT: vand.vx v8, v8, a1672; CHECK-NEXT: vse16.v v8, (a0)673; CHECK-NEXT: ret674 %a = load <6 x bfloat>, ptr %x675 %b = call <6 x bfloat> @llvm.fabs.v6bf16(<6 x bfloat> %a)676 store <6 x bfloat> %b, ptr %x677 ret void678}679 680define void @fabs_v8f16(ptr %x) {681; ZVFH-LABEL: fabs_v8f16:682; ZVFH: # %bb.0:683; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma684; ZVFH-NEXT: vle16.v v8, (a0)685; ZVFH-NEXT: vfabs.v v8, v8686; ZVFH-NEXT: vse16.v v8, (a0)687; ZVFH-NEXT: ret688;689; ZVFHMIN-LABEL: fabs_v8f16:690; ZVFHMIN: # %bb.0:691; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma692; ZVFHMIN-NEXT: vle16.v v8, (a0)693; ZVFHMIN-NEXT: lui a1, 8694; ZVFHMIN-NEXT: addi a1, a1, -1695; ZVFHMIN-NEXT: vand.vx v8, v8, a1696; ZVFHMIN-NEXT: vse16.v v8, (a0)697; ZVFHMIN-NEXT: ret698 %a = load <8 x half>, ptr %x699 %b = call <8 x half> @llvm.fabs.v8f16(<8 x half> %a)700 store <8 x half> %b, ptr %x701 ret void702}703 704define void @fabs_v6f16(ptr %x) {705; ZVFH-LABEL: fabs_v6f16:706; ZVFH: # %bb.0:707; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma708; ZVFH-NEXT: vle16.v v8, (a0)709; ZVFH-NEXT: vfabs.v v8, v8710; ZVFH-NEXT: vse16.v v8, (a0)711; ZVFH-NEXT: ret712;713; ZVFHMIN-LABEL: fabs_v6f16:714; ZVFHMIN: # %bb.0:715; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma716; ZVFHMIN-NEXT: vle16.v v8, (a0)717; ZVFHMIN-NEXT: lui a1, 8718; ZVFHMIN-NEXT: addi a1, a1, -1719; ZVFHMIN-NEXT: vand.vx v8, v8, a1720; ZVFHMIN-NEXT: vse16.v v8, (a0)721; ZVFHMIN-NEXT: ret722 %a = load <6 x half>, ptr %x723 %b = call <6 x half> @llvm.fabs.v6f16(<6 x half> %a)724 store <6 x half> %b, ptr %x725 ret void726}727 728define void @fabs_v4f32(ptr %x) {729; CHECK-LABEL: fabs_v4f32:730; CHECK: # %bb.0:731; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma732; CHECK-NEXT: vle32.v v8, (a0)733; CHECK-NEXT: vfabs.v v8, v8734; CHECK-NEXT: vse32.v v8, (a0)735; CHECK-NEXT: ret736 %a = load <4 x float>, ptr %x737 %b = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)738 store <4 x float> %b, ptr %x739 ret void740}741 742define void @fabs_v2f64(ptr %x) {743; CHECK-LABEL: fabs_v2f64:744; CHECK: # %bb.0:745; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma746; CHECK-NEXT: vle64.v v8, (a0)747; CHECK-NEXT: vfabs.v v8, v8748; CHECK-NEXT: vse64.v v8, (a0)749; CHECK-NEXT: ret750 %a = load <2 x double>, ptr %x751 %b = call <2 x double> @llvm.fabs.v2f64(<2 x double> %a)752 store <2 x double> %b, ptr %x753 ret void754}755 756define void @copysign_v8bf16(ptr %x, ptr %y) {757; CHECK-LABEL: copysign_v8bf16:758; CHECK: # %bb.0:759; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma760; CHECK-NEXT: vle16.v v8, (a1)761; CHECK-NEXT: vle16.v v9, (a0)762; CHECK-NEXT: lui a1, 8763; CHECK-NEXT: vand.vx v8, v8, a1764; CHECK-NEXT: addi a1, a1, -1765; CHECK-NEXT: vand.vx v9, v9, a1766; CHECK-NEXT: vor.vv v8, v9, v8767; CHECK-NEXT: vse16.v v8, (a0)768; CHECK-NEXT: ret769 %a = load <8 x bfloat>, ptr %x770 %b = load <8 x bfloat>, ptr %y771 %c = call <8 x bfloat> @llvm.copysign.v8bf16(<8 x bfloat> %a, <8 x bfloat> %b)772 store <8 x bfloat> %c, ptr %x773 ret void774}775 776define void @copysign_v6bf16(ptr %x, ptr %y) {777; CHECK-LABEL: copysign_v6bf16:778; CHECK: # %bb.0:779; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma780; CHECK-NEXT: vle16.v v8, (a1)781; CHECK-NEXT: vle16.v v9, (a0)782; CHECK-NEXT: lui a1, 8783; CHECK-NEXT: vand.vx v8, v8, a1784; CHECK-NEXT: addi a1, a1, -1785; CHECK-NEXT: vand.vx v9, v9, a1786; CHECK-NEXT: vor.vv v8, v9, v8787; CHECK-NEXT: vse16.v v8, (a0)788; CHECK-NEXT: ret789 %a = load <6 x bfloat>, ptr %x790 %b = load <6 x bfloat>, ptr %y791 %c = call <6 x bfloat> @llvm.copysign.v6bf16(<6 x bfloat> %a, <6 x bfloat> %b)792 store <6 x bfloat> %c, ptr %x793 ret void794}795 796define void @copysign_v8f16(ptr %x, ptr %y) {797; ZVFH-LABEL: copysign_v8f16:798; ZVFH: # %bb.0:799; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma800; ZVFH-NEXT: vle16.v v8, (a0)801; ZVFH-NEXT: vle16.v v9, (a1)802; ZVFH-NEXT: vfsgnj.vv v8, v8, v9803; ZVFH-NEXT: vse16.v v8, (a0)804; ZVFH-NEXT: ret805;806; ZVFHMIN-LABEL: copysign_v8f16:807; ZVFHMIN: # %bb.0:808; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma809; ZVFHMIN-NEXT: vle16.v v8, (a1)810; ZVFHMIN-NEXT: vle16.v v9, (a0)811; ZVFHMIN-NEXT: lui a1, 8812; ZVFHMIN-NEXT: vand.vx v8, v8, a1813; ZVFHMIN-NEXT: addi a1, a1, -1814; ZVFHMIN-NEXT: vand.vx v9, v9, a1815; ZVFHMIN-NEXT: vor.vv v8, v9, v8816; ZVFHMIN-NEXT: vse16.v v8, (a0)817; ZVFHMIN-NEXT: ret818 %a = load <8 x half>, ptr %x819 %b = load <8 x half>, ptr %y820 %c = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %b)821 store <8 x half> %c, ptr %x822 ret void823}824 825define void @copysign_v6f16(ptr %x, ptr %y) {826; ZVFH-LABEL: copysign_v6f16:827; ZVFH: # %bb.0:828; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma829; ZVFH-NEXT: vle16.v v8, (a0)830; ZVFH-NEXT: vle16.v v9, (a1)831; ZVFH-NEXT: vfsgnj.vv v8, v8, v9832; ZVFH-NEXT: vse16.v v8, (a0)833; ZVFH-NEXT: ret834;835; ZVFHMIN-LABEL: copysign_v6f16:836; ZVFHMIN: # %bb.0:837; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma838; ZVFHMIN-NEXT: vle16.v v8, (a1)839; ZVFHMIN-NEXT: vle16.v v9, (a0)840; ZVFHMIN-NEXT: lui a1, 8841; ZVFHMIN-NEXT: vand.vx v8, v8, a1842; ZVFHMIN-NEXT: addi a1, a1, -1843; ZVFHMIN-NEXT: vand.vx v9, v9, a1844; ZVFHMIN-NEXT: vor.vv v8, v9, v8845; ZVFHMIN-NEXT: vse16.v v8, (a0)846; ZVFHMIN-NEXT: ret847 %a = load <6 x half>, ptr %x848 %b = load <6 x half>, ptr %y849 %c = call <6 x half> @llvm.copysign.v6f16(<6 x half> %a, <6 x half> %b)850 store <6 x half> %c, ptr %x851 ret void852}853 854define void @copysign_v4f32(ptr %x, ptr %y) {855; CHECK-LABEL: copysign_v4f32:856; CHECK: # %bb.0:857; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma858; CHECK-NEXT: vle32.v v8, (a0)859; CHECK-NEXT: vle32.v v9, (a1)860; CHECK-NEXT: vfsgnj.vv v8, v8, v9861; CHECK-NEXT: vse32.v v8, (a0)862; CHECK-NEXT: ret863 %a = load <4 x float>, ptr %x864 %b = load <4 x float>, ptr %y865 %c = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b)866 store <4 x float> %c, ptr %x867 ret void868}869 870define void @copysign_v2f64(ptr %x, ptr %y) {871; CHECK-LABEL: copysign_v2f64:872; CHECK: # %bb.0:873; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma874; CHECK-NEXT: vle64.v v8, (a0)875; CHECK-NEXT: vle64.v v9, (a1)876; CHECK-NEXT: vfsgnj.vv v8, v8, v9877; CHECK-NEXT: vse64.v v8, (a0)878; CHECK-NEXT: ret879 %a = load <2 x double>, ptr %x880 %b = load <2 x double>, ptr %y881 %c = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b)882 store <2 x double> %c, ptr %x883 ret void884}885 886define void @copysign_vf_v8bf16(ptr %x, bfloat %y) {887; CHECK-LABEL: copysign_vf_v8bf16:888; CHECK: # %bb.0:889; CHECK-NEXT: fmv.x.w a1, fa0890; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma891; CHECK-NEXT: vle16.v v8, (a0)892; CHECK-NEXT: lui a2, 8893; CHECK-NEXT: vmv.v.x v9, a1894; CHECK-NEXT: addi a1, a2, -1895; CHECK-NEXT: vand.vx v8, v8, a1896; CHECK-NEXT: vand.vx v9, v9, a2897; CHECK-NEXT: vor.vv v8, v8, v9898; CHECK-NEXT: vse16.v v8, (a0)899; CHECK-NEXT: ret900 %a = load <8 x bfloat>, ptr %x901 %b = insertelement <8 x bfloat> poison, bfloat %y, i32 0902 %c = shufflevector <8 x bfloat> %b, <8 x bfloat> poison, <8 x i32> zeroinitializer903 %d = call <8 x bfloat> @llvm.copysign.v8bf16(<8 x bfloat> %a, <8 x bfloat> %c)904 store <8 x bfloat> %d, ptr %x905 ret void906}907 908define void @copysign_vf_v6bf16(ptr %x, bfloat %y) {909; CHECK-LABEL: copysign_vf_v6bf16:910; CHECK: # %bb.0:911; CHECK-NEXT: fmv.x.w a1, fa0912; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma913; CHECK-NEXT: vle16.v v8, (a0)914; CHECK-NEXT: lui a2, 8915; CHECK-NEXT: vmv.v.x v9, a1916; CHECK-NEXT: addi a1, a2, -1917; CHECK-NEXT: vand.vx v8, v8, a1918; CHECK-NEXT: vand.vx v9, v9, a2919; CHECK-NEXT: vor.vv v8, v8, v9920; CHECK-NEXT: vse16.v v8, (a0)921; CHECK-NEXT: ret922 %a = load <6 x bfloat>, ptr %x923 %b = insertelement <6 x bfloat> poison, bfloat %y, i32 0924 %c = shufflevector <6 x bfloat> %b, <6 x bfloat> poison, <6 x i32> zeroinitializer925 %d = call <6 x bfloat> @llvm.copysign.v6bf16(<6 x bfloat> %a, <6 x bfloat> %c)926 store <6 x bfloat> %d, ptr %x927 ret void928}929 930define void @copysign_vf_v8f16(ptr %x, half %y) {931; ZVFH-LABEL: copysign_vf_v8f16:932; ZVFH: # %bb.0:933; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma934; ZVFH-NEXT: vle16.v v8, (a0)935; ZVFH-NEXT: vfsgnj.vf v8, v8, fa0936; ZVFH-NEXT: vse16.v v8, (a0)937; ZVFH-NEXT: ret938;939; ZVFHMIN-LABEL: copysign_vf_v8f16:940; ZVFHMIN: # %bb.0:941; ZVFHMIN-NEXT: fmv.x.w a1, fa0942; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma943; ZVFHMIN-NEXT: vle16.v v8, (a0)944; ZVFHMIN-NEXT: lui a2, 8945; ZVFHMIN-NEXT: vmv.v.x v9, a1946; ZVFHMIN-NEXT: addi a1, a2, -1947; ZVFHMIN-NEXT: vand.vx v8, v8, a1948; ZVFHMIN-NEXT: vand.vx v9, v9, a2949; ZVFHMIN-NEXT: vor.vv v8, v8, v9950; ZVFHMIN-NEXT: vse16.v v8, (a0)951; ZVFHMIN-NEXT: ret952 %a = load <8 x half>, ptr %x953 %b = insertelement <8 x half> poison, half %y, i32 0954 %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer955 %d = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %c)956 store <8 x half> %d, ptr %x957 ret void958}959 960define void @copysign_vf_v6f16(ptr %x, half %y) {961; ZVFH-LABEL: copysign_vf_v6f16:962; ZVFH: # %bb.0:963; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma964; ZVFH-NEXT: vle16.v v8, (a0)965; ZVFH-NEXT: vfsgnj.vf v8, v8, fa0966; ZVFH-NEXT: vse16.v v8, (a0)967; ZVFH-NEXT: ret968;969; ZVFHMIN-LABEL: copysign_vf_v6f16:970; ZVFHMIN: # %bb.0:971; ZVFHMIN-NEXT: fmv.x.w a1, fa0972; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma973; ZVFHMIN-NEXT: vle16.v v8, (a0)974; ZVFHMIN-NEXT: lui a2, 8975; ZVFHMIN-NEXT: vmv.v.x v9, a1976; ZVFHMIN-NEXT: addi a1, a2, -1977; ZVFHMIN-NEXT: vand.vx v8, v8, a1978; ZVFHMIN-NEXT: vand.vx v9, v9, a2979; ZVFHMIN-NEXT: vor.vv v8, v8, v9980; ZVFHMIN-NEXT: vse16.v v8, (a0)981; ZVFHMIN-NEXT: ret982 %a = load <6 x half>, ptr %x983 %b = insertelement <6 x half> poison, half %y, i32 0984 %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer985 %d = call <6 x half> @llvm.copysign.v6f16(<6 x half> %a, <6 x half> %c)986 store <6 x half> %d, ptr %x987 ret void988}989 990define void @copysign_vf_v4f32(ptr %x, float %y) {991; CHECK-LABEL: copysign_vf_v4f32:992; CHECK: # %bb.0:993; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma994; CHECK-NEXT: vle32.v v8, (a0)995; CHECK-NEXT: vfsgnj.vf v8, v8, fa0996; CHECK-NEXT: vse32.v v8, (a0)997; CHECK-NEXT: ret998 %a = load <4 x float>, ptr %x999 %b = insertelement <4 x float> poison, float %y, i32 01000 %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer1001 %d = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %c)1002 store <4 x float> %d, ptr %x1003 ret void1004}1005 1006define void @copysign_vf_v2f64(ptr %x, double %y) {1007; CHECK-LABEL: copysign_vf_v2f64:1008; CHECK: # %bb.0:1009; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma1010; CHECK-NEXT: vle64.v v8, (a0)1011; CHECK-NEXT: vfsgnj.vf v8, v8, fa01012; CHECK-NEXT: vse64.v v8, (a0)1013; CHECK-NEXT: ret1014 %a = load <2 x double>, ptr %x1015 %b = insertelement <2 x double> poison, double %y, i32 01016 %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer1017 %d = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %c)1018 store <2 x double> %d, ptr %x1019 ret void1020}1021 1022define void @copysign_neg_v8bf16(ptr %x, ptr %y) {1023; CHECK-LABEL: copysign_neg_v8bf16:1024; CHECK: # %bb.0:1025; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma1026; CHECK-NEXT: vle16.v v8, (a1)1027; CHECK-NEXT: vle16.v v9, (a0)1028; CHECK-NEXT: lui a1, 81029; CHECK-NEXT: addi a2, a1, -11030; CHECK-NEXT: vxor.vx v8, v8, a11031; CHECK-NEXT: vand.vx v9, v9, a21032; CHECK-NEXT: vand.vx v8, v8, a11033; CHECK-NEXT: vor.vv v8, v9, v81034; CHECK-NEXT: vse16.v v8, (a0)1035; CHECK-NEXT: ret1036 %a = load <8 x bfloat>, ptr %x1037 %b = load <8 x bfloat>, ptr %y1038 %c = fneg <8 x bfloat> %b1039 %d = call <8 x bfloat> @llvm.copysign.v8bf16(<8 x bfloat> %a, <8 x bfloat> %c)1040 store <8 x bfloat> %d, ptr %x1041 ret void1042}1043 1044define void @copysign_neg_v6bf16(ptr %x, ptr %y) {1045; CHECK-LABEL: copysign_neg_v6bf16:1046; CHECK: # %bb.0:1047; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma1048; CHECK-NEXT: vle16.v v8, (a1)1049; CHECK-NEXT: vle16.v v9, (a0)1050; CHECK-NEXT: lui a1, 81051; CHECK-NEXT: addi a2, a1, -11052; CHECK-NEXT: vxor.vx v8, v8, a11053; CHECK-NEXT: vand.vx v9, v9, a21054; CHECK-NEXT: vand.vx v8, v8, a11055; CHECK-NEXT: vor.vv v8, v9, v81056; CHECK-NEXT: vse16.v v8, (a0)1057; CHECK-NEXT: ret1058 %a = load <6 x bfloat>, ptr %x1059 %b = load <6 x bfloat>, ptr %y1060 %c = fneg <6 x bfloat> %b1061 %d = call <6 x bfloat> @llvm.copysign.v6bf16(<6 x bfloat> %a, <6 x bfloat> %c)1062 store <6 x bfloat> %d, ptr %x1063 ret void1064}1065 1066define void @copysign_neg_v8f16(ptr %x, ptr %y) {1067; ZVFH-LABEL: copysign_neg_v8f16:1068; ZVFH: # %bb.0:1069; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma1070; ZVFH-NEXT: vle16.v v8, (a0)1071; ZVFH-NEXT: vle16.v v9, (a1)1072; ZVFH-NEXT: vfsgnjn.vv v8, v8, v91073; ZVFH-NEXT: vse16.v v8, (a0)1074; ZVFH-NEXT: ret1075;1076; ZVFHMIN-LABEL: copysign_neg_v8f16:1077; ZVFHMIN: # %bb.0:1078; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma1079; ZVFHMIN-NEXT: vle16.v v8, (a1)1080; ZVFHMIN-NEXT: vle16.v v9, (a0)1081; ZVFHMIN-NEXT: lui a1, 81082; ZVFHMIN-NEXT: addi a2, a1, -11083; ZVFHMIN-NEXT: vxor.vx v8, v8, a11084; ZVFHMIN-NEXT: vand.vx v9, v9, a21085; ZVFHMIN-NEXT: vand.vx v8, v8, a11086; ZVFHMIN-NEXT: vor.vv v8, v9, v81087; ZVFHMIN-NEXT: vse16.v v8, (a0)1088; ZVFHMIN-NEXT: ret1089 %a = load <8 x half>, ptr %x1090 %b = load <8 x half>, ptr %y1091 %c = fneg <8 x half> %b1092 %d = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %c)1093 store <8 x half> %d, ptr %x1094 ret void1095}1096 1097define void @copysign_neg_v6f16(ptr %x, ptr %y) {1098; ZVFH-LABEL: copysign_neg_v6f16:1099; ZVFH: # %bb.0:1100; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma1101; ZVFH-NEXT: vle16.v v8, (a0)1102; ZVFH-NEXT: vle16.v v9, (a1)1103; ZVFH-NEXT: vfsgnjn.vv v8, v8, v91104; ZVFH-NEXT: vse16.v v8, (a0)1105; ZVFH-NEXT: ret1106;1107; ZVFHMIN-LABEL: copysign_neg_v6f16:1108; ZVFHMIN: # %bb.0:1109; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma1110; ZVFHMIN-NEXT: vle16.v v8, (a1)1111; ZVFHMIN-NEXT: vle16.v v9, (a0)1112; ZVFHMIN-NEXT: lui a1, 81113; ZVFHMIN-NEXT: addi a2, a1, -11114; ZVFHMIN-NEXT: vxor.vx v8, v8, a11115; ZVFHMIN-NEXT: vand.vx v9, v9, a21116; ZVFHMIN-NEXT: vand.vx v8, v8, a11117; ZVFHMIN-NEXT: vor.vv v8, v9, v81118; ZVFHMIN-NEXT: vse16.v v8, (a0)1119; ZVFHMIN-NEXT: ret1120 %a = load <6 x half>, ptr %x1121 %b = load <6 x half>, ptr %y1122 %c = fneg <6 x half> %b1123 %d = call <6 x half> @llvm.copysign.v6f16(<6 x half> %a, <6 x half> %c)1124 store <6 x half> %d, ptr %x1125 ret void1126}1127 1128define void @copysign_neg_v4f32(ptr %x, ptr %y) {1129; CHECK-LABEL: copysign_neg_v4f32:1130; CHECK: # %bb.0:1131; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1132; CHECK-NEXT: vle32.v v8, (a0)1133; CHECK-NEXT: vle32.v v9, (a1)1134; CHECK-NEXT: vfsgnjn.vv v8, v8, v91135; CHECK-NEXT: vse32.v v8, (a0)1136; CHECK-NEXT: ret1137 %a = load <4 x float>, ptr %x1138 %b = load <4 x float>, ptr %y1139 %c = fneg <4 x float> %b1140 %d = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %c)1141 store <4 x float> %d, ptr %x1142 ret void1143}1144 1145define void @copysign_neg_v2f64(ptr %x, ptr %y) {1146; CHECK-LABEL: copysign_neg_v2f64:1147; CHECK: # %bb.0:1148; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma1149; CHECK-NEXT: vle64.v v8, (a0)1150; CHECK-NEXT: vle64.v v9, (a1)1151; CHECK-NEXT: vfsgnjn.vv v8, v8, v91152; CHECK-NEXT: vse64.v v8, (a0)1153; CHECK-NEXT: ret1154 %a = load <2 x double>, ptr %x1155 %b = load <2 x double>, ptr %y1156 %c = fneg <2 x double> %b1157 %d = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %c)1158 store <2 x double> %d, ptr %x1159 ret void1160}1161 1162define void @copysign_neg_trunc_v4bf16_v4f32(ptr %x, ptr %y) {1163; CHECK-LABEL: copysign_neg_trunc_v4bf16_v4f32:1164; CHECK: # %bb.0:1165; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1166; CHECK-NEXT: vle16.v v8, (a0)1167; CHECK-NEXT: vle32.v v9, (a1)1168; CHECK-NEXT: lui a1, 81169; CHECK-NEXT: addi a2, a1, -11170; CHECK-NEXT: vand.vx v8, v8, a21171; CHECK-NEXT: vfncvtbf16.f.f.w v10, v91172; CHECK-NEXT: vxor.vx v9, v10, a11173; CHECK-NEXT: vand.vx v9, v9, a11174; CHECK-NEXT: vor.vv v8, v8, v91175; CHECK-NEXT: vse16.v v8, (a0)1176; CHECK-NEXT: ret1177 %a = load <4 x bfloat>, ptr %x1178 %b = load <4 x float>, ptr %y1179 %c = fneg <4 x float> %b1180 %d = fptrunc <4 x float> %c to <4 x bfloat>1181 %e = call <4 x bfloat> @llvm.copysign.v4bf16(<4 x bfloat> %a, <4 x bfloat> %d)1182 store <4 x bfloat> %e, ptr %x1183 ret void1184}1185 1186define void @copysign_neg_trunc_v3bf16_v3f32(ptr %x, ptr %y) {1187; CHECK-LABEL: copysign_neg_trunc_v3bf16_v3f32:1188; CHECK: # %bb.0:1189; CHECK-NEXT: vsetivli zero, 3, e16, mf2, ta, ma1190; CHECK-NEXT: vle16.v v8, (a0)1191; CHECK-NEXT: vle32.v v9, (a1)1192; CHECK-NEXT: lui a1, 81193; CHECK-NEXT: addi a2, a1, -11194; CHECK-NEXT: vand.vx v8, v8, a21195; CHECK-NEXT: vfncvtbf16.f.f.w v10, v91196; CHECK-NEXT: vxor.vx v9, v10, a11197; CHECK-NEXT: vand.vx v9, v9, a11198; CHECK-NEXT: vor.vv v8, v8, v91199; CHECK-NEXT: vse16.v v8, (a0)1200; CHECK-NEXT: ret1201 %a = load <3 x bfloat>, ptr %x1202 %b = load <3 x float>, ptr %y1203 %c = fneg <3 x float> %b1204 %d = fptrunc <3 x float> %c to <3 x bfloat>1205 %e = call <3 x bfloat> @llvm.copysign.v3bf16(<3 x bfloat> %a, <3 x bfloat> %d)1206 store <3 x bfloat> %e, ptr %x1207 ret void1208}1209 1210define void @copysign_neg_trunc_v4f16_v4f32(ptr %x, ptr %y) {1211; ZVFH-LABEL: copysign_neg_trunc_v4f16_v4f32:1212; ZVFH: # %bb.0:1213; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1214; ZVFH-NEXT: vle32.v v8, (a1)1215; ZVFH-NEXT: vle16.v v9, (a0)1216; ZVFH-NEXT: vfncvt.f.f.w v10, v81217; ZVFH-NEXT: vfsgnjn.vv v8, v9, v101218; ZVFH-NEXT: vse16.v v8, (a0)1219; ZVFH-NEXT: ret1220;1221; ZVFHMIN-LABEL: copysign_neg_trunc_v4f16_v4f32:1222; ZVFHMIN: # %bb.0:1223; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1224; ZVFHMIN-NEXT: vle16.v v8, (a0)1225; ZVFHMIN-NEXT: vle32.v v9, (a1)1226; ZVFHMIN-NEXT: lui a1, 81227; ZVFHMIN-NEXT: addi a2, a1, -11228; ZVFHMIN-NEXT: vand.vx v8, v8, a21229; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v91230; ZVFHMIN-NEXT: vxor.vx v9, v10, a11231; ZVFHMIN-NEXT: vand.vx v9, v9, a11232; ZVFHMIN-NEXT: vor.vv v8, v8, v91233; ZVFHMIN-NEXT: vse16.v v8, (a0)1234; ZVFHMIN-NEXT: ret1235 %a = load <4 x half>, ptr %x1236 %b = load <4 x float>, ptr %y1237 %c = fneg <4 x float> %b1238 %d = fptrunc <4 x float> %c to <4 x half>1239 %e = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %d)1240 store <4 x half> %e, ptr %x1241 ret void1242}1243 1244define void @copysign_neg_trunc_v3f16_v3f32(ptr %x, ptr %y) {1245; ZVFH-LABEL: copysign_neg_trunc_v3f16_v3f32:1246; ZVFH: # %bb.0:1247; ZVFH-NEXT: vsetivli zero, 3, e16, mf2, ta, ma1248; ZVFH-NEXT: vle32.v v8, (a1)1249; ZVFH-NEXT: vle16.v v9, (a0)1250; ZVFH-NEXT: vfncvt.f.f.w v10, v81251; ZVFH-NEXT: vfsgnjn.vv v8, v9, v101252; ZVFH-NEXT: vse16.v v8, (a0)1253; ZVFH-NEXT: ret1254;1255; ZVFHMIN-LABEL: copysign_neg_trunc_v3f16_v3f32:1256; ZVFHMIN: # %bb.0:1257; ZVFHMIN-NEXT: vsetivli zero, 3, e16, mf2, ta, ma1258; ZVFHMIN-NEXT: vle16.v v8, (a0)1259; ZVFHMIN-NEXT: vle32.v v9, (a1)1260; ZVFHMIN-NEXT: lui a1, 81261; ZVFHMIN-NEXT: addi a2, a1, -11262; ZVFHMIN-NEXT: vand.vx v8, v8, a21263; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v91264; ZVFHMIN-NEXT: vxor.vx v9, v10, a11265; ZVFHMIN-NEXT: vand.vx v9, v9, a11266; ZVFHMIN-NEXT: vor.vv v8, v8, v91267; ZVFHMIN-NEXT: vse16.v v8, (a0)1268; ZVFHMIN-NEXT: ret1269 %a = load <3 x half>, ptr %x1270 %b = load <3 x float>, ptr %y1271 %c = fneg <3 x float> %b1272 %d = fptrunc <3 x float> %c to <3 x half>1273 %e = call <3 x half> @llvm.copysign.v3f16(<3 x half> %a, <3 x half> %d)1274 store <3 x half> %e, ptr %x1275 ret void1276}1277 1278define void @copysign_neg_ext_v2f64_v2f32(ptr %x, ptr %y) {1279; CHECK-LABEL: copysign_neg_ext_v2f64_v2f32:1280; CHECK: # %bb.0:1281; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1282; CHECK-NEXT: vle32.v v8, (a1)1283; CHECK-NEXT: vle64.v v9, (a0)1284; CHECK-NEXT: vfwcvt.f.f.v v10, v81285; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma1286; CHECK-NEXT: vfsgnjn.vv v8, v9, v101287; CHECK-NEXT: vse64.v v8, (a0)1288; CHECK-NEXT: ret1289 %a = load <2 x double>, ptr %x1290 %b = load <2 x float>, ptr %y1291 %c = fneg <2 x float> %b1292 %d = fpext <2 x float> %c to <2 x double>1293 %e = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %d)1294 store <2 x double> %e, ptr %x1295 ret void1296}1297 1298define void @sqrt_v8bf16(ptr %x) {1299; CHECK-LABEL: sqrt_v8bf16:1300; CHECK: # %bb.0:1301; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma1302; CHECK-NEXT: vle16.v v10, (a0)1303; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v101304; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma1305; CHECK-NEXT: vfsqrt.v v8, v81306; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma1307; CHECK-NEXT: vfncvtbf16.f.f.w v10, v81308; CHECK-NEXT: vse16.v v10, (a0)1309; CHECK-NEXT: ret1310 %a = load <8 x bfloat>, ptr %x1311 %b = call <8 x bfloat> @llvm.sqrt.v8bf16(<8 x bfloat> %a)1312 store <8 x bfloat> %b, ptr %x1313 ret void1314}1315 1316define void @sqrt_v6bf16(ptr %x) {1317; CHECK-LABEL: sqrt_v6bf16:1318; CHECK: # %bb.0:1319; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma1320; CHECK-NEXT: vle16.v v10, (a0)1321; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v101322; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma1323; CHECK-NEXT: vfsqrt.v v8, v81324; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma1325; CHECK-NEXT: vfncvtbf16.f.f.w v10, v81326; CHECK-NEXT: vse16.v v10, (a0)1327; CHECK-NEXT: ret1328 %a = load <6 x bfloat>, ptr %x1329 %b = call <6 x bfloat> @llvm.sqrt.v6bf16(<6 x bfloat> %a)1330 store <6 x bfloat> %b, ptr %x1331 ret void1332}1333 1334define void @sqrt_v8f16(ptr %x) {1335; ZVFH-LABEL: sqrt_v8f16:1336; ZVFH: # %bb.0:1337; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma1338; ZVFH-NEXT: vle16.v v8, (a0)1339; ZVFH-NEXT: vfsqrt.v v8, v81340; ZVFH-NEXT: vse16.v v8, (a0)1341; ZVFH-NEXT: ret1342;1343; ZVFHMIN-LABEL: sqrt_v8f16:1344; ZVFHMIN: # %bb.0:1345; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma1346; ZVFHMIN-NEXT: vle16.v v10, (a0)1347; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v101348; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma1349; ZVFHMIN-NEXT: vfsqrt.v v8, v81350; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma1351; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v81352; ZVFHMIN-NEXT: vse16.v v10, (a0)1353; ZVFHMIN-NEXT: ret1354 %a = load <8 x half>, ptr %x1355 %b = call <8 x half> @llvm.sqrt.v8f16(<8 x half> %a)1356 store <8 x half> %b, ptr %x1357 ret void1358}1359 1360define void @sqrt_v6f16(ptr %x) {1361; ZVFH-LABEL: sqrt_v6f16:1362; ZVFH: # %bb.0:1363; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma1364; ZVFH-NEXT: vle16.v v8, (a0)1365; ZVFH-NEXT: vfsqrt.v v8, v81366; ZVFH-NEXT: vse16.v v8, (a0)1367; ZVFH-NEXT: ret1368;1369; ZVFHMIN-LABEL: sqrt_v6f16:1370; ZVFHMIN: # %bb.0:1371; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma1372; ZVFHMIN-NEXT: vle16.v v10, (a0)1373; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v101374; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma1375; ZVFHMIN-NEXT: vfsqrt.v v8, v81376; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma1377; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v81378; ZVFHMIN-NEXT: vse16.v v10, (a0)1379; ZVFHMIN-NEXT: ret1380 %a = load <6 x half>, ptr %x1381 %b = call <6 x half> @llvm.sqrt.v6f16(<6 x half> %a)1382 store <6 x half> %b, ptr %x1383 ret void1384}1385 1386define void @sqrt_v4f32(ptr %x) {1387; CHECK-LABEL: sqrt_v4f32:1388; CHECK: # %bb.0:1389; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1390; CHECK-NEXT: vle32.v v8, (a0)1391; CHECK-NEXT: vfsqrt.v v8, v81392; CHECK-NEXT: vse32.v v8, (a0)1393; CHECK-NEXT: ret1394 %a = load <4 x float>, ptr %x1395 %b = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)1396 store <4 x float> %b, ptr %x1397 ret void1398}1399 1400define void @sqrt_v2f64(ptr %x) {1401; CHECK-LABEL: sqrt_v2f64:1402; CHECK: # %bb.0:1403; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma1404; CHECK-NEXT: vle64.v v8, (a0)1405; CHECK-NEXT: vfsqrt.v v8, v81406; CHECK-NEXT: vse64.v v8, (a0)1407; CHECK-NEXT: ret1408 %a = load <2 x double>, ptr %x1409 %b = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a)1410 store <2 x double> %b, ptr %x1411 ret void1412}1413 1414define void @fma_v8bf16(ptr %x, ptr %y, ptr %z) {1415; CHECK-LABEL: fma_v8bf16:1416; CHECK: # %bb.0:1417; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma1418; CHECK-NEXT: vle16.v v10, (a2)1419; CHECK-NEXT: vle16.v v12, (a0)1420; CHECK-NEXT: vle16.v v14, (a1)1421; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v101422; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v121423; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v141424; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma1425; CHECK-NEXT: vfmadd.vv v12, v10, v81426; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma1427; CHECK-NEXT: vfncvtbf16.f.f.w v8, v121428; CHECK-NEXT: vse16.v v8, (a0)1429; CHECK-NEXT: ret1430 %a = load <8 x bfloat>, ptr %x1431 %b = load <8 x bfloat>, ptr %y1432 %c = load <8 x bfloat>, ptr %z1433 %d = call <8 x bfloat> @llvm.fma.v8bf16(<8 x bfloat> %a, <8 x bfloat> %b, <8 x bfloat> %c)1434 store <8 x bfloat> %d, ptr %x1435 ret void1436}1437 1438define void @fma_v6bf16(ptr %x, ptr %y, ptr %z) {1439; CHECK-LABEL: fma_v6bf16:1440; CHECK: # %bb.0:1441; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma1442; CHECK-NEXT: vle16.v v10, (a2)1443; CHECK-NEXT: vle16.v v12, (a0)1444; CHECK-NEXT: vle16.v v14, (a1)1445; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v101446; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v121447; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v141448; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma1449; CHECK-NEXT: vfmadd.vv v12, v10, v81450; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma1451; CHECK-NEXT: vfncvtbf16.f.f.w v8, v121452; CHECK-NEXT: vse16.v v8, (a0)1453; CHECK-NEXT: ret1454 %a = load <6 x bfloat>, ptr %x1455 %b = load <6 x bfloat>, ptr %y1456 %c = load <6 x bfloat>, ptr %z1457 %d = call <6 x bfloat> @llvm.fma.v6bf16(<6 x bfloat> %a, <6 x bfloat> %b, <6 x bfloat> %c)1458 store <6 x bfloat> %d, ptr %x1459 ret void1460}1461 1462define void @fma_v8f16(ptr %x, ptr %y, ptr %z) {1463; ZVFH-LABEL: fma_v8f16:1464; ZVFH: # %bb.0:1465; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma1466; ZVFH-NEXT: vle16.v v8, (a0)1467; ZVFH-NEXT: vle16.v v9, (a1)1468; ZVFH-NEXT: vle16.v v10, (a2)1469; ZVFH-NEXT: vfmacc.vv v10, v8, v91470; ZVFH-NEXT: vse16.v v10, (a0)1471; ZVFH-NEXT: ret1472;1473; ZVFHMIN-LABEL: fma_v8f16:1474; ZVFHMIN: # %bb.0:1475; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma1476; ZVFHMIN-NEXT: vle16.v v10, (a2)1477; ZVFHMIN-NEXT: vle16.v v12, (a0)1478; ZVFHMIN-NEXT: vle16.v v14, (a1)1479; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v101480; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v121481; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v141482; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma1483; ZVFHMIN-NEXT: vfmadd.vv v12, v10, v81484; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma1485; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v121486; ZVFHMIN-NEXT: vse16.v v8, (a0)1487; ZVFHMIN-NEXT: ret1488 %a = load <8 x half>, ptr %x1489 %b = load <8 x half>, ptr %y1490 %c = load <8 x half>, ptr %z1491 %d = call <8 x half> @llvm.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c)1492 store <8 x half> %d, ptr %x1493 ret void1494}1495 1496define void @fma_v6f16(ptr %x, ptr %y, ptr %z) {1497; ZVFH-LABEL: fma_v6f16:1498; ZVFH: # %bb.0:1499; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma1500; ZVFH-NEXT: vle16.v v8, (a0)1501; ZVFH-NEXT: vle16.v v9, (a1)1502; ZVFH-NEXT: vle16.v v10, (a2)1503; ZVFH-NEXT: vfmacc.vv v10, v8, v91504; ZVFH-NEXT: vse16.v v10, (a0)1505; ZVFH-NEXT: ret1506;1507; ZVFHMIN-LABEL: fma_v6f16:1508; ZVFHMIN: # %bb.0:1509; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma1510; ZVFHMIN-NEXT: vle16.v v10, (a2)1511; ZVFHMIN-NEXT: vle16.v v12, (a0)1512; ZVFHMIN-NEXT: vle16.v v14, (a1)1513; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v101514; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v121515; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v141516; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma1517; ZVFHMIN-NEXT: vfmadd.vv v12, v10, v81518; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma1519; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v121520; ZVFHMIN-NEXT: vse16.v v8, (a0)1521; ZVFHMIN-NEXT: ret1522 %a = load <6 x half>, ptr %x1523 %b = load <6 x half>, ptr %y1524 %c = load <6 x half>, ptr %z1525 %d = call <6 x half> @llvm.fma.v6f16(<6 x half> %a, <6 x half> %b, <6 x half> %c)1526 store <6 x half> %d, ptr %x1527 ret void1528}1529 1530define void @fma_v4f32(ptr %x, ptr %y, ptr %z) {1531; CHECK-LABEL: fma_v4f32:1532; CHECK: # %bb.0:1533; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1534; CHECK-NEXT: vle32.v v8, (a0)1535; CHECK-NEXT: vle32.v v9, (a1)1536; CHECK-NEXT: vle32.v v10, (a2)1537; CHECK-NEXT: vfmacc.vv v10, v8, v91538; CHECK-NEXT: vse32.v v10, (a0)1539; CHECK-NEXT: ret1540 %a = load <4 x float>, ptr %x1541 %b = load <4 x float>, ptr %y1542 %c = load <4 x float>, ptr %z1543 %d = call <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)1544 store <4 x float> %d, ptr %x1545 ret void1546}1547 1548define void @fma_v2f64(ptr %x, ptr %y, ptr %z) {1549; CHECK-LABEL: fma_v2f64:1550; CHECK: # %bb.0:1551; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma1552; CHECK-NEXT: vle64.v v8, (a0)1553; CHECK-NEXT: vle64.v v9, (a1)1554; CHECK-NEXT: vle64.v v10, (a2)1555; CHECK-NEXT: vfmacc.vv v10, v8, v91556; CHECK-NEXT: vse64.v v10, (a0)1557; CHECK-NEXT: ret1558 %a = load <2 x double>, ptr %x1559 %b = load <2 x double>, ptr %y1560 %c = load <2 x double>, ptr %z1561 %d = call <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c)1562 store <2 x double> %d, ptr %x1563 ret void1564}1565 1566define void @fmsub_v8bf16(ptr %x, ptr %y, ptr %z) {1567; CHECK-LABEL: fmsub_v8bf16:1568; CHECK: # %bb.0:1569; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma1570; CHECK-NEXT: vle16.v v8, (a2)1571; CHECK-NEXT: vle16.v v10, (a0)1572; CHECK-NEXT: vle16.v v14, (a1)1573; CHECK-NEXT: lui a1, 81574; CHECK-NEXT: vxor.vx v12, v8, a11575; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v101576; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v121577; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v141578; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma1579; CHECK-NEXT: vfmadd.vv v12, v8, v101580; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma1581; CHECK-NEXT: vfncvtbf16.f.f.w v8, v121582; CHECK-NEXT: vse16.v v8, (a0)1583; CHECK-NEXT: ret1584 %a = load <8 x bfloat>, ptr %x1585 %b = load <8 x bfloat>, ptr %y1586 %c = load <8 x bfloat>, ptr %z1587 %neg = fneg <8 x bfloat> %c1588 %d = call <8 x bfloat> @llvm.fma.v8bf16(<8 x bfloat> %a, <8 x bfloat> %b, <8 x bfloat> %neg)1589 store <8 x bfloat> %d, ptr %x1590 ret void1591}1592 1593define void @fmsub_v6bf16(ptr %x, ptr %y, ptr %z) {1594; CHECK-LABEL: fmsub_v6bf16:1595; CHECK: # %bb.0:1596; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma1597; CHECK-NEXT: vle16.v v8, (a2)1598; CHECK-NEXT: vle16.v v10, (a0)1599; CHECK-NEXT: vle16.v v14, (a1)1600; CHECK-NEXT: lui a1, 81601; CHECK-NEXT: vxor.vx v12, v8, a11602; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v101603; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v121604; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v141605; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma1606; CHECK-NEXT: vfmadd.vv v12, v8, v101607; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma1608; CHECK-NEXT: vfncvtbf16.f.f.w v8, v121609; CHECK-NEXT: vse16.v v8, (a0)1610; CHECK-NEXT: ret1611 %a = load <6 x bfloat>, ptr %x1612 %b = load <6 x bfloat>, ptr %y1613 %c = load <6 x bfloat>, ptr %z1614 %neg = fneg <6 x bfloat> %c1615 %d = call <6 x bfloat> @llvm.fma.v6bf16(<6 x bfloat> %a, <6 x bfloat> %b, <6 x bfloat> %neg)1616 store <6 x bfloat> %d, ptr %x1617 ret void1618}1619 1620define void @fmsub_v8f16(ptr %x, ptr %y, ptr %z) {1621; ZVFH-LABEL: fmsub_v8f16:1622; ZVFH: # %bb.0:1623; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma1624; ZVFH-NEXT: vle16.v v8, (a0)1625; ZVFH-NEXT: vle16.v v9, (a1)1626; ZVFH-NEXT: vle16.v v10, (a2)1627; ZVFH-NEXT: vfmsac.vv v10, v8, v91628; ZVFH-NEXT: vse16.v v10, (a0)1629; ZVFH-NEXT: ret1630;1631; ZVFHMIN-LABEL: fmsub_v8f16:1632; ZVFHMIN: # %bb.0:1633; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma1634; ZVFHMIN-NEXT: vle16.v v8, (a2)1635; ZVFHMIN-NEXT: vle16.v v10, (a0)1636; ZVFHMIN-NEXT: vle16.v v14, (a1)1637; ZVFHMIN-NEXT: lui a1, 81638; ZVFHMIN-NEXT: vxor.vx v12, v8, a11639; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v101640; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v121641; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v141642; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma1643; ZVFHMIN-NEXT: vfmadd.vv v12, v8, v101644; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma1645; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v121646; ZVFHMIN-NEXT: vse16.v v8, (a0)1647; ZVFHMIN-NEXT: ret1648 %a = load <8 x half>, ptr %x1649 %b = load <8 x half>, ptr %y1650 %c = load <8 x half>, ptr %z1651 %neg = fneg <8 x half> %c1652 %d = call <8 x half> @llvm.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %neg)1653 store <8 x half> %d, ptr %x1654 ret void1655}1656 1657define void @fmsub_v6f16(ptr %x, ptr %y, ptr %z) {1658; ZVFH-LABEL: fmsub_v6f16:1659; ZVFH: # %bb.0:1660; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma1661; ZVFH-NEXT: vle16.v v8, (a0)1662; ZVFH-NEXT: vle16.v v9, (a1)1663; ZVFH-NEXT: vle16.v v10, (a2)1664; ZVFH-NEXT: vfmsac.vv v10, v8, v91665; ZVFH-NEXT: vse16.v v10, (a0)1666; ZVFH-NEXT: ret1667;1668; ZVFHMIN-LABEL: fmsub_v6f16:1669; ZVFHMIN: # %bb.0:1670; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma1671; ZVFHMIN-NEXT: vle16.v v8, (a2)1672; ZVFHMIN-NEXT: vle16.v v10, (a0)1673; ZVFHMIN-NEXT: vle16.v v14, (a1)1674; ZVFHMIN-NEXT: lui a1, 81675; ZVFHMIN-NEXT: vxor.vx v12, v8, a11676; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v101677; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v121678; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v141679; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma1680; ZVFHMIN-NEXT: vfmadd.vv v12, v8, v101681; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma1682; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v121683; ZVFHMIN-NEXT: vse16.v v8, (a0)1684; ZVFHMIN-NEXT: ret1685 %a = load <6 x half>, ptr %x1686 %b = load <6 x half>, ptr %y1687 %c = load <6 x half>, ptr %z1688 %neg = fneg <6 x half> %c1689 %d = call <6 x half> @llvm.fma.v6f16(<6 x half> %a, <6 x half> %b, <6 x half> %neg)1690 store <6 x half> %d, ptr %x1691 ret void1692}1693 1694define void @fnmsub_v4f32(ptr %x, ptr %y, ptr %z) {1695; CHECK-LABEL: fnmsub_v4f32:1696; CHECK: # %bb.0:1697; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1698; CHECK-NEXT: vle32.v v8, (a0)1699; CHECK-NEXT: vle32.v v9, (a1)1700; CHECK-NEXT: vle32.v v10, (a2)1701; CHECK-NEXT: vfnmsac.vv v10, v8, v91702; CHECK-NEXT: vse32.v v10, (a0)1703; CHECK-NEXT: ret1704 %a = load <4 x float>, ptr %x1705 %b = load <4 x float>, ptr %y1706 %c = load <4 x float>, ptr %z1707 %neg = fneg <4 x float> %a1708 %d = call <4 x float> @llvm.fma.v4f32(<4 x float> %neg, <4 x float> %b, <4 x float> %c)1709 store <4 x float> %d, ptr %x1710 ret void1711}1712 1713define void @fnmadd_v2f64(ptr %x, ptr %y, ptr %z) {1714; CHECK-LABEL: fnmadd_v2f64:1715; CHECK: # %bb.0:1716; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma1717; CHECK-NEXT: vle64.v v8, (a0)1718; CHECK-NEXT: vle64.v v9, (a1)1719; CHECK-NEXT: vle64.v v10, (a2)1720; CHECK-NEXT: vfnmacc.vv v10, v8, v91721; CHECK-NEXT: vse64.v v10, (a0)1722; CHECK-NEXT: ret1723 %a = load <2 x double>, ptr %x1724 %b = load <2 x double>, ptr %y1725 %c = load <2 x double>, ptr %z1726 %neg = fneg <2 x double> %b1727 %neg2 = fneg <2 x double> %c1728 %d = call <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> %neg, <2 x double> %neg2)1729 store <2 x double> %d, ptr %x1730 ret void1731}1732 1733define void @fadd_v16bf16(ptr %x, ptr %y) {1734; CHECK-LABEL: fadd_v16bf16:1735; CHECK: # %bb.0:1736; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma1737; CHECK-NEXT: vle16.v v12, (a1)1738; CHECK-NEXT: vle16.v v16, (a0)1739; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v121740; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v161741; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma1742; CHECK-NEXT: vfadd.vv v8, v12, v81743; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma1744; CHECK-NEXT: vfncvtbf16.f.f.w v12, v81745; CHECK-NEXT: vse16.v v12, (a0)1746; CHECK-NEXT: ret1747 %a = load <16 x bfloat>, ptr %x1748 %b = load <16 x bfloat>, ptr %y1749 %c = fadd <16 x bfloat> %a, %b1750 store <16 x bfloat> %c, ptr %x1751 ret void1752}1753 1754define void @fadd_v16f16(ptr %x, ptr %y) {1755; ZVFH-LABEL: fadd_v16f16:1756; ZVFH: # %bb.0:1757; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma1758; ZVFH-NEXT: vle16.v v8, (a0)1759; ZVFH-NEXT: vle16.v v10, (a1)1760; ZVFH-NEXT: vfadd.vv v8, v8, v101761; ZVFH-NEXT: vse16.v v8, (a0)1762; ZVFH-NEXT: ret1763;1764; ZVFHMIN-LABEL: fadd_v16f16:1765; ZVFHMIN: # %bb.0:1766; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma1767; ZVFHMIN-NEXT: vle16.v v12, (a1)1768; ZVFHMIN-NEXT: vle16.v v16, (a0)1769; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v121770; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v161771; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma1772; ZVFHMIN-NEXT: vfadd.vv v8, v12, v81773; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma1774; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v81775; ZVFHMIN-NEXT: vse16.v v12, (a0)1776; ZVFHMIN-NEXT: ret1777 %a = load <16 x half>, ptr %x1778 %b = load <16 x half>, ptr %y1779 %c = fadd <16 x half> %a, %b1780 store <16 x half> %c, ptr %x1781 ret void1782}1783 1784define void @fadd_v8f32(ptr %x, ptr %y) {1785; CHECK-LABEL: fadd_v8f32:1786; CHECK: # %bb.0:1787; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1788; CHECK-NEXT: vle32.v v8, (a0)1789; CHECK-NEXT: vle32.v v10, (a1)1790; CHECK-NEXT: vfadd.vv v8, v8, v101791; CHECK-NEXT: vse32.v v8, (a0)1792; CHECK-NEXT: ret1793 %a = load <8 x float>, ptr %x1794 %b = load <8 x float>, ptr %y1795 %c = fadd <8 x float> %a, %b1796 store <8 x float> %c, ptr %x1797 ret void1798}1799 1800define void @fadd_v4f64(ptr %x, ptr %y) {1801; CHECK-LABEL: fadd_v4f64:1802; CHECK: # %bb.0:1803; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma1804; CHECK-NEXT: vle64.v v8, (a0)1805; CHECK-NEXT: vle64.v v10, (a1)1806; CHECK-NEXT: vfadd.vv v8, v8, v101807; CHECK-NEXT: vse64.v v8, (a0)1808; CHECK-NEXT: ret1809 %a = load <4 x double>, ptr %x1810 %b = load <4 x double>, ptr %y1811 %c = fadd <4 x double> %a, %b1812 store <4 x double> %c, ptr %x1813 ret void1814}1815 1816define void @fsub_v16bf16(ptr %x, ptr %y) {1817; CHECK-LABEL: fsub_v16bf16:1818; CHECK: # %bb.0:1819; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma1820; CHECK-NEXT: vle16.v v12, (a1)1821; CHECK-NEXT: vle16.v v16, (a0)1822; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v121823; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v161824; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma1825; CHECK-NEXT: vfsub.vv v8, v12, v81826; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma1827; CHECK-NEXT: vfncvtbf16.f.f.w v12, v81828; CHECK-NEXT: vse16.v v12, (a0)1829; CHECK-NEXT: ret1830 %a = load <16 x bfloat>, ptr %x1831 %b = load <16 x bfloat>, ptr %y1832 %c = fsub <16 x bfloat> %a, %b1833 store <16 x bfloat> %c, ptr %x1834 ret void1835}1836 1837define void @fsub_v16f16(ptr %x, ptr %y) {1838; ZVFH-LABEL: fsub_v16f16:1839; ZVFH: # %bb.0:1840; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma1841; ZVFH-NEXT: vle16.v v8, (a0)1842; ZVFH-NEXT: vle16.v v10, (a1)1843; ZVFH-NEXT: vfsub.vv v8, v8, v101844; ZVFH-NEXT: vse16.v v8, (a0)1845; ZVFH-NEXT: ret1846;1847; ZVFHMIN-LABEL: fsub_v16f16:1848; ZVFHMIN: # %bb.0:1849; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma1850; ZVFHMIN-NEXT: vle16.v v12, (a1)1851; ZVFHMIN-NEXT: vle16.v v16, (a0)1852; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v121853; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v161854; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma1855; ZVFHMIN-NEXT: vfsub.vv v8, v12, v81856; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma1857; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v81858; ZVFHMIN-NEXT: vse16.v v12, (a0)1859; ZVFHMIN-NEXT: ret1860 %a = load <16 x half>, ptr %x1861 %b = load <16 x half>, ptr %y1862 %c = fsub <16 x half> %a, %b1863 store <16 x half> %c, ptr %x1864 ret void1865}1866 1867define void @fsub_v8f32(ptr %x, ptr %y) {1868; CHECK-LABEL: fsub_v8f32:1869; CHECK: # %bb.0:1870; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1871; CHECK-NEXT: vle32.v v8, (a0)1872; CHECK-NEXT: vle32.v v10, (a1)1873; CHECK-NEXT: vfsub.vv v8, v8, v101874; CHECK-NEXT: vse32.v v8, (a0)1875; CHECK-NEXT: ret1876 %a = load <8 x float>, ptr %x1877 %b = load <8 x float>, ptr %y1878 %c = fsub <8 x float> %a, %b1879 store <8 x float> %c, ptr %x1880 ret void1881}1882 1883define void @fsub_v4f64(ptr %x, ptr %y) {1884; CHECK-LABEL: fsub_v4f64:1885; CHECK: # %bb.0:1886; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma1887; CHECK-NEXT: vle64.v v8, (a0)1888; CHECK-NEXT: vle64.v v10, (a1)1889; CHECK-NEXT: vfsub.vv v8, v8, v101890; CHECK-NEXT: vse64.v v8, (a0)1891; CHECK-NEXT: ret1892 %a = load <4 x double>, ptr %x1893 %b = load <4 x double>, ptr %y1894 %c = fsub <4 x double> %a, %b1895 store <4 x double> %c, ptr %x1896 ret void1897}1898 1899define void @fmul_v16bf16(ptr %x, ptr %y) {1900; CHECK-LABEL: fmul_v16bf16:1901; CHECK: # %bb.0:1902; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma1903; CHECK-NEXT: vle16.v v12, (a1)1904; CHECK-NEXT: vle16.v v16, (a0)1905; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v121906; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v161907; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma1908; CHECK-NEXT: vfmul.vv v8, v12, v81909; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma1910; CHECK-NEXT: vfncvtbf16.f.f.w v12, v81911; CHECK-NEXT: vse16.v v12, (a0)1912; CHECK-NEXT: ret1913 %a = load <16 x bfloat>, ptr %x1914 %b = load <16 x bfloat>, ptr %y1915 %c = fmul <16 x bfloat> %a, %b1916 store <16 x bfloat> %c, ptr %x1917 ret void1918}1919 1920define void @fmul_v16f16(ptr %x, ptr %y) {1921; ZVFH-LABEL: fmul_v16f16:1922; ZVFH: # %bb.0:1923; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma1924; ZVFH-NEXT: vle16.v v8, (a0)1925; ZVFH-NEXT: vle16.v v10, (a1)1926; ZVFH-NEXT: vfmul.vv v8, v8, v101927; ZVFH-NEXT: vse16.v v8, (a0)1928; ZVFH-NEXT: ret1929;1930; ZVFHMIN-LABEL: fmul_v16f16:1931; ZVFHMIN: # %bb.0:1932; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma1933; ZVFHMIN-NEXT: vle16.v v12, (a1)1934; ZVFHMIN-NEXT: vle16.v v16, (a0)1935; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v121936; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v161937; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma1938; ZVFHMIN-NEXT: vfmul.vv v8, v12, v81939; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma1940; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v81941; ZVFHMIN-NEXT: vse16.v v12, (a0)1942; ZVFHMIN-NEXT: ret1943 %a = load <16 x half>, ptr %x1944 %b = load <16 x half>, ptr %y1945 %c = fmul <16 x half> %a, %b1946 store <16 x half> %c, ptr %x1947 ret void1948}1949 1950define void @fmul_v8f32(ptr %x, ptr %y) {1951; CHECK-LABEL: fmul_v8f32:1952; CHECK: # %bb.0:1953; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1954; CHECK-NEXT: vle32.v v8, (a0)1955; CHECK-NEXT: vle32.v v10, (a1)1956; CHECK-NEXT: vfmul.vv v8, v8, v101957; CHECK-NEXT: vse32.v v8, (a0)1958; CHECK-NEXT: ret1959 %a = load <8 x float>, ptr %x1960 %b = load <8 x float>, ptr %y1961 %c = fmul <8 x float> %a, %b1962 store <8 x float> %c, ptr %x1963 ret void1964}1965 1966define void @fmul_v4f64(ptr %x, ptr %y) {1967; CHECK-LABEL: fmul_v4f64:1968; CHECK: # %bb.0:1969; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma1970; CHECK-NEXT: vle64.v v8, (a0)1971; CHECK-NEXT: vle64.v v10, (a1)1972; CHECK-NEXT: vfmul.vv v8, v8, v101973; CHECK-NEXT: vse64.v v8, (a0)1974; CHECK-NEXT: ret1975 %a = load <4 x double>, ptr %x1976 %b = load <4 x double>, ptr %y1977 %c = fmul <4 x double> %a, %b1978 store <4 x double> %c, ptr %x1979 ret void1980}1981 1982define void @fdiv_v16bf16(ptr %x, ptr %y) {1983; CHECK-LABEL: fdiv_v16bf16:1984; CHECK: # %bb.0:1985; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma1986; CHECK-NEXT: vle16.v v12, (a1)1987; CHECK-NEXT: vle16.v v16, (a0)1988; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v121989; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v161990; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma1991; CHECK-NEXT: vfdiv.vv v8, v12, v81992; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma1993; CHECK-NEXT: vfncvtbf16.f.f.w v12, v81994; CHECK-NEXT: vse16.v v12, (a0)1995; CHECK-NEXT: ret1996 %a = load <16 x bfloat>, ptr %x1997 %b = load <16 x bfloat>, ptr %y1998 %c = fdiv <16 x bfloat> %a, %b1999 store <16 x bfloat> %c, ptr %x2000 ret void2001}2002 2003define void @fdiv_v16f16(ptr %x, ptr %y) {2004; ZVFH-LABEL: fdiv_v16f16:2005; ZVFH: # %bb.0:2006; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma2007; ZVFH-NEXT: vle16.v v8, (a0)2008; ZVFH-NEXT: vle16.v v10, (a1)2009; ZVFH-NEXT: vfdiv.vv v8, v8, v102010; ZVFH-NEXT: vse16.v v8, (a0)2011; ZVFH-NEXT: ret2012;2013; ZVFHMIN-LABEL: fdiv_v16f16:2014; ZVFHMIN: # %bb.0:2015; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma2016; ZVFHMIN-NEXT: vle16.v v12, (a1)2017; ZVFHMIN-NEXT: vle16.v v16, (a0)2018; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v122019; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v162020; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma2021; ZVFHMIN-NEXT: vfdiv.vv v8, v12, v82022; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma2023; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v82024; ZVFHMIN-NEXT: vse16.v v12, (a0)2025; ZVFHMIN-NEXT: ret2026 %a = load <16 x half>, ptr %x2027 %b = load <16 x half>, ptr %y2028 %c = fdiv <16 x half> %a, %b2029 store <16 x half> %c, ptr %x2030 ret void2031}2032 2033define void @fdiv_v8f32(ptr %x, ptr %y) {2034; CHECK-LABEL: fdiv_v8f32:2035; CHECK: # %bb.0:2036; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma2037; CHECK-NEXT: vle32.v v8, (a0)2038; CHECK-NEXT: vle32.v v10, (a1)2039; CHECK-NEXT: vfdiv.vv v8, v8, v102040; CHECK-NEXT: vse32.v v8, (a0)2041; CHECK-NEXT: ret2042 %a = load <8 x float>, ptr %x2043 %b = load <8 x float>, ptr %y2044 %c = fdiv <8 x float> %a, %b2045 store <8 x float> %c, ptr %x2046 ret void2047}2048 2049define void @fdiv_v4f64(ptr %x, ptr %y) {2050; CHECK-LABEL: fdiv_v4f64:2051; CHECK: # %bb.0:2052; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma2053; CHECK-NEXT: vle64.v v8, (a0)2054; CHECK-NEXT: vle64.v v10, (a1)2055; CHECK-NEXT: vfdiv.vv v8, v8, v102056; CHECK-NEXT: vse64.v v8, (a0)2057; CHECK-NEXT: ret2058 %a = load <4 x double>, ptr %x2059 %b = load <4 x double>, ptr %y2060 %c = fdiv <4 x double> %a, %b2061 store <4 x double> %c, ptr %x2062 ret void2063}2064 2065define void @fneg_v16bf16(ptr %x) {2066; CHECK-LABEL: fneg_v16bf16:2067; CHECK: # %bb.0:2068; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma2069; CHECK-NEXT: vle16.v v8, (a0)2070; CHECK-NEXT: lui a1, 82071; CHECK-NEXT: vxor.vx v8, v8, a12072; CHECK-NEXT: vse16.v v8, (a0)2073; CHECK-NEXT: ret2074 %a = load <16 x bfloat>, ptr %x2075 %b = fneg <16 x bfloat> %a2076 store <16 x bfloat> %b, ptr %x2077 ret void2078}2079 2080define void @fneg_v16f16(ptr %x) {2081; ZVFH-LABEL: fneg_v16f16:2082; ZVFH: # %bb.0:2083; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma2084; ZVFH-NEXT: vle16.v v8, (a0)2085; ZVFH-NEXT: vfneg.v v8, v82086; ZVFH-NEXT: vse16.v v8, (a0)2087; ZVFH-NEXT: ret2088;2089; ZVFHMIN-LABEL: fneg_v16f16:2090; ZVFHMIN: # %bb.0:2091; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma2092; ZVFHMIN-NEXT: vle16.v v8, (a0)2093; ZVFHMIN-NEXT: lui a1, 82094; ZVFHMIN-NEXT: vxor.vx v8, v8, a12095; ZVFHMIN-NEXT: vse16.v v8, (a0)2096; ZVFHMIN-NEXT: ret2097 %a = load <16 x half>, ptr %x2098 %b = fneg <16 x half> %a2099 store <16 x half> %b, ptr %x2100 ret void2101}2102 2103define void @fneg_v8f32(ptr %x) {2104; CHECK-LABEL: fneg_v8f32:2105; CHECK: # %bb.0:2106; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma2107; CHECK-NEXT: vle32.v v8, (a0)2108; CHECK-NEXT: vfneg.v v8, v82109; CHECK-NEXT: vse32.v v8, (a0)2110; CHECK-NEXT: ret2111 %a = load <8 x float>, ptr %x2112 %b = fneg <8 x float> %a2113 store <8 x float> %b, ptr %x2114 ret void2115}2116 2117define void @fneg_v4f64(ptr %x) {2118; CHECK-LABEL: fneg_v4f64:2119; CHECK: # %bb.0:2120; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma2121; CHECK-NEXT: vle64.v v8, (a0)2122; CHECK-NEXT: vfneg.v v8, v82123; CHECK-NEXT: vse64.v v8, (a0)2124; CHECK-NEXT: ret2125 %a = load <4 x double>, ptr %x2126 %b = fneg <4 x double> %a2127 store <4 x double> %b, ptr %x2128 ret void2129}2130 2131define void @fma_v16bf16(ptr %x, ptr %y, ptr %z) {2132; CHECK-LABEL: fma_v16bf16:2133; CHECK: # %bb.0:2134; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma2135; CHECK-NEXT: vle16.v v12, (a2)2136; CHECK-NEXT: vle16.v v16, (a0)2137; CHECK-NEXT: vle16.v v20, (a1)2138; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v122139; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v162140; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v202141; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma2142; CHECK-NEXT: vfmadd.vv v16, v12, v82143; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma2144; CHECK-NEXT: vfncvtbf16.f.f.w v8, v162145; CHECK-NEXT: vse16.v v8, (a0)2146; CHECK-NEXT: ret2147 %a = load <16 x bfloat>, ptr %x2148 %b = load <16 x bfloat>, ptr %y2149 %c = load <16 x bfloat>, ptr %z2150 %d = call <16 x bfloat> @llvm.fma.v16bf16(<16 x bfloat> %a, <16 x bfloat> %b, <16 x bfloat> %c)2151 store <16 x bfloat> %d, ptr %x2152 ret void2153}2154 2155define void @fma_v16f16(ptr %x, ptr %y, ptr %z) {2156; ZVFH-LABEL: fma_v16f16:2157; ZVFH: # %bb.0:2158; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma2159; ZVFH-NEXT: vle16.v v8, (a0)2160; ZVFH-NEXT: vle16.v v10, (a1)2161; ZVFH-NEXT: vle16.v v12, (a2)2162; ZVFH-NEXT: vfmacc.vv v12, v8, v102163; ZVFH-NEXT: vse16.v v12, (a0)2164; ZVFH-NEXT: ret2165;2166; ZVFHMIN-LABEL: fma_v16f16:2167; ZVFHMIN: # %bb.0:2168; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma2169; ZVFHMIN-NEXT: vle16.v v12, (a2)2170; ZVFHMIN-NEXT: vle16.v v16, (a0)2171; ZVFHMIN-NEXT: vle16.v v20, (a1)2172; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v122173; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v162174; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v202175; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma2176; ZVFHMIN-NEXT: vfmadd.vv v16, v12, v82177; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma2178; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v162179; ZVFHMIN-NEXT: vse16.v v8, (a0)2180; ZVFHMIN-NEXT: ret2181 %a = load <16 x half>, ptr %x2182 %b = load <16 x half>, ptr %y2183 %c = load <16 x half>, ptr %z2184 %d = call <16 x half> @llvm.fma.v16f16(<16 x half> %a, <16 x half> %b, <16 x half> %c)2185 store <16 x half> %d, ptr %x2186 ret void2187}2188 2189define void @fma_v8f32(ptr %x, ptr %y, ptr %z) {2190; CHECK-LABEL: fma_v8f32:2191; CHECK: # %bb.0:2192; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma2193; CHECK-NEXT: vle32.v v8, (a0)2194; CHECK-NEXT: vle32.v v10, (a1)2195; CHECK-NEXT: vle32.v v12, (a2)2196; CHECK-NEXT: vfmacc.vv v12, v8, v102197; CHECK-NEXT: vse32.v v12, (a0)2198; CHECK-NEXT: ret2199 %a = load <8 x float>, ptr %x2200 %b = load <8 x float>, ptr %y2201 %c = load <8 x float>, ptr %z2202 %d = call <8 x float> @llvm.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c)2203 store <8 x float> %d, ptr %x2204 ret void2205}2206 2207define void @fma_v4f64(ptr %x, ptr %y, ptr %z) {2208; CHECK-LABEL: fma_v4f64:2209; CHECK: # %bb.0:2210; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma2211; CHECK-NEXT: vle64.v v8, (a0)2212; CHECK-NEXT: vle64.v v10, (a1)2213; CHECK-NEXT: vle64.v v12, (a2)2214; CHECK-NEXT: vfmacc.vv v12, v8, v102215; CHECK-NEXT: vse64.v v12, (a0)2216; CHECK-NEXT: ret2217 %a = load <4 x double>, ptr %x2218 %b = load <4 x double>, ptr %y2219 %c = load <4 x double>, ptr %z2220 %d = call <4 x double> @llvm.fma.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %c)2221 store <4 x double> %d, ptr %x2222 ret void2223}2224 2225define void @fadd_vf_v8bf16(ptr %x, bfloat %y) {2226; CHECK-LABEL: fadd_vf_v8bf16:2227; CHECK: # %bb.0:2228; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma2229; CHECK-NEXT: vle16.v v10, (a0)2230; CHECK-NEXT: fmv.x.w a1, fa02231; CHECK-NEXT: vmv.v.x v12, a12232; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v102233; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v122234; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma2235; CHECK-NEXT: vfadd.vv v8, v8, v102236; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma2237; CHECK-NEXT: vfncvtbf16.f.f.w v10, v82238; CHECK-NEXT: vse16.v v10, (a0)2239; CHECK-NEXT: ret2240 %a = load <8 x bfloat>, ptr %x2241 %b = insertelement <8 x bfloat> poison, bfloat %y, i32 02242 %c = shufflevector <8 x bfloat> %b, <8 x bfloat> poison, <8 x i32> zeroinitializer2243 %d = fadd <8 x bfloat> %a, %c2244 store <8 x bfloat> %d, ptr %x2245 ret void2246}2247 2248define void @fadd_vf_v6bf16(ptr %x, bfloat %y) {2249; CHECK-LABEL: fadd_vf_v6bf16:2250; CHECK: # %bb.0:2251; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma2252; CHECK-NEXT: vle16.v v10, (a0)2253; CHECK-NEXT: fmv.x.w a1, fa02254; CHECK-NEXT: vmv.v.x v12, a12255; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v102256; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v122257; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma2258; CHECK-NEXT: vfadd.vv v8, v8, v102259; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma2260; CHECK-NEXT: vfncvtbf16.f.f.w v10, v82261; CHECK-NEXT: vse16.v v10, (a0)2262; CHECK-NEXT: ret2263 %a = load <6 x bfloat>, ptr %x2264 %b = insertelement <6 x bfloat> poison, bfloat %y, i32 02265 %c = shufflevector <6 x bfloat> %b, <6 x bfloat> poison, <6 x i32> zeroinitializer2266 %d = fadd <6 x bfloat> %a, %c2267 store <6 x bfloat> %d, ptr %x2268 ret void2269}2270 2271define void @fadd_vf_v8f16(ptr %x, half %y) {2272; ZVFH-LABEL: fadd_vf_v8f16:2273; ZVFH: # %bb.0:2274; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma2275; ZVFH-NEXT: vle16.v v8, (a0)2276; ZVFH-NEXT: vfadd.vf v8, v8, fa02277; ZVFH-NEXT: vse16.v v8, (a0)2278; ZVFH-NEXT: ret2279;2280; ZVFHMIN-LABEL: fadd_vf_v8f16:2281; ZVFHMIN: # %bb.0:2282; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma2283; ZVFHMIN-NEXT: vle16.v v10, (a0)2284; ZVFHMIN-NEXT: fmv.x.w a1, fa02285; ZVFHMIN-NEXT: vmv.v.x v12, a12286; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v102287; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v122288; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma2289; ZVFHMIN-NEXT: vfadd.vv v8, v8, v102290; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma2291; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v82292; ZVFHMIN-NEXT: vse16.v v10, (a0)2293; ZVFHMIN-NEXT: ret2294 %a = load <8 x half>, ptr %x2295 %b = insertelement <8 x half> poison, half %y, i32 02296 %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer2297 %d = fadd <8 x half> %a, %c2298 store <8 x half> %d, ptr %x2299 ret void2300}2301 2302define void @fadd_vf_v6f16(ptr %x, half %y) {2303; ZVFH-LABEL: fadd_vf_v6f16:2304; ZVFH: # %bb.0:2305; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma2306; ZVFH-NEXT: vle16.v v8, (a0)2307; ZVFH-NEXT: vfadd.vf v8, v8, fa02308; ZVFH-NEXT: vse16.v v8, (a0)2309; ZVFH-NEXT: ret2310;2311; ZVFHMIN-LABEL: fadd_vf_v6f16:2312; ZVFHMIN: # %bb.0:2313; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma2314; ZVFHMIN-NEXT: vle16.v v10, (a0)2315; ZVFHMIN-NEXT: fmv.x.w a1, fa02316; ZVFHMIN-NEXT: vmv.v.x v12, a12317; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v102318; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v122319; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma2320; ZVFHMIN-NEXT: vfadd.vv v8, v8, v102321; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma2322; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v82323; ZVFHMIN-NEXT: vse16.v v10, (a0)2324; ZVFHMIN-NEXT: ret2325 %a = load <6 x half>, ptr %x2326 %b = insertelement <6 x half> poison, half %y, i32 02327 %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer2328 %d = fadd <6 x half> %a, %c2329 store <6 x half> %d, ptr %x2330 ret void2331}2332 2333define void @fadd_vf_v4f32(ptr %x, float %y) {2334; CHECK-LABEL: fadd_vf_v4f32:2335; CHECK: # %bb.0:2336; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma2337; CHECK-NEXT: vle32.v v8, (a0)2338; CHECK-NEXT: vfadd.vf v8, v8, fa02339; CHECK-NEXT: vse32.v v8, (a0)2340; CHECK-NEXT: ret2341 %a = load <4 x float>, ptr %x2342 %b = insertelement <4 x float> poison, float %y, i32 02343 %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer2344 %d = fadd <4 x float> %a, %c2345 store <4 x float> %d, ptr %x2346 ret void2347}2348 2349define void @fadd_vf_v2f64(ptr %x, double %y) {2350; CHECK-LABEL: fadd_vf_v2f64:2351; CHECK: # %bb.0:2352; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma2353; CHECK-NEXT: vle64.v v8, (a0)2354; CHECK-NEXT: vfadd.vf v8, v8, fa02355; CHECK-NEXT: vse64.v v8, (a0)2356; CHECK-NEXT: ret2357 %a = load <2 x double>, ptr %x2358 %b = insertelement <2 x double> poison, double %y, i32 02359 %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer2360 %d = fadd <2 x double> %a, %c2361 store <2 x double> %d, ptr %x2362 ret void2363}2364 2365define void @fadd_fv_v8bf16(ptr %x, bfloat %y) {2366; CHECK-LABEL: fadd_fv_v8bf16:2367; CHECK: # %bb.0:2368; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma2369; CHECK-NEXT: vle16.v v10, (a0)2370; CHECK-NEXT: fmv.x.w a1, fa02371; CHECK-NEXT: vmv.v.x v12, a12372; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v102373; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v122374; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma2375; CHECK-NEXT: vfadd.vv v8, v10, v82376; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma2377; CHECK-NEXT: vfncvtbf16.f.f.w v10, v82378; CHECK-NEXT: vse16.v v10, (a0)2379; CHECK-NEXT: ret2380 %a = load <8 x bfloat>, ptr %x2381 %b = insertelement <8 x bfloat> poison, bfloat %y, i32 02382 %c = shufflevector <8 x bfloat> %b, <8 x bfloat> poison, <8 x i32> zeroinitializer2383 %d = fadd <8 x bfloat> %c, %a2384 store <8 x bfloat> %d, ptr %x2385 ret void2386}2387 2388define void @fadd_fv_v6bf16(ptr %x, bfloat %y) {2389; CHECK-LABEL: fadd_fv_v6bf16:2390; CHECK: # %bb.0:2391; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma2392; CHECK-NEXT: vle16.v v10, (a0)2393; CHECK-NEXT: fmv.x.w a1, fa02394; CHECK-NEXT: vmv.v.x v12, a12395; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v102396; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v122397; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma2398; CHECK-NEXT: vfadd.vv v8, v10, v82399; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma2400; CHECK-NEXT: vfncvtbf16.f.f.w v10, v82401; CHECK-NEXT: vse16.v v10, (a0)2402; CHECK-NEXT: ret2403 %a = load <6 x bfloat>, ptr %x2404 %b = insertelement <6 x bfloat> poison, bfloat %y, i32 02405 %c = shufflevector <6 x bfloat> %b, <6 x bfloat> poison, <6 x i32> zeroinitializer2406 %d = fadd <6 x bfloat> %c, %a2407 store <6 x bfloat> %d, ptr %x2408 ret void2409}2410 2411define void @fadd_fv_v8f16(ptr %x, half %y) {2412; ZVFH-LABEL: fadd_fv_v8f16:2413; ZVFH: # %bb.0:2414; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma2415; ZVFH-NEXT: vle16.v v8, (a0)2416; ZVFH-NEXT: vfadd.vf v8, v8, fa02417; ZVFH-NEXT: vse16.v v8, (a0)2418; ZVFH-NEXT: ret2419;2420; ZVFHMIN-LABEL: fadd_fv_v8f16:2421; ZVFHMIN: # %bb.0:2422; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma2423; ZVFHMIN-NEXT: vle16.v v10, (a0)2424; ZVFHMIN-NEXT: fmv.x.w a1, fa02425; ZVFHMIN-NEXT: vmv.v.x v12, a12426; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v102427; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v122428; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma2429; ZVFHMIN-NEXT: vfadd.vv v8, v10, v82430; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma2431; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v82432; ZVFHMIN-NEXT: vse16.v v10, (a0)2433; ZVFHMIN-NEXT: ret2434 %a = load <8 x half>, ptr %x2435 %b = insertelement <8 x half> poison, half %y, i32 02436 %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer2437 %d = fadd <8 x half> %c, %a2438 store <8 x half> %d, ptr %x2439 ret void2440}2441 2442define void @fadd_fv_v6f16(ptr %x, half %y) {2443; ZVFH-LABEL: fadd_fv_v6f16:2444; ZVFH: # %bb.0:2445; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma2446; ZVFH-NEXT: vle16.v v8, (a0)2447; ZVFH-NEXT: vfadd.vf v8, v8, fa02448; ZVFH-NEXT: vse16.v v8, (a0)2449; ZVFH-NEXT: ret2450;2451; ZVFHMIN-LABEL: fadd_fv_v6f16:2452; ZVFHMIN: # %bb.0:2453; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma2454; ZVFHMIN-NEXT: vle16.v v10, (a0)2455; ZVFHMIN-NEXT: fmv.x.w a1, fa02456; ZVFHMIN-NEXT: vmv.v.x v12, a12457; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v102458; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v122459; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma2460; ZVFHMIN-NEXT: vfadd.vv v8, v10, v82461; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma2462; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v82463; ZVFHMIN-NEXT: vse16.v v10, (a0)2464; ZVFHMIN-NEXT: ret2465 %a = load <6 x half>, ptr %x2466 %b = insertelement <6 x half> poison, half %y, i32 02467 %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer2468 %d = fadd <6 x half> %c, %a2469 store <6 x half> %d, ptr %x2470 ret void2471}2472 2473define void @fadd_fv_v4f32(ptr %x, float %y) {2474; CHECK-LABEL: fadd_fv_v4f32:2475; CHECK: # %bb.0:2476; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma2477; CHECK-NEXT: vle32.v v8, (a0)2478; CHECK-NEXT: vfadd.vf v8, v8, fa02479; CHECK-NEXT: vse32.v v8, (a0)2480; CHECK-NEXT: ret2481 %a = load <4 x float>, ptr %x2482 %b = insertelement <4 x float> poison, float %y, i32 02483 %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer2484 %d = fadd <4 x float> %c, %a2485 store <4 x float> %d, ptr %x2486 ret void2487}2488 2489define void @fadd_fv_v2f64(ptr %x, double %y) {2490; CHECK-LABEL: fadd_fv_v2f64:2491; CHECK: # %bb.0:2492; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma2493; CHECK-NEXT: vle64.v v8, (a0)2494; CHECK-NEXT: vfadd.vf v8, v8, fa02495; CHECK-NEXT: vse64.v v8, (a0)2496; CHECK-NEXT: ret2497 %a = load <2 x double>, ptr %x2498 %b = insertelement <2 x double> poison, double %y, i32 02499 %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer2500 %d = fadd <2 x double> %c, %a2501 store <2 x double> %d, ptr %x2502 ret void2503}2504 2505define void @fsub_vf_v8bf16(ptr %x, bfloat %y) {2506; CHECK-LABEL: fsub_vf_v8bf16:2507; CHECK: # %bb.0:2508; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma2509; CHECK-NEXT: vle16.v v10, (a0)2510; CHECK-NEXT: fmv.x.w a1, fa02511; CHECK-NEXT: vmv.v.x v12, a12512; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v102513; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v122514; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma2515; CHECK-NEXT: vfsub.vv v8, v8, v102516; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma2517; CHECK-NEXT: vfncvtbf16.f.f.w v10, v82518; CHECK-NEXT: vse16.v v10, (a0)2519; CHECK-NEXT: ret2520 %a = load <8 x bfloat>, ptr %x2521 %b = insertelement <8 x bfloat> poison, bfloat %y, i32 02522 %c = shufflevector <8 x bfloat> %b, <8 x bfloat> poison, <8 x i32> zeroinitializer2523 %d = fsub <8 x bfloat> %a, %c2524 store <8 x bfloat> %d, ptr %x2525 ret void2526}2527 2528define void @fsub_vf_v6bf16(ptr %x, bfloat %y) {2529; CHECK-LABEL: fsub_vf_v6bf16:2530; CHECK: # %bb.0:2531; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma2532; CHECK-NEXT: vle16.v v10, (a0)2533; CHECK-NEXT: fmv.x.w a1, fa02534; CHECK-NEXT: vmv.v.x v12, a12535; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v102536; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v122537; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma2538; CHECK-NEXT: vfsub.vv v8, v8, v102539; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma2540; CHECK-NEXT: vfncvtbf16.f.f.w v10, v82541; CHECK-NEXT: vse16.v v10, (a0)2542; CHECK-NEXT: ret2543 %a = load <6 x bfloat>, ptr %x2544 %b = insertelement <6 x bfloat> poison, bfloat %y, i32 02545 %c = shufflevector <6 x bfloat> %b, <6 x bfloat> poison, <6 x i32> zeroinitializer2546 %d = fsub <6 x bfloat> %a, %c2547 store <6 x bfloat> %d, ptr %x2548 ret void2549}2550 2551define void @fsub_vf_v8f16(ptr %x, half %y) {2552; ZVFH-LABEL: fsub_vf_v8f16:2553; ZVFH: # %bb.0:2554; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma2555; ZVFH-NEXT: vle16.v v8, (a0)2556; ZVFH-NEXT: vfsub.vf v8, v8, fa02557; ZVFH-NEXT: vse16.v v8, (a0)2558; ZVFH-NEXT: ret2559;2560; ZVFHMIN-LABEL: fsub_vf_v8f16:2561; ZVFHMIN: # %bb.0:2562; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma2563; ZVFHMIN-NEXT: vle16.v v10, (a0)2564; ZVFHMIN-NEXT: fmv.x.w a1, fa02565; ZVFHMIN-NEXT: vmv.v.x v12, a12566; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v102567; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v122568; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma2569; ZVFHMIN-NEXT: vfsub.vv v8, v8, v102570; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma2571; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v82572; ZVFHMIN-NEXT: vse16.v v10, (a0)2573; ZVFHMIN-NEXT: ret2574 %a = load <8 x half>, ptr %x2575 %b = insertelement <8 x half> poison, half %y, i32 02576 %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer2577 %d = fsub <8 x half> %a, %c2578 store <8 x half> %d, ptr %x2579 ret void2580}2581 2582define void @fsub_vf_v6f16(ptr %x, half %y) {2583; ZVFH-LABEL: fsub_vf_v6f16:2584; ZVFH: # %bb.0:2585; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma2586; ZVFH-NEXT: vle16.v v8, (a0)2587; ZVFH-NEXT: vfsub.vf v8, v8, fa02588; ZVFH-NEXT: vse16.v v8, (a0)2589; ZVFH-NEXT: ret2590;2591; ZVFHMIN-LABEL: fsub_vf_v6f16:2592; ZVFHMIN: # %bb.0:2593; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma2594; ZVFHMIN-NEXT: vle16.v v10, (a0)2595; ZVFHMIN-NEXT: fmv.x.w a1, fa02596; ZVFHMIN-NEXT: vmv.v.x v12, a12597; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v102598; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v122599; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma2600; ZVFHMIN-NEXT: vfsub.vv v8, v8, v102601; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma2602; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v82603; ZVFHMIN-NEXT: vse16.v v10, (a0)2604; ZVFHMIN-NEXT: ret2605 %a = load <6 x half>, ptr %x2606 %b = insertelement <6 x half> poison, half %y, i32 02607 %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer2608 %d = fsub <6 x half> %a, %c2609 store <6 x half> %d, ptr %x2610 ret void2611}2612 2613define void @fsub_vf_v4f32(ptr %x, float %y) {2614; CHECK-LABEL: fsub_vf_v4f32:2615; CHECK: # %bb.0:2616; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma2617; CHECK-NEXT: vle32.v v8, (a0)2618; CHECK-NEXT: vfsub.vf v8, v8, fa02619; CHECK-NEXT: vse32.v v8, (a0)2620; CHECK-NEXT: ret2621 %a = load <4 x float>, ptr %x2622 %b = insertelement <4 x float> poison, float %y, i32 02623 %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer2624 %d = fsub <4 x float> %a, %c2625 store <4 x float> %d, ptr %x2626 ret void2627}2628 2629define void @fsub_vf_v2f64(ptr %x, double %y) {2630; CHECK-LABEL: fsub_vf_v2f64:2631; CHECK: # %bb.0:2632; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma2633; CHECK-NEXT: vle64.v v8, (a0)2634; CHECK-NEXT: vfsub.vf v8, v8, fa02635; CHECK-NEXT: vse64.v v8, (a0)2636; CHECK-NEXT: ret2637 %a = load <2 x double>, ptr %x2638 %b = insertelement <2 x double> poison, double %y, i32 02639 %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer2640 %d = fsub <2 x double> %a, %c2641 store <2 x double> %d, ptr %x2642 ret void2643}2644 2645define void @fsub_fv_v8bf16(ptr %x, bfloat %y) {2646; CHECK-LABEL: fsub_fv_v8bf16:2647; CHECK: # %bb.0:2648; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma2649; CHECK-NEXT: vle16.v v10, (a0)2650; CHECK-NEXT: fmv.x.w a1, fa02651; CHECK-NEXT: vmv.v.x v12, a12652; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v102653; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v122654; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma2655; CHECK-NEXT: vfsub.vv v8, v10, v82656; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma2657; CHECK-NEXT: vfncvtbf16.f.f.w v10, v82658; CHECK-NEXT: vse16.v v10, (a0)2659; CHECK-NEXT: ret2660 %a = load <8 x bfloat>, ptr %x2661 %b = insertelement <8 x bfloat> poison, bfloat %y, i32 02662 %c = shufflevector <8 x bfloat> %b, <8 x bfloat> poison, <8 x i32> zeroinitializer2663 %d = fsub <8 x bfloat> %c, %a2664 store <8 x bfloat> %d, ptr %x2665 ret void2666}2667 2668define void @fsub_fv_v6bf16(ptr %x, bfloat %y) {2669; CHECK-LABEL: fsub_fv_v6bf16:2670; CHECK: # %bb.0:2671; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma2672; CHECK-NEXT: vle16.v v10, (a0)2673; CHECK-NEXT: fmv.x.w a1, fa02674; CHECK-NEXT: vmv.v.x v12, a12675; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v102676; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v122677; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma2678; CHECK-NEXT: vfsub.vv v8, v10, v82679; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma2680; CHECK-NEXT: vfncvtbf16.f.f.w v10, v82681; CHECK-NEXT: vse16.v v10, (a0)2682; CHECK-NEXT: ret2683 %a = load <6 x bfloat>, ptr %x2684 %b = insertelement <6 x bfloat> poison, bfloat %y, i32 02685 %c = shufflevector <6 x bfloat> %b, <6 x bfloat> poison, <6 x i32> zeroinitializer2686 %d = fsub <6 x bfloat> %c, %a2687 store <6 x bfloat> %d, ptr %x2688 ret void2689}2690 2691define void @fsub_fv_v8f16(ptr %x, half %y) {2692; ZVFH-LABEL: fsub_fv_v8f16:2693; ZVFH: # %bb.0:2694; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma2695; ZVFH-NEXT: vle16.v v8, (a0)2696; ZVFH-NEXT: vfrsub.vf v8, v8, fa02697; ZVFH-NEXT: vse16.v v8, (a0)2698; ZVFH-NEXT: ret2699;2700; ZVFHMIN-LABEL: fsub_fv_v8f16:2701; ZVFHMIN: # %bb.0:2702; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma2703; ZVFHMIN-NEXT: vle16.v v10, (a0)2704; ZVFHMIN-NEXT: fmv.x.w a1, fa02705; ZVFHMIN-NEXT: vmv.v.x v12, a12706; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v102707; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v122708; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma2709; ZVFHMIN-NEXT: vfsub.vv v8, v10, v82710; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma2711; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v82712; ZVFHMIN-NEXT: vse16.v v10, (a0)2713; ZVFHMIN-NEXT: ret2714 %a = load <8 x half>, ptr %x2715 %b = insertelement <8 x half> poison, half %y, i32 02716 %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer2717 %d = fsub <8 x half> %c, %a2718 store <8 x half> %d, ptr %x2719 ret void2720}2721 2722define void @fsub_fv_v6f16(ptr %x, half %y) {2723; ZVFH-LABEL: fsub_fv_v6f16:2724; ZVFH: # %bb.0:2725; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma2726; ZVFH-NEXT: vle16.v v8, (a0)2727; ZVFH-NEXT: vfrsub.vf v8, v8, fa02728; ZVFH-NEXT: vse16.v v8, (a0)2729; ZVFH-NEXT: ret2730;2731; ZVFHMIN-LABEL: fsub_fv_v6f16:2732; ZVFHMIN: # %bb.0:2733; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma2734; ZVFHMIN-NEXT: vle16.v v10, (a0)2735; ZVFHMIN-NEXT: fmv.x.w a1, fa02736; ZVFHMIN-NEXT: vmv.v.x v12, a12737; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v102738; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v122739; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma2740; ZVFHMIN-NEXT: vfsub.vv v8, v10, v82741; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma2742; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v82743; ZVFHMIN-NEXT: vse16.v v10, (a0)2744; ZVFHMIN-NEXT: ret2745 %a = load <6 x half>, ptr %x2746 %b = insertelement <6 x half> poison, half %y, i32 02747 %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer2748 %d = fsub <6 x half> %c, %a2749 store <6 x half> %d, ptr %x2750 ret void2751}2752 2753define void @fsub_fv_v4f32(ptr %x, float %y) {2754; CHECK-LABEL: fsub_fv_v4f32:2755; CHECK: # %bb.0:2756; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma2757; CHECK-NEXT: vle32.v v8, (a0)2758; CHECK-NEXT: vfrsub.vf v8, v8, fa02759; CHECK-NEXT: vse32.v v8, (a0)2760; CHECK-NEXT: ret2761 %a = load <4 x float>, ptr %x2762 %b = insertelement <4 x float> poison, float %y, i32 02763 %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer2764 %d = fsub <4 x float> %c, %a2765 store <4 x float> %d, ptr %x2766 ret void2767}2768 2769define void @fsub_fv_v2f64(ptr %x, double %y) {2770; CHECK-LABEL: fsub_fv_v2f64:2771; CHECK: # %bb.0:2772; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma2773; CHECK-NEXT: vle64.v v8, (a0)2774; CHECK-NEXT: vfrsub.vf v8, v8, fa02775; CHECK-NEXT: vse64.v v8, (a0)2776; CHECK-NEXT: ret2777 %a = load <2 x double>, ptr %x2778 %b = insertelement <2 x double> poison, double %y, i32 02779 %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer2780 %d = fsub <2 x double> %c, %a2781 store <2 x double> %d, ptr %x2782 ret void2783}2784 2785define void @fmul_vf_v8bf16(ptr %x, bfloat %y) {2786; CHECK-LABEL: fmul_vf_v8bf16:2787; CHECK: # %bb.0:2788; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma2789; CHECK-NEXT: vle16.v v10, (a0)2790; CHECK-NEXT: fmv.x.w a1, fa02791; CHECK-NEXT: vmv.v.x v12, a12792; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v102793; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v122794; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma2795; CHECK-NEXT: vfmul.vv v8, v8, v102796; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma2797; CHECK-NEXT: vfncvtbf16.f.f.w v10, v82798; CHECK-NEXT: vse16.v v10, (a0)2799; CHECK-NEXT: ret2800 %a = load <8 x bfloat>, ptr %x2801 %b = insertelement <8 x bfloat> poison, bfloat %y, i32 02802 %c = shufflevector <8 x bfloat> %b, <8 x bfloat> poison, <8 x i32> zeroinitializer2803 %d = fmul <8 x bfloat> %a, %c2804 store <8 x bfloat> %d, ptr %x2805 ret void2806}2807 2808define void @fmul_vf_v6bf16(ptr %x, bfloat %y) {2809; CHECK-LABEL: fmul_vf_v6bf16:2810; CHECK: # %bb.0:2811; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma2812; CHECK-NEXT: vle16.v v10, (a0)2813; CHECK-NEXT: fmv.x.w a1, fa02814; CHECK-NEXT: vmv.v.x v12, a12815; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v102816; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v122817; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma2818; CHECK-NEXT: vfmul.vv v8, v8, v102819; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma2820; CHECK-NEXT: vfncvtbf16.f.f.w v10, v82821; CHECK-NEXT: vse16.v v10, (a0)2822; CHECK-NEXT: ret2823 %a = load <6 x bfloat>, ptr %x2824 %b = insertelement <6 x bfloat> poison, bfloat %y, i32 02825 %c = shufflevector <6 x bfloat> %b, <6 x bfloat> poison, <6 x i32> zeroinitializer2826 %d = fmul <6 x bfloat> %a, %c2827 store <6 x bfloat> %d, ptr %x2828 ret void2829}2830 2831define void @fmul_vf_v8f16(ptr %x, half %y) {2832; ZVFH-LABEL: fmul_vf_v8f16:2833; ZVFH: # %bb.0:2834; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma2835; ZVFH-NEXT: vle16.v v8, (a0)2836; ZVFH-NEXT: vfmul.vf v8, v8, fa02837; ZVFH-NEXT: vse16.v v8, (a0)2838; ZVFH-NEXT: ret2839;2840; ZVFHMIN-LABEL: fmul_vf_v8f16:2841; ZVFHMIN: # %bb.0:2842; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma2843; ZVFHMIN-NEXT: vle16.v v10, (a0)2844; ZVFHMIN-NEXT: fmv.x.w a1, fa02845; ZVFHMIN-NEXT: vmv.v.x v12, a12846; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v102847; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v122848; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma2849; ZVFHMIN-NEXT: vfmul.vv v8, v8, v102850; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma2851; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v82852; ZVFHMIN-NEXT: vse16.v v10, (a0)2853; ZVFHMIN-NEXT: ret2854 %a = load <8 x half>, ptr %x2855 %b = insertelement <8 x half> poison, half %y, i32 02856 %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer2857 %d = fmul <8 x half> %a, %c2858 store <8 x half> %d, ptr %x2859 ret void2860}2861 2862define void @fmul_vf_v6f16(ptr %x, half %y) {2863; ZVFH-LABEL: fmul_vf_v6f16:2864; ZVFH: # %bb.0:2865; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma2866; ZVFH-NEXT: vle16.v v8, (a0)2867; ZVFH-NEXT: vfmul.vf v8, v8, fa02868; ZVFH-NEXT: vse16.v v8, (a0)2869; ZVFH-NEXT: ret2870;2871; ZVFHMIN-LABEL: fmul_vf_v6f16:2872; ZVFHMIN: # %bb.0:2873; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma2874; ZVFHMIN-NEXT: vle16.v v10, (a0)2875; ZVFHMIN-NEXT: fmv.x.w a1, fa02876; ZVFHMIN-NEXT: vmv.v.x v12, a12877; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v102878; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v122879; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma2880; ZVFHMIN-NEXT: vfmul.vv v8, v8, v102881; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma2882; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v82883; ZVFHMIN-NEXT: vse16.v v10, (a0)2884; ZVFHMIN-NEXT: ret2885 %a = load <6 x half>, ptr %x2886 %b = insertelement <6 x half> poison, half %y, i32 02887 %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer2888 %d = fmul <6 x half> %a, %c2889 store <6 x half> %d, ptr %x2890 ret void2891}2892 2893define void @fmul_vf_v4f32(ptr %x, float %y) {2894; CHECK-LABEL: fmul_vf_v4f32:2895; CHECK: # %bb.0:2896; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma2897; CHECK-NEXT: vle32.v v8, (a0)2898; CHECK-NEXT: vfmul.vf v8, v8, fa02899; CHECK-NEXT: vse32.v v8, (a0)2900; CHECK-NEXT: ret2901 %a = load <4 x float>, ptr %x2902 %b = insertelement <4 x float> poison, float %y, i32 02903 %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer2904 %d = fmul <4 x float> %a, %c2905 store <4 x float> %d, ptr %x2906 ret void2907}2908 2909define void @fmul_vf_v2f64(ptr %x, double %y) {2910; CHECK-LABEL: fmul_vf_v2f64:2911; CHECK: # %bb.0:2912; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma2913; CHECK-NEXT: vle64.v v8, (a0)2914; CHECK-NEXT: vfmul.vf v8, v8, fa02915; CHECK-NEXT: vse64.v v8, (a0)2916; CHECK-NEXT: ret2917 %a = load <2 x double>, ptr %x2918 %b = insertelement <2 x double> poison, double %y, i32 02919 %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer2920 %d = fmul <2 x double> %a, %c2921 store <2 x double> %d, ptr %x2922 ret void2923}2924 2925define void @fmul_fv_v8bf16(ptr %x, bfloat %y) {2926; CHECK-LABEL: fmul_fv_v8bf16:2927; CHECK: # %bb.0:2928; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma2929; CHECK-NEXT: vle16.v v10, (a0)2930; CHECK-NEXT: fmv.x.w a1, fa02931; CHECK-NEXT: vmv.v.x v12, a12932; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v102933; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v122934; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma2935; CHECK-NEXT: vfmul.vv v8, v10, v82936; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma2937; CHECK-NEXT: vfncvtbf16.f.f.w v10, v82938; CHECK-NEXT: vse16.v v10, (a0)2939; CHECK-NEXT: ret2940 %a = load <8 x bfloat>, ptr %x2941 %b = insertelement <8 x bfloat> poison, bfloat %y, i32 02942 %c = shufflevector <8 x bfloat> %b, <8 x bfloat> poison, <8 x i32> zeroinitializer2943 %d = fmul <8 x bfloat> %c, %a2944 store <8 x bfloat> %d, ptr %x2945 ret void2946}2947 2948define void @fmul_fv_v6bf16(ptr %x, bfloat %y) {2949; CHECK-LABEL: fmul_fv_v6bf16:2950; CHECK: # %bb.0:2951; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma2952; CHECK-NEXT: vle16.v v10, (a0)2953; CHECK-NEXT: fmv.x.w a1, fa02954; CHECK-NEXT: vmv.v.x v12, a12955; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v102956; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v122957; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma2958; CHECK-NEXT: vfmul.vv v8, v10, v82959; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma2960; CHECK-NEXT: vfncvtbf16.f.f.w v10, v82961; CHECK-NEXT: vse16.v v10, (a0)2962; CHECK-NEXT: ret2963 %a = load <6 x bfloat>, ptr %x2964 %b = insertelement <6 x bfloat> poison, bfloat %y, i32 02965 %c = shufflevector <6 x bfloat> %b, <6 x bfloat> poison, <6 x i32> zeroinitializer2966 %d = fmul <6 x bfloat> %c, %a2967 store <6 x bfloat> %d, ptr %x2968 ret void2969}2970 2971define void @fmul_fv_v8f16(ptr %x, half %y) {2972; ZVFH-LABEL: fmul_fv_v8f16:2973; ZVFH: # %bb.0:2974; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma2975; ZVFH-NEXT: vle16.v v8, (a0)2976; ZVFH-NEXT: vfmul.vf v8, v8, fa02977; ZVFH-NEXT: vse16.v v8, (a0)2978; ZVFH-NEXT: ret2979;2980; ZVFHMIN-LABEL: fmul_fv_v8f16:2981; ZVFHMIN: # %bb.0:2982; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma2983; ZVFHMIN-NEXT: vle16.v v10, (a0)2984; ZVFHMIN-NEXT: fmv.x.w a1, fa02985; ZVFHMIN-NEXT: vmv.v.x v12, a12986; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v102987; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v122988; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma2989; ZVFHMIN-NEXT: vfmul.vv v8, v10, v82990; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma2991; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v82992; ZVFHMIN-NEXT: vse16.v v10, (a0)2993; ZVFHMIN-NEXT: ret2994 %a = load <8 x half>, ptr %x2995 %b = insertelement <8 x half> poison, half %y, i32 02996 %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer2997 %d = fmul <8 x half> %c, %a2998 store <8 x half> %d, ptr %x2999 ret void3000}3001 3002define void @fmul_fv_v6f16(ptr %x, half %y) {3003; ZVFH-LABEL: fmul_fv_v6f16:3004; ZVFH: # %bb.0:3005; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma3006; ZVFH-NEXT: vle16.v v8, (a0)3007; ZVFH-NEXT: vfmul.vf v8, v8, fa03008; ZVFH-NEXT: vse16.v v8, (a0)3009; ZVFH-NEXT: ret3010;3011; ZVFHMIN-LABEL: fmul_fv_v6f16:3012; ZVFHMIN: # %bb.0:3013; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma3014; ZVFHMIN-NEXT: vle16.v v10, (a0)3015; ZVFHMIN-NEXT: fmv.x.w a1, fa03016; ZVFHMIN-NEXT: vmv.v.x v12, a13017; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v103018; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v123019; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma3020; ZVFHMIN-NEXT: vfmul.vv v8, v10, v83021; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma3022; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v83023; ZVFHMIN-NEXT: vse16.v v10, (a0)3024; ZVFHMIN-NEXT: ret3025 %a = load <6 x half>, ptr %x3026 %b = insertelement <6 x half> poison, half %y, i32 03027 %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer3028 %d = fmul <6 x half> %c, %a3029 store <6 x half> %d, ptr %x3030 ret void3031}3032 3033define void @fmul_fv_v4f32(ptr %x, float %y) {3034; CHECK-LABEL: fmul_fv_v4f32:3035; CHECK: # %bb.0:3036; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma3037; CHECK-NEXT: vle32.v v8, (a0)3038; CHECK-NEXT: vfmul.vf v8, v8, fa03039; CHECK-NEXT: vse32.v v8, (a0)3040; CHECK-NEXT: ret3041 %a = load <4 x float>, ptr %x3042 %b = insertelement <4 x float> poison, float %y, i32 03043 %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer3044 %d = fmul <4 x float> %c, %a3045 store <4 x float> %d, ptr %x3046 ret void3047}3048 3049define void @fmul_fv_v2f64(ptr %x, double %y) {3050; CHECK-LABEL: fmul_fv_v2f64:3051; CHECK: # %bb.0:3052; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma3053; CHECK-NEXT: vle64.v v8, (a0)3054; CHECK-NEXT: vfmul.vf v8, v8, fa03055; CHECK-NEXT: vse64.v v8, (a0)3056; CHECK-NEXT: ret3057 %a = load <2 x double>, ptr %x3058 %b = insertelement <2 x double> poison, double %y, i32 03059 %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer3060 %d = fmul <2 x double> %c, %a3061 store <2 x double> %d, ptr %x3062 ret void3063}3064 3065define void @fdiv_vf_v8bf16(ptr %x, bfloat %y) {3066; CHECK-LABEL: fdiv_vf_v8bf16:3067; CHECK: # %bb.0:3068; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma3069; CHECK-NEXT: vle16.v v10, (a0)3070; CHECK-NEXT: fmv.x.w a1, fa03071; CHECK-NEXT: vmv.v.x v12, a13072; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v103073; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v123074; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma3075; CHECK-NEXT: vfdiv.vv v8, v8, v103076; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma3077; CHECK-NEXT: vfncvtbf16.f.f.w v10, v83078; CHECK-NEXT: vse16.v v10, (a0)3079; CHECK-NEXT: ret3080 %a = load <8 x bfloat>, ptr %x3081 %b = insertelement <8 x bfloat> poison, bfloat %y, i32 03082 %c = shufflevector <8 x bfloat> %b, <8 x bfloat> poison, <8 x i32> zeroinitializer3083 %d = fdiv <8 x bfloat> %a, %c3084 store <8 x bfloat> %d, ptr %x3085 ret void3086}3087 3088define void @fdiv_vf_v6bf16(ptr %x, bfloat %y) {3089; CHECK-LABEL: fdiv_vf_v6bf16:3090; CHECK: # %bb.0:3091; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma3092; CHECK-NEXT: vle16.v v10, (a0)3093; CHECK-NEXT: fmv.x.w a1, fa03094; CHECK-NEXT: vmv.v.x v12, a13095; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v103096; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v123097; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma3098; CHECK-NEXT: vfdiv.vv v8, v8, v103099; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma3100; CHECK-NEXT: vfncvtbf16.f.f.w v10, v83101; CHECK-NEXT: vse16.v v10, (a0)3102; CHECK-NEXT: ret3103 %a = load <6 x bfloat>, ptr %x3104 %b = insertelement <6 x bfloat> poison, bfloat %y, i32 03105 %c = shufflevector <6 x bfloat> %b, <6 x bfloat> poison, <6 x i32> zeroinitializer3106 %d = fdiv <6 x bfloat> %a, %c3107 store <6 x bfloat> %d, ptr %x3108 ret void3109}3110 3111define void @fdiv_vf_v8f16(ptr %x, half %y) {3112; ZVFH-LABEL: fdiv_vf_v8f16:3113; ZVFH: # %bb.0:3114; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma3115; ZVFH-NEXT: vle16.v v8, (a0)3116; ZVFH-NEXT: vfdiv.vf v8, v8, fa03117; ZVFH-NEXT: vse16.v v8, (a0)3118; ZVFH-NEXT: ret3119;3120; ZVFHMIN-LABEL: fdiv_vf_v8f16:3121; ZVFHMIN: # %bb.0:3122; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma3123; ZVFHMIN-NEXT: vle16.v v10, (a0)3124; ZVFHMIN-NEXT: fmv.x.w a1, fa03125; ZVFHMIN-NEXT: vmv.v.x v12, a13126; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v103127; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v123128; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma3129; ZVFHMIN-NEXT: vfdiv.vv v8, v8, v103130; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma3131; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v83132; ZVFHMIN-NEXT: vse16.v v10, (a0)3133; ZVFHMIN-NEXT: ret3134 %a = load <8 x half>, ptr %x3135 %b = insertelement <8 x half> poison, half %y, i32 03136 %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer3137 %d = fdiv <8 x half> %a, %c3138 store <8 x half> %d, ptr %x3139 ret void3140}3141 3142define void @fdiv_vf_v6f16(ptr %x, half %y) {3143; ZVFH-LABEL: fdiv_vf_v6f16:3144; ZVFH: # %bb.0:3145; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma3146; ZVFH-NEXT: vle16.v v8, (a0)3147; ZVFH-NEXT: vfdiv.vf v8, v8, fa03148; ZVFH-NEXT: vse16.v v8, (a0)3149; ZVFH-NEXT: ret3150;3151; ZVFHMIN-LABEL: fdiv_vf_v6f16:3152; ZVFHMIN: # %bb.0:3153; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma3154; ZVFHMIN-NEXT: vle16.v v10, (a0)3155; ZVFHMIN-NEXT: fmv.x.w a1, fa03156; ZVFHMIN-NEXT: vmv.v.x v12, a13157; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v103158; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v123159; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma3160; ZVFHMIN-NEXT: vfdiv.vv v8, v8, v103161; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma3162; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v83163; ZVFHMIN-NEXT: vse16.v v10, (a0)3164; ZVFHMIN-NEXT: ret3165 %a = load <6 x half>, ptr %x3166 %b = insertelement <6 x half> poison, half %y, i32 03167 %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer3168 %d = fdiv <6 x half> %a, %c3169 store <6 x half> %d, ptr %x3170 ret void3171}3172 3173define void @fdiv_vf_v4f32(ptr %x, float %y) {3174; CHECK-LABEL: fdiv_vf_v4f32:3175; CHECK: # %bb.0:3176; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma3177; CHECK-NEXT: vle32.v v8, (a0)3178; CHECK-NEXT: vfdiv.vf v8, v8, fa03179; CHECK-NEXT: vse32.v v8, (a0)3180; CHECK-NEXT: ret3181 %a = load <4 x float>, ptr %x3182 %b = insertelement <4 x float> poison, float %y, i32 03183 %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer3184 %d = fdiv <4 x float> %a, %c3185 store <4 x float> %d, ptr %x3186 ret void3187}3188 3189define void @fdiv_vf_v2f64(ptr %x, double %y) {3190; CHECK-LABEL: fdiv_vf_v2f64:3191; CHECK: # %bb.0:3192; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma3193; CHECK-NEXT: vle64.v v8, (a0)3194; CHECK-NEXT: vfdiv.vf v8, v8, fa03195; CHECK-NEXT: vse64.v v8, (a0)3196; CHECK-NEXT: ret3197 %a = load <2 x double>, ptr %x3198 %b = insertelement <2 x double> poison, double %y, i32 03199 %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer3200 %d = fdiv <2 x double> %a, %c3201 store <2 x double> %d, ptr %x3202 ret void3203}3204 3205define void @fdiv_fv_v8bf16(ptr %x, bfloat %y) {3206; CHECK-LABEL: fdiv_fv_v8bf16:3207; CHECK: # %bb.0:3208; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma3209; CHECK-NEXT: vle16.v v10, (a0)3210; CHECK-NEXT: fmv.x.w a1, fa03211; CHECK-NEXT: vmv.v.x v12, a13212; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v103213; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v123214; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma3215; CHECK-NEXT: vfdiv.vv v8, v10, v83216; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma3217; CHECK-NEXT: vfncvtbf16.f.f.w v10, v83218; CHECK-NEXT: vse16.v v10, (a0)3219; CHECK-NEXT: ret3220 %a = load <8 x bfloat>, ptr %x3221 %b = insertelement <8 x bfloat> poison, bfloat %y, i32 03222 %c = shufflevector <8 x bfloat> %b, <8 x bfloat> poison, <8 x i32> zeroinitializer3223 %d = fdiv <8 x bfloat> %c, %a3224 store <8 x bfloat> %d, ptr %x3225 ret void3226}3227 3228define void @fdiv_fv_v6bf16(ptr %x, bfloat %y) {3229; CHECK-LABEL: fdiv_fv_v6bf16:3230; CHECK: # %bb.0:3231; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma3232; CHECK-NEXT: vle16.v v10, (a0)3233; CHECK-NEXT: fmv.x.w a1, fa03234; CHECK-NEXT: vmv.v.x v12, a13235; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v103236; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v123237; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma3238; CHECK-NEXT: vfdiv.vv v8, v10, v83239; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma3240; CHECK-NEXT: vfncvtbf16.f.f.w v10, v83241; CHECK-NEXT: vse16.v v10, (a0)3242; CHECK-NEXT: ret3243 %a = load <6 x bfloat>, ptr %x3244 %b = insertelement <6 x bfloat> poison, bfloat %y, i32 03245 %c = shufflevector <6 x bfloat> %b, <6 x bfloat> poison, <6 x i32> zeroinitializer3246 %d = fdiv <6 x bfloat> %c, %a3247 store <6 x bfloat> %d, ptr %x3248 ret void3249}3250 3251define void @fdiv_fv_v8f16(ptr %x, half %y) {3252; ZVFH-LABEL: fdiv_fv_v8f16:3253; ZVFH: # %bb.0:3254; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma3255; ZVFH-NEXT: vle16.v v8, (a0)3256; ZVFH-NEXT: vfrdiv.vf v8, v8, fa03257; ZVFH-NEXT: vse16.v v8, (a0)3258; ZVFH-NEXT: ret3259;3260; ZVFHMIN-LABEL: fdiv_fv_v8f16:3261; ZVFHMIN: # %bb.0:3262; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma3263; ZVFHMIN-NEXT: vle16.v v10, (a0)3264; ZVFHMIN-NEXT: fmv.x.w a1, fa03265; ZVFHMIN-NEXT: vmv.v.x v12, a13266; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v103267; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v123268; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma3269; ZVFHMIN-NEXT: vfdiv.vv v8, v10, v83270; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma3271; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v83272; ZVFHMIN-NEXT: vse16.v v10, (a0)3273; ZVFHMIN-NEXT: ret3274 %a = load <8 x half>, ptr %x3275 %b = insertelement <8 x half> poison, half %y, i32 03276 %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer3277 %d = fdiv <8 x half> %c, %a3278 store <8 x half> %d, ptr %x3279 ret void3280}3281 3282define void @fdiv_fv_v6f16(ptr %x, half %y) {3283; ZVFH-LABEL: fdiv_fv_v6f16:3284; ZVFH: # %bb.0:3285; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma3286; ZVFH-NEXT: vle16.v v8, (a0)3287; ZVFH-NEXT: vfrdiv.vf v8, v8, fa03288; ZVFH-NEXT: vse16.v v8, (a0)3289; ZVFH-NEXT: ret3290;3291; ZVFHMIN-LABEL: fdiv_fv_v6f16:3292; ZVFHMIN: # %bb.0:3293; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma3294; ZVFHMIN-NEXT: vle16.v v10, (a0)3295; ZVFHMIN-NEXT: fmv.x.w a1, fa03296; ZVFHMIN-NEXT: vmv.v.x v12, a13297; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v103298; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v123299; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma3300; ZVFHMIN-NEXT: vfdiv.vv v8, v10, v83301; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma3302; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v83303; ZVFHMIN-NEXT: vse16.v v10, (a0)3304; ZVFHMIN-NEXT: ret3305 %a = load <6 x half>, ptr %x3306 %b = insertelement <6 x half> poison, half %y, i32 03307 %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer3308 %d = fdiv <6 x half> %c, %a3309 store <6 x half> %d, ptr %x3310 ret void3311}3312 3313define void @fdiv_fv_v4f32(ptr %x, float %y) {3314; CHECK-LABEL: fdiv_fv_v4f32:3315; CHECK: # %bb.0:3316; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma3317; CHECK-NEXT: vle32.v v8, (a0)3318; CHECK-NEXT: vfrdiv.vf v8, v8, fa03319; CHECK-NEXT: vse32.v v8, (a0)3320; CHECK-NEXT: ret3321 %a = load <4 x float>, ptr %x3322 %b = insertelement <4 x float> poison, float %y, i32 03323 %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer3324 %d = fdiv <4 x float> %c, %a3325 store <4 x float> %d, ptr %x3326 ret void3327}3328 3329define void @fdiv_fv_v2f64(ptr %x, double %y) {3330; CHECK-LABEL: fdiv_fv_v2f64:3331; CHECK: # %bb.0:3332; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma3333; CHECK-NEXT: vle64.v v8, (a0)3334; CHECK-NEXT: vfrdiv.vf v8, v8, fa03335; CHECK-NEXT: vse64.v v8, (a0)3336; CHECK-NEXT: ret3337 %a = load <2 x double>, ptr %x3338 %b = insertelement <2 x double> poison, double %y, i32 03339 %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer3340 %d = fdiv <2 x double> %c, %a3341 store <2 x double> %d, ptr %x3342 ret void3343}3344 3345define void @fma_vf_v8bf16(ptr %x, ptr %y, bfloat %z) {3346; CHECK-LABEL: fma_vf_v8bf16:3347; CHECK: # %bb.0:3348; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma3349; CHECK-NEXT: vle16.v v10, (a1)3350; CHECK-NEXT: vle16.v v12, (a0)3351; CHECK-NEXT: fmv.x.w a1, fa03352; CHECK-NEXT: vmv.v.x v14, a13353; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v103354; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v123355; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v143356; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma3357; CHECK-NEXT: vfmadd.vv v12, v10, v83358; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma3359; CHECK-NEXT: vfncvtbf16.f.f.w v8, v123360; CHECK-NEXT: vse16.v v8, (a0)3361; CHECK-NEXT: ret3362 %a = load <8 x bfloat>, ptr %x3363 %b = load <8 x bfloat>, ptr %y3364 %c = insertelement <8 x bfloat> poison, bfloat %z, i32 03365 %d = shufflevector <8 x bfloat> %c, <8 x bfloat> poison, <8 x i32> zeroinitializer3366 %e = call <8 x bfloat> @llvm.fma.v8bf16(<8 x bfloat> %a, <8 x bfloat> %d, <8 x bfloat> %b)3367 store <8 x bfloat> %e, ptr %x3368 ret void3369}3370 3371define void @fma_vf_v6bf16(ptr %x, ptr %y, bfloat %z) {3372; CHECK-LABEL: fma_vf_v6bf16:3373; CHECK: # %bb.0:3374; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma3375; CHECK-NEXT: vle16.v v10, (a1)3376; CHECK-NEXT: vle16.v v12, (a0)3377; CHECK-NEXT: fmv.x.w a1, fa03378; CHECK-NEXT: vmv.v.x v14, a13379; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v103380; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v123381; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v143382; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma3383; CHECK-NEXT: vfmadd.vv v12, v10, v83384; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma3385; CHECK-NEXT: vfncvtbf16.f.f.w v8, v123386; CHECK-NEXT: vse16.v v8, (a0)3387; CHECK-NEXT: ret3388 %a = load <6 x bfloat>, ptr %x3389 %b = load <6 x bfloat>, ptr %y3390 %c = insertelement <6 x bfloat> poison, bfloat %z, i32 03391 %d = shufflevector <6 x bfloat> %c, <6 x bfloat> poison, <6 x i32> zeroinitializer3392 %e = call <6 x bfloat> @llvm.fma.v6bf16(<6 x bfloat> %a, <6 x bfloat> %d, <6 x bfloat> %b)3393 store <6 x bfloat> %e, ptr %x3394 ret void3395}3396 3397define void @fma_vf_v8f16(ptr %x, ptr %y, half %z) {3398; ZVFH-LABEL: fma_vf_v8f16:3399; ZVFH: # %bb.0:3400; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma3401; ZVFH-NEXT: vle16.v v8, (a0)3402; ZVFH-NEXT: vle16.v v9, (a1)3403; ZVFH-NEXT: vfmacc.vf v9, fa0, v83404; ZVFH-NEXT: vse16.v v9, (a0)3405; ZVFH-NEXT: ret3406;3407; ZVFHMIN-LABEL: fma_vf_v8f16:3408; ZVFHMIN: # %bb.0:3409; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma3410; ZVFHMIN-NEXT: vle16.v v10, (a1)3411; ZVFHMIN-NEXT: vle16.v v12, (a0)3412; ZVFHMIN-NEXT: fmv.x.w a1, fa03413; ZVFHMIN-NEXT: vmv.v.x v14, a13414; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v103415; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v123416; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v143417; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma3418; ZVFHMIN-NEXT: vfmadd.vv v12, v10, v83419; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma3420; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v123421; ZVFHMIN-NEXT: vse16.v v8, (a0)3422; ZVFHMIN-NEXT: ret3423 %a = load <8 x half>, ptr %x3424 %b = load <8 x half>, ptr %y3425 %c = insertelement <8 x half> poison, half %z, i32 03426 %d = shufflevector <8 x half> %c, <8 x half> poison, <8 x i32> zeroinitializer3427 %e = call <8 x half> @llvm.fma.v8f16(<8 x half> %a, <8 x half> %d, <8 x half> %b)3428 store <8 x half> %e, ptr %x3429 ret void3430}3431 3432define void @fma_vf_v6f16(ptr %x, ptr %y, half %z) {3433; ZVFH-LABEL: fma_vf_v6f16:3434; ZVFH: # %bb.0:3435; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma3436; ZVFH-NEXT: vle16.v v8, (a0)3437; ZVFH-NEXT: vle16.v v9, (a1)3438; ZVFH-NEXT: vfmacc.vf v9, fa0, v83439; ZVFH-NEXT: vse16.v v9, (a0)3440; ZVFH-NEXT: ret3441;3442; ZVFHMIN-LABEL: fma_vf_v6f16:3443; ZVFHMIN: # %bb.0:3444; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma3445; ZVFHMIN-NEXT: vle16.v v10, (a1)3446; ZVFHMIN-NEXT: vle16.v v12, (a0)3447; ZVFHMIN-NEXT: fmv.x.w a1, fa03448; ZVFHMIN-NEXT: vmv.v.x v14, a13449; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v103450; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v123451; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v143452; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma3453; ZVFHMIN-NEXT: vfmadd.vv v12, v10, v83454; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma3455; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v123456; ZVFHMIN-NEXT: vse16.v v8, (a0)3457; ZVFHMIN-NEXT: ret3458 %a = load <6 x half>, ptr %x3459 %b = load <6 x half>, ptr %y3460 %c = insertelement <6 x half> poison, half %z, i32 03461 %d = shufflevector <6 x half> %c, <6 x half> poison, <6 x i32> zeroinitializer3462 %e = call <6 x half> @llvm.fma.v6f16(<6 x half> %a, <6 x half> %d, <6 x half> %b)3463 store <6 x half> %e, ptr %x3464 ret void3465}3466 3467define void @fma_vf_v4f32(ptr %x, ptr %y, float %z) {3468; CHECK-LABEL: fma_vf_v4f32:3469; CHECK: # %bb.0:3470; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma3471; CHECK-NEXT: vle32.v v8, (a0)3472; CHECK-NEXT: vle32.v v9, (a1)3473; CHECK-NEXT: vfmacc.vf v9, fa0, v83474; CHECK-NEXT: vse32.v v9, (a0)3475; CHECK-NEXT: ret3476 %a = load <4 x float>, ptr %x3477 %b = load <4 x float>, ptr %y3478 %c = insertelement <4 x float> poison, float %z, i32 03479 %d = shufflevector <4 x float> %c, <4 x float> poison, <4 x i32> zeroinitializer3480 %e = call <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %d, <4 x float> %b)3481 store <4 x float> %e, ptr %x3482 ret void3483}3484 3485define void @fma_vf_v2f64(ptr %x, ptr %y, double %z) {3486; CHECK-LABEL: fma_vf_v2f64:3487; CHECK: # %bb.0:3488; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma3489; CHECK-NEXT: vle64.v v8, (a0)3490; CHECK-NEXT: vle64.v v9, (a1)3491; CHECK-NEXT: vfmacc.vf v9, fa0, v83492; CHECK-NEXT: vse64.v v9, (a0)3493; CHECK-NEXT: ret3494 %a = load <2 x double>, ptr %x3495 %b = load <2 x double>, ptr %y3496 %c = insertelement <2 x double> poison, double %z, i32 03497 %d = shufflevector <2 x double> %c, <2 x double> poison, <2 x i32> zeroinitializer3498 %e = call <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> %d, <2 x double> %b)3499 store <2 x double> %e, ptr %x3500 ret void3501}3502 3503define void @fma_fv_v8bf16(ptr %x, ptr %y, bfloat %z) {3504; CHECK-LABEL: fma_fv_v8bf16:3505; CHECK: # %bb.0:3506; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma3507; CHECK-NEXT: vle16.v v10, (a1)3508; CHECK-NEXT: vle16.v v12, (a0)3509; CHECK-NEXT: fmv.x.w a1, fa03510; CHECK-NEXT: vmv.v.x v14, a13511; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v103512; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v123513; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v143514; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma3515; CHECK-NEXT: vfmadd.vv v12, v10, v83516; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma3517; CHECK-NEXT: vfncvtbf16.f.f.w v8, v123518; CHECK-NEXT: vse16.v v8, (a0)3519; CHECK-NEXT: ret3520 %a = load <8 x bfloat>, ptr %x3521 %b = load <8 x bfloat>, ptr %y3522 %c = insertelement <8 x bfloat> poison, bfloat %z, i32 03523 %d = shufflevector <8 x bfloat> %c, <8 x bfloat> poison, <8 x i32> zeroinitializer3524 %e = call <8 x bfloat> @llvm.fma.v8bf16(<8 x bfloat> %d, <8 x bfloat> %a, <8 x bfloat> %b)3525 store <8 x bfloat> %e, ptr %x3526 ret void3527}3528 3529define void @fma_fv_v6bf16(ptr %x, ptr %y, bfloat %z) {3530; CHECK-LABEL: fma_fv_v6bf16:3531; CHECK: # %bb.0:3532; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma3533; CHECK-NEXT: vle16.v v10, (a1)3534; CHECK-NEXT: vle16.v v12, (a0)3535; CHECK-NEXT: fmv.x.w a1, fa03536; CHECK-NEXT: vmv.v.x v14, a13537; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v103538; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v123539; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v143540; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma3541; CHECK-NEXT: vfmadd.vv v12, v10, v83542; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma3543; CHECK-NEXT: vfncvtbf16.f.f.w v8, v123544; CHECK-NEXT: vse16.v v8, (a0)3545; CHECK-NEXT: ret3546 %a = load <6 x bfloat>, ptr %x3547 %b = load <6 x bfloat>, ptr %y3548 %c = insertelement <6 x bfloat> poison, bfloat %z, i32 03549 %d = shufflevector <6 x bfloat> %c, <6 x bfloat> poison, <6 x i32> zeroinitializer3550 %e = call <6 x bfloat> @llvm.fma.v6bf16(<6 x bfloat> %d, <6 x bfloat> %a, <6 x bfloat> %b)3551 store <6 x bfloat> %e, ptr %x3552 ret void3553}3554 3555define void @fma_fv_v8f16(ptr %x, ptr %y, half %z) {3556; ZVFH-LABEL: fma_fv_v8f16:3557; ZVFH: # %bb.0:3558; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma3559; ZVFH-NEXT: vle16.v v8, (a0)3560; ZVFH-NEXT: vle16.v v9, (a1)3561; ZVFH-NEXT: vfmacc.vf v9, fa0, v83562; ZVFH-NEXT: vse16.v v9, (a0)3563; ZVFH-NEXT: ret3564;3565; ZVFHMIN-LABEL: fma_fv_v8f16:3566; ZVFHMIN: # %bb.0:3567; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma3568; ZVFHMIN-NEXT: vle16.v v10, (a1)3569; ZVFHMIN-NEXT: vle16.v v12, (a0)3570; ZVFHMIN-NEXT: fmv.x.w a1, fa03571; ZVFHMIN-NEXT: vmv.v.x v14, a13572; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v103573; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v123574; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v143575; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma3576; ZVFHMIN-NEXT: vfmadd.vv v12, v10, v83577; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma3578; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v123579; ZVFHMIN-NEXT: vse16.v v8, (a0)3580; ZVFHMIN-NEXT: ret3581 %a = load <8 x half>, ptr %x3582 %b = load <8 x half>, ptr %y3583 %c = insertelement <8 x half> poison, half %z, i32 03584 %d = shufflevector <8 x half> %c, <8 x half> poison, <8 x i32> zeroinitializer3585 %e = call <8 x half> @llvm.fma.v8f16(<8 x half> %d, <8 x half> %a, <8 x half> %b)3586 store <8 x half> %e, ptr %x3587 ret void3588}3589 3590define void @fma_fv_v6f16(ptr %x, ptr %y, half %z) {3591; ZVFH-LABEL: fma_fv_v6f16:3592; ZVFH: # %bb.0:3593; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma3594; ZVFH-NEXT: vle16.v v8, (a0)3595; ZVFH-NEXT: vle16.v v9, (a1)3596; ZVFH-NEXT: vfmacc.vf v9, fa0, v83597; ZVFH-NEXT: vse16.v v9, (a0)3598; ZVFH-NEXT: ret3599;3600; ZVFHMIN-LABEL: fma_fv_v6f16:3601; ZVFHMIN: # %bb.0:3602; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma3603; ZVFHMIN-NEXT: vle16.v v10, (a1)3604; ZVFHMIN-NEXT: vle16.v v12, (a0)3605; ZVFHMIN-NEXT: fmv.x.w a1, fa03606; ZVFHMIN-NEXT: vmv.v.x v14, a13607; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v103608; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v123609; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v143610; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma3611; ZVFHMIN-NEXT: vfmadd.vv v12, v10, v83612; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma3613; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v123614; ZVFHMIN-NEXT: vse16.v v8, (a0)3615; ZVFHMIN-NEXT: ret3616 %a = load <6 x half>, ptr %x3617 %b = load <6 x half>, ptr %y3618 %c = insertelement <6 x half> poison, half %z, i32 03619 %d = shufflevector <6 x half> %c, <6 x half> poison, <6 x i32> zeroinitializer3620 %e = call <6 x half> @llvm.fma.v6f16(<6 x half> %d, <6 x half> %a, <6 x half> %b)3621 store <6 x half> %e, ptr %x3622 ret void3623}3624 3625define void @fma_fv_v4f32(ptr %x, ptr %y, float %z) {3626; CHECK-LABEL: fma_fv_v4f32:3627; CHECK: # %bb.0:3628; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma3629; CHECK-NEXT: vle32.v v8, (a0)3630; CHECK-NEXT: vle32.v v9, (a1)3631; CHECK-NEXT: vfmacc.vf v9, fa0, v83632; CHECK-NEXT: vse32.v v9, (a0)3633; CHECK-NEXT: ret3634 %a = load <4 x float>, ptr %x3635 %b = load <4 x float>, ptr %y3636 %c = insertelement <4 x float> poison, float %z, i32 03637 %d = shufflevector <4 x float> %c, <4 x float> poison, <4 x i32> zeroinitializer3638 %e = call <4 x float> @llvm.fma.v4f32(<4 x float> %d, <4 x float> %a, <4 x float> %b)3639 store <4 x float> %e, ptr %x3640 ret void3641}3642 3643define void @fma_fv_v2f64(ptr %x, ptr %y, double %z) {3644; CHECK-LABEL: fma_fv_v2f64:3645; CHECK: # %bb.0:3646; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma3647; CHECK-NEXT: vle64.v v8, (a0)3648; CHECK-NEXT: vle64.v v9, (a1)3649; CHECK-NEXT: vfmacc.vf v9, fa0, v83650; CHECK-NEXT: vse64.v v9, (a0)3651; CHECK-NEXT: ret3652 %a = load <2 x double>, ptr %x3653 %b = load <2 x double>, ptr %y3654 %c = insertelement <2 x double> poison, double %z, i32 03655 %d = shufflevector <2 x double> %c, <2 x double> poison, <2 x i32> zeroinitializer3656 %e = call <2 x double> @llvm.fma.v2f64(<2 x double> %d, <2 x double> %a, <2 x double> %b)3657 store <2 x double> %e, ptr %x3658 ret void3659}3660 3661define void @fmsub_vf_v8bf16(ptr %x, ptr %y, bfloat %z) {3662; CHECK-LABEL: fmsub_vf_v8bf16:3663; CHECK: # %bb.0:3664; CHECK-NEXT: fmv.x.w a2, fa03665; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma3666; CHECK-NEXT: vle16.v v8, (a1)3667; CHECK-NEXT: vle16.v v10, (a0)3668; CHECK-NEXT: lui a1, 83669; CHECK-NEXT: vmv.v.x v14, a23670; CHECK-NEXT: vxor.vx v12, v8, a13671; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v103672; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v123673; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v143674; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma3675; CHECK-NEXT: vfmadd.vv v12, v8, v103676; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma3677; CHECK-NEXT: vfncvtbf16.f.f.w v8, v123678; CHECK-NEXT: vse16.v v8, (a0)3679; CHECK-NEXT: ret3680 %a = load <8 x bfloat>, ptr %x3681 %b = load <8 x bfloat>, ptr %y3682 %c = insertelement <8 x bfloat> poison, bfloat %z, i32 03683 %d = shufflevector <8 x bfloat> %c, <8 x bfloat> poison, <8 x i32> zeroinitializer3684 %neg = fneg <8 x bfloat> %b3685 %e = call <8 x bfloat> @llvm.fma.v8bf16(<8 x bfloat> %a, <8 x bfloat> %d, <8 x bfloat> %neg)3686 store <8 x bfloat> %e, ptr %x3687 ret void3688}3689 3690define void @fmsub_vf_v6bf16(ptr %x, ptr %y, bfloat %z) {3691; CHECK-LABEL: fmsub_vf_v6bf16:3692; CHECK: # %bb.0:3693; CHECK-NEXT: fmv.x.w a2, fa03694; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma3695; CHECK-NEXT: vle16.v v8, (a1)3696; CHECK-NEXT: vle16.v v10, (a0)3697; CHECK-NEXT: lui a1, 83698; CHECK-NEXT: vmv.v.x v14, a23699; CHECK-NEXT: vxor.vx v12, v8, a13700; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v103701; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v123702; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v143703; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma3704; CHECK-NEXT: vfmadd.vv v12, v8, v103705; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma3706; CHECK-NEXT: vfncvtbf16.f.f.w v8, v123707; CHECK-NEXT: vse16.v v8, (a0)3708; CHECK-NEXT: ret3709 %a = load <6 x bfloat>, ptr %x3710 %b = load <6 x bfloat>, ptr %y3711 %c = insertelement <6 x bfloat> poison, bfloat %z, i32 03712 %d = shufflevector <6 x bfloat> %c, <6 x bfloat> poison, <6 x i32> zeroinitializer3713 %neg = fneg <6 x bfloat> %b3714 %e = call <6 x bfloat> @llvm.fma.v6bf16(<6 x bfloat> %a, <6 x bfloat> %d, <6 x bfloat> %neg)3715 store <6 x bfloat> %e, ptr %x3716 ret void3717}3718 3719define void @fmsub_vf_v8f16(ptr %x, ptr %y, half %z) {3720; ZVFH-LABEL: fmsub_vf_v8f16:3721; ZVFH: # %bb.0:3722; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma3723; ZVFH-NEXT: vle16.v v8, (a0)3724; ZVFH-NEXT: vle16.v v9, (a1)3725; ZVFH-NEXT: vfmsac.vf v9, fa0, v83726; ZVFH-NEXT: vse16.v v9, (a0)3727; ZVFH-NEXT: ret3728;3729; ZVFHMIN-LABEL: fmsub_vf_v8f16:3730; ZVFHMIN: # %bb.0:3731; ZVFHMIN-NEXT: fmv.x.w a2, fa03732; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma3733; ZVFHMIN-NEXT: vle16.v v8, (a1)3734; ZVFHMIN-NEXT: vle16.v v10, (a0)3735; ZVFHMIN-NEXT: lui a1, 83736; ZVFHMIN-NEXT: vmv.v.x v14, a23737; ZVFHMIN-NEXT: vxor.vx v12, v8, a13738; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v103739; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v123740; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v143741; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma3742; ZVFHMIN-NEXT: vfmadd.vv v12, v8, v103743; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma3744; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v123745; ZVFHMIN-NEXT: vse16.v v8, (a0)3746; ZVFHMIN-NEXT: ret3747 %a = load <8 x half>, ptr %x3748 %b = load <8 x half>, ptr %y3749 %c = insertelement <8 x half> poison, half %z, i32 03750 %d = shufflevector <8 x half> %c, <8 x half> poison, <8 x i32> zeroinitializer3751 %neg = fneg <8 x half> %b3752 %e = call <8 x half> @llvm.fma.v8f16(<8 x half> %a, <8 x half> %d, <8 x half> %neg)3753 store <8 x half> %e, ptr %x3754 ret void3755}3756 3757define void @fmsub_vf_v6f16(ptr %x, ptr %y, half %z) {3758; ZVFH-LABEL: fmsub_vf_v6f16:3759; ZVFH: # %bb.0:3760; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma3761; ZVFH-NEXT: vle16.v v8, (a0)3762; ZVFH-NEXT: vle16.v v9, (a1)3763; ZVFH-NEXT: vfmsac.vf v9, fa0, v83764; ZVFH-NEXT: vse16.v v9, (a0)3765; ZVFH-NEXT: ret3766;3767; ZVFHMIN-LABEL: fmsub_vf_v6f16:3768; ZVFHMIN: # %bb.0:3769; ZVFHMIN-NEXT: fmv.x.w a2, fa03770; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma3771; ZVFHMIN-NEXT: vle16.v v8, (a1)3772; ZVFHMIN-NEXT: vle16.v v10, (a0)3773; ZVFHMIN-NEXT: lui a1, 83774; ZVFHMIN-NEXT: vmv.v.x v14, a23775; ZVFHMIN-NEXT: vxor.vx v12, v8, a13776; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v103777; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v123778; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v143779; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma3780; ZVFHMIN-NEXT: vfmadd.vv v12, v8, v103781; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma3782; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v123783; ZVFHMIN-NEXT: vse16.v v8, (a0)3784; ZVFHMIN-NEXT: ret3785 %a = load <6 x half>, ptr %x3786 %b = load <6 x half>, ptr %y3787 %c = insertelement <6 x half> poison, half %z, i32 03788 %d = shufflevector <6 x half> %c, <6 x half> poison, <6 x i32> zeroinitializer3789 %neg = fneg <6 x half> %b3790 %e = call <6 x half> @llvm.fma.v6f16(<6 x half> %a, <6 x half> %d, <6 x half> %neg)3791 store <6 x half> %e, ptr %x3792 ret void3793}3794 3795define void @fnmsub_vf_v4f32(ptr %x, ptr %y, float %z) {3796; CHECK-LABEL: fnmsub_vf_v4f32:3797; CHECK: # %bb.0:3798; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma3799; CHECK-NEXT: vle32.v v8, (a0)3800; CHECK-NEXT: vle32.v v9, (a1)3801; CHECK-NEXT: vfnmsac.vf v9, fa0, v83802; CHECK-NEXT: vse32.v v9, (a0)3803; CHECK-NEXT: ret3804 %a = load <4 x float>, ptr %x3805 %b = load <4 x float>, ptr %y3806 %c = insertelement <4 x float> poison, float %z, i32 03807 %d = shufflevector <4 x float> %c, <4 x float> poison, <4 x i32> zeroinitializer3808 %neg = fneg <4 x float> %a3809 %e = call <4 x float> @llvm.fma.v4f32(<4 x float> %neg, <4 x float> %d, <4 x float> %b)3810 store <4 x float> %e, ptr %x3811 ret void3812}3813 3814define void @fnmadd_vf_v2f64(ptr %x, ptr %y, double %z) {3815; CHECK-LABEL: fnmadd_vf_v2f64:3816; CHECK: # %bb.0:3817; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma3818; CHECK-NEXT: vle64.v v8, (a0)3819; CHECK-NEXT: vle64.v v9, (a1)3820; CHECK-NEXT: vfnmacc.vf v9, fa0, v83821; CHECK-NEXT: vse64.v v9, (a0)3822; CHECK-NEXT: ret3823 %a = load <2 x double>, ptr %x3824 %b = load <2 x double>, ptr %y3825 %c = insertelement <2 x double> poison, double %z, i32 03826 %d = shufflevector <2 x double> %c, <2 x double> poison, <2 x i32> zeroinitializer3827 %neg = fneg <2 x double> %a3828 %neg2 = fneg <2 x double> %b3829 %e = call <2 x double> @llvm.fma.v2f64(<2 x double> %neg, <2 x double> %d, <2 x double> %neg2)3830 store <2 x double> %e, ptr %x3831 ret void3832}3833 3834define void @fnmsub_fv_v4f32(ptr %x, ptr %y, float %z) {3835; CHECK-LABEL: fnmsub_fv_v4f32:3836; CHECK: # %bb.0:3837; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma3838; CHECK-NEXT: vle32.v v8, (a0)3839; CHECK-NEXT: vle32.v v9, (a1)3840; CHECK-NEXT: vfnmsac.vf v9, fa0, v83841; CHECK-NEXT: vse32.v v9, (a0)3842; CHECK-NEXT: ret3843 %a = load <4 x float>, ptr %x3844 %b = load <4 x float>, ptr %y3845 %c = insertelement <4 x float> poison, float %z, i32 03846 %d = shufflevector <4 x float> %c, <4 x float> poison, <4 x i32> zeroinitializer3847 %neg = fneg <4 x float> %d3848 %e = call <4 x float> @llvm.fma.v4f32(<4 x float> %neg, <4 x float> %a, <4 x float> %b)3849 store <4 x float> %e, ptr %x3850 ret void3851}3852 3853define void @fnmadd_fv_v2f64(ptr %x, ptr %y, double %z) {3854; CHECK-LABEL: fnmadd_fv_v2f64:3855; CHECK: # %bb.0:3856; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma3857; CHECK-NEXT: vle64.v v8, (a0)3858; CHECK-NEXT: vle64.v v9, (a1)3859; CHECK-NEXT: vfnmacc.vf v9, fa0, v83860; CHECK-NEXT: vse64.v v9, (a0)3861; CHECK-NEXT: ret3862 %a = load <2 x double>, ptr %x3863 %b = load <2 x double>, ptr %y3864 %c = insertelement <2 x double> poison, double %z, i32 03865 %d = shufflevector <2 x double> %c, <2 x double> poison, <2 x i32> zeroinitializer3866 %neg = fneg <2 x double> %d3867 %neg2 = fneg <2 x double> %b3868 %e = call <2 x double> @llvm.fma.v2f64(<2 x double> %neg, <2 x double> %a, <2 x double> %neg2)3869 store <2 x double> %e, ptr %x3870 ret void3871}3872 3873define void @trunc_v8bf16(ptr %x) {3874; CHECK-LABEL: trunc_v8bf16:3875; CHECK: # %bb.0:3876; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma3877; CHECK-NEXT: vle16.v v10, (a0)3878; CHECK-NEXT: lui a1, 3072003879; CHECK-NEXT: fmv.w.x fa5, a13880; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v103881; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma3882; CHECK-NEXT: vfabs.v v10, v83883; CHECK-NEXT: vmflt.vf v0, v10, fa53884; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t3885; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t3886; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu3887; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t3888; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma3889; CHECK-NEXT: vfncvtbf16.f.f.w v10, v83890; CHECK-NEXT: vse16.v v10, (a0)3891; CHECK-NEXT: ret3892 %a = load <8 x bfloat>, ptr %x3893 %b = call <8 x bfloat> @llvm.trunc.v8bf16(<8 x bfloat> %a)3894 store <8 x bfloat> %b, ptr %x3895 ret void3896}3897 3898define void @trunc_v6bf16(ptr %x) {3899; CHECK-LABEL: trunc_v6bf16:3900; CHECK: # %bb.0:3901; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma3902; CHECK-NEXT: vle16.v v10, (a0)3903; CHECK-NEXT: lui a1, 3072003904; CHECK-NEXT: fmv.w.x fa5, a13905; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v103906; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma3907; CHECK-NEXT: vfabs.v v10, v83908; CHECK-NEXT: vmflt.vf v0, v10, fa53909; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t3910; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t3911; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu3912; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t3913; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma3914; CHECK-NEXT: vfncvtbf16.f.f.w v10, v83915; CHECK-NEXT: vse16.v v10, (a0)3916; CHECK-NEXT: ret3917 %a = load <6 x bfloat>, ptr %x3918 %b = call <6 x bfloat> @llvm.trunc.v6bf16(<6 x bfloat> %a)3919 store <6 x bfloat> %b, ptr %x3920 ret void3921}3922 3923define void @trunc_v8f16(ptr %x) {3924; ZVFH-LABEL: trunc_v8f16:3925; ZVFH: # %bb.0:3926; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma3927; ZVFH-NEXT: vle16.v v8, (a0)3928; ZVFH-NEXT: li a1, 253929; ZVFH-NEXT: slli a1, a1, 103930; ZVFH-NEXT: fmv.h.x fa5, a13931; ZVFH-NEXT: vfabs.v v9, v83932; ZVFH-NEXT: vmflt.vf v0, v9, fa53933; ZVFH-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t3934; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t3935; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu3936; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t3937; ZVFH-NEXT: vse16.v v8, (a0)3938; ZVFH-NEXT: ret3939;3940; ZVFHMIN-LABEL: trunc_v8f16:3941; ZVFHMIN: # %bb.0:3942; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma3943; ZVFHMIN-NEXT: vle16.v v10, (a0)3944; ZVFHMIN-NEXT: lui a1, 3072003945; ZVFHMIN-NEXT: fmv.w.x fa5, a13946; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v103947; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma3948; ZVFHMIN-NEXT: vfabs.v v10, v83949; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa53950; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t3951; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t3952; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu3953; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t3954; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma3955; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v83956; ZVFHMIN-NEXT: vse16.v v10, (a0)3957; ZVFHMIN-NEXT: ret3958 %a = load <8 x half>, ptr %x3959 %b = call <8 x half> @llvm.trunc.v8f16(<8 x half> %a)3960 store <8 x half> %b, ptr %x3961 ret void3962}3963 3964define void @trunc_v6f16(ptr %x) {3965; ZVFH-LABEL: trunc_v6f16:3966; ZVFH: # %bb.0:3967; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma3968; ZVFH-NEXT: vle16.v v8, (a0)3969; ZVFH-NEXT: li a1, 253970; ZVFH-NEXT: slli a1, a1, 103971; ZVFH-NEXT: fmv.h.x fa5, a13972; ZVFH-NEXT: vfabs.v v9, v83973; ZVFH-NEXT: vmflt.vf v0, v9, fa53974; ZVFH-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t3975; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t3976; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu3977; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t3978; ZVFH-NEXT: vse16.v v8, (a0)3979; ZVFH-NEXT: ret3980;3981; ZVFHMIN-LABEL: trunc_v6f16:3982; ZVFHMIN: # %bb.0:3983; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma3984; ZVFHMIN-NEXT: vle16.v v10, (a0)3985; ZVFHMIN-NEXT: lui a1, 3072003986; ZVFHMIN-NEXT: fmv.w.x fa5, a13987; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v103988; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma3989; ZVFHMIN-NEXT: vfabs.v v10, v83990; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa53991; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t3992; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t3993; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu3994; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t3995; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma3996; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v83997; ZVFHMIN-NEXT: vse16.v v10, (a0)3998; ZVFHMIN-NEXT: ret3999 %a = load <6 x half>, ptr %x4000 %b = call <6 x half> @llvm.trunc.v6f16(<6 x half> %a)4001 store <6 x half> %b, ptr %x4002 ret void4003}4004 4005define void @trunc_v4f32(ptr %x) {4006; CHECK-LABEL: trunc_v4f32:4007; CHECK: # %bb.0:4008; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma4009; CHECK-NEXT: vle32.v v8, (a0)4010; CHECK-NEXT: lui a1, 3072004011; CHECK-NEXT: fmv.w.x fa5, a14012; CHECK-NEXT: vfabs.v v9, v84013; CHECK-NEXT: vmflt.vf v0, v9, fa54014; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t4015; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t4016; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu4017; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t4018; CHECK-NEXT: vse32.v v8, (a0)4019; CHECK-NEXT: ret4020 %a = load <4 x float>, ptr %x4021 %b = call <4 x float> @llvm.trunc.v4f32(<4 x float> %a)4022 store <4 x float> %b, ptr %x4023 ret void4024}4025 4026define void @trunc_v2f64(ptr %x) {4027; RV32ZVFH-LABEL: trunc_v2f64:4028; RV32ZVFH: # %bb.0:4029; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma4030; RV32ZVFH-NEXT: vle64.v v8, (a0)4031; RV32ZVFH-NEXT: lui a1, %hi(.LCPI174_0)4032; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI174_0)(a1)4033; RV32ZVFH-NEXT: vfabs.v v9, v84034; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa54035; RV32ZVFH-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t4036; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4037; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu4038; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4039; RV32ZVFH-NEXT: vse64.v v8, (a0)4040; RV32ZVFH-NEXT: ret4041;4042; RV64ZVFH-LABEL: trunc_v2f64:4043; RV64ZVFH: # %bb.0:4044; RV64ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma4045; RV64ZVFH-NEXT: vle64.v v8, (a0)4046; RV64ZVFH-NEXT: li a1, 10754047; RV64ZVFH-NEXT: slli a1, a1, 524048; RV64ZVFH-NEXT: fmv.d.x fa5, a14049; RV64ZVFH-NEXT: vfabs.v v9, v84050; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa54051; RV64ZVFH-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t4052; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4053; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu4054; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4055; RV64ZVFH-NEXT: vse64.v v8, (a0)4056; RV64ZVFH-NEXT: ret4057;4058; RV32ZVFHMIN-LABEL: trunc_v2f64:4059; RV32ZVFHMIN: # %bb.0:4060; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma4061; RV32ZVFHMIN-NEXT: vle64.v v8, (a0)4062; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI174_0)4063; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI174_0)(a1)4064; RV32ZVFHMIN-NEXT: vfabs.v v9, v84065; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa54066; RV32ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t4067; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t4068; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu4069; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t4070; RV32ZVFHMIN-NEXT: vse64.v v8, (a0)4071; RV32ZVFHMIN-NEXT: ret4072;4073; RV64ZVFHMIN-LABEL: trunc_v2f64:4074; RV64ZVFHMIN: # %bb.0:4075; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma4076; RV64ZVFHMIN-NEXT: vle64.v v8, (a0)4077; RV64ZVFHMIN-NEXT: li a1, 10754078; RV64ZVFHMIN-NEXT: slli a1, a1, 524079; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a14080; RV64ZVFHMIN-NEXT: vfabs.v v9, v84081; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa54082; RV64ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t4083; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t4084; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu4085; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t4086; RV64ZVFHMIN-NEXT: vse64.v v8, (a0)4087; RV64ZVFHMIN-NEXT: ret4088 %a = load <2 x double>, ptr %x4089 %b = call <2 x double> @llvm.trunc.v2f64(<2 x double> %a)4090 store <2 x double> %b, ptr %x4091 ret void4092}4093 4094define void @ceil_v8bf16(ptr %x) {4095; CHECK-LABEL: ceil_v8bf16:4096; CHECK: # %bb.0:4097; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma4098; CHECK-NEXT: vle16.v v10, (a0)4099; CHECK-NEXT: lui a1, 3072004100; CHECK-NEXT: fmv.w.x fa5, a14101; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v104102; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma4103; CHECK-NEXT: vfabs.v v10, v84104; CHECK-NEXT: vmflt.vf v0, v10, fa54105; CHECK-NEXT: fsrmi a1, 34106; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t4107; CHECK-NEXT: fsrm a14108; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t4109; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu4110; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t4111; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma4112; CHECK-NEXT: vfncvtbf16.f.f.w v10, v84113; CHECK-NEXT: vse16.v v10, (a0)4114; CHECK-NEXT: ret4115 %a = load <8 x bfloat>, ptr %x4116 %b = call <8 x bfloat> @llvm.ceil.v8bf16(<8 x bfloat> %a)4117 store <8 x bfloat> %b, ptr %x4118 ret void4119}4120 4121define void @ceil_v6bf16(ptr %x) {4122; CHECK-LABEL: ceil_v6bf16:4123; CHECK: # %bb.0:4124; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma4125; CHECK-NEXT: vle16.v v10, (a0)4126; CHECK-NEXT: lui a1, 3072004127; CHECK-NEXT: fmv.w.x fa5, a14128; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v104129; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma4130; CHECK-NEXT: vfabs.v v10, v84131; CHECK-NEXT: vmflt.vf v0, v10, fa54132; CHECK-NEXT: fsrmi a1, 34133; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t4134; CHECK-NEXT: fsrm a14135; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t4136; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu4137; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t4138; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma4139; CHECK-NEXT: vfncvtbf16.f.f.w v10, v84140; CHECK-NEXT: vse16.v v10, (a0)4141; CHECK-NEXT: ret4142 %a = load <6 x bfloat>, ptr %x4143 %b = call <6 x bfloat> @llvm.ceil.v6bf16(<6 x bfloat> %a)4144 store <6 x bfloat> %b, ptr %x4145 ret void4146}4147 4148define void @ceil_v8f16(ptr %x) {4149; ZVFH-LABEL: ceil_v8f16:4150; ZVFH: # %bb.0:4151; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma4152; ZVFH-NEXT: vle16.v v8, (a0)4153; ZVFH-NEXT: li a1, 254154; ZVFH-NEXT: slli a1, a1, 104155; ZVFH-NEXT: fmv.h.x fa5, a14156; ZVFH-NEXT: vfabs.v v9, v84157; ZVFH-NEXT: vmflt.vf v0, v9, fa54158; ZVFH-NEXT: fsrmi a1, 34159; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t4160; ZVFH-NEXT: fsrm a14161; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4162; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu4163; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4164; ZVFH-NEXT: vse16.v v8, (a0)4165; ZVFH-NEXT: ret4166;4167; ZVFHMIN-LABEL: ceil_v8f16:4168; ZVFHMIN: # %bb.0:4169; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma4170; ZVFHMIN-NEXT: vle16.v v10, (a0)4171; ZVFHMIN-NEXT: lui a1, 3072004172; ZVFHMIN-NEXT: fmv.w.x fa5, a14173; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v104174; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma4175; ZVFHMIN-NEXT: vfabs.v v10, v84176; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa54177; ZVFHMIN-NEXT: fsrmi a1, 34178; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t4179; ZVFHMIN-NEXT: fsrm a14180; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t4181; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu4182; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t4183; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma4184; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v84185; ZVFHMIN-NEXT: vse16.v v10, (a0)4186; ZVFHMIN-NEXT: ret4187 %a = load <8 x half>, ptr %x4188 %b = call <8 x half> @llvm.ceil.v8f16(<8 x half> %a)4189 store <8 x half> %b, ptr %x4190 ret void4191}4192 4193define void @ceil_v6f16(ptr %x) {4194; ZVFH-LABEL: ceil_v6f16:4195; ZVFH: # %bb.0:4196; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma4197; ZVFH-NEXT: vle16.v v8, (a0)4198; ZVFH-NEXT: li a1, 254199; ZVFH-NEXT: slli a1, a1, 104200; ZVFH-NEXT: fmv.h.x fa5, a14201; ZVFH-NEXT: vfabs.v v9, v84202; ZVFH-NEXT: vmflt.vf v0, v9, fa54203; ZVFH-NEXT: fsrmi a1, 34204; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t4205; ZVFH-NEXT: fsrm a14206; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4207; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu4208; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4209; ZVFH-NEXT: vse16.v v8, (a0)4210; ZVFH-NEXT: ret4211;4212; ZVFHMIN-LABEL: ceil_v6f16:4213; ZVFHMIN: # %bb.0:4214; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma4215; ZVFHMIN-NEXT: vle16.v v10, (a0)4216; ZVFHMIN-NEXT: lui a1, 3072004217; ZVFHMIN-NEXT: fmv.w.x fa5, a14218; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v104219; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma4220; ZVFHMIN-NEXT: vfabs.v v10, v84221; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa54222; ZVFHMIN-NEXT: fsrmi a1, 34223; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t4224; ZVFHMIN-NEXT: fsrm a14225; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t4226; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu4227; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t4228; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma4229; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v84230; ZVFHMIN-NEXT: vse16.v v10, (a0)4231; ZVFHMIN-NEXT: ret4232 %a = load <6 x half>, ptr %x4233 %b = call <6 x half> @llvm.ceil.v6f16(<6 x half> %a)4234 store <6 x half> %b, ptr %x4235 ret void4236}4237 4238define void @ceil_v4f32(ptr %x) {4239; CHECK-LABEL: ceil_v4f32:4240; CHECK: # %bb.0:4241; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma4242; CHECK-NEXT: vle32.v v8, (a0)4243; CHECK-NEXT: lui a1, 3072004244; CHECK-NEXT: fmv.w.x fa5, a14245; CHECK-NEXT: vfabs.v v9, v84246; CHECK-NEXT: vmflt.vf v0, v9, fa54247; CHECK-NEXT: fsrmi a1, 34248; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t4249; CHECK-NEXT: fsrm a14250; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t4251; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu4252; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t4253; CHECK-NEXT: vse32.v v8, (a0)4254; CHECK-NEXT: ret4255 %a = load <4 x float>, ptr %x4256 %b = call <4 x float> @llvm.ceil.v4f32(<4 x float> %a)4257 store <4 x float> %b, ptr %x4258 ret void4259}4260 4261define void @ceil_v2f64(ptr %x) {4262; RV32ZVFH-LABEL: ceil_v2f64:4263; RV32ZVFH: # %bb.0:4264; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma4265; RV32ZVFH-NEXT: vle64.v v8, (a0)4266; RV32ZVFH-NEXT: lui a1, %hi(.LCPI180_0)4267; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI180_0)(a1)4268; RV32ZVFH-NEXT: vfabs.v v9, v84269; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa54270; RV32ZVFH-NEXT: fsrmi a1, 34271; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t4272; RV32ZVFH-NEXT: fsrm a14273; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4274; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu4275; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4276; RV32ZVFH-NEXT: vse64.v v8, (a0)4277; RV32ZVFH-NEXT: ret4278;4279; RV64ZVFH-LABEL: ceil_v2f64:4280; RV64ZVFH: # %bb.0:4281; RV64ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma4282; RV64ZVFH-NEXT: vle64.v v8, (a0)4283; RV64ZVFH-NEXT: li a1, 10754284; RV64ZVFH-NEXT: slli a1, a1, 524285; RV64ZVFH-NEXT: fmv.d.x fa5, a14286; RV64ZVFH-NEXT: vfabs.v v9, v84287; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa54288; RV64ZVFH-NEXT: fsrmi a1, 34289; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t4290; RV64ZVFH-NEXT: fsrm a14291; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4292; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu4293; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4294; RV64ZVFH-NEXT: vse64.v v8, (a0)4295; RV64ZVFH-NEXT: ret4296;4297; RV32ZVFHMIN-LABEL: ceil_v2f64:4298; RV32ZVFHMIN: # %bb.0:4299; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma4300; RV32ZVFHMIN-NEXT: vle64.v v8, (a0)4301; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI180_0)4302; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI180_0)(a1)4303; RV32ZVFHMIN-NEXT: vfabs.v v9, v84304; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa54305; RV32ZVFHMIN-NEXT: fsrmi a1, 34306; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t4307; RV32ZVFHMIN-NEXT: fsrm a14308; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t4309; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu4310; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t4311; RV32ZVFHMIN-NEXT: vse64.v v8, (a0)4312; RV32ZVFHMIN-NEXT: ret4313;4314; RV64ZVFHMIN-LABEL: ceil_v2f64:4315; RV64ZVFHMIN: # %bb.0:4316; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma4317; RV64ZVFHMIN-NEXT: vle64.v v8, (a0)4318; RV64ZVFHMIN-NEXT: li a1, 10754319; RV64ZVFHMIN-NEXT: slli a1, a1, 524320; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a14321; RV64ZVFHMIN-NEXT: vfabs.v v9, v84322; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa54323; RV64ZVFHMIN-NEXT: fsrmi a1, 34324; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t4325; RV64ZVFHMIN-NEXT: fsrm a14326; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t4327; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu4328; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t4329; RV64ZVFHMIN-NEXT: vse64.v v8, (a0)4330; RV64ZVFHMIN-NEXT: ret4331 %a = load <2 x double>, ptr %x4332 %b = call <2 x double> @llvm.ceil.v2f64(<2 x double> %a)4333 store <2 x double> %b, ptr %x4334 ret void4335}4336 4337define void @floor_v8bf16(ptr %x) {4338; CHECK-LABEL: floor_v8bf16:4339; CHECK: # %bb.0:4340; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma4341; CHECK-NEXT: vle16.v v10, (a0)4342; CHECK-NEXT: lui a1, 3072004343; CHECK-NEXT: fmv.w.x fa5, a14344; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v104345; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma4346; CHECK-NEXT: vfabs.v v10, v84347; CHECK-NEXT: vmflt.vf v0, v10, fa54348; CHECK-NEXT: fsrmi a1, 24349; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t4350; CHECK-NEXT: fsrm a14351; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t4352; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu4353; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t4354; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma4355; CHECK-NEXT: vfncvtbf16.f.f.w v10, v84356; CHECK-NEXT: vse16.v v10, (a0)4357; CHECK-NEXT: ret4358 %a = load <8 x bfloat>, ptr %x4359 %b = call <8 x bfloat> @llvm.floor.v8bf16(<8 x bfloat> %a)4360 store <8 x bfloat> %b, ptr %x4361 ret void4362}4363 4364define void @floor_v6bf16(ptr %x) {4365; CHECK-LABEL: floor_v6bf16:4366; CHECK: # %bb.0:4367; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma4368; CHECK-NEXT: vle16.v v10, (a0)4369; CHECK-NEXT: lui a1, 3072004370; CHECK-NEXT: fmv.w.x fa5, a14371; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v104372; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma4373; CHECK-NEXT: vfabs.v v10, v84374; CHECK-NEXT: vmflt.vf v0, v10, fa54375; CHECK-NEXT: fsrmi a1, 24376; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t4377; CHECK-NEXT: fsrm a14378; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t4379; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu4380; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t4381; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma4382; CHECK-NEXT: vfncvtbf16.f.f.w v10, v84383; CHECK-NEXT: vse16.v v10, (a0)4384; CHECK-NEXT: ret4385 %a = load <6 x bfloat>, ptr %x4386 %b = call <6 x bfloat> @llvm.floor.v6bf16(<6 x bfloat> %a)4387 store <6 x bfloat> %b, ptr %x4388 ret void4389}4390 4391define void @floor_v8f16(ptr %x) {4392; ZVFH-LABEL: floor_v8f16:4393; ZVFH: # %bb.0:4394; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma4395; ZVFH-NEXT: vle16.v v8, (a0)4396; ZVFH-NEXT: li a1, 254397; ZVFH-NEXT: slli a1, a1, 104398; ZVFH-NEXT: fmv.h.x fa5, a14399; ZVFH-NEXT: vfabs.v v9, v84400; ZVFH-NEXT: vmflt.vf v0, v9, fa54401; ZVFH-NEXT: fsrmi a1, 24402; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t4403; ZVFH-NEXT: fsrm a14404; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4405; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu4406; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4407; ZVFH-NEXT: vse16.v v8, (a0)4408; ZVFH-NEXT: ret4409;4410; ZVFHMIN-LABEL: floor_v8f16:4411; ZVFHMIN: # %bb.0:4412; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma4413; ZVFHMIN-NEXT: vle16.v v10, (a0)4414; ZVFHMIN-NEXT: lui a1, 3072004415; ZVFHMIN-NEXT: fmv.w.x fa5, a14416; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v104417; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma4418; ZVFHMIN-NEXT: vfabs.v v10, v84419; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa54420; ZVFHMIN-NEXT: fsrmi a1, 24421; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t4422; ZVFHMIN-NEXT: fsrm a14423; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t4424; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu4425; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t4426; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma4427; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v84428; ZVFHMIN-NEXT: vse16.v v10, (a0)4429; ZVFHMIN-NEXT: ret4430 %a = load <8 x half>, ptr %x4431 %b = call <8 x half> @llvm.floor.v8f16(<8 x half> %a)4432 store <8 x half> %b, ptr %x4433 ret void4434}4435 4436define void @floor_v6f16(ptr %x) {4437; ZVFH-LABEL: floor_v6f16:4438; ZVFH: # %bb.0:4439; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma4440; ZVFH-NEXT: vle16.v v8, (a0)4441; ZVFH-NEXT: li a1, 254442; ZVFH-NEXT: slli a1, a1, 104443; ZVFH-NEXT: fmv.h.x fa5, a14444; ZVFH-NEXT: vfabs.v v9, v84445; ZVFH-NEXT: vmflt.vf v0, v9, fa54446; ZVFH-NEXT: fsrmi a1, 24447; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t4448; ZVFH-NEXT: fsrm a14449; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4450; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu4451; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4452; ZVFH-NEXT: vse16.v v8, (a0)4453; ZVFH-NEXT: ret4454;4455; ZVFHMIN-LABEL: floor_v6f16:4456; ZVFHMIN: # %bb.0:4457; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma4458; ZVFHMIN-NEXT: vle16.v v10, (a0)4459; ZVFHMIN-NEXT: lui a1, 3072004460; ZVFHMIN-NEXT: fmv.w.x fa5, a14461; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v104462; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma4463; ZVFHMIN-NEXT: vfabs.v v10, v84464; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa54465; ZVFHMIN-NEXT: fsrmi a1, 24466; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t4467; ZVFHMIN-NEXT: fsrm a14468; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t4469; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu4470; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t4471; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma4472; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v84473; ZVFHMIN-NEXT: vse16.v v10, (a0)4474; ZVFHMIN-NEXT: ret4475 %a = load <6 x half>, ptr %x4476 %b = call <6 x half> @llvm.floor.v6f16(<6 x half> %a)4477 store <6 x half> %b, ptr %x4478 ret void4479}4480 4481define void @floor_v4f32(ptr %x) {4482; CHECK-LABEL: floor_v4f32:4483; CHECK: # %bb.0:4484; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma4485; CHECK-NEXT: vle32.v v8, (a0)4486; CHECK-NEXT: lui a1, 3072004487; CHECK-NEXT: fmv.w.x fa5, a14488; CHECK-NEXT: vfabs.v v9, v84489; CHECK-NEXT: vmflt.vf v0, v9, fa54490; CHECK-NEXT: fsrmi a1, 24491; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t4492; CHECK-NEXT: fsrm a14493; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t4494; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu4495; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t4496; CHECK-NEXT: vse32.v v8, (a0)4497; CHECK-NEXT: ret4498 %a = load <4 x float>, ptr %x4499 %b = call <4 x float> @llvm.floor.v4f32(<4 x float> %a)4500 store <4 x float> %b, ptr %x4501 ret void4502}4503 4504define void @floor_v2f64(ptr %x) {4505; RV32ZVFH-LABEL: floor_v2f64:4506; RV32ZVFH: # %bb.0:4507; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma4508; RV32ZVFH-NEXT: vle64.v v8, (a0)4509; RV32ZVFH-NEXT: lui a1, %hi(.LCPI186_0)4510; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI186_0)(a1)4511; RV32ZVFH-NEXT: vfabs.v v9, v84512; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa54513; RV32ZVFH-NEXT: fsrmi a1, 24514; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t4515; RV32ZVFH-NEXT: fsrm a14516; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4517; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu4518; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4519; RV32ZVFH-NEXT: vse64.v v8, (a0)4520; RV32ZVFH-NEXT: ret4521;4522; RV64ZVFH-LABEL: floor_v2f64:4523; RV64ZVFH: # %bb.0:4524; RV64ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma4525; RV64ZVFH-NEXT: vle64.v v8, (a0)4526; RV64ZVFH-NEXT: li a1, 10754527; RV64ZVFH-NEXT: slli a1, a1, 524528; RV64ZVFH-NEXT: fmv.d.x fa5, a14529; RV64ZVFH-NEXT: vfabs.v v9, v84530; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa54531; RV64ZVFH-NEXT: fsrmi a1, 24532; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t4533; RV64ZVFH-NEXT: fsrm a14534; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4535; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu4536; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4537; RV64ZVFH-NEXT: vse64.v v8, (a0)4538; RV64ZVFH-NEXT: ret4539;4540; RV32ZVFHMIN-LABEL: floor_v2f64:4541; RV32ZVFHMIN: # %bb.0:4542; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma4543; RV32ZVFHMIN-NEXT: vle64.v v8, (a0)4544; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI186_0)4545; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI186_0)(a1)4546; RV32ZVFHMIN-NEXT: vfabs.v v9, v84547; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa54548; RV32ZVFHMIN-NEXT: fsrmi a1, 24549; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t4550; RV32ZVFHMIN-NEXT: fsrm a14551; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t4552; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu4553; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t4554; RV32ZVFHMIN-NEXT: vse64.v v8, (a0)4555; RV32ZVFHMIN-NEXT: ret4556;4557; RV64ZVFHMIN-LABEL: floor_v2f64:4558; RV64ZVFHMIN: # %bb.0:4559; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma4560; RV64ZVFHMIN-NEXT: vle64.v v8, (a0)4561; RV64ZVFHMIN-NEXT: li a1, 10754562; RV64ZVFHMIN-NEXT: slli a1, a1, 524563; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a14564; RV64ZVFHMIN-NEXT: vfabs.v v9, v84565; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa54566; RV64ZVFHMIN-NEXT: fsrmi a1, 24567; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t4568; RV64ZVFHMIN-NEXT: fsrm a14569; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t4570; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu4571; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t4572; RV64ZVFHMIN-NEXT: vse64.v v8, (a0)4573; RV64ZVFHMIN-NEXT: ret4574 %a = load <2 x double>, ptr %x4575 %b = call <2 x double> @llvm.floor.v2f64(<2 x double> %a)4576 store <2 x double> %b, ptr %x4577 ret void4578}4579 4580define void @round_v8bf16(ptr %x) {4581; CHECK-LABEL: round_v8bf16:4582; CHECK: # %bb.0:4583; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma4584; CHECK-NEXT: vle16.v v10, (a0)4585; CHECK-NEXT: lui a1, 3072004586; CHECK-NEXT: fmv.w.x fa5, a14587; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v104588; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma4589; CHECK-NEXT: vfabs.v v10, v84590; CHECK-NEXT: vmflt.vf v0, v10, fa54591; CHECK-NEXT: fsrmi a1, 44592; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t4593; CHECK-NEXT: fsrm a14594; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t4595; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu4596; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t4597; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma4598; CHECK-NEXT: vfncvtbf16.f.f.w v10, v84599; CHECK-NEXT: vse16.v v10, (a0)4600; CHECK-NEXT: ret4601 %a = load <8 x bfloat>, ptr %x4602 %b = call <8 x bfloat> @llvm.round.v8bf16(<8 x bfloat> %a)4603 store <8 x bfloat> %b, ptr %x4604 ret void4605}4606 4607define void @round_v6bf16(ptr %x) {4608; CHECK-LABEL: round_v6bf16:4609; CHECK: # %bb.0:4610; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma4611; CHECK-NEXT: vle16.v v10, (a0)4612; CHECK-NEXT: lui a1, 3072004613; CHECK-NEXT: fmv.w.x fa5, a14614; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v104615; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma4616; CHECK-NEXT: vfabs.v v10, v84617; CHECK-NEXT: vmflt.vf v0, v10, fa54618; CHECK-NEXT: fsrmi a1, 44619; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t4620; CHECK-NEXT: fsrm a14621; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t4622; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu4623; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t4624; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma4625; CHECK-NEXT: vfncvtbf16.f.f.w v10, v84626; CHECK-NEXT: vse16.v v10, (a0)4627; CHECK-NEXT: ret4628 %a = load <6 x bfloat>, ptr %x4629 %b = call <6 x bfloat> @llvm.round.v6bf16(<6 x bfloat> %a)4630 store <6 x bfloat> %b, ptr %x4631 ret void4632}4633 4634define void @round_v8f16(ptr %x) {4635; ZVFH-LABEL: round_v8f16:4636; ZVFH: # %bb.0:4637; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma4638; ZVFH-NEXT: vle16.v v8, (a0)4639; ZVFH-NEXT: li a1, 254640; ZVFH-NEXT: slli a1, a1, 104641; ZVFH-NEXT: fmv.h.x fa5, a14642; ZVFH-NEXT: vfabs.v v9, v84643; ZVFH-NEXT: vmflt.vf v0, v9, fa54644; ZVFH-NEXT: fsrmi a1, 44645; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t4646; ZVFH-NEXT: fsrm a14647; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4648; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu4649; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4650; ZVFH-NEXT: vse16.v v8, (a0)4651; ZVFH-NEXT: ret4652;4653; ZVFHMIN-LABEL: round_v8f16:4654; ZVFHMIN: # %bb.0:4655; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma4656; ZVFHMIN-NEXT: vle16.v v10, (a0)4657; ZVFHMIN-NEXT: lui a1, 3072004658; ZVFHMIN-NEXT: fmv.w.x fa5, a14659; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v104660; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma4661; ZVFHMIN-NEXT: vfabs.v v10, v84662; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa54663; ZVFHMIN-NEXT: fsrmi a1, 44664; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t4665; ZVFHMIN-NEXT: fsrm a14666; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t4667; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu4668; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t4669; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma4670; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v84671; ZVFHMIN-NEXT: vse16.v v10, (a0)4672; ZVFHMIN-NEXT: ret4673 %a = load <8 x half>, ptr %x4674 %b = call <8 x half> @llvm.round.v8f16(<8 x half> %a)4675 store <8 x half> %b, ptr %x4676 ret void4677}4678 4679define void @round_v6f16(ptr %x) {4680; ZVFH-LABEL: round_v6f16:4681; ZVFH: # %bb.0:4682; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma4683; ZVFH-NEXT: vle16.v v8, (a0)4684; ZVFH-NEXT: li a1, 254685; ZVFH-NEXT: slli a1, a1, 104686; ZVFH-NEXT: fmv.h.x fa5, a14687; ZVFH-NEXT: vfabs.v v9, v84688; ZVFH-NEXT: vmflt.vf v0, v9, fa54689; ZVFH-NEXT: fsrmi a1, 44690; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t4691; ZVFH-NEXT: fsrm a14692; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4693; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu4694; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4695; ZVFH-NEXT: vse16.v v8, (a0)4696; ZVFH-NEXT: ret4697;4698; ZVFHMIN-LABEL: round_v6f16:4699; ZVFHMIN: # %bb.0:4700; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma4701; ZVFHMIN-NEXT: vle16.v v10, (a0)4702; ZVFHMIN-NEXT: lui a1, 3072004703; ZVFHMIN-NEXT: fmv.w.x fa5, a14704; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v104705; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma4706; ZVFHMIN-NEXT: vfabs.v v10, v84707; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa54708; ZVFHMIN-NEXT: fsrmi a1, 44709; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t4710; ZVFHMIN-NEXT: fsrm a14711; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t4712; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu4713; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t4714; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma4715; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v84716; ZVFHMIN-NEXT: vse16.v v10, (a0)4717; ZVFHMIN-NEXT: ret4718 %a = load <6 x half>, ptr %x4719 %b = call <6 x half> @llvm.round.v6f16(<6 x half> %a)4720 store <6 x half> %b, ptr %x4721 ret void4722}4723 4724define void @round_v4f32(ptr %x) {4725; CHECK-LABEL: round_v4f32:4726; CHECK: # %bb.0:4727; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma4728; CHECK-NEXT: vle32.v v8, (a0)4729; CHECK-NEXT: lui a1, 3072004730; CHECK-NEXT: fmv.w.x fa5, a14731; CHECK-NEXT: vfabs.v v9, v84732; CHECK-NEXT: vmflt.vf v0, v9, fa54733; CHECK-NEXT: fsrmi a1, 44734; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t4735; CHECK-NEXT: fsrm a14736; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t4737; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu4738; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t4739; CHECK-NEXT: vse32.v v8, (a0)4740; CHECK-NEXT: ret4741 %a = load <4 x float>, ptr %x4742 %b = call <4 x float> @llvm.round.v4f32(<4 x float> %a)4743 store <4 x float> %b, ptr %x4744 ret void4745}4746 4747define void @round_v2f64(ptr %x) {4748; RV32ZVFH-LABEL: round_v2f64:4749; RV32ZVFH: # %bb.0:4750; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma4751; RV32ZVFH-NEXT: vle64.v v8, (a0)4752; RV32ZVFH-NEXT: lui a1, %hi(.LCPI192_0)4753; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI192_0)(a1)4754; RV32ZVFH-NEXT: vfabs.v v9, v84755; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa54756; RV32ZVFH-NEXT: fsrmi a1, 44757; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t4758; RV32ZVFH-NEXT: fsrm a14759; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4760; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu4761; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4762; RV32ZVFH-NEXT: vse64.v v8, (a0)4763; RV32ZVFH-NEXT: ret4764;4765; RV64ZVFH-LABEL: round_v2f64:4766; RV64ZVFH: # %bb.0:4767; RV64ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma4768; RV64ZVFH-NEXT: vle64.v v8, (a0)4769; RV64ZVFH-NEXT: li a1, 10754770; RV64ZVFH-NEXT: slli a1, a1, 524771; RV64ZVFH-NEXT: fmv.d.x fa5, a14772; RV64ZVFH-NEXT: vfabs.v v9, v84773; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa54774; RV64ZVFH-NEXT: fsrmi a1, 44775; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t4776; RV64ZVFH-NEXT: fsrm a14777; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4778; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu4779; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4780; RV64ZVFH-NEXT: vse64.v v8, (a0)4781; RV64ZVFH-NEXT: ret4782;4783; RV32ZVFHMIN-LABEL: round_v2f64:4784; RV32ZVFHMIN: # %bb.0:4785; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma4786; RV32ZVFHMIN-NEXT: vle64.v v8, (a0)4787; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI192_0)4788; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI192_0)(a1)4789; RV32ZVFHMIN-NEXT: vfabs.v v9, v84790; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa54791; RV32ZVFHMIN-NEXT: fsrmi a1, 44792; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t4793; RV32ZVFHMIN-NEXT: fsrm a14794; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t4795; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu4796; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t4797; RV32ZVFHMIN-NEXT: vse64.v v8, (a0)4798; RV32ZVFHMIN-NEXT: ret4799;4800; RV64ZVFHMIN-LABEL: round_v2f64:4801; RV64ZVFHMIN: # %bb.0:4802; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma4803; RV64ZVFHMIN-NEXT: vle64.v v8, (a0)4804; RV64ZVFHMIN-NEXT: li a1, 10754805; RV64ZVFHMIN-NEXT: slli a1, a1, 524806; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a14807; RV64ZVFHMIN-NEXT: vfabs.v v9, v84808; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa54809; RV64ZVFHMIN-NEXT: fsrmi a1, 44810; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t4811; RV64ZVFHMIN-NEXT: fsrm a14812; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t4813; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu4814; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t4815; RV64ZVFHMIN-NEXT: vse64.v v8, (a0)4816; RV64ZVFHMIN-NEXT: ret4817 %a = load <2 x double>, ptr %x4818 %b = call <2 x double> @llvm.round.v2f64(<2 x double> %a)4819 store <2 x double> %b, ptr %x4820 ret void4821}4822 4823define void @rint_v8bf16(ptr %x) {4824; CHECK-LABEL: rint_v8bf16:4825; CHECK: # %bb.0:4826; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma4827; CHECK-NEXT: vle16.v v10, (a0)4828; CHECK-NEXT: lui a1, 3072004829; CHECK-NEXT: fmv.w.x fa5, a14830; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v104831; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma4832; CHECK-NEXT: vfabs.v v10, v84833; CHECK-NEXT: vmflt.vf v0, v10, fa54834; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t4835; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t4836; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu4837; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t4838; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma4839; CHECK-NEXT: vfncvtbf16.f.f.w v10, v84840; CHECK-NEXT: vse16.v v10, (a0)4841; CHECK-NEXT: ret4842 %a = load <8 x bfloat>, ptr %x4843 %b = call <8 x bfloat> @llvm.rint.v8bf16(<8 x bfloat> %a)4844 store <8 x bfloat> %b, ptr %x4845 ret void4846}4847 4848define void @rint_v8f16(ptr %x) {4849; ZVFH-LABEL: rint_v8f16:4850; ZVFH: # %bb.0:4851; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma4852; ZVFH-NEXT: vle16.v v8, (a0)4853; ZVFH-NEXT: li a1, 254854; ZVFH-NEXT: slli a1, a1, 104855; ZVFH-NEXT: fmv.h.x fa5, a14856; ZVFH-NEXT: vfabs.v v9, v84857; ZVFH-NEXT: vmflt.vf v0, v9, fa54858; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t4859; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4860; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu4861; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4862; ZVFH-NEXT: vse16.v v8, (a0)4863; ZVFH-NEXT: ret4864;4865; ZVFHMIN-LABEL: rint_v8f16:4866; ZVFHMIN: # %bb.0:4867; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma4868; ZVFHMIN-NEXT: vle16.v v10, (a0)4869; ZVFHMIN-NEXT: lui a1, 3072004870; ZVFHMIN-NEXT: fmv.w.x fa5, a14871; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v104872; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma4873; ZVFHMIN-NEXT: vfabs.v v10, v84874; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa54875; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t4876; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t4877; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu4878; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t4879; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma4880; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v84881; ZVFHMIN-NEXT: vse16.v v10, (a0)4882; ZVFHMIN-NEXT: ret4883 %a = load <8 x half>, ptr %x4884 %b = call <8 x half> @llvm.rint.v8f16(<8 x half> %a)4885 store <8 x half> %b, ptr %x4886 ret void4887}4888 4889define void @rint_v4f32(ptr %x) {4890; CHECK-LABEL: rint_v4f32:4891; CHECK: # %bb.0:4892; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma4893; CHECK-NEXT: vle32.v v8, (a0)4894; CHECK-NEXT: lui a1, 3072004895; CHECK-NEXT: fmv.w.x fa5, a14896; CHECK-NEXT: vfabs.v v9, v84897; CHECK-NEXT: vmflt.vf v0, v9, fa54898; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t4899; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t4900; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu4901; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t4902; CHECK-NEXT: vse32.v v8, (a0)4903; CHECK-NEXT: ret4904 %a = load <4 x float>, ptr %x4905 %b = call <4 x float> @llvm.rint.v4f32(<4 x float> %a)4906 store <4 x float> %b, ptr %x4907 ret void4908}4909 4910define void @rint_v2f64(ptr %x) {4911; RV32ZVFH-LABEL: rint_v2f64:4912; RV32ZVFH: # %bb.0:4913; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma4914; RV32ZVFH-NEXT: vle64.v v8, (a0)4915; RV32ZVFH-NEXT: lui a1, %hi(.LCPI196_0)4916; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI196_0)(a1)4917; RV32ZVFH-NEXT: vfabs.v v9, v84918; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa54919; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t4920; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4921; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu4922; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4923; RV32ZVFH-NEXT: vse64.v v8, (a0)4924; RV32ZVFH-NEXT: ret4925;4926; RV64ZVFH-LABEL: rint_v2f64:4927; RV64ZVFH: # %bb.0:4928; RV64ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma4929; RV64ZVFH-NEXT: vle64.v v8, (a0)4930; RV64ZVFH-NEXT: li a1, 10754931; RV64ZVFH-NEXT: slli a1, a1, 524932; RV64ZVFH-NEXT: fmv.d.x fa5, a14933; RV64ZVFH-NEXT: vfabs.v v9, v84934; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa54935; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t4936; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t4937; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu4938; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t4939; RV64ZVFH-NEXT: vse64.v v8, (a0)4940; RV64ZVFH-NEXT: ret4941;4942; RV32ZVFHMIN-LABEL: rint_v2f64:4943; RV32ZVFHMIN: # %bb.0:4944; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma4945; RV32ZVFHMIN-NEXT: vle64.v v8, (a0)4946; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI196_0)4947; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI196_0)(a1)4948; RV32ZVFHMIN-NEXT: vfabs.v v9, v84949; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa54950; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t4951; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t4952; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu4953; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t4954; RV32ZVFHMIN-NEXT: vse64.v v8, (a0)4955; RV32ZVFHMIN-NEXT: ret4956;4957; RV64ZVFHMIN-LABEL: rint_v2f64:4958; RV64ZVFHMIN: # %bb.0:4959; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma4960; RV64ZVFHMIN-NEXT: vle64.v v8, (a0)4961; RV64ZVFHMIN-NEXT: li a1, 10754962; RV64ZVFHMIN-NEXT: slli a1, a1, 524963; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a14964; RV64ZVFHMIN-NEXT: vfabs.v v9, v84965; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa54966; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t4967; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t4968; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu4969; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t4970; RV64ZVFHMIN-NEXT: vse64.v v8, (a0)4971; RV64ZVFHMIN-NEXT: ret4972 %a = load <2 x double>, ptr %x4973 %b = call <2 x double> @llvm.rint.v2f64(<2 x double> %a)4974 store <2 x double> %b, ptr %x4975 ret void4976}4977 4978define void @nearbyint_v8bf16(ptr %x) {4979; CHECK-LABEL: nearbyint_v8bf16:4980; CHECK: # %bb.0:4981; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma4982; CHECK-NEXT: vle16.v v10, (a0)4983; CHECK-NEXT: lui a1, 3072004984; CHECK-NEXT: fmv.w.x fa5, a14985; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v104986; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma4987; CHECK-NEXT: vfabs.v v10, v84988; CHECK-NEXT: vmflt.vf v0, v10, fa54989; CHECK-NEXT: frflags a14990; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t4991; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t4992; CHECK-NEXT: fsflags a14993; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu4994; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t4995; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma4996; CHECK-NEXT: vfncvtbf16.f.f.w v10, v84997; CHECK-NEXT: vse16.v v10, (a0)4998; CHECK-NEXT: ret4999 %a = load <8 x bfloat>, ptr %x5000 %b = call <8 x bfloat> @llvm.nearbyint.v8bf16(<8 x bfloat> %a)5001 store <8 x bfloat> %b, ptr %x5002 ret void5003}5004 5005define void @nearbyint_v8f16(ptr %x) {5006; ZVFH-LABEL: nearbyint_v8f16:5007; ZVFH: # %bb.0:5008; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma5009; ZVFH-NEXT: vle16.v v8, (a0)5010; ZVFH-NEXT: li a1, 255011; ZVFH-NEXT: slli a1, a1, 105012; ZVFH-NEXT: fmv.h.x fa5, a15013; ZVFH-NEXT: vfabs.v v9, v85014; ZVFH-NEXT: vmflt.vf v0, v9, fa55015; ZVFH-NEXT: frflags a15016; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t5017; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t5018; ZVFH-NEXT: fsflags a15019; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu5020; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t5021; ZVFH-NEXT: vse16.v v8, (a0)5022; ZVFH-NEXT: ret5023;5024; ZVFHMIN-LABEL: nearbyint_v8f16:5025; ZVFHMIN: # %bb.0:5026; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma5027; ZVFHMIN-NEXT: vle16.v v10, (a0)5028; ZVFHMIN-NEXT: lui a1, 3072005029; ZVFHMIN-NEXT: fmv.w.x fa5, a15030; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v105031; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma5032; ZVFHMIN-NEXT: vfabs.v v10, v85033; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa55034; ZVFHMIN-NEXT: frflags a15035; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t5036; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t5037; ZVFHMIN-NEXT: fsflags a15038; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu5039; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t5040; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma5041; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v85042; ZVFHMIN-NEXT: vse16.v v10, (a0)5043; ZVFHMIN-NEXT: ret5044 %a = load <8 x half>, ptr %x5045 %b = call <8 x half> @llvm.nearbyint.v8f16(<8 x half> %a)5046 store <8 x half> %b, ptr %x5047 ret void5048}5049 5050define void @nearbyint_v4f32(ptr %x) {5051; CHECK-LABEL: nearbyint_v4f32:5052; CHECK: # %bb.0:5053; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma5054; CHECK-NEXT: vle32.v v8, (a0)5055; CHECK-NEXT: lui a1, 3072005056; CHECK-NEXT: fmv.w.x fa5, a15057; CHECK-NEXT: vfabs.v v9, v85058; CHECK-NEXT: vmflt.vf v0, v9, fa55059; CHECK-NEXT: frflags a15060; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t5061; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t5062; CHECK-NEXT: fsflags a15063; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu5064; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t5065; CHECK-NEXT: vse32.v v8, (a0)5066; CHECK-NEXT: ret5067 %a = load <4 x float>, ptr %x5068 %b = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %a)5069 store <4 x float> %b, ptr %x5070 ret void5071}5072 5073define void @nearbyint_v2f64(ptr %x) {5074; RV32ZVFH-LABEL: nearbyint_v2f64:5075; RV32ZVFH: # %bb.0:5076; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma5077; RV32ZVFH-NEXT: vle64.v v8, (a0)5078; RV32ZVFH-NEXT: lui a1, %hi(.LCPI200_0)5079; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI200_0)(a1)5080; RV32ZVFH-NEXT: vfabs.v v9, v85081; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa55082; RV32ZVFH-NEXT: frflags a15083; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t5084; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t5085; RV32ZVFH-NEXT: fsflags a15086; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu5087; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t5088; RV32ZVFH-NEXT: vse64.v v8, (a0)5089; RV32ZVFH-NEXT: ret5090;5091; RV64ZVFH-LABEL: nearbyint_v2f64:5092; RV64ZVFH: # %bb.0:5093; RV64ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma5094; RV64ZVFH-NEXT: vle64.v v8, (a0)5095; RV64ZVFH-NEXT: li a1, 10755096; RV64ZVFH-NEXT: slli a1, a1, 525097; RV64ZVFH-NEXT: fmv.d.x fa5, a15098; RV64ZVFH-NEXT: vfabs.v v9, v85099; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa55100; RV64ZVFH-NEXT: frflags a15101; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t5102; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t5103; RV64ZVFH-NEXT: fsflags a15104; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu5105; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t5106; RV64ZVFH-NEXT: vse64.v v8, (a0)5107; RV64ZVFH-NEXT: ret5108;5109; RV32ZVFHMIN-LABEL: nearbyint_v2f64:5110; RV32ZVFHMIN: # %bb.0:5111; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma5112; RV32ZVFHMIN-NEXT: vle64.v v8, (a0)5113; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI200_0)5114; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI200_0)(a1)5115; RV32ZVFHMIN-NEXT: vfabs.v v9, v85116; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa55117; RV32ZVFHMIN-NEXT: frflags a15118; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t5119; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t5120; RV32ZVFHMIN-NEXT: fsflags a15121; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu5122; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t5123; RV32ZVFHMIN-NEXT: vse64.v v8, (a0)5124; RV32ZVFHMIN-NEXT: ret5125;5126; RV64ZVFHMIN-LABEL: nearbyint_v2f64:5127; RV64ZVFHMIN: # %bb.0:5128; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma5129; RV64ZVFHMIN-NEXT: vle64.v v8, (a0)5130; RV64ZVFHMIN-NEXT: li a1, 10755131; RV64ZVFHMIN-NEXT: slli a1, a1, 525132; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a15133; RV64ZVFHMIN-NEXT: vfabs.v v9, v85134; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa55135; RV64ZVFHMIN-NEXT: frflags a15136; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t5137; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t5138; RV64ZVFHMIN-NEXT: fsflags a15139; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu5140; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t5141; RV64ZVFHMIN-NEXT: vse64.v v8, (a0)5142; RV64ZVFHMIN-NEXT: ret5143 %a = load <2 x double>, ptr %x5144 %b = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %a)5145 store <2 x double> %b, ptr %x5146 ret void5147}5148 5149define void @fmuladd_v8bf16(ptr %x, ptr %y, ptr %z) {5150; CHECK-LABEL: fmuladd_v8bf16:5151; CHECK: # %bb.0:5152; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma5153; CHECK-NEXT: vle16.v v10, (a1)5154; CHECK-NEXT: vle16.v v12, (a0)5155; CHECK-NEXT: vle16.v v13, (a2)5156; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v105157; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v125158; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma5159; CHECK-NEXT: vfmul.vv v8, v10, v85160; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma5161; CHECK-NEXT: vfncvtbf16.f.f.w v10, v85162; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v105163; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v135164; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma5165; CHECK-NEXT: vfadd.vv v8, v8, v105166; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma5167; CHECK-NEXT: vfncvtbf16.f.f.w v10, v85168; CHECK-NEXT: vse16.v v10, (a0)5169; CHECK-NEXT: ret5170 %a = load <8 x bfloat>, ptr %x5171 %b = load <8 x bfloat>, ptr %y5172 %c = load <8 x bfloat>, ptr %z5173 %d = call <8 x bfloat> @llvm.fmuladd.v8bf16(<8 x bfloat> %a, <8 x bfloat> %b, <8 x bfloat> %c)5174 store <8 x bfloat> %d, ptr %x5175 ret void5176}5177 5178define void @fmuladd_v6bf16(ptr %x, ptr %y, ptr %z) {5179; CHECK-LABEL: fmuladd_v6bf16:5180; CHECK: # %bb.0:5181; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma5182; CHECK-NEXT: vle16.v v10, (a1)5183; CHECK-NEXT: vle16.v v12, (a0)5184; CHECK-NEXT: vle16.v v13, (a2)5185; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v105186; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v125187; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma5188; CHECK-NEXT: vfmul.vv v8, v10, v85189; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma5190; CHECK-NEXT: vfncvtbf16.f.f.w v10, v85191; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v105192; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v135193; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma5194; CHECK-NEXT: vfadd.vv v8, v8, v105195; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma5196; CHECK-NEXT: vfncvtbf16.f.f.w v10, v85197; CHECK-NEXT: vse16.v v10, (a0)5198; CHECK-NEXT: ret5199 %a = load <6 x bfloat>, ptr %x5200 %b = load <6 x bfloat>, ptr %y5201 %c = load <6 x bfloat>, ptr %z5202 %d = call <6 x bfloat> @llvm.fmuladd.v6bf16(<6 x bfloat> %a, <6 x bfloat> %b, <6 x bfloat> %c)5203 store <6 x bfloat> %d, ptr %x5204 ret void5205}5206 5207define void @fmuladd_v8f16(ptr %x, ptr %y, ptr %z) {5208; ZVFH-LABEL: fmuladd_v8f16:5209; ZVFH: # %bb.0:5210; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma5211; ZVFH-NEXT: vle16.v v8, (a0)5212; ZVFH-NEXT: vle16.v v9, (a1)5213; ZVFH-NEXT: vle16.v v10, (a2)5214; ZVFH-NEXT: vfmacc.vv v10, v8, v95215; ZVFH-NEXT: vse16.v v10, (a0)5216; ZVFH-NEXT: ret5217;5218; ZVFHMIN-LABEL: fmuladd_v8f16:5219; ZVFHMIN: # %bb.0:5220; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma5221; ZVFHMIN-NEXT: vle16.v v10, (a1)5222; ZVFHMIN-NEXT: vle16.v v12, (a0)5223; ZVFHMIN-NEXT: vle16.v v13, (a2)5224; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v105225; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v125226; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma5227; ZVFHMIN-NEXT: vfmul.vv v8, v10, v85228; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma5229; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v85230; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v105231; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v135232; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma5233; ZVFHMIN-NEXT: vfadd.vv v8, v8, v105234; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma5235; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v85236; ZVFHMIN-NEXT: vse16.v v10, (a0)5237; ZVFHMIN-NEXT: ret5238 %a = load <8 x half>, ptr %x5239 %b = load <8 x half>, ptr %y5240 %c = load <8 x half>, ptr %z5241 %d = call <8 x half> @llvm.fmuladd.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c)5242 store <8 x half> %d, ptr %x5243 ret void5244}5245 5246define void @fmuladd_v6f16(ptr %x, ptr %y, ptr %z) {5247; ZVFH-LABEL: fmuladd_v6f16:5248; ZVFH: # %bb.0:5249; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma5250; ZVFH-NEXT: vle16.v v8, (a0)5251; ZVFH-NEXT: vle16.v v9, (a1)5252; ZVFH-NEXT: vle16.v v10, (a2)5253; ZVFH-NEXT: vfmacc.vv v10, v8, v95254; ZVFH-NEXT: vse16.v v10, (a0)5255; ZVFH-NEXT: ret5256;5257; ZVFHMIN-LABEL: fmuladd_v6f16:5258; ZVFHMIN: # %bb.0:5259; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma5260; ZVFHMIN-NEXT: vle16.v v10, (a1)5261; ZVFHMIN-NEXT: vle16.v v12, (a0)5262; ZVFHMIN-NEXT: vle16.v v13, (a2)5263; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v105264; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v125265; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma5266; ZVFHMIN-NEXT: vfmul.vv v8, v10, v85267; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma5268; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v85269; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v105270; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v135271; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma5272; ZVFHMIN-NEXT: vfadd.vv v8, v8, v105273; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma5274; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v85275; ZVFHMIN-NEXT: vse16.v v10, (a0)5276; ZVFHMIN-NEXT: ret5277 %a = load <6 x half>, ptr %x5278 %b = load <6 x half>, ptr %y5279 %c = load <6 x half>, ptr %z5280 %d = call <6 x half> @llvm.fmuladd.v6f16(<6 x half> %a, <6 x half> %b, <6 x half> %c)5281 store <6 x half> %d, ptr %x5282 ret void5283}5284 5285define void @fmuladd_v4f32(ptr %x, ptr %y, ptr %z) {5286; CHECK-LABEL: fmuladd_v4f32:5287; CHECK: # %bb.0:5288; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma5289; CHECK-NEXT: vle32.v v8, (a0)5290; CHECK-NEXT: vle32.v v9, (a1)5291; CHECK-NEXT: vle32.v v10, (a2)5292; CHECK-NEXT: vfmacc.vv v10, v8, v95293; CHECK-NEXT: vse32.v v10, (a0)5294; CHECK-NEXT: ret5295 %a = load <4 x float>, ptr %x5296 %b = load <4 x float>, ptr %y5297 %c = load <4 x float>, ptr %z5298 %d = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)5299 store <4 x float> %d, ptr %x5300 ret void5301}5302 5303define void @fmuladd_v2f64(ptr %x, ptr %y, ptr %z) {5304; CHECK-LABEL: fmuladd_v2f64:5305; CHECK: # %bb.0:5306; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma5307; CHECK-NEXT: vle64.v v8, (a0)5308; CHECK-NEXT: vle64.v v9, (a1)5309; CHECK-NEXT: vle64.v v10, (a2)5310; CHECK-NEXT: vfmacc.vv v10, v8, v95311; CHECK-NEXT: vse64.v v10, (a0)5312; CHECK-NEXT: ret5313 %a = load <2 x double>, ptr %x5314 %b = load <2 x double>, ptr %y5315 %c = load <2 x double>, ptr %z5316 %d = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c)5317 store <2 x double> %d, ptr %x5318 ret void5319}5320 5321define void @fmsub_fmuladd_v8bf16(ptr %x, ptr %y, ptr %z) {5322; CHECK-LABEL: fmsub_fmuladd_v8bf16:5323; CHECK: # %bb.0:5324; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma5325; CHECK-NEXT: vle16.v v10, (a1)5326; CHECK-NEXT: vle16.v v12, (a0)5327; CHECK-NEXT: vle16.v v13, (a2)5328; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v105329; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v125330; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma5331; CHECK-NEXT: vfmul.vv v8, v10, v85332; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma5333; CHECK-NEXT: vfncvtbf16.f.f.w v10, v85334; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v105335; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v135336; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma5337; CHECK-NEXT: vfsub.vv v8, v8, v105338; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma5339; CHECK-NEXT: vfncvtbf16.f.f.w v10, v85340; CHECK-NEXT: vse16.v v10, (a0)5341; CHECK-NEXT: ret5342 %a = load <8 x bfloat>, ptr %x5343 %b = load <8 x bfloat>, ptr %y5344 %c = load <8 x bfloat>, ptr %z5345 %neg = fneg <8 x bfloat> %c5346 %d = call <8 x bfloat> @llvm.fmuladd.v8bf16(<8 x bfloat> %a, <8 x bfloat> %b, <8 x bfloat> %neg)5347 store <8 x bfloat> %d, ptr %x5348 ret void5349}5350 5351define void @fmsub_fmuladd_v6bf16(ptr %x, ptr %y, ptr %z) {5352; CHECK-LABEL: fmsub_fmuladd_v6bf16:5353; CHECK: # %bb.0:5354; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma5355; CHECK-NEXT: vle16.v v10, (a1)5356; CHECK-NEXT: vle16.v v12, (a0)5357; CHECK-NEXT: vle16.v v13, (a2)5358; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v105359; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v125360; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma5361; CHECK-NEXT: vfmul.vv v8, v10, v85362; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma5363; CHECK-NEXT: vfncvtbf16.f.f.w v10, v85364; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v105365; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v135366; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma5367; CHECK-NEXT: vfsub.vv v8, v8, v105368; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma5369; CHECK-NEXT: vfncvtbf16.f.f.w v10, v85370; CHECK-NEXT: vse16.v v10, (a0)5371; CHECK-NEXT: ret5372 %a = load <6 x bfloat>, ptr %x5373 %b = load <6 x bfloat>, ptr %y5374 %c = load <6 x bfloat>, ptr %z5375 %neg = fneg <6 x bfloat> %c5376 %d = call <6 x bfloat> @llvm.fmuladd.v6bf16(<6 x bfloat> %a, <6 x bfloat> %b, <6 x bfloat> %neg)5377 store <6 x bfloat> %d, ptr %x5378 ret void5379}5380 5381define void @fmsub_fmuladd_v8f16(ptr %x, ptr %y, ptr %z) {5382; ZVFH-LABEL: fmsub_fmuladd_v8f16:5383; ZVFH: # %bb.0:5384; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma5385; ZVFH-NEXT: vle16.v v8, (a0)5386; ZVFH-NEXT: vle16.v v9, (a1)5387; ZVFH-NEXT: vle16.v v10, (a2)5388; ZVFH-NEXT: vfmsac.vv v10, v8, v95389; ZVFH-NEXT: vse16.v v10, (a0)5390; ZVFH-NEXT: ret5391;5392; ZVFHMIN-LABEL: fmsub_fmuladd_v8f16:5393; ZVFHMIN: # %bb.0:5394; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma5395; ZVFHMIN-NEXT: vle16.v v10, (a1)5396; ZVFHMIN-NEXT: vle16.v v12, (a0)5397; ZVFHMIN-NEXT: vle16.v v13, (a2)5398; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v105399; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v125400; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma5401; ZVFHMIN-NEXT: vfmul.vv v8, v10, v85402; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma5403; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v85404; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v105405; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v135406; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma5407; ZVFHMIN-NEXT: vfsub.vv v8, v8, v105408; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma5409; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v85410; ZVFHMIN-NEXT: vse16.v v10, (a0)5411; ZVFHMIN-NEXT: ret5412 %a = load <8 x half>, ptr %x5413 %b = load <8 x half>, ptr %y5414 %c = load <8 x half>, ptr %z5415 %neg = fneg <8 x half> %c5416 %d = call <8 x half> @llvm.fmuladd.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %neg)5417 store <8 x half> %d, ptr %x5418 ret void5419}5420 5421define void @fmsub_fmuladd_v6f16(ptr %x, ptr %y, ptr %z) {5422; ZVFH-LABEL: fmsub_fmuladd_v6f16:5423; ZVFH: # %bb.0:5424; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma5425; ZVFH-NEXT: vle16.v v8, (a0)5426; ZVFH-NEXT: vle16.v v9, (a1)5427; ZVFH-NEXT: vle16.v v10, (a2)5428; ZVFH-NEXT: vfmsac.vv v10, v8, v95429; ZVFH-NEXT: vse16.v v10, (a0)5430; ZVFH-NEXT: ret5431;5432; ZVFHMIN-LABEL: fmsub_fmuladd_v6f16:5433; ZVFHMIN: # %bb.0:5434; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma5435; ZVFHMIN-NEXT: vle16.v v10, (a1)5436; ZVFHMIN-NEXT: vle16.v v12, (a0)5437; ZVFHMIN-NEXT: vle16.v v13, (a2)5438; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v105439; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v125440; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma5441; ZVFHMIN-NEXT: vfmul.vv v8, v10, v85442; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma5443; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v85444; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v105445; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v135446; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma5447; ZVFHMIN-NEXT: vfsub.vv v8, v8, v105448; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma5449; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v85450; ZVFHMIN-NEXT: vse16.v v10, (a0)5451; ZVFHMIN-NEXT: ret5452 %a = load <6 x half>, ptr %x5453 %b = load <6 x half>, ptr %y5454 %c = load <6 x half>, ptr %z5455 %neg = fneg <6 x half> %c5456 %d = call <6 x half> @llvm.fmuladd.v6f16(<6 x half> %a, <6 x half> %b, <6 x half> %neg)5457 store <6 x half> %d, ptr %x5458 ret void5459}5460 5461define void @fnmsub_fmuladd_v4f32(ptr %x, ptr %y, ptr %z) {5462; CHECK-LABEL: fnmsub_fmuladd_v4f32:5463; CHECK: # %bb.0:5464; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma5465; CHECK-NEXT: vle32.v v8, (a0)5466; CHECK-NEXT: vle32.v v9, (a1)5467; CHECK-NEXT: vle32.v v10, (a2)5468; CHECK-NEXT: vfnmsac.vv v10, v8, v95469; CHECK-NEXT: vse32.v v10, (a0)5470; CHECK-NEXT: ret5471 %a = load <4 x float>, ptr %x5472 %b = load <4 x float>, ptr %y5473 %c = load <4 x float>, ptr %z5474 %neg = fneg <4 x float> %a5475 %d = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %neg, <4 x float> %b, <4 x float> %c)5476 store <4 x float> %d, ptr %x5477 ret void5478}5479 5480define void @fnmadd_fmuladd_v2f64(ptr %x, ptr %y, ptr %z) {5481; CHECK-LABEL: fnmadd_fmuladd_v2f64:5482; CHECK: # %bb.0:5483; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma5484; CHECK-NEXT: vle64.v v8, (a0)5485; CHECK-NEXT: vle64.v v9, (a1)5486; CHECK-NEXT: vle64.v v10, (a2)5487; CHECK-NEXT: vfnmacc.vv v10, v8, v95488; CHECK-NEXT: vse64.v v10, (a0)5489; CHECK-NEXT: ret5490 %a = load <2 x double>, ptr %x5491 %b = load <2 x double>, ptr %y5492 %c = load <2 x double>, ptr %z5493 %neg = fneg <2 x double> %b5494 %neg2 = fneg <2 x double> %c5495 %d = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %a, <2 x double> %neg, <2 x double> %neg2)5496 store <2 x double> %d, ptr %x5497 ret void5498}5499