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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH3; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH4; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN5; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN6 7define <4 x i1> @vfptosi_v4i1_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {8; ZVFH-LABEL: vfptosi_v4i1_v4f16:9; ZVFH: # %bb.0:10; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma11; ZVFH-NEXT: vfcvt.rtz.x.f.v v8, v8, v0.t12; ZVFH-NEXT: vmsne.vi v0, v8, 0, v0.t13; ZVFH-NEXT: ret14;15; ZVFHMIN-LABEL: vfptosi_v4i1_v4f16:16; ZVFHMIN: # %bb.0:17; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma18; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v819; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma20; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t21; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0, v0.t22; ZVFHMIN-NEXT: ret23 %v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)24 ret <4 x i1> %v25}26 27define <4 x i1> @vfptosi_v4i1_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {28; ZVFH-LABEL: vfptosi_v4i1_v4f16_unmasked:29; ZVFH: # %bb.0:30; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma31; ZVFH-NEXT: vfcvt.rtz.x.f.v v8, v832; ZVFH-NEXT: vmsne.vi v0, v8, 033; ZVFH-NEXT: ret34;35; ZVFHMIN-LABEL: vfptosi_v4i1_v4f16_unmasked:36; ZVFHMIN: # %bb.0:37; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma38; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v839; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma40; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v8, v941; ZVFHMIN-NEXT: vmsne.vi v0, v8, 042; ZVFHMIN-NEXT: ret43 %v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl)44 ret <4 x i1> %v45}46 47define <4 x i1> @vfptosi_v4i1_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl) {48; CHECK-LABEL: vfptosi_v4i1_v4f32:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma51; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8, v0.t52; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t53; CHECK-NEXT: ret54 %v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl)55 ret <4 x i1> %v56}57 58define <4 x i1> @vfptosi_v4i1_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {59; CHECK-LABEL: vfptosi_v4i1_v4f32_unmasked:60; CHECK: # %bb.0:61; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma62; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v863; CHECK-NEXT: vmsne.vi v0, v8, 064; CHECK-NEXT: ret65 %v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl)66 ret <4 x i1> %v67}68 69define <4 x i1> @vfptosi_v4i1_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {70; CHECK-LABEL: vfptosi_v4i1_v4f64:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma73; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t74; CHECK-NEXT: vmsne.vi v8, v10, 0, v0.t75; CHECK-NEXT: vmv1r.v v0, v876; CHECK-NEXT: ret77 %v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)78 ret <4 x i1> %v79}80 81define <4 x i1> @vfptosi_v4i1_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) {82; CHECK-LABEL: vfptosi_v4i1_v4f64_unmasked:83; CHECK: # %bb.0:84; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma85; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v886; CHECK-NEXT: vmsne.vi v0, v8, 087; CHECK-NEXT: ret88 %v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl)89 ret <4 x i1> %v90}91