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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV32ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV64ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV32ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV64ZVFHMIN10 11; This file tests the code generation for `llvm.round.*` on fixed vector type.12 13define <1 x half> @round_v1f16(<1 x half> %x) {14; ZVFH-LABEL: round_v1f16:15; ZVFH: # %bb.0:16; ZVFH-NEXT: vsetivli zero, 1, e16, mf4, ta, ma17; ZVFH-NEXT: vfabs.v v9, v818; ZVFH-NEXT: li a0, 2519; ZVFH-NEXT: slli a0, a0, 1020; ZVFH-NEXT: fmv.h.x fa5, a021; ZVFH-NEXT: vmflt.vf v0, v9, fa522; ZVFH-NEXT: fsrmi a0, 423; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t24; ZVFH-NEXT: fsrm a025; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t26; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu27; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t28; ZVFH-NEXT: ret29;30; ZVFHMIN-LABEL: round_v1f16:31; ZVFHMIN: # %bb.0:32; ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf4, ta, ma33; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v834; ZVFHMIN-NEXT: lui a0, 30720035; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma36; ZVFHMIN-NEXT: vfabs.v v8, v937; ZVFHMIN-NEXT: fmv.w.x fa5, a038; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa539; ZVFHMIN-NEXT: fsrmi a0, 440; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t41; ZVFHMIN-NEXT: fsrm a042; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t43; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu44; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t45; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma46; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v947; ZVFHMIN-NEXT: ret48 %a = call <1 x half> @llvm.round.v1f16(<1 x half> %x)49 ret <1 x half> %a50}51 52define <2 x half> @round_v2f16(<2 x half> %x) {53; ZVFH-LABEL: round_v2f16:54; ZVFH: # %bb.0:55; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma56; ZVFH-NEXT: vfabs.v v9, v857; ZVFH-NEXT: li a0, 2558; ZVFH-NEXT: slli a0, a0, 1059; ZVFH-NEXT: fmv.h.x fa5, a060; ZVFH-NEXT: vmflt.vf v0, v9, fa561; ZVFH-NEXT: fsrmi a0, 462; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t63; ZVFH-NEXT: fsrm a064; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t65; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu66; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t67; ZVFH-NEXT: ret68;69; ZVFHMIN-LABEL: round_v2f16:70; ZVFHMIN: # %bb.0:71; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma72; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v873; ZVFHMIN-NEXT: lui a0, 30720074; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma75; ZVFHMIN-NEXT: vfabs.v v8, v976; ZVFHMIN-NEXT: fmv.w.x fa5, a077; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa578; ZVFHMIN-NEXT: fsrmi a0, 479; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t80; ZVFHMIN-NEXT: fsrm a081; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t82; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu83; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t84; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma85; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v986; ZVFHMIN-NEXT: ret87 %a = call <2 x half> @llvm.round.v2f16(<2 x half> %x)88 ret <2 x half> %a89}90 91define <4 x half> @round_v4f16(<4 x half> %x) {92; ZVFH-LABEL: round_v4f16:93; ZVFH: # %bb.0:94; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma95; ZVFH-NEXT: vfabs.v v9, v896; ZVFH-NEXT: li a0, 2597; ZVFH-NEXT: slli a0, a0, 1098; ZVFH-NEXT: fmv.h.x fa5, a099; ZVFH-NEXT: vmflt.vf v0, v9, fa5100; ZVFH-NEXT: fsrmi a0, 4101; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t102; ZVFH-NEXT: fsrm a0103; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t104; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu105; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t106; ZVFH-NEXT: ret107;108; ZVFHMIN-LABEL: round_v4f16:109; ZVFHMIN: # %bb.0:110; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma111; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8112; ZVFHMIN-NEXT: lui a0, 307200113; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma114; ZVFHMIN-NEXT: vfabs.v v8, v9115; ZVFHMIN-NEXT: fmv.w.x fa5, a0116; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5117; ZVFHMIN-NEXT: fsrmi a0, 4118; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t119; ZVFHMIN-NEXT: fsrm a0120; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t121; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu122; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t123; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma124; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9125; ZVFHMIN-NEXT: ret126 %a = call <4 x half> @llvm.round.v4f16(<4 x half> %x)127 ret <4 x half> %a128}129 130define <8 x half> @round_v8f16(<8 x half> %x) {131; ZVFH-LABEL: round_v8f16:132; ZVFH: # %bb.0:133; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma134; ZVFH-NEXT: vfabs.v v9, v8135; ZVFH-NEXT: li a0, 25136; ZVFH-NEXT: slli a0, a0, 10137; ZVFH-NEXT: fmv.h.x fa5, a0138; ZVFH-NEXT: vmflt.vf v0, v9, fa5139; ZVFH-NEXT: fsrmi a0, 4140; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t141; ZVFH-NEXT: fsrm a0142; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t143; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu144; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t145; ZVFH-NEXT: ret146;147; ZVFHMIN-LABEL: round_v8f16:148; ZVFHMIN: # %bb.0:149; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma150; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8151; ZVFHMIN-NEXT: lui a0, 307200152; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma153; ZVFHMIN-NEXT: vfabs.v v8, v10154; ZVFHMIN-NEXT: fmv.w.x fa5, a0155; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5156; ZVFHMIN-NEXT: fsrmi a0, 4157; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t158; ZVFHMIN-NEXT: fsrm a0159; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t160; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu161; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t162; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma163; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10164; ZVFHMIN-NEXT: ret165 %a = call <8 x half> @llvm.round.v8f16(<8 x half> %x)166 ret <8 x half> %a167}168 169define <16 x half> @round_v16f16(<16 x half> %x) {170; ZVFH-LABEL: round_v16f16:171; ZVFH: # %bb.0:172; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma173; ZVFH-NEXT: vfabs.v v10, v8174; ZVFH-NEXT: li a0, 25175; ZVFH-NEXT: slli a0, a0, 10176; ZVFH-NEXT: fmv.h.x fa5, a0177; ZVFH-NEXT: vmflt.vf v0, v10, fa5178; ZVFH-NEXT: fsrmi a0, 4179; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t180; ZVFH-NEXT: fsrm a0181; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t182; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu183; ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t184; ZVFH-NEXT: ret185;186; ZVFHMIN-LABEL: round_v16f16:187; ZVFHMIN: # %bb.0:188; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma189; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8190; ZVFHMIN-NEXT: lui a0, 307200191; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma192; ZVFHMIN-NEXT: vfabs.v v8, v12193; ZVFHMIN-NEXT: fmv.w.x fa5, a0194; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5195; ZVFHMIN-NEXT: fsrmi a0, 4196; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t197; ZVFHMIN-NEXT: fsrm a0198; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t199; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu200; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t201; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma202; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12203; ZVFHMIN-NEXT: ret204 %a = call <16 x half> @llvm.round.v16f16(<16 x half> %x)205 ret <16 x half> %a206}207 208define <32 x half> @round_v32f16(<32 x half> %x) {209; ZVFH-LABEL: round_v32f16:210; ZVFH: # %bb.0:211; ZVFH-NEXT: li a0, 32212; ZVFH-NEXT: li a1, 25213; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma214; ZVFH-NEXT: vfabs.v v12, v8215; ZVFH-NEXT: slli a1, a1, 10216; ZVFH-NEXT: fmv.h.x fa5, a1217; ZVFH-NEXT: vmflt.vf v0, v12, fa5218; ZVFH-NEXT: fsrmi a0, 4219; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t220; ZVFH-NEXT: fsrm a0221; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t222; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu223; ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t224; ZVFH-NEXT: ret225;226; ZVFHMIN-LABEL: round_v32f16:227; ZVFHMIN: # %bb.0:228; ZVFHMIN-NEXT: li a0, 32229; ZVFHMIN-NEXT: lui a1, 307200230; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma231; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8232; ZVFHMIN-NEXT: fmv.w.x fa5, a1233; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma234; ZVFHMIN-NEXT: vfabs.v v8, v16235; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5236; ZVFHMIN-NEXT: fsrmi a0, 4237; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t238; ZVFHMIN-NEXT: fsrm a0239; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t240; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu241; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t242; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma243; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16244; ZVFHMIN-NEXT: ret245 %a = call <32 x half> @llvm.round.v32f16(<32 x half> %x)246 ret <32 x half> %a247}248 249define <1 x float> @round_v1f32(<1 x float> %x) {250; CHECK-LABEL: round_v1f32:251; CHECK: # %bb.0:252; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma253; CHECK-NEXT: vfabs.v v9, v8254; CHECK-NEXT: lui a0, 307200255; CHECK-NEXT: fmv.w.x fa5, a0256; CHECK-NEXT: vmflt.vf v0, v9, fa5257; CHECK-NEXT: fsrmi a0, 4258; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t259; CHECK-NEXT: fsrm a0260; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t261; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu262; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t263; CHECK-NEXT: ret264 %a = call <1 x float> @llvm.round.v1f32(<1 x float> %x)265 ret <1 x float> %a266}267 268define <2 x float> @round_v2f32(<2 x float> %x) {269; CHECK-LABEL: round_v2f32:270; CHECK: # %bb.0:271; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma272; CHECK-NEXT: vfabs.v v9, v8273; CHECK-NEXT: lui a0, 307200274; CHECK-NEXT: fmv.w.x fa5, a0275; CHECK-NEXT: vmflt.vf v0, v9, fa5276; CHECK-NEXT: fsrmi a0, 4277; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t278; CHECK-NEXT: fsrm a0279; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t280; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu281; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t282; CHECK-NEXT: ret283 %a = call <2 x float> @llvm.round.v2f32(<2 x float> %x)284 ret <2 x float> %a285}286 287define <4 x float> @round_v4f32(<4 x float> %x) {288; CHECK-LABEL: round_v4f32:289; CHECK: # %bb.0:290; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma291; CHECK-NEXT: vfabs.v v9, v8292; CHECK-NEXT: lui a0, 307200293; CHECK-NEXT: fmv.w.x fa5, a0294; CHECK-NEXT: vmflt.vf v0, v9, fa5295; CHECK-NEXT: fsrmi a0, 4296; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t297; CHECK-NEXT: fsrm a0298; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t299; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu300; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t301; CHECK-NEXT: ret302 %a = call <4 x float> @llvm.round.v4f32(<4 x float> %x)303 ret <4 x float> %a304}305 306define <8 x float> @round_v8f32(<8 x float> %x) {307; CHECK-LABEL: round_v8f32:308; CHECK: # %bb.0:309; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma310; CHECK-NEXT: vfabs.v v10, v8311; CHECK-NEXT: lui a0, 307200312; CHECK-NEXT: fmv.w.x fa5, a0313; CHECK-NEXT: vmflt.vf v0, v10, fa5314; CHECK-NEXT: fsrmi a0, 4315; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t316; CHECK-NEXT: fsrm a0317; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t318; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu319; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t320; CHECK-NEXT: ret321 %a = call <8 x float> @llvm.round.v8f32(<8 x float> %x)322 ret <8 x float> %a323}324 325define <16 x float> @round_v16f32(<16 x float> %x) {326; CHECK-LABEL: round_v16f32:327; CHECK: # %bb.0:328; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma329; CHECK-NEXT: vfabs.v v12, v8330; CHECK-NEXT: lui a0, 307200331; CHECK-NEXT: fmv.w.x fa5, a0332; CHECK-NEXT: vmflt.vf v0, v12, fa5333; CHECK-NEXT: fsrmi a0, 4334; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t335; CHECK-NEXT: fsrm a0336; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t337; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu338; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t339; CHECK-NEXT: ret340 %a = call <16 x float> @llvm.round.v16f32(<16 x float> %x)341 ret <16 x float> %a342}343 344define <1 x double> @round_v1f64(<1 x double> %x) {345; RV32ZVFH-LABEL: round_v1f64:346; RV32ZVFH: # %bb.0:347; RV32ZVFH-NEXT: lui a0, %hi(.LCPI11_0)348; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI11_0)(a0)349; RV32ZVFH-NEXT: vsetivli zero, 1, e64, m1, ta, ma350; RV32ZVFH-NEXT: vfabs.v v9, v8351; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5352; RV32ZVFH-NEXT: fsrmi a0, 4353; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t354; RV32ZVFH-NEXT: fsrm a0355; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t356; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu357; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t358; RV32ZVFH-NEXT: ret359;360; RV64ZVFH-LABEL: round_v1f64:361; RV64ZVFH: # %bb.0:362; RV64ZVFH-NEXT: vsetivli zero, 1, e64, m1, ta, ma363; RV64ZVFH-NEXT: vfabs.v v9, v8364; RV64ZVFH-NEXT: li a0, 1075365; RV64ZVFH-NEXT: slli a0, a0, 52366; RV64ZVFH-NEXT: fmv.d.x fa5, a0367; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5368; RV64ZVFH-NEXT: fsrmi a0, 4369; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t370; RV64ZVFH-NEXT: fsrm a0371; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t372; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu373; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t374; RV64ZVFH-NEXT: ret375;376; RV32ZVFHMIN-LABEL: round_v1f64:377; RV32ZVFHMIN: # %bb.0:378; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI11_0)379; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI11_0)(a0)380; RV32ZVFHMIN-NEXT: vsetivli zero, 1, e64, m1, ta, ma381; RV32ZVFHMIN-NEXT: vfabs.v v9, v8382; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5383; RV32ZVFHMIN-NEXT: fsrmi a0, 4384; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t385; RV32ZVFHMIN-NEXT: fsrm a0386; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t387; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu388; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t389; RV32ZVFHMIN-NEXT: ret390;391; RV64ZVFHMIN-LABEL: round_v1f64:392; RV64ZVFHMIN: # %bb.0:393; RV64ZVFHMIN-NEXT: vsetivli zero, 1, e64, m1, ta, ma394; RV64ZVFHMIN-NEXT: vfabs.v v9, v8395; RV64ZVFHMIN-NEXT: li a0, 1075396; RV64ZVFHMIN-NEXT: slli a0, a0, 52397; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0398; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5399; RV64ZVFHMIN-NEXT: fsrmi a0, 4400; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t401; RV64ZVFHMIN-NEXT: fsrm a0402; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t403; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu404; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t405; RV64ZVFHMIN-NEXT: ret406 %a = call <1 x double> @llvm.round.v1f64(<1 x double> %x)407 ret <1 x double> %a408}409 410define <2 x double> @round_v2f64(<2 x double> %x) {411; RV32ZVFH-LABEL: round_v2f64:412; RV32ZVFH: # %bb.0:413; RV32ZVFH-NEXT: lui a0, %hi(.LCPI12_0)414; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI12_0)(a0)415; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma416; RV32ZVFH-NEXT: vfabs.v v9, v8417; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5418; RV32ZVFH-NEXT: fsrmi a0, 4419; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t420; RV32ZVFH-NEXT: fsrm a0421; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t422; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu423; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t424; RV32ZVFH-NEXT: ret425;426; RV64ZVFH-LABEL: round_v2f64:427; RV64ZVFH: # %bb.0:428; RV64ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma429; RV64ZVFH-NEXT: vfabs.v v9, v8430; RV64ZVFH-NEXT: li a0, 1075431; RV64ZVFH-NEXT: slli a0, a0, 52432; RV64ZVFH-NEXT: fmv.d.x fa5, a0433; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5434; RV64ZVFH-NEXT: fsrmi a0, 4435; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t436; RV64ZVFH-NEXT: fsrm a0437; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t438; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu439; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t440; RV64ZVFH-NEXT: ret441;442; RV32ZVFHMIN-LABEL: round_v2f64:443; RV32ZVFHMIN: # %bb.0:444; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI12_0)445; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI12_0)(a0)446; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma447; RV32ZVFHMIN-NEXT: vfabs.v v9, v8448; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5449; RV32ZVFHMIN-NEXT: fsrmi a0, 4450; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t451; RV32ZVFHMIN-NEXT: fsrm a0452; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t453; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu454; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t455; RV32ZVFHMIN-NEXT: ret456;457; RV64ZVFHMIN-LABEL: round_v2f64:458; RV64ZVFHMIN: # %bb.0:459; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma460; RV64ZVFHMIN-NEXT: vfabs.v v9, v8461; RV64ZVFHMIN-NEXT: li a0, 1075462; RV64ZVFHMIN-NEXT: slli a0, a0, 52463; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0464; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5465; RV64ZVFHMIN-NEXT: fsrmi a0, 4466; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t467; RV64ZVFHMIN-NEXT: fsrm a0468; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t469; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu470; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t471; RV64ZVFHMIN-NEXT: ret472 %a = call <2 x double> @llvm.round.v2f64(<2 x double> %x)473 ret <2 x double> %a474}475 476define <4 x double> @round_v4f64(<4 x double> %x) {477; RV32ZVFH-LABEL: round_v4f64:478; RV32ZVFH: # %bb.0:479; RV32ZVFH-NEXT: lui a0, %hi(.LCPI13_0)480; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI13_0)(a0)481; RV32ZVFH-NEXT: vsetivli zero, 4, e64, m2, ta, ma482; RV32ZVFH-NEXT: vfabs.v v10, v8483; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5484; RV32ZVFH-NEXT: fsrmi a0, 4485; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t486; RV32ZVFH-NEXT: fsrm a0487; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t488; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu489; RV32ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t490; RV32ZVFH-NEXT: ret491;492; RV64ZVFH-LABEL: round_v4f64:493; RV64ZVFH: # %bb.0:494; RV64ZVFH-NEXT: vsetivli zero, 4, e64, m2, ta, ma495; RV64ZVFH-NEXT: vfabs.v v10, v8496; RV64ZVFH-NEXT: li a0, 1075497; RV64ZVFH-NEXT: slli a0, a0, 52498; RV64ZVFH-NEXT: fmv.d.x fa5, a0499; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5500; RV64ZVFH-NEXT: fsrmi a0, 4501; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t502; RV64ZVFH-NEXT: fsrm a0503; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t504; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu505; RV64ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t506; RV64ZVFH-NEXT: ret507;508; RV32ZVFHMIN-LABEL: round_v4f64:509; RV32ZVFHMIN: # %bb.0:510; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI13_0)511; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI13_0)(a0)512; RV32ZVFHMIN-NEXT: vsetivli zero, 4, e64, m2, ta, ma513; RV32ZVFHMIN-NEXT: vfabs.v v10, v8514; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5515; RV32ZVFHMIN-NEXT: fsrmi a0, 4516; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t517; RV32ZVFHMIN-NEXT: fsrm a0518; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t519; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu520; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t521; RV32ZVFHMIN-NEXT: ret522;523; RV64ZVFHMIN-LABEL: round_v4f64:524; RV64ZVFHMIN: # %bb.0:525; RV64ZVFHMIN-NEXT: vsetivli zero, 4, e64, m2, ta, ma526; RV64ZVFHMIN-NEXT: vfabs.v v10, v8527; RV64ZVFHMIN-NEXT: li a0, 1075528; RV64ZVFHMIN-NEXT: slli a0, a0, 52529; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0530; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5531; RV64ZVFHMIN-NEXT: fsrmi a0, 4532; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t533; RV64ZVFHMIN-NEXT: fsrm a0534; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t535; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu536; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t537; RV64ZVFHMIN-NEXT: ret538 %a = call <4 x double> @llvm.round.v4f64(<4 x double> %x)539 ret <4 x double> %a540}541 542define <8 x double> @round_v8f64(<8 x double> %x) {543; RV32ZVFH-LABEL: round_v8f64:544; RV32ZVFH: # %bb.0:545; RV32ZVFH-NEXT: lui a0, %hi(.LCPI14_0)546; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI14_0)(a0)547; RV32ZVFH-NEXT: vsetivli zero, 8, e64, m4, ta, ma548; RV32ZVFH-NEXT: vfabs.v v12, v8549; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5550; RV32ZVFH-NEXT: fsrmi a0, 4551; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t552; RV32ZVFH-NEXT: fsrm a0553; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t554; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu555; RV32ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t556; RV32ZVFH-NEXT: ret557;558; RV64ZVFH-LABEL: round_v8f64:559; RV64ZVFH: # %bb.0:560; RV64ZVFH-NEXT: vsetivli zero, 8, e64, m4, ta, ma561; RV64ZVFH-NEXT: vfabs.v v12, v8562; RV64ZVFH-NEXT: li a0, 1075563; RV64ZVFH-NEXT: slli a0, a0, 52564; RV64ZVFH-NEXT: fmv.d.x fa5, a0565; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5566; RV64ZVFH-NEXT: fsrmi a0, 4567; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t568; RV64ZVFH-NEXT: fsrm a0569; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t570; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu571; RV64ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t572; RV64ZVFH-NEXT: ret573;574; RV32ZVFHMIN-LABEL: round_v8f64:575; RV32ZVFHMIN: # %bb.0:576; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI14_0)577; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI14_0)(a0)578; RV32ZVFHMIN-NEXT: vsetivli zero, 8, e64, m4, ta, ma579; RV32ZVFHMIN-NEXT: vfabs.v v12, v8580; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5581; RV32ZVFHMIN-NEXT: fsrmi a0, 4582; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t583; RV32ZVFHMIN-NEXT: fsrm a0584; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t585; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu586; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t587; RV32ZVFHMIN-NEXT: ret588;589; RV64ZVFHMIN-LABEL: round_v8f64:590; RV64ZVFHMIN: # %bb.0:591; RV64ZVFHMIN-NEXT: vsetivli zero, 8, e64, m4, ta, ma592; RV64ZVFHMIN-NEXT: vfabs.v v12, v8593; RV64ZVFHMIN-NEXT: li a0, 1075594; RV64ZVFHMIN-NEXT: slli a0, a0, 52595; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0596; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5597; RV64ZVFHMIN-NEXT: fsrmi a0, 4598; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t599; RV64ZVFHMIN-NEXT: fsrm a0600; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t601; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu602; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t603; RV64ZVFHMIN-NEXT: ret604 %a = call <8 x double> @llvm.round.v8f64(<8 x double> %x)605 ret <8 x double> %a606}607