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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s4 5define <2 x i8> @fshr_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i1> %m, i32 zeroext %evl) {6; CHECK-LABEL: fshr_v2i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma9; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t10; CHECK-NEXT: vnot.v v11, v10, v0.t11; CHECK-NEXT: vand.vi v11, v11, 7, v0.t12; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t13; CHECK-NEXT: vand.vi v10, v10, 7, v0.t14; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t15; CHECK-NEXT: vor.vv v8, v8, v9, v0.t16; CHECK-NEXT: ret17 %res = call <2 x i8> @llvm.vp.fshr.v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i1> %m, i32 %evl)18 ret <2 x i8> %res19}20 21define <2 x i8> @fshl_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i1> %m, i32 zeroext %evl) {22; CHECK-LABEL: fshl_v2i8:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma25; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t26; CHECK-NEXT: vnot.v v11, v10, v0.t27; CHECK-NEXT: vand.vi v11, v11, 7, v0.t28; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t29; CHECK-NEXT: vand.vi v10, v10, 7, v0.t30; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t31; CHECK-NEXT: vor.vv v8, v8, v9, v0.t32; CHECK-NEXT: ret33 %res = call <2 x i8> @llvm.vp.fshl.v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i1> %m, i32 %evl)34 ret <2 x i8> %res35}36 37define <4 x i8> @fshr_v4i8(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c, <4 x i1> %m, i32 zeroext %evl) {38; CHECK-LABEL: fshr_v4i8:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma41; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t42; CHECK-NEXT: vnot.v v11, v10, v0.t43; CHECK-NEXT: vand.vi v11, v11, 7, v0.t44; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t45; CHECK-NEXT: vand.vi v10, v10, 7, v0.t46; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t47; CHECK-NEXT: vor.vv v8, v8, v9, v0.t48; CHECK-NEXT: ret49 %res = call <4 x i8> @llvm.vp.fshr.v4i8(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c, <4 x i1> %m, i32 %evl)50 ret <4 x i8> %res51}52 53define <4 x i8> @fshl_v4i8(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c, <4 x i1> %m, i32 zeroext %evl) {54; CHECK-LABEL: fshl_v4i8:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma57; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t58; CHECK-NEXT: vnot.v v11, v10, v0.t59; CHECK-NEXT: vand.vi v11, v11, 7, v0.t60; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t61; CHECK-NEXT: vand.vi v10, v10, 7, v0.t62; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t63; CHECK-NEXT: vor.vv v8, v8, v9, v0.t64; CHECK-NEXT: ret65 %res = call <4 x i8> @llvm.vp.fshl.v4i8(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c, <4 x i1> %m, i32 %evl)66 ret <4 x i8> %res67}68 69define <8 x i8> @fshr_v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i1> %m, i32 zeroext %evl) {70; CHECK-LABEL: fshr_v8i8:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma73; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t74; CHECK-NEXT: vnot.v v11, v10, v0.t75; CHECK-NEXT: vand.vi v11, v11, 7, v0.t76; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t77; CHECK-NEXT: vand.vi v10, v10, 7, v0.t78; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t79; CHECK-NEXT: vor.vv v8, v8, v9, v0.t80; CHECK-NEXT: ret81 %res = call <8 x i8> @llvm.vp.fshr.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i1> %m, i32 %evl)82 ret <8 x i8> %res83}84 85define <8 x i8> @fshl_v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i1> %m, i32 zeroext %evl) {86; CHECK-LABEL: fshl_v8i8:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma89; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t90; CHECK-NEXT: vnot.v v11, v10, v0.t91; CHECK-NEXT: vand.vi v11, v11, 7, v0.t92; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t93; CHECK-NEXT: vand.vi v10, v10, 7, v0.t94; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t95; CHECK-NEXT: vor.vv v8, v8, v9, v0.t96; CHECK-NEXT: ret97 %res = call <8 x i8> @llvm.vp.fshl.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i1> %m, i32 %evl)98 ret <8 x i8> %res99}100 101define <16 x i8> @fshr_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i1> %m, i32 zeroext %evl) {102; CHECK-LABEL: fshr_v16i8:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma105; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t106; CHECK-NEXT: vnot.v v11, v10, v0.t107; CHECK-NEXT: vand.vi v11, v11, 7, v0.t108; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t109; CHECK-NEXT: vand.vi v10, v10, 7, v0.t110; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t111; CHECK-NEXT: vor.vv v8, v8, v9, v0.t112; CHECK-NEXT: ret113 %res = call <16 x i8> @llvm.vp.fshr.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i1> %m, i32 %evl)114 ret <16 x i8> %res115}116 117define <16 x i8> @fshl_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i1> %m, i32 zeroext %evl) {118; CHECK-LABEL: fshl_v16i8:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma121; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t122; CHECK-NEXT: vnot.v v11, v10, v0.t123; CHECK-NEXT: vand.vi v11, v11, 7, v0.t124; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t125; CHECK-NEXT: vand.vi v10, v10, 7, v0.t126; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t127; CHECK-NEXT: vor.vv v8, v8, v9, v0.t128; CHECK-NEXT: ret129 %res = call <16 x i8> @llvm.vp.fshl.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i1> %m, i32 %evl)130 ret <16 x i8> %res131}132 133define <32 x i8> @fshr_v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %c, <32 x i1> %m, i32 zeroext %evl) {134; CHECK-LABEL: fshr_v32i8:135; CHECK: # %bb.0:136; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma137; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t138; CHECK-NEXT: vnot.v v14, v12, v0.t139; CHECK-NEXT: vand.vi v14, v14, 7, v0.t140; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t141; CHECK-NEXT: vand.vi v12, v12, 7, v0.t142; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t143; CHECK-NEXT: vor.vv v8, v8, v10, v0.t144; CHECK-NEXT: ret145 %res = call <32 x i8> @llvm.vp.fshr.v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %c, <32 x i1> %m, i32 %evl)146 ret <32 x i8> %res147}148 149define <32 x i8> @fshl_v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %c, <32 x i1> %m, i32 zeroext %evl) {150; CHECK-LABEL: fshl_v32i8:151; CHECK: # %bb.0:152; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma153; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t154; CHECK-NEXT: vnot.v v14, v12, v0.t155; CHECK-NEXT: vand.vi v14, v14, 7, v0.t156; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t157; CHECK-NEXT: vand.vi v12, v12, 7, v0.t158; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t159; CHECK-NEXT: vor.vv v8, v8, v10, v0.t160; CHECK-NEXT: ret161 %res = call <32 x i8> @llvm.vp.fshl.v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %c, <32 x i1> %m, i32 %evl)162 ret <32 x i8> %res163}164 165define <64 x i8> @fshr_v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c, <64 x i1> %m, i32 zeroext %evl) {166; CHECK-LABEL: fshr_v64i8:167; CHECK: # %bb.0:168; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma169; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t170; CHECK-NEXT: vnot.v v20, v16, v0.t171; CHECK-NEXT: vand.vi v20, v20, 7, v0.t172; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t173; CHECK-NEXT: vand.vi v16, v16, 7, v0.t174; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t175; CHECK-NEXT: vor.vv v8, v8, v12, v0.t176; CHECK-NEXT: ret177 %res = call <64 x i8> @llvm.vp.fshr.v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c, <64 x i1> %m, i32 %evl)178 ret <64 x i8> %res179}180 181define <64 x i8> @fshl_v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c, <64 x i1> %m, i32 zeroext %evl) {182; CHECK-LABEL: fshl_v64i8:183; CHECK: # %bb.0:184; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma185; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t186; CHECK-NEXT: vnot.v v20, v16, v0.t187; CHECK-NEXT: vand.vi v20, v20, 7, v0.t188; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t189; CHECK-NEXT: vand.vi v16, v16, 7, v0.t190; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t191; CHECK-NEXT: vor.vv v8, v8, v12, v0.t192; CHECK-NEXT: ret193 %res = call <64 x i8> @llvm.vp.fshl.v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c, <64 x i1> %m, i32 %evl)194 ret <64 x i8> %res195}196 197define <2 x i16> @fshr_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i1> %m, i32 zeroext %evl) {198; CHECK-LABEL: fshr_v2i16:199; CHECK: # %bb.0:200; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma201; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t202; CHECK-NEXT: vnot.v v11, v10, v0.t203; CHECK-NEXT: vand.vi v11, v11, 15, v0.t204; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t205; CHECK-NEXT: vand.vi v10, v10, 15, v0.t206; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t207; CHECK-NEXT: vor.vv v8, v8, v9, v0.t208; CHECK-NEXT: ret209 %res = call <2 x i16> @llvm.vp.fshr.v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i1> %m, i32 %evl)210 ret <2 x i16> %res211}212 213define <2 x i16> @fshl_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i1> %m, i32 zeroext %evl) {214; CHECK-LABEL: fshl_v2i16:215; CHECK: # %bb.0:216; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma217; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t218; CHECK-NEXT: vnot.v v11, v10, v0.t219; CHECK-NEXT: vand.vi v11, v11, 15, v0.t220; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t221; CHECK-NEXT: vand.vi v10, v10, 15, v0.t222; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t223; CHECK-NEXT: vor.vv v8, v8, v9, v0.t224; CHECK-NEXT: ret225 %res = call <2 x i16> @llvm.vp.fshl.v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i1> %m, i32 %evl)226 ret <2 x i16> %res227}228 229define <4 x i16> @fshr_v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i1> %m, i32 zeroext %evl) {230; CHECK-LABEL: fshr_v4i16:231; CHECK: # %bb.0:232; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma233; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t234; CHECK-NEXT: vnot.v v11, v10, v0.t235; CHECK-NEXT: vand.vi v11, v11, 15, v0.t236; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t237; CHECK-NEXT: vand.vi v10, v10, 15, v0.t238; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t239; CHECK-NEXT: vor.vv v8, v8, v9, v0.t240; CHECK-NEXT: ret241 %res = call <4 x i16> @llvm.vp.fshr.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i1> %m, i32 %evl)242 ret <4 x i16> %res243}244 245define <4 x i16> @fshl_v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i1> %m, i32 zeroext %evl) {246; CHECK-LABEL: fshl_v4i16:247; CHECK: # %bb.0:248; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma249; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t250; CHECK-NEXT: vnot.v v11, v10, v0.t251; CHECK-NEXT: vand.vi v11, v11, 15, v0.t252; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t253; CHECK-NEXT: vand.vi v10, v10, 15, v0.t254; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t255; CHECK-NEXT: vor.vv v8, v8, v9, v0.t256; CHECK-NEXT: ret257 %res = call <4 x i16> @llvm.vp.fshl.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i1> %m, i32 %evl)258 ret <4 x i16> %res259}260 261define <8 x i16> @fshr_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i1> %m, i32 zeroext %evl) {262; CHECK-LABEL: fshr_v8i16:263; CHECK: # %bb.0:264; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma265; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t266; CHECK-NEXT: vnot.v v11, v10, v0.t267; CHECK-NEXT: vand.vi v11, v11, 15, v0.t268; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t269; CHECK-NEXT: vand.vi v10, v10, 15, v0.t270; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t271; CHECK-NEXT: vor.vv v8, v8, v9, v0.t272; CHECK-NEXT: ret273 %res = call <8 x i16> @llvm.vp.fshr.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i1> %m, i32 %evl)274 ret <8 x i16> %res275}276 277define <8 x i16> @fshl_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i1> %m, i32 zeroext %evl) {278; CHECK-LABEL: fshl_v8i16:279; CHECK: # %bb.0:280; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma281; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t282; CHECK-NEXT: vnot.v v11, v10, v0.t283; CHECK-NEXT: vand.vi v11, v11, 15, v0.t284; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t285; CHECK-NEXT: vand.vi v10, v10, 15, v0.t286; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t287; CHECK-NEXT: vor.vv v8, v8, v9, v0.t288; CHECK-NEXT: ret289 %res = call <8 x i16> @llvm.vp.fshl.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i1> %m, i32 %evl)290 ret <8 x i16> %res291}292 293define <16 x i16> @fshr_v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16 x i1> %m, i32 zeroext %evl) {294; CHECK-LABEL: fshr_v16i16:295; CHECK: # %bb.0:296; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma297; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t298; CHECK-NEXT: vnot.v v14, v12, v0.t299; CHECK-NEXT: vand.vi v14, v14, 15, v0.t300; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t301; CHECK-NEXT: vand.vi v12, v12, 15, v0.t302; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t303; CHECK-NEXT: vor.vv v8, v8, v10, v0.t304; CHECK-NEXT: ret305 %res = call <16 x i16> @llvm.vp.fshr.v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16 x i1> %m, i32 %evl)306 ret <16 x i16> %res307}308 309define <16 x i16> @fshl_v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16 x i1> %m, i32 zeroext %evl) {310; CHECK-LABEL: fshl_v16i16:311; CHECK: # %bb.0:312; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma313; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t314; CHECK-NEXT: vnot.v v14, v12, v0.t315; CHECK-NEXT: vand.vi v14, v14, 15, v0.t316; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t317; CHECK-NEXT: vand.vi v12, v12, 15, v0.t318; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t319; CHECK-NEXT: vor.vv v8, v8, v10, v0.t320; CHECK-NEXT: ret321 %res = call <16 x i16> @llvm.vp.fshl.v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16 x i1> %m, i32 %evl)322 ret <16 x i16> %res323}324 325define <32 x i16> @fshr_v32i16(<32 x i16> %a, <32 x i16> %b, <32 x i16> %c, <32 x i1> %m, i32 zeroext %evl) {326; CHECK-LABEL: fshr_v32i16:327; CHECK: # %bb.0:328; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma329; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t330; CHECK-NEXT: vnot.v v20, v16, v0.t331; CHECK-NEXT: vand.vi v20, v20, 15, v0.t332; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t333; CHECK-NEXT: vand.vi v16, v16, 15, v0.t334; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t335; CHECK-NEXT: vor.vv v8, v8, v12, v0.t336; CHECK-NEXT: ret337 %res = call <32 x i16> @llvm.vp.fshr.v32i16(<32 x i16> %a, <32 x i16> %b, <32 x i16> %c, <32 x i1> %m, i32 %evl)338 ret <32 x i16> %res339}340 341define <32 x i16> @fshl_v32i16(<32 x i16> %a, <32 x i16> %b, <32 x i16> %c, <32 x i1> %m, i32 zeroext %evl) {342; CHECK-LABEL: fshl_v32i16:343; CHECK: # %bb.0:344; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma345; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t346; CHECK-NEXT: vnot.v v20, v16, v0.t347; CHECK-NEXT: vand.vi v20, v20, 15, v0.t348; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t349; CHECK-NEXT: vand.vi v16, v16, 15, v0.t350; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t351; CHECK-NEXT: vor.vv v8, v8, v12, v0.t352; CHECK-NEXT: ret353 %res = call <32 x i16> @llvm.vp.fshl.v32i16(<32 x i16> %a, <32 x i16> %b, <32 x i16> %c, <32 x i1> %m, i32 %evl)354 ret <32 x i16> %res355}356 357define <2 x i32> @fshr_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i1> %m, i32 zeroext %evl) {358; CHECK-LABEL: fshr_v2i32:359; CHECK: # %bb.0:360; CHECK-NEXT: li a1, 31361; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma362; CHECK-NEXT: vand.vx v11, v10, a1, v0.t363; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t364; CHECK-NEXT: vnot.v v10, v10, v0.t365; CHECK-NEXT: vand.vx v10, v10, a1, v0.t366; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t367; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t368; CHECK-NEXT: vor.vv v8, v8, v9, v0.t369; CHECK-NEXT: ret370 %res = call <2 x i32> @llvm.vp.fshr.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i1> %m, i32 %evl)371 ret <2 x i32> %res372}373 374define <2 x i32> @fshl_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i1> %m, i32 zeroext %evl) {375; CHECK-LABEL: fshl_v2i32:376; CHECK: # %bb.0:377; CHECK-NEXT: li a1, 31378; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma379; CHECK-NEXT: vand.vx v11, v10, a1, v0.t380; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t381; CHECK-NEXT: vnot.v v10, v10, v0.t382; CHECK-NEXT: vand.vx v10, v10, a1, v0.t383; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t384; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t385; CHECK-NEXT: vor.vv v8, v8, v9, v0.t386; CHECK-NEXT: ret387 %res = call <2 x i32> @llvm.vp.fshl.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i1> %m, i32 %evl)388 ret <2 x i32> %res389}390 391define <4 x i32> @fshr_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %m, i32 zeroext %evl) {392; CHECK-LABEL: fshr_v4i32:393; CHECK: # %bb.0:394; CHECK-NEXT: li a1, 31395; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma396; CHECK-NEXT: vand.vx v11, v10, a1, v0.t397; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t398; CHECK-NEXT: vnot.v v10, v10, v0.t399; CHECK-NEXT: vand.vx v10, v10, a1, v0.t400; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t401; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t402; CHECK-NEXT: vor.vv v8, v8, v9, v0.t403; CHECK-NEXT: ret404 %res = call <4 x i32> @llvm.vp.fshr.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %m, i32 %evl)405 ret <4 x i32> %res406}407 408define <4 x i32> @fshl_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %m, i32 zeroext %evl) {409; CHECK-LABEL: fshl_v4i32:410; CHECK: # %bb.0:411; CHECK-NEXT: li a1, 31412; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma413; CHECK-NEXT: vand.vx v11, v10, a1, v0.t414; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t415; CHECK-NEXT: vnot.v v10, v10, v0.t416; CHECK-NEXT: vand.vx v10, v10, a1, v0.t417; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t418; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t419; CHECK-NEXT: vor.vv v8, v8, v9, v0.t420; CHECK-NEXT: ret421 %res = call <4 x i32> @llvm.vp.fshl.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %m, i32 %evl)422 ret <4 x i32> %res423}424 425define <8 x i32> @fshr_v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i1> %m, i32 zeroext %evl) {426; CHECK-LABEL: fshr_v8i32:427; CHECK: # %bb.0:428; CHECK-NEXT: li a1, 31429; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma430; CHECK-NEXT: vand.vx v14, v12, a1, v0.t431; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t432; CHECK-NEXT: vnot.v v12, v12, v0.t433; CHECK-NEXT: vand.vx v12, v12, a1, v0.t434; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t435; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t436; CHECK-NEXT: vor.vv v8, v8, v10, v0.t437; CHECK-NEXT: ret438 %res = call <8 x i32> @llvm.vp.fshr.v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i1> %m, i32 %evl)439 ret <8 x i32> %res440}441 442define <8 x i32> @fshl_v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i1> %m, i32 zeroext %evl) {443; CHECK-LABEL: fshl_v8i32:444; CHECK: # %bb.0:445; CHECK-NEXT: li a1, 31446; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma447; CHECK-NEXT: vand.vx v14, v12, a1, v0.t448; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t449; CHECK-NEXT: vnot.v v12, v12, v0.t450; CHECK-NEXT: vand.vx v12, v12, a1, v0.t451; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t452; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t453; CHECK-NEXT: vor.vv v8, v8, v10, v0.t454; CHECK-NEXT: ret455 %res = call <8 x i32> @llvm.vp.fshl.v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i1> %m, i32 %evl)456 ret <8 x i32> %res457}458 459define <16 x i32> @fshr_v16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16 x i1> %m, i32 zeroext %evl) {460; CHECK-LABEL: fshr_v16i32:461; CHECK: # %bb.0:462; CHECK-NEXT: li a1, 31463; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma464; CHECK-NEXT: vand.vx v20, v16, a1, v0.t465; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t466; CHECK-NEXT: vnot.v v16, v16, v0.t467; CHECK-NEXT: vand.vx v16, v16, a1, v0.t468; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t469; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t470; CHECK-NEXT: vor.vv v8, v8, v12, v0.t471; CHECK-NEXT: ret472 %res = call <16 x i32> @llvm.vp.fshr.v16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16 x i1> %m, i32 %evl)473 ret <16 x i32> %res474}475 476define <16 x i32> @fshl_v16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16 x i1> %m, i32 zeroext %evl) {477; CHECK-LABEL: fshl_v16i32:478; CHECK: # %bb.0:479; CHECK-NEXT: li a1, 31480; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma481; CHECK-NEXT: vand.vx v20, v16, a1, v0.t482; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t483; CHECK-NEXT: vnot.v v16, v16, v0.t484; CHECK-NEXT: vand.vx v16, v16, a1, v0.t485; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t486; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t487; CHECK-NEXT: vor.vv v8, v8, v12, v0.t488; CHECK-NEXT: ret489 %res = call <16 x i32> @llvm.vp.fshl.v16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16 x i1> %m, i32 %evl)490 ret <16 x i32> %res491}492 493define <2 x i64> @fshr_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i1> %m, i32 zeroext %evl) {494; CHECK-LABEL: fshr_v2i64:495; CHECK: # %bb.0:496; CHECK-NEXT: li a1, 63497; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma498; CHECK-NEXT: vand.vx v11, v10, a1, v0.t499; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t500; CHECK-NEXT: vnot.v v10, v10, v0.t501; CHECK-NEXT: vand.vx v10, v10, a1, v0.t502; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t503; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t504; CHECK-NEXT: vor.vv v8, v8, v9, v0.t505; CHECK-NEXT: ret506 %res = call <2 x i64> @llvm.vp.fshr.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i1> %m, i32 %evl)507 ret <2 x i64> %res508}509 510define <2 x i64> @fshl_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i1> %m, i32 zeroext %evl) {511; CHECK-LABEL: fshl_v2i64:512; CHECK: # %bb.0:513; CHECK-NEXT: li a1, 63514; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma515; CHECK-NEXT: vand.vx v11, v10, a1, v0.t516; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t517; CHECK-NEXT: vnot.v v10, v10, v0.t518; CHECK-NEXT: vand.vx v10, v10, a1, v0.t519; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t520; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t521; CHECK-NEXT: vor.vv v8, v8, v9, v0.t522; CHECK-NEXT: ret523 %res = call <2 x i64> @llvm.vp.fshl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i1> %m, i32 %evl)524 ret <2 x i64> %res525}526 527define <4 x i64> @fshr_v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i1> %m, i32 zeroext %evl) {528; CHECK-LABEL: fshr_v4i64:529; CHECK: # %bb.0:530; CHECK-NEXT: li a1, 63531; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma532; CHECK-NEXT: vand.vx v14, v12, a1, v0.t533; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t534; CHECK-NEXT: vnot.v v12, v12, v0.t535; CHECK-NEXT: vand.vx v12, v12, a1, v0.t536; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t537; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t538; CHECK-NEXT: vor.vv v8, v8, v10, v0.t539; CHECK-NEXT: ret540 %res = call <4 x i64> @llvm.vp.fshr.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i1> %m, i32 %evl)541 ret <4 x i64> %res542}543 544define <4 x i64> @fshl_v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i1> %m, i32 zeroext %evl) {545; CHECK-LABEL: fshl_v4i64:546; CHECK: # %bb.0:547; CHECK-NEXT: li a1, 63548; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma549; CHECK-NEXT: vand.vx v14, v12, a1, v0.t550; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t551; CHECK-NEXT: vnot.v v12, v12, v0.t552; CHECK-NEXT: vand.vx v12, v12, a1, v0.t553; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t554; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t555; CHECK-NEXT: vor.vv v8, v8, v10, v0.t556; CHECK-NEXT: ret557 %res = call <4 x i64> @llvm.vp.fshl.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i1> %m, i32 %evl)558 ret <4 x i64> %res559}560 561define <7 x i64> @fshr_v7i64(<7 x i64> %a, <7 x i64> %b, <7 x i64> %c, <7 x i1> %m, i32 zeroext %evl) {562; CHECK-LABEL: fshr_v7i64:563; CHECK: # %bb.0:564; CHECK-NEXT: li a1, 63565; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma566; CHECK-NEXT: vand.vx v20, v16, a1, v0.t567; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t568; CHECK-NEXT: vnot.v v16, v16, v0.t569; CHECK-NEXT: vand.vx v16, v16, a1, v0.t570; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t571; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t572; CHECK-NEXT: vor.vv v8, v8, v12, v0.t573; CHECK-NEXT: ret574 %res = call <7 x i64> @llvm.vp.fshr.v7i64(<7 x i64> %a, <7 x i64> %b, <7 x i64> %c, <7 x i1> %m, i32 %evl)575 ret <7 x i64> %res576}577 578define <7 x i64> @fshl_v7i64(<7 x i64> %a, <7 x i64> %b, <7 x i64> %c, <7 x i1> %m, i32 zeroext %evl) {579; CHECK-LABEL: fshl_v7i64:580; CHECK: # %bb.0:581; CHECK-NEXT: li a1, 63582; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma583; CHECK-NEXT: vand.vx v20, v16, a1, v0.t584; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t585; CHECK-NEXT: vnot.v v16, v16, v0.t586; CHECK-NEXT: vand.vx v16, v16, a1, v0.t587; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t588; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t589; CHECK-NEXT: vor.vv v8, v8, v12, v0.t590; CHECK-NEXT: ret591 %res = call <7 x i64> @llvm.vp.fshl.v7i64(<7 x i64> %a, <7 x i64> %b, <7 x i64> %c, <7 x i1> %m, i32 %evl)592 ret <7 x i64> %res593}594 595define <8 x i64> @fshr_v8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i1> %m, i32 zeroext %evl) {596; CHECK-LABEL: fshr_v8i64:597; CHECK: # %bb.0:598; CHECK-NEXT: li a1, 63599; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma600; CHECK-NEXT: vand.vx v20, v16, a1, v0.t601; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t602; CHECK-NEXT: vnot.v v16, v16, v0.t603; CHECK-NEXT: vand.vx v16, v16, a1, v0.t604; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t605; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t606; CHECK-NEXT: vor.vv v8, v8, v12, v0.t607; CHECK-NEXT: ret608 %res = call <8 x i64> @llvm.vp.fshr.v8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i1> %m, i32 %evl)609 ret <8 x i64> %res610}611 612define <8 x i64> @fshl_v8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i1> %m, i32 zeroext %evl) {613; CHECK-LABEL: fshl_v8i64:614; CHECK: # %bb.0:615; CHECK-NEXT: li a1, 63616; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma617; CHECK-NEXT: vand.vx v20, v16, a1, v0.t618; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t619; CHECK-NEXT: vnot.v v16, v16, v0.t620; CHECK-NEXT: vand.vx v16, v16, a1, v0.t621; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t622; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t623; CHECK-NEXT: vor.vv v8, v8, v12, v0.t624; CHECK-NEXT: ret625 %res = call <8 x i64> @llvm.vp.fshl.v8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i1> %m, i32 %evl)626 ret <8 x i64> %res627}628 629define <16 x i64> @fshr_v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16 x i1> %m, i32 zeroext %evl) {630; CHECK-LABEL: fshr_v16i64:631; CHECK: # %bb.0:632; CHECK-NEXT: addi sp, sp, -16633; CHECK-NEXT: .cfi_def_cfa_offset 16634; CHECK-NEXT: csrr a2, vlenb635; CHECK-NEXT: slli a2, a2, 3636; CHECK-NEXT: sub sp, sp, a2637; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb638; CHECK-NEXT: addi a2, sp, 16639; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill640; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma641; CHECK-NEXT: vle64.v v24, (a0)642; CHECK-NEXT: li a0, 63643; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma644; CHECK-NEXT: vand.vx v8, v24, a0, v0.t645; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t646; CHECK-NEXT: vnot.v v8, v24, v0.t647; CHECK-NEXT: vand.vx v8, v8, a0, v0.t648; CHECK-NEXT: addi a0, sp, 16649; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload650; CHECK-NEXT: vsll.vi v24, v24, 1, v0.t651; CHECK-NEXT: vsll.vv v8, v24, v8, v0.t652; CHECK-NEXT: vor.vv v8, v8, v16, v0.t653; CHECK-NEXT: csrr a0, vlenb654; CHECK-NEXT: slli a0, a0, 3655; CHECK-NEXT: add sp, sp, a0656; CHECK-NEXT: .cfi_def_cfa sp, 16657; CHECK-NEXT: addi sp, sp, 16658; CHECK-NEXT: .cfi_def_cfa_offset 0659; CHECK-NEXT: ret660 %res = call <16 x i64> @llvm.vp.fshr.v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16 x i1> %m, i32 %evl)661 ret <16 x i64> %res662}663 664define <16 x i64> @fshl_v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16 x i1> %m, i32 zeroext %evl) {665; CHECK-LABEL: fshl_v16i64:666; CHECK: # %bb.0:667; CHECK-NEXT: addi sp, sp, -16668; CHECK-NEXT: .cfi_def_cfa_offset 16669; CHECK-NEXT: csrr a2, vlenb670; CHECK-NEXT: slli a2, a2, 3671; CHECK-NEXT: sub sp, sp, a2672; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb673; CHECK-NEXT: addi a2, sp, 16674; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill675; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma676; CHECK-NEXT: vmv8r.v v16, v8677; CHECK-NEXT: vle64.v v24, (a0)678; CHECK-NEXT: li a0, 63679; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma680; CHECK-NEXT: vand.vx v8, v24, a0, v0.t681; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t682; CHECK-NEXT: vnot.v v16, v24, v0.t683; CHECK-NEXT: vand.vx v16, v16, a0, v0.t684; CHECK-NEXT: addi a0, sp, 16685; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload686; CHECK-NEXT: vsrl.vi v24, v24, 1, v0.t687; CHECK-NEXT: vsrl.vv v16, v24, v16, v0.t688; CHECK-NEXT: vor.vv v8, v8, v16, v0.t689; CHECK-NEXT: csrr a0, vlenb690; CHECK-NEXT: slli a0, a0, 3691; CHECK-NEXT: add sp, sp, a0692; CHECK-NEXT: .cfi_def_cfa sp, 16693; CHECK-NEXT: addi sp, sp, 16694; CHECK-NEXT: .cfi_def_cfa_offset 0695; CHECK-NEXT: ret696 %res = call <16 x i64> @llvm.vp.fshl.v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16 x i1> %m, i32 %evl)697 ret <16 x i64> %res698}699