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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mattr=+v -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mattr=+v -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s4 5define <4 x i32> @insert_subvector_load_v4i32_v4i32(<4 x i32> %v1, ptr %p) {6; CHECK-LABEL: insert_subvector_load_v4i32_v4i32:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma9; CHECK-NEXT: vle32.v v8, (a0)10; CHECK-NEXT: ret11 %v2 = load <4 x i32>, ptr %p12 %v3 = shufflevector <4 x i32> %v2, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>13 ret <4 x i32> %v314}15 16define <4 x i32> @insert_subvector_vp_load_v4i32_v4i32(<4 x i32> %v1, ptr %p, <4 x i1> %mask) {17; CHECK-LABEL: insert_subvector_vp_load_v4i32_v4i32:18; CHECK: # %bb.0:19; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu20; CHECK-NEXT: vle32.v v8, (a0), v0.t21; CHECK-NEXT: ret22 %v2 = call <4 x i32> @llvm.vp.load.v4i32(ptr %p, <4 x i1> %mask, i32 4)23 %v3 = shufflevector <4 x i32> %v2, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>24 ret <4 x i32> %v325}26 27; Can't fold this in because the load has a non-poison passthru that isn't equal to the vmv.v.v passtrhu28define <4 x i32> @insert_subvector_load_unfoldable_passthru_v4i32_v4i32(<4 x i32> %v1, ptr %p, <4 x i1> %mask, <4 x i32> %passthru) {29; CHECK-LABEL: insert_subvector_load_unfoldable_passthru_v4i32_v4i32:30; CHECK: # %bb.0:31; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu32; CHECK-NEXT: vle32.v v9, (a0), v0.t33; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma34; CHECK-NEXT: vmv.v.v v8, v935; CHECK-NEXT: ret36 %v2 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %p, i32 4, <4 x i1> %mask, <4 x i32> %passthru)37 %v3 = shufflevector <4 x i32> %v2, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>38 ret <4 x i32> %v339}40 41; Can fold this in because the load has a non-poison passthru, but it's equal to the vmv.v.v passtrhu42define <4 x i32> @insert_subvector_load_foldable_passthru_v4i32_v4i32(<4 x i32> %v1, ptr %p, <4 x i1> %mask) {43; CHECK-LABEL: insert_subvector_load_foldable_passthru_v4i32_v4i32:44; CHECK: # %bb.0:45; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu46; CHECK-NEXT: vle32.v v8, (a0), v0.t47; CHECK-NEXT: ret48 %v2 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %p, i32 4, <4 x i1> %mask, <4 x i32> %v1)49 %v3 = shufflevector <4 x i32> %v2, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>50 ret <4 x i32> %v351}52 53define <4 x i32> @insert_subvector_add_v4i32_v4i32(<4 x i32> %v1, <4 x i32> %v2) {54; CHECK-LABEL: insert_subvector_add_v4i32_v4i32:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma57; CHECK-NEXT: vid.v v1058; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma59; CHECK-NEXT: vadd.vv v8, v9, v1060; CHECK-NEXT: ret61 %v3 = add <4 x i32> %v2, <i32 0, i32 1, i32 2, i32 3>62 %v4 = shufflevector <4 x i32> %v3, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>63 ret <4 x i32> %v464}65 66define <4 x i32> @insert_subvector_vp_add_v4i32_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i1> %mask) {67; CHECK-LABEL: insert_subvector_vp_add_v4i32_v4i32:68; CHECK: # %bb.0:69; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu70; CHECK-NEXT: vadd.vi v8, v9, 1, v0.t71; CHECK-NEXT: ret72 %v3 = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %v2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i1> %mask, i32 4)73 %v4 = shufflevector <4 x i32> %v3, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>74 ret <4 x i32> %v475}76 77define <4 x i32> @insert_subvector_load_v4i32_v2i32(<4 x i32> %v1, ptr %p) {78; CHECK-LABEL: insert_subvector_load_v4i32_v2i32:79; CHECK: # %bb.0:80; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma81; CHECK-NEXT: vle32.v v9, (a0)82; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma83; CHECK-NEXT: vmv.v.v v8, v984; CHECK-NEXT: ret85 %v2 = load <2 x i32>, ptr %p86 %v3 = shufflevector <2 x i32> %v2, <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>87 %v4 = shufflevector <4 x i32> %v3, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>88 ret <4 x i32> %v489}90 91define <4 x i32> @insert_subvector_vp_load_v4i32_v2i32(<4 x i32> %v1, ptr %p, <2 x i1> %mask) {92; CHECK-LABEL: insert_subvector_vp_load_v4i32_v2i32:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma95; CHECK-NEXT: vle32.v v9, (a0), v0.t96; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma97; CHECK-NEXT: vmv.v.v v8, v998; CHECK-NEXT: ret99 %v2 = call <2 x i32> @llvm.vp.load.v2i32(ptr %p, <2 x i1> %mask, i32 2)100 %v3 = shufflevector <2 x i32> %v2, <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>101 %v4 = shufflevector <4 x i32> %v3, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>102 ret <4 x i32> %v4103}104 105define <4 x i32> @insert_subvector_add_v4i32_v2i32(<4 x i32> %v1, <2 x i32> %v2) {106; CHECK-LABEL: insert_subvector_add_v4i32_v2i32:107; CHECK: # %bb.0:108; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma109; CHECK-NEXT: vid.v v10110; CHECK-NEXT: vadd.vv v9, v9, v10111; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma112; CHECK-NEXT: vmv.v.v v8, v9113; CHECK-NEXT: ret114 %v3 = add <2 x i32> %v2, <i32 0, i32 1>115 %v4 = shufflevector <2 x i32> %v3, <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>116 %v5 = shufflevector <4 x i32> %v4, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>117 ret <4 x i32> %v5118}119 120define <4 x i32> @insert_subvector_vp_add_v4i32_v2i32(<4 x i32> %v1, <2 x i32> %v2, <2 x i1> %mask) {121; CHECK-LABEL: insert_subvector_vp_add_v4i32_v2i32:122; CHECK: # %bb.0:123; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma124; CHECK-NEXT: vadd.vi v9, v9, 1, v0.t125; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma126; CHECK-NEXT: vmv.v.v v8, v9127; CHECK-NEXT: ret128 %v3 = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %v2, <2 x i32> <i32 1, i32 1>, <2 x i1> %mask, i32 2)129 %v4 = shufflevector <2 x i32> %v3, <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>130 %v5 = shufflevector <4 x i32> %v4, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>131 ret <4 x i32> %v5132}133 134define <4 x i32> @insert_subvector_load_v4i32_v8i32(<4 x i32> %v1, ptr %p) {135; CHECK-LABEL: insert_subvector_load_v4i32_v8i32:136; CHECK: # %bb.0:137; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma138; CHECK-NEXT: vle32.v v8, (a0)139; CHECK-NEXT: ret140 %v2 = load <8 x i32>, ptr %p141 %v3 = shufflevector <8 x i32> %v2, <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>142 %v4 = shufflevector <4 x i32> %v3, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>143 ret <4 x i32> %v4144}145 146define <4 x i32> @insert_subvector_vp_load_v4i32_v8i32(<4 x i32> %v1, ptr %p, <8 x i1> %mask) {147; CHECK-LABEL: insert_subvector_vp_load_v4i32_v8i32:148; CHECK: # %bb.0:149; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma150; CHECK-NEXT: vle32.v v10, (a0), v0.t151; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma152; CHECK-NEXT: vmv.v.v v8, v10153; CHECK-NEXT: ret154 %v2 = call <8 x i32> @llvm.vp.load.v8i32(ptr %p, <8 x i1> %mask, i32 8)155 %v3 = shufflevector <8 x i32> %v2, <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>156 %v4 = shufflevector <4 x i32> %v3, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>157 ret <4 x i32> %v4158}159 160define <4 x i32> @insert_subvector_add_v4i32_v8i32(<4 x i32> %v1, <8 x i32> %v2) {161; CHECK-LABEL: insert_subvector_add_v4i32_v8i32:162; CHECK: # %bb.0:163; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma164; CHECK-NEXT: vid.v v9165; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma166; CHECK-NEXT: vadd.vv v8, v10, v9167; CHECK-NEXT: ret168 %v3 = add <8 x i32> %v2, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>169 %v4 = shufflevector <8 x i32> %v3, <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>170 %v5 = shufflevector <4 x i32> %v4, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>171 ret <4 x i32> %v5172}173 174define <4 x i32> @insert_subvector_vp_add_v4i32_v8i32(<4 x i32> %v1, <8 x i32> %v2, <8 x i1> %mask) {175; CHECK-LABEL: insert_subvector_vp_add_v4i32_v8i32:176; CHECK: # %bb.0:177; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma178; CHECK-NEXT: vadd.vi v10, v10, 1, v0.t179; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma180; CHECK-NEXT: vmv.v.v v8, v10181; CHECK-NEXT: ret182 %v3 = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %v2, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, <8 x i1> %mask, i32 8)183 %v4 = shufflevector <8 x i32> %v3, <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>184 %v5 = shufflevector <4 x i32> %v4, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>185 ret <4 x i32> %v5186}187 188; %v2 depends on the chain of %v1, so make sure the peephole optimisation189; doesn't introduce a loop in the DAG190define <4 x i32> @insert_subvector_dag_loop(ptr %p, ptr %q) {191; CHECK-LABEL: insert_subvector_dag_loop:192; CHECK: # %bb.0:193; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma194; CHECK-NEXT: vle32.v v9, (a0)195; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma196; CHECK-NEXT: vle32.v v8, (a1)197; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma198; CHECK-NEXT: vmv.v.v v8, v9199; CHECK-NEXT: ret200 %v1 = load volatile <4 x i32>, ptr %p201 %v2 = load volatile <4 x i32>, ptr %q202 %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 0, i32 1, i32 6, i32 7>203 ret <4 x i32> %v3204}205