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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV32VLA3; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV64VLA4; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV32VLA5; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV64VLA6 7; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV32VLA8; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV64VLA9; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV32VLA10; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV64VLA11 12; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS,RV32VLS %s13; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS,RV64VLS %s14; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS,RV32VLS %s15; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS,RV64VLS %s16 17define <vscale x 8 x i32> @insert_nxv8i32_v2i32_0(<vscale x 8 x i32> %vec, ptr %svp) {18; VLA-LABEL: insert_nxv8i32_v2i32_0:19; VLA: # %bb.0:20; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma21; VLA-NEXT: vle32.v v12, (a0)22; VLA-NEXT: vsetivli zero, 2, e32, m4, tu, ma23; VLA-NEXT: vmv.v.v v8, v1224; VLA-NEXT: ret25;26; VLS-LABEL: insert_nxv8i32_v2i32_0:27; VLS: # %bb.0:28; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma29; VLS-NEXT: vle32.v v12, (a0)30; VLS-NEXT: vsetivli zero, 2, e32, m1, tu, ma31; VLS-NEXT: vmv.v.v v8, v1232; VLS-NEXT: ret33 %sv = load <2 x i32>, ptr %svp34 %v = call <vscale x 8 x i32> @llvm.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 0)35 ret <vscale x 8 x i32> %v36}37 38define <vscale x 8 x i32> @insert_nxv8i32_v2i32_2(<vscale x 8 x i32> %vec, ptr %svp) {39; VLA-LABEL: insert_nxv8i32_v2i32_2:40; VLA: # %bb.0:41; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma42; VLA-NEXT: vle32.v v12, (a0)43; VLA-NEXT: vsetivli zero, 4, e32, m4, tu, ma44; VLA-NEXT: vslideup.vi v8, v12, 245; VLA-NEXT: ret46;47; VLS-LABEL: insert_nxv8i32_v2i32_2:48; VLS: # %bb.0:49; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma50; VLS-NEXT: vle32.v v12, (a0)51; VLS-NEXT: vsetivli zero, 4, e32, m1, ta, ma52; VLS-NEXT: vslideup.vi v8, v12, 253; VLS-NEXT: ret54 %sv = load <2 x i32>, ptr %svp55 %v = call <vscale x 8 x i32> @llvm.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 2)56 ret <vscale x 8 x i32> %v57}58 59define <vscale x 8 x i32> @insert_nxv8i32_v2i32_6(<vscale x 8 x i32> %vec, ptr %svp) {60; VLA-LABEL: insert_nxv8i32_v2i32_6:61; VLA: # %bb.0:62; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma63; VLA-NEXT: vle32.v v12, (a0)64; VLA-NEXT: vsetivli zero, 8, e32, m4, tu, ma65; VLA-NEXT: vslideup.vi v8, v12, 666; VLA-NEXT: ret67;68; VLS-LABEL: insert_nxv8i32_v2i32_6:69; VLS: # %bb.0:70; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma71; VLS-NEXT: vle32.v v12, (a0)72; VLS-NEXT: vsetivli zero, 4, e32, m1, ta, ma73; VLS-NEXT: vslideup.vi v9, v12, 274; VLS-NEXT: ret75 %sv = load <2 x i32>, ptr %svp76 %v = call <vscale x 8 x i32> @llvm.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 6)77 ret <vscale x 8 x i32> %v78}79 80define <vscale x 8 x i32> @insert_nxv8i32_v8i32_0(<vscale x 8 x i32> %vec, ptr %svp) {81; VLA-LABEL: insert_nxv8i32_v8i32_0:82; VLA: # %bb.0:83; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma84; VLA-NEXT: vle32.v v12, (a0)85; VLA-NEXT: vsetivli zero, 8, e32, m4, tu, ma86; VLA-NEXT: vmv.v.v v8, v1287; VLA-NEXT: ret88;89; VLS-LABEL: insert_nxv8i32_v8i32_0:90; VLS: # %bb.0:91; VLS-NEXT: vl2re32.v v8, (a0)92; VLS-NEXT: ret93 %sv = load <8 x i32>, ptr %svp94 %v = call <vscale x 8 x i32> @llvm.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32> %vec, <8 x i32> %sv, i64 0)95 ret <vscale x 8 x i32> %v96}97 98define <vscale x 8 x i32> @insert_nxv8i32_v8i32_8(<vscale x 8 x i32> %vec, ptr %svp) {99; VLA-LABEL: insert_nxv8i32_v8i32_8:100; VLA: # %bb.0:101; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma102; VLA-NEXT: vle32.v v12, (a0)103; VLA-NEXT: vsetivli zero, 16, e32, m4, tu, ma104; VLA-NEXT: vslideup.vi v8, v12, 8105; VLA-NEXT: ret106;107; VLS-LABEL: insert_nxv8i32_v8i32_8:108; VLS: # %bb.0:109; VLS-NEXT: vl2re32.v v10, (a0)110; VLS-NEXT: ret111 %sv = load <8 x i32>, ptr %svp112 %v = call <vscale x 8 x i32> @llvm.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32> %vec, <8 x i32> %sv, i64 8)113 ret <vscale x 8 x i32> %v114}115 116define <vscale x 8 x i32> @insert_nxv8i32_undef_v2i32_0(ptr %svp) {117; CHECK-LABEL: insert_nxv8i32_undef_v2i32_0:118; CHECK: # %bb.0:119; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma120; CHECK-NEXT: vle32.v v8, (a0)121; CHECK-NEXT: ret122 %sv = load <2 x i32>, ptr %svp123 %v = call <vscale x 8 x i32> @llvm.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> poison, <2 x i32> %sv, i64 0)124 ret <vscale x 8 x i32> %v125}126 127define <vscale x 2 x i32> @insert_nxv8i32_v4i32_0(<vscale x 2 x i32> %vec, <4 x i32> %subvec) {128; VLA-LABEL: insert_nxv8i32_v4i32_0:129; VLA: # %bb.0:130; VLA-NEXT: vsetivli zero, 4, e32, m1, tu, ma131; VLA-NEXT: vmv.v.v v8, v9132; VLA-NEXT: ret133;134; VLS-LABEL: insert_nxv8i32_v4i32_0:135; VLS: # %bb.0:136; VLS-NEXT: vsetivli zero, 1, e8, m1, ta, ma137; VLS-NEXT: vmv1r.v v8, v9138; VLS-NEXT: ret139 %v = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v4i32(<vscale x 2 x i32> %vec, <4 x i32> %subvec, i64 0)140 ret <vscale x 2 x i32> %v141}142 143define <4 x i32> @insert_v4i32_v4i32_0(<4 x i32> %vec, <4 x i32> %subvec) {144; CHECK-LABEL: insert_v4i32_v4i32_0:145; CHECK: # %bb.0:146; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma147; CHECK-NEXT: vmv1r.v v8, v9148; CHECK-NEXT: ret149 %v = call <4 x i32> @llvm.vector.insert.v4i32.v4i32(<4 x i32> %vec, <4 x i32> %subvec, i64 0)150 ret <4 x i32> %v151}152 153define void @insert_v4i32_v2i32_0(ptr %vp, ptr %svp) {154; VLA-LABEL: insert_v4i32_v2i32_0:155; VLA: # %bb.0:156; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma157; VLA-NEXT: vle32.v v8, (a1)158; VLA-NEXT: vsetivli zero, 4, e32, m1, ta, ma159; VLA-NEXT: vle32.v v9, (a0)160; VLA-NEXT: vsetivli zero, 2, e32, m1, tu, ma161; VLA-NEXT: vmv.v.v v9, v8162; VLA-NEXT: vsetivli zero, 4, e32, m1, ta, ma163; VLA-NEXT: vse32.v v9, (a0)164; VLA-NEXT: ret165;166; VLS-LABEL: insert_v4i32_v2i32_0:167; VLS: # %bb.0:168; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma169; VLS-NEXT: vle32.v v8, (a1)170; VLS-NEXT: vl1re32.v v9, (a0)171; VLS-NEXT: vsetivli zero, 2, e32, m1, tu, ma172; VLS-NEXT: vmv.v.v v9, v8173; VLS-NEXT: vs1r.v v9, (a0)174; VLS-NEXT: ret175 %sv = load <2 x i32>, ptr %svp176 %vec = load <4 x i32>, ptr %vp177 %v = call <4 x i32> @llvm.vector.insert.v2i32.v4i32(<4 x i32> %vec, <2 x i32> %sv, i64 0)178 store <4 x i32> %v, ptr %vp179 ret void180}181 182define void @insert_v4i32_v2i32_2(ptr %vp, ptr %svp) {183; VLA-LABEL: insert_v4i32_v2i32_2:184; VLA: # %bb.0:185; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma186; VLA-NEXT: vle32.v v8, (a1)187; VLA-NEXT: vsetivli zero, 4, e32, m1, ta, ma188; VLA-NEXT: vle32.v v9, (a0)189; VLA-NEXT: vslideup.vi v9, v8, 2190; VLA-NEXT: vse32.v v9, (a0)191; VLA-NEXT: ret192;193; VLS-LABEL: insert_v4i32_v2i32_2:194; VLS: # %bb.0:195; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma196; VLS-NEXT: vle32.v v8, (a1)197; VLS-NEXT: vl1re32.v v9, (a0)198; VLS-NEXT: vsetivli zero, 4, e32, m1, ta, ma199; VLS-NEXT: vslideup.vi v9, v8, 2200; VLS-NEXT: vs1r.v v9, (a0)201; VLS-NEXT: ret202 %sv = load <2 x i32>, ptr %svp203 %vec = load <4 x i32>, ptr %vp204 %v = call <4 x i32> @llvm.vector.insert.v2i32.v4i32(<4 x i32> %vec, <2 x i32> %sv, i64 2)205 store <4 x i32> %v, ptr %vp206 ret void207}208 209define void @insert_v4i32_undef_v2i32_0(ptr %vp, ptr %svp) {210; VLA-LABEL: insert_v4i32_undef_v2i32_0:211; VLA: # %bb.0:212; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma213; VLA-NEXT: vle32.v v8, (a1)214; VLA-NEXT: vsetivli zero, 4, e32, m1, ta, ma215; VLA-NEXT: vse32.v v8, (a0)216; VLA-NEXT: ret217;218; VLS-LABEL: insert_v4i32_undef_v2i32_0:219; VLS: # %bb.0:220; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma221; VLS-NEXT: vle32.v v8, (a1)222; VLS-NEXT: vs1r.v v8, (a0)223; VLS-NEXT: ret224 %sv = load <2 x i32>, ptr %svp225 %v = call <4 x i32> @llvm.vector.insert.v2i32.v4i32(<4 x i32> poison, <2 x i32> %sv, i64 0)226 store <4 x i32> %v, ptr %vp227 ret void228}229 230; This tests the code path in RISCVISelDAGToDAG::Select where we select an231; insert_subvector with a fixed vector and fixed subvector type. The phi here is232; used to prevent the fixed insert_subvector from being combined away into a233; scalable insert_subvector.234define <4 x i32> @insert_v4i32_undef_v2i32_0_phi(<2 x i32> %subvec, i1 %cond) {235; CHECK-LABEL: insert_v4i32_undef_v2i32_0_phi:236; CHECK: # %bb.0: # %entry237; CHECK-NEXT: andi a0, a0, 1238; CHECK-NEXT: bnez a0, .LBB11_2239; CHECK-NEXT: # %bb.1:240; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma241; CHECK-NEXT: vmv.v.i v8, 0242; CHECK-NEXT: .LBB11_2: # %bar243; CHECK-NEXT: ret244entry:245 br i1 %cond, label %foo, label %bar246foo:247 %v = call <4 x i32> @llvm.vector.insert.v2i32.v4i32(<4 x i32> poison, <2 x i32> %subvec, i64 0)248 br label %bar249bar:250 %w = phi <4 x i32> [%v, %foo], [zeroinitializer, %entry]251 ret <4 x i32> %w252}253 254define void @insert_v8i32_v2i32_0(ptr %vp, ptr %svp) {255; VLA-LABEL: insert_v8i32_v2i32_0:256; VLA: # %bb.0:257; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma258; VLA-NEXT: vle32.v v8, (a1)259; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma260; VLA-NEXT: vle32.v v10, (a0)261; VLA-NEXT: vsetivli zero, 2, e32, m2, tu, ma262; VLA-NEXT: vmv.v.v v10, v8263; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma264; VLA-NEXT: vse32.v v10, (a0)265; VLA-NEXT: ret266;267; VLS-LABEL: insert_v8i32_v2i32_0:268; VLS: # %bb.0:269; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma270; VLS-NEXT: vle32.v v10, (a1)271; VLS-NEXT: vl2re32.v v8, (a0)272; VLS-NEXT: vsetivli zero, 2, e32, m1, tu, ma273; VLS-NEXT: vmv.v.v v8, v10274; VLS-NEXT: vs2r.v v8, (a0)275; VLS-NEXT: ret276 %sv = load <2 x i32>, ptr %svp277 %vec = load <8 x i32>, ptr %vp278 %v = call <8 x i32> @llvm.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 0)279 store <8 x i32> %v, ptr %vp280 ret void281}282 283define void @insert_v8i32_v2i32_2(ptr %vp, ptr %svp) {284; VLA-LABEL: insert_v8i32_v2i32_2:285; VLA: # %bb.0:286; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma287; VLA-NEXT: vle32.v v8, (a0)288; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma289; VLA-NEXT: vle32.v v10, (a1)290; VLA-NEXT: vsetivli zero, 4, e32, m2, tu, ma291; VLA-NEXT: vslideup.vi v8, v10, 2292; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma293; VLA-NEXT: vse32.v v8, (a0)294; VLA-NEXT: ret295;296; VLS-LABEL: insert_v8i32_v2i32_2:297; VLS: # %bb.0:298; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma299; VLS-NEXT: vle32.v v10, (a1)300; VLS-NEXT: vl2re32.v v8, (a0)301; VLS-NEXT: vsetivli zero, 4, e32, m1, ta, ma302; VLS-NEXT: vslideup.vi v8, v10, 2303; VLS-NEXT: vs2r.v v8, (a0)304; VLS-NEXT: ret305 %sv = load <2 x i32>, ptr %svp306 %vec = load <8 x i32>, ptr %vp307 %v = call <8 x i32> @llvm.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 2)308 store <8 x i32> %v, ptr %vp309 ret void310}311 312define void @insert_v8i32_v2i32_6(ptr %vp, ptr %svp) {313; VLA-LABEL: insert_v8i32_v2i32_6:314; VLA: # %bb.0:315; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma316; VLA-NEXT: vle32.v v8, (a0)317; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma318; VLA-NEXT: vle32.v v10, (a1)319; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma320; VLA-NEXT: vslideup.vi v8, v10, 6321; VLA-NEXT: vse32.v v8, (a0)322; VLA-NEXT: ret323;324; VLS-LABEL: insert_v8i32_v2i32_6:325; VLS: # %bb.0:326; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma327; VLS-NEXT: vle32.v v10, (a1)328; VLS-NEXT: vl2re32.v v8, (a0)329; VLS-NEXT: vsetivli zero, 4, e32, m1, ta, ma330; VLS-NEXT: vslideup.vi v9, v10, 2331; VLS-NEXT: vs2r.v v8, (a0)332; VLS-NEXT: ret333 %sv = load <2 x i32>, ptr %svp334 %vec = load <8 x i32>, ptr %vp335 %v = call <8 x i32> @llvm.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 6)336 store <8 x i32> %v, ptr %vp337 ret void338}339 340define void @insert_v8i32_undef_v2i32_6(ptr %vp, ptr %svp) {341; VLA-LABEL: insert_v8i32_undef_v2i32_6:342; VLA: # %bb.0:343; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma344; VLA-NEXT: vle32.v v8, (a1)345; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma346; VLA-NEXT: vslideup.vi v10, v8, 6347; VLA-NEXT: vse32.v v10, (a0)348; VLA-NEXT: ret349;350; VLS-LABEL: insert_v8i32_undef_v2i32_6:351; VLS: # %bb.0:352; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma353; VLS-NEXT: vle32.v v8, (a1)354; VLS-NEXT: vsetivli zero, 4, e32, m1, ta, ma355; VLS-NEXT: vslideup.vi v9, v8, 2356; VLS-NEXT: vs2r.v v8, (a0)357; VLS-NEXT: ret358 %sv = load <2 x i32>, ptr %svp359 %v = call <8 x i32> @llvm.vector.insert.v2i32.v8i32(<8 x i32> poison, <2 x i32> %sv, i64 6)360 store <8 x i32> %v, ptr %vp361 ret void362}363 364define void @insert_v4i16_v2i16_0(ptr %vp, ptr %svp) {365; CHECK-LABEL: insert_v4i16_v2i16_0:366; CHECK: # %bb.0:367; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma368; CHECK-NEXT: vle16.v v8, (a0)369; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma370; CHECK-NEXT: vle16.v v9, (a1)371; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma372; CHECK-NEXT: vmv.v.v v8, v9373; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma374; CHECK-NEXT: vse16.v v8, (a0)375; CHECK-NEXT: ret376 %v = load <4 x i16>, ptr %vp377 %sv = load <2 x i16>, ptr %svp378 %c = call <4 x i16> @llvm.vector.insert.v2i16.v4i16(<4 x i16> %v, <2 x i16> %sv, i64 0)379 store <4 x i16> %c, ptr %vp380 ret void381}382 383define void @insert_v4i16_v2i16_2(ptr %vp, ptr %svp) {384; CHECK-LABEL: insert_v4i16_v2i16_2:385; CHECK: # %bb.0:386; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma387; CHECK-NEXT: vle16.v v8, (a0)388; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma389; CHECK-NEXT: vle16.v v9, (a1)390; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma391; CHECK-NEXT: vslideup.vi v8, v9, 2392; CHECK-NEXT: vse16.v v8, (a0)393; CHECK-NEXT: ret394 %v = load <4 x i16>, ptr %vp395 %sv = load <2 x i16>, ptr %svp396 %c = call <4 x i16> @llvm.vector.insert.v2i16.v4i16(<4 x i16> %v, <2 x i16> %sv, i64 2)397 store <4 x i16> %c, ptr %vp398 ret void399}400 401define void @insert_v32i1_v8i1_0(ptr %vp, ptr %svp) {402; VLA-LABEL: insert_v32i1_v8i1_0:403; VLA: # %bb.0:404; VLA-NEXT: li a2, 32405; VLA-NEXT: vsetvli zero, a2, e8, m2, ta, ma406; VLA-NEXT: vlm.v v8, (a0)407; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma408; VLA-NEXT: vlm.v v9, (a1)409; VLA-NEXT: vsetivli zero, 1, e8, mf4, tu, ma410; VLA-NEXT: vmv.v.v v8, v9411; VLA-NEXT: vsetvli zero, a2, e8, m2, ta, ma412; VLA-NEXT: vsm.v v8, (a0)413; VLA-NEXT: ret414;415; VLS-LABEL: insert_v32i1_v8i1_0:416; VLS: # %bb.0:417; VLS-NEXT: vsetvli a2, zero, e8, m2, ta, ma418; VLS-NEXT: vlm.v v8, (a0)419; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma420; VLS-NEXT: vlm.v v9, (a1)421; VLS-NEXT: vsetivli zero, 1, e8, mf4, tu, ma422; VLS-NEXT: vmv.v.v v8, v9423; VLS-NEXT: vsetvli a1, zero, e8, m2, ta, ma424; VLS-NEXT: vsm.v v8, (a0)425; VLS-NEXT: ret426 %v = load <32 x i1>, ptr %vp427 %sv = load <8 x i1>, ptr %svp428 %c = call <32 x i1> @llvm.vector.insert.v8i1.v32i1(<32 x i1> %v, <8 x i1> %sv, i64 0)429 store <32 x i1> %c, ptr %vp430 ret void431}432 433define void @insert_v32i1_v8i1_16(ptr %vp, ptr %svp) {434; VLA-LABEL: insert_v32i1_v8i1_16:435; VLA: # %bb.0:436; VLA-NEXT: li a2, 32437; VLA-NEXT: vsetvli zero, a2, e8, m2, ta, ma438; VLA-NEXT: vlm.v v8, (a0)439; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma440; VLA-NEXT: vlm.v v9, (a1)441; VLA-NEXT: vsetivli zero, 3, e8, mf4, tu, ma442; VLA-NEXT: vslideup.vi v8, v9, 2443; VLA-NEXT: vsetvli zero, a2, e8, m2, ta, ma444; VLA-NEXT: vsm.v v8, (a0)445; VLA-NEXT: ret446;447; VLS-LABEL: insert_v32i1_v8i1_16:448; VLS: # %bb.0:449; VLS-NEXT: vsetvli a2, zero, e8, m2, ta, ma450; VLS-NEXT: vlm.v v8, (a0)451; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma452; VLS-NEXT: vlm.v v9, (a1)453; VLS-NEXT: vsetivli zero, 3, e8, mf4, tu, ma454; VLS-NEXT: vslideup.vi v8, v9, 2455; VLS-NEXT: vsetvli a1, zero, e8, m2, ta, ma456; VLS-NEXT: vsm.v v8, (a0)457; VLS-NEXT: ret458 %v = load <32 x i1>, ptr %vp459 %sv = load <8 x i1>, ptr %svp460 %c = call <32 x i1> @llvm.vector.insert.v8i1.v32i1(<32 x i1> %v, <8 x i1> %sv, i64 16)461 store <32 x i1> %c, ptr %vp462 ret void463}464 465define void @insert_v8i1_v4i1_0(ptr %vp, ptr %svp) {466; CHECK-LABEL: insert_v8i1_v4i1_0:467; CHECK: # %bb.0:468; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma469; CHECK-NEXT: vlm.v v0, (a0)470; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma471; CHECK-NEXT: vlm.v v8, (a1)472; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma473; CHECK-NEXT: vmv.v.i v9, 0474; CHECK-NEXT: vmerge.vim v9, v9, 1, v0475; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma476; CHECK-NEXT: vmv.v.i v10, 0477; CHECK-NEXT: vmv1r.v v0, v8478; CHECK-NEXT: vmerge.vim v8, v10, 1, v0479; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma480; CHECK-NEXT: vmv.v.v v9, v8481; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma482; CHECK-NEXT: vmsne.vi v8, v9, 0483; CHECK-NEXT: vsm.v v8, (a0)484; CHECK-NEXT: ret485 %v = load <8 x i1>, ptr %vp486 %sv = load <4 x i1>, ptr %svp487 %c = call <8 x i1> @llvm.vector.insert.v4i1.v8i1(<8 x i1> %v, <4 x i1> %sv, i64 0)488 store <8 x i1> %c, ptr %vp489 ret void490}491 492define void @insert_v8i1_v4i1_4(ptr %vp, ptr %svp) {493; CHECK-LABEL: insert_v8i1_v4i1_4:494; CHECK: # %bb.0:495; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma496; CHECK-NEXT: vlm.v v0, (a0)497; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma498; CHECK-NEXT: vlm.v v8, (a1)499; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma500; CHECK-NEXT: vmv.v.i v9, 0501; CHECK-NEXT: vmerge.vim v9, v9, 1, v0502; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma503; CHECK-NEXT: vmv.v.i v10, 0504; CHECK-NEXT: vmv1r.v v0, v8505; CHECK-NEXT: vmerge.vim v8, v10, 1, v0506; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma507; CHECK-NEXT: vslideup.vi v9, v8, 4508; CHECK-NEXT: vmsne.vi v8, v9, 0509; CHECK-NEXT: vsm.v v8, (a0)510; CHECK-NEXT: ret511 %v = load <8 x i1>, ptr %vp512 %sv = load <4 x i1>, ptr %svp513 %c = call <8 x i1> @llvm.vector.insert.v4i1.v8i1(<8 x i1> %v, <4 x i1> %sv, i64 4)514 store <8 x i1> %c, ptr %vp515 ret void516}517 518define <vscale x 2 x i16> @insert_nxv2i16_v2i16_0(<vscale x 2 x i16> %v, ptr %svp) {519; CHECK-LABEL: insert_nxv2i16_v2i16_0:520; CHECK: # %bb.0:521; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma522; CHECK-NEXT: vle16.v v9, (a0)523; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma524; CHECK-NEXT: vmv.v.v v8, v9525; CHECK-NEXT: ret526 %sv = load <2 x i16>, ptr %svp527 %c = call <vscale x 2 x i16> @llvm.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16> %v, <2 x i16> %sv, i64 0)528 ret <vscale x 2 x i16> %c529}530 531define <vscale x 2 x i16> @insert_nxv2i16_v2i16_2(<vscale x 2 x i16> %v, ptr %svp) {532; CHECK-LABEL: insert_nxv2i16_v2i16_2:533; CHECK: # %bb.0:534; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma535; CHECK-NEXT: vle16.v v9, (a0)536; CHECK-NEXT: vsetivli zero, 6, e16, mf2, tu, ma537; CHECK-NEXT: vslideup.vi v8, v9, 4538; CHECK-NEXT: ret539 %sv = load <2 x i16>, ptr %svp540 %c = call <vscale x 2 x i16> @llvm.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16> %v, <2 x i16> %sv, i64 4)541 ret <vscale x 2 x i16> %c542}543 544define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, ptr %svp) {545; VLA-LABEL: insert_nxv2i1_v4i1_0:546; VLA: # %bb.0:547; VLA-NEXT: vsetivli zero, 4, e8, mf4, ta, ma548; VLA-NEXT: vlm.v v8, (a0)549; VLA-NEXT: vsetvli a0, zero, e8, mf4, ta, ma550; VLA-NEXT: vmv.v.i v9, 0551; VLA-NEXT: vmerge.vim v9, v9, 1, v0552; VLA-NEXT: vsetivli zero, 4, e8, mf4, ta, ma553; VLA-NEXT: vmv.v.i v10, 0554; VLA-NEXT: vmv1r.v v0, v8555; VLA-NEXT: vsetvli zero, zero, e8, mf4, tu, ma556; VLA-NEXT: vmerge.vim v9, v10, 1, v0557; VLA-NEXT: vsetvli a0, zero, e8, mf4, ta, ma558; VLA-NEXT: vmsne.vi v0, v9, 0559; VLA-NEXT: ret560;561; VLS-LABEL: insert_nxv2i1_v4i1_0:562; VLS: # %bb.0:563; VLS-NEXT: vsetivli zero, 4, e8, mf4, ta, ma564; VLS-NEXT: vlm.v v8, (a0)565; VLS-NEXT: vmv.v.i v9, 0566; VLS-NEXT: vmerge.vim v10, v9, 1, v0567; VLS-NEXT: vmv1r.v v0, v8568; VLS-NEXT: vsetvli zero, zero, e8, mf4, tu, ma569; VLS-NEXT: vmerge.vim v10, v9, 1, v0570; VLS-NEXT: vsetvli zero, zero, e8, mf4, ta, ma571; VLS-NEXT: vmsne.vi v0, v10, 0572; VLS-NEXT: ret573 %sv = load <4 x i1>, ptr %svp574 %c = call <vscale x 2 x i1> @llvm.vector.insert.v4i1.nxv2i1(<vscale x 2 x i1> %v, <4 x i1> %sv, i64 0)575 ret <vscale x 2 x i1> %c576}577 578define <vscale x 8 x i1> @insert_nxv8i1_v4i1_0(<vscale x 8 x i1> %v, ptr %svp) {579; CHECK-LABEL: insert_nxv8i1_v4i1_0:580; CHECK: # %bb.0:581; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma582; CHECK-NEXT: vlm.v v8, (a0)583; CHECK-NEXT: vsetivli zero, 1, e8, mf8, tu, ma584; CHECK-NEXT: vmv.v.v v0, v8585; CHECK-NEXT: ret586 %sv = load <8 x i1>, ptr %svp587 %c = call <vscale x 8 x i1> @llvm.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1> %v, <8 x i1> %sv, i64 0)588 ret <vscale x 8 x i1> %c589}590 591define <vscale x 8 x i1> @insert_nxv8i1_v8i1_16(<vscale x 8 x i1> %v, ptr %svp) {592; CHECK-LABEL: insert_nxv8i1_v8i1_16:593; CHECK: # %bb.0:594; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma595; CHECK-NEXT: vlm.v v8, (a0)596; CHECK-NEXT: vsetivli zero, 3, e8, mf8, tu, ma597; CHECK-NEXT: vslideup.vi v0, v8, 2598; CHECK-NEXT: ret599 %sv = load <8 x i1>, ptr %svp600 %c = call <vscale x 8 x i1> @llvm.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1> %v, <8 x i1> %sv, i64 16)601 ret <vscale x 8 x i1> %c602}603 604define void @insert_v2i64_nxv16i64(ptr %psv0, ptr %psv1, ptr %out) {605; VLA-LABEL: insert_v2i64_nxv16i64:606; VLA: # %bb.0:607; VLA-NEXT: vsetivli zero, 2, e64, m1, ta, ma608; VLA-NEXT: vle64.v v8, (a0)609; VLA-NEXT: vle64.v v16, (a1)610; VLA-NEXT: vsetivli zero, 6, e64, m8, tu, ma611; VLA-NEXT: vslideup.vi v8, v16, 4612; VLA-NEXT: vs8r.v v8, (a2)613; VLA-NEXT: ret614;615; VLS-LABEL: insert_v2i64_nxv16i64:616; VLS: # %bb.0:617; VLS-NEXT: vl1re64.v v8, (a0)618; VLS-NEXT: vl1re64.v v10, (a1)619; VLS-NEXT: vs8r.v v8, (a2)620; VLS-NEXT: ret621 %sv0 = load <2 x i64>, ptr %psv0622 %sv1 = load <2 x i64>, ptr %psv1623 %v0 = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> poison, <2 x i64> %sv0, i64 0)624 %v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4)625 store <vscale x 16 x i64> %v, ptr %out626 ret void627}628 629define void @insert_v2i64_nxv16i64_lo0(ptr %psv, ptr %out) {630; VLA-LABEL: insert_v2i64_nxv16i64_lo0:631; VLA: # %bb.0:632; VLA-NEXT: vsetivli zero, 2, e64, m1, ta, ma633; VLA-NEXT: vle64.v v8, (a0)634; VLA-NEXT: vs8r.v v8, (a1)635; VLA-NEXT: ret636;637; VLS-LABEL: insert_v2i64_nxv16i64_lo0:638; VLS: # %bb.0:639; VLS-NEXT: vl1re64.v v8, (a0)640; VLS-NEXT: vs8r.v v8, (a1)641; VLS-NEXT: ret642 %sv = load <2 x i64>, ptr %psv643 %v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> poison, <2 x i64> %sv, i64 0)644 store <vscale x 16 x i64> %v, ptr %out645 ret void646}647 648define void @insert_v2i64_nxv16i64_lo2(ptr %psv, ptr %out) {649; VLA-LABEL: insert_v2i64_nxv16i64_lo2:650; VLA: # %bb.0:651; VLA-NEXT: vsetivli zero, 2, e64, m1, ta, ma652; VLA-NEXT: vle64.v v8, (a0)653; VLA-NEXT: vsetivli zero, 4, e64, m8, ta, ma654; VLA-NEXT: vslideup.vi v16, v8, 2655; VLA-NEXT: vs8r.v v16, (a1)656; VLA-NEXT: ret657;658; VLS-LABEL: insert_v2i64_nxv16i64_lo2:659; VLS: # %bb.0:660; VLS-NEXT: vl1re64.v v9, (a0)661; VLS-NEXT: vs8r.v v8, (a1)662; VLS-NEXT: ret663 %sv = load <2 x i64>, ptr %psv664 %v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> poison, <2 x i64> %sv, i64 2)665 store <vscale x 16 x i64> %v, ptr %out666 ret void667}668 669; Check we don't mistakenly optimize this: we don't know whether this is670; inserted into the low or high split vector.671define void @insert_v2i64_nxv16i64_hi(ptr %psv, ptr %out) {672; RV32-LABEL: insert_v2i64_nxv16i64_hi:673; RV32: # %bb.0:674; RV32-NEXT: addi sp, sp, -80675; RV32-NEXT: .cfi_def_cfa_offset 80676; RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill677; RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill678; RV32-NEXT: .cfi_offset ra, -4679; RV32-NEXT: .cfi_offset s0, -8680; RV32-NEXT: addi s0, sp, 80681; RV32-NEXT: .cfi_def_cfa s0, 0682; RV32-NEXT: csrr a2, vlenb683; RV32-NEXT: slli a2, a2, 4684; RV32-NEXT: sub sp, sp, a2685; RV32-NEXT: andi sp, sp, -64686; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma687; RV32-NEXT: vle64.v v8, (a0)688; RV32-NEXT: addi a0, sp, 128689; RV32-NEXT: vse64.v v8, (a0)690; RV32-NEXT: csrr a0, vlenb691; RV32-NEXT: slli a0, a0, 3692; RV32-NEXT: addi a2, sp, 64693; RV32-NEXT: add a3, a2, a0694; RV32-NEXT: vl8re64.v v8, (a3)695; RV32-NEXT: vl8re64.v v16, (a2)696; RV32-NEXT: add a0, a1, a0697; RV32-NEXT: vs8r.v v8, (a0)698; RV32-NEXT: vs8r.v v16, (a1)699; RV32-NEXT: addi sp, s0, -80700; RV32-NEXT: .cfi_def_cfa sp, 80701; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload702; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload703; RV32-NEXT: addi sp, sp, 80704; RV32-NEXT: ret705; RV64-LABEL: insert_v2i64_nxv16i64_hi:706; RV64: # %bb.0:707; RV64-NEXT: addi sp, sp, -80708; RV64-NEXT: .cfi_def_cfa_offset 80709; RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill710; RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill711; RV64-NEXT: .cfi_offset ra, -8712; RV64-NEXT: .cfi_offset s0, -16713; RV64-NEXT: addi s0, sp, 80714; RV64-NEXT: .cfi_def_cfa s0, 0715; RV64-NEXT: csrr a2, vlenb716; RV64-NEXT: slli a2, a2, 4717; RV64-NEXT: sub sp, sp, a2718; RV64-NEXT: andi sp, sp, -64719; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma720; RV64-NEXT: vle64.v v8, (a0)721; RV64-NEXT: addi a0, sp, 128722; RV64-NEXT: vse64.v v8, (a0)723; RV64-NEXT: csrr a0, vlenb724; RV64-NEXT: slli a0, a0, 3725; RV64-NEXT: addi a2, sp, 64726; RV64-NEXT: add a3, a2, a0727; RV64-NEXT: vl8re64.v v8, (a3)728; RV64-NEXT: vl8re64.v v16, (a2)729; RV64-NEXT: add a0, a1, a0730; RV64-NEXT: vs8r.v v8, (a0)731; RV64-NEXT: vs8r.v v16, (a1)732; RV64-NEXT: addi sp, s0, -80733; RV64-NEXT: .cfi_def_cfa sp, 80734; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload735; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload736; RV64-NEXT: addi sp, sp, 80737; RV64-NEXT: ret738; RV32VLA-LABEL: insert_v2i64_nxv16i64_hi:739; RV32VLA: # %bb.0:740; RV32VLA-NEXT: addi sp, sp, -80741; RV32VLA-NEXT: .cfi_def_cfa_offset 80742; RV32VLA-NEXT: sw ra, 76(sp) # 4-byte Folded Spill743; RV32VLA-NEXT: sw s0, 72(sp) # 4-byte Folded Spill744; RV32VLA-NEXT: .cfi_offset ra, -4745; RV32VLA-NEXT: .cfi_offset s0, -8746; RV32VLA-NEXT: addi s0, sp, 80747; RV32VLA-NEXT: .cfi_def_cfa s0, 0748; RV32VLA-NEXT: csrr a2, vlenb749; RV32VLA-NEXT: slli a2, a2, 4750; RV32VLA-NEXT: sub sp, sp, a2751; RV32VLA-NEXT: andi sp, sp, -64752; RV32VLA-NEXT: vsetivli zero, 2, e64, m1, ta, ma753; RV32VLA-NEXT: vle64.v v8, (a0)754; RV32VLA-NEXT: addi a0, sp, 128755; RV32VLA-NEXT: csrr a2, vlenb756; RV32VLA-NEXT: addi a3, sp, 64757; RV32VLA-NEXT: slli a2, a2, 3758; RV32VLA-NEXT: vse64.v v8, (a0)759; RV32VLA-NEXT: add a0, a3, a2760; RV32VLA-NEXT: vl8re64.v v8, (a0)761; RV32VLA-NEXT: vl8re64.v v16, (a3)762; RV32VLA-NEXT: add a2, a1, a2763; RV32VLA-NEXT: vs8r.v v8, (a2)764; RV32VLA-NEXT: vs8r.v v16, (a1)765; RV32VLA-NEXT: addi sp, s0, -80766; RV32VLA-NEXT: .cfi_def_cfa sp, 80767; RV32VLA-NEXT: lw ra, 76(sp) # 4-byte Folded Reload768; RV32VLA-NEXT: lw s0, 72(sp) # 4-byte Folded Reload769; RV32VLA-NEXT: .cfi_restore ra770; RV32VLA-NEXT: .cfi_restore s0771; RV32VLA-NEXT: addi sp, sp, 80772; RV32VLA-NEXT: .cfi_def_cfa_offset 0773; RV32VLA-NEXT: ret774;775; RV64VLA-LABEL: insert_v2i64_nxv16i64_hi:776; RV64VLA: # %bb.0:777; RV64VLA-NEXT: addi sp, sp, -80778; RV64VLA-NEXT: .cfi_def_cfa_offset 80779; RV64VLA-NEXT: sd ra, 72(sp) # 8-byte Folded Spill780; RV64VLA-NEXT: sd s0, 64(sp) # 8-byte Folded Spill781; RV64VLA-NEXT: .cfi_offset ra, -8782; RV64VLA-NEXT: .cfi_offset s0, -16783; RV64VLA-NEXT: addi s0, sp, 80784; RV64VLA-NEXT: .cfi_def_cfa s0, 0785; RV64VLA-NEXT: csrr a2, vlenb786; RV64VLA-NEXT: slli a2, a2, 4787; RV64VLA-NEXT: sub sp, sp, a2788; RV64VLA-NEXT: andi sp, sp, -64789; RV64VLA-NEXT: vsetivli zero, 2, e64, m1, ta, ma790; RV64VLA-NEXT: vle64.v v8, (a0)791; RV64VLA-NEXT: addi a0, sp, 128792; RV64VLA-NEXT: csrr a2, vlenb793; RV64VLA-NEXT: addi a3, sp, 64794; RV64VLA-NEXT: slli a2, a2, 3795; RV64VLA-NEXT: vse64.v v8, (a0)796; RV64VLA-NEXT: add a0, a3, a2797; RV64VLA-NEXT: vl8re64.v v8, (a0)798; RV64VLA-NEXT: vl8re64.v v16, (a3)799; RV64VLA-NEXT: add a2, a1, a2800; RV64VLA-NEXT: vs8r.v v8, (a2)801; RV64VLA-NEXT: vs8r.v v16, (a1)802; RV64VLA-NEXT: addi sp, s0, -80803; RV64VLA-NEXT: .cfi_def_cfa sp, 80804; RV64VLA-NEXT: ld ra, 72(sp) # 8-byte Folded Reload805; RV64VLA-NEXT: ld s0, 64(sp) # 8-byte Folded Reload806; RV64VLA-NEXT: .cfi_restore ra807; RV64VLA-NEXT: .cfi_restore s0808; RV64VLA-NEXT: addi sp, sp, 80809; RV64VLA-NEXT: .cfi_def_cfa_offset 0810; RV64VLA-NEXT: ret811;812; RV32VLS-LABEL: insert_v2i64_nxv16i64_hi:813; RV32VLS: # %bb.0:814; RV32VLS-NEXT: addi sp, sp, -80815; RV32VLS-NEXT: .cfi_def_cfa_offset 80816; RV32VLS-NEXT: sw ra, 76(sp) # 4-byte Folded Spill817; RV32VLS-NEXT: sw s0, 72(sp) # 4-byte Folded Spill818; RV32VLS-NEXT: .cfi_offset ra, -4819; RV32VLS-NEXT: .cfi_offset s0, -8820; RV32VLS-NEXT: addi s0, sp, 80821; RV32VLS-NEXT: .cfi_def_cfa s0, 0822; RV32VLS-NEXT: addi sp, sp, -256823; RV32VLS-NEXT: andi sp, sp, -64824; RV32VLS-NEXT: vl1re64.v v8, (a0)825; RV32VLS-NEXT: addi a0, sp, 128826; RV32VLS-NEXT: vs1r.v v8, (a0)827; RV32VLS-NEXT: addi a0, sp, 192828; RV32VLS-NEXT: vl8re64.v v8, (a0)829; RV32VLS-NEXT: addi a0, sp, 64830; RV32VLS-NEXT: vl8re64.v v16, (a0)831; RV32VLS-NEXT: addi a0, a1, 128832; RV32VLS-NEXT: vs8r.v v8, (a0)833; RV32VLS-NEXT: vs8r.v v16, (a1)834; RV32VLS-NEXT: addi sp, s0, -80835; RV32VLS-NEXT: .cfi_def_cfa sp, 80836; RV32VLS-NEXT: lw ra, 76(sp) # 4-byte Folded Reload837; RV32VLS-NEXT: lw s0, 72(sp) # 4-byte Folded Reload838; RV32VLS-NEXT: .cfi_restore ra839; RV32VLS-NEXT: .cfi_restore s0840; RV32VLS-NEXT: addi sp, sp, 80841; RV32VLS-NEXT: .cfi_def_cfa_offset 0842; RV32VLS-NEXT: ret843;844; RV64VLS-LABEL: insert_v2i64_nxv16i64_hi:845; RV64VLS: # %bb.0:846; RV64VLS-NEXT: addi sp, sp, -80847; RV64VLS-NEXT: .cfi_def_cfa_offset 80848; RV64VLS-NEXT: sd ra, 72(sp) # 8-byte Folded Spill849; RV64VLS-NEXT: sd s0, 64(sp) # 8-byte Folded Spill850; RV64VLS-NEXT: .cfi_offset ra, -8851; RV64VLS-NEXT: .cfi_offset s0, -16852; RV64VLS-NEXT: addi s0, sp, 80853; RV64VLS-NEXT: .cfi_def_cfa s0, 0854; RV64VLS-NEXT: addi sp, sp, -256855; RV64VLS-NEXT: andi sp, sp, -64856; RV64VLS-NEXT: vl1re64.v v8, (a0)857; RV64VLS-NEXT: addi a0, sp, 128858; RV64VLS-NEXT: vs1r.v v8, (a0)859; RV64VLS-NEXT: addi a0, sp, 192860; RV64VLS-NEXT: vl8re64.v v8, (a0)861; RV64VLS-NEXT: addi a0, sp, 64862; RV64VLS-NEXT: vl8re64.v v16, (a0)863; RV64VLS-NEXT: addi a0, a1, 128864; RV64VLS-NEXT: vs8r.v v8, (a0)865; RV64VLS-NEXT: vs8r.v v16, (a1)866; RV64VLS-NEXT: addi sp, s0, -80867; RV64VLS-NEXT: .cfi_def_cfa sp, 80868; RV64VLS-NEXT: ld ra, 72(sp) # 8-byte Folded Reload869; RV64VLS-NEXT: ld s0, 64(sp) # 8-byte Folded Reload870; RV64VLS-NEXT: .cfi_restore ra871; RV64VLS-NEXT: .cfi_restore s0872; RV64VLS-NEXT: addi sp, sp, 80873; RV64VLS-NEXT: .cfi_def_cfa_offset 0874; RV64VLS-NEXT: ret875 %sv = load <2 x i64>, ptr %psv876 %v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> poison, <2 x i64> %sv, i64 8)877 store <vscale x 16 x i64> %v, ptr %out878 ret void879}880 881define <vscale x 8 x bfloat> @insert_nxv8bf16_v2bf16_0(<vscale x 8 x bfloat> %vec, ptr %svp) {882; VLA-LABEL: insert_nxv8bf16_v2bf16_0:883; VLA: # %bb.0:884; VLA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma885; VLA-NEXT: vle16.v v10, (a0)886; VLA-NEXT: vsetivli zero, 2, e16, m2, tu, ma887; VLA-NEXT: vmv.v.v v8, v10888; VLA-NEXT: ret889;890; VLS-LABEL: insert_nxv8bf16_v2bf16_0:891; VLS: # %bb.0:892; VLS-NEXT: vsetivli zero, 2, e16, mf4, ta, ma893; VLS-NEXT: vle16.v v10, (a0)894; VLS-NEXT: vsetivli zero, 2, e16, m1, tu, ma895; VLS-NEXT: vmv.v.v v8, v10896; VLS-NEXT: ret897 %sv = load <2 x bfloat>, ptr %svp898 %v = call <vscale x 8 x bfloat> @llvm.vector.insert.v2bf16.nxv8bf16(<vscale x 8 x bfloat> %vec, <2 x bfloat> %sv, i64 0)899 ret <vscale x 8 x bfloat> %v900}901 902define <vscale x 8 x bfloat> @insert_nxv8bf16_v2bf16_2(<vscale x 8 x bfloat> %vec, ptr %svp) {903; VLA-LABEL: insert_nxv8bf16_v2bf16_2:904; VLA: # %bb.0:905; VLA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma906; VLA-NEXT: vle16.v v10, (a0)907; VLA-NEXT: vsetivli zero, 4, e16, m2, tu, ma908; VLA-NEXT: vslideup.vi v8, v10, 2909; VLA-NEXT: ret910;911; VLS-LABEL: insert_nxv8bf16_v2bf16_2:912; VLS: # %bb.0:913; VLS-NEXT: vsetivli zero, 2, e16, mf4, ta, ma914; VLS-NEXT: vle16.v v10, (a0)915; VLS-NEXT: vsetivli zero, 4, e16, m1, tu, ma916; VLS-NEXT: vslideup.vi v8, v10, 2917; VLS-NEXT: ret918 %sv = load <2 x bfloat>, ptr %svp919 %v = call <vscale x 8 x bfloat> @llvm.vector.insert.v2bf16.nxv8bf16(<vscale x 8 x bfloat> %vec, <2 x bfloat> %sv, i64 2)920 ret <vscale x 8 x bfloat> %v921}922 923define <vscale x 8 x half> @insert_nxv8f16_v2f16_0(<vscale x 8 x half> %vec, ptr %svp) {924; VLA-LABEL: insert_nxv8f16_v2f16_0:925; VLA: # %bb.0:926; VLA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma927; VLA-NEXT: vle16.v v10, (a0)928; VLA-NEXT: vsetivli zero, 2, e16, m2, tu, ma929; VLA-NEXT: vmv.v.v v8, v10930; VLA-NEXT: ret931;932; VLS-LABEL: insert_nxv8f16_v2f16_0:933; VLS: # %bb.0:934; VLS-NEXT: vsetivli zero, 2, e16, mf4, ta, ma935; VLS-NEXT: vle16.v v10, (a0)936; VLS-NEXT: vsetivli zero, 2, e16, m1, tu, ma937; VLS-NEXT: vmv.v.v v8, v10938; VLS-NEXT: ret939 %sv = load <2 x half>, ptr %svp940 %v = call <vscale x 8 x half> @llvm.vector.insert.v2f16.nxv8f16(<vscale x 8 x half> %vec, <2 x half> %sv, i64 0)941 ret <vscale x 8 x half> %v942}943 944define <vscale x 8 x half> @insert_nxv8f16_v2f16_2(<vscale x 8 x half> %vec, ptr %svp) {945; VLA-LABEL: insert_nxv8f16_v2f16_2:946; VLA: # %bb.0:947; VLA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma948; VLA-NEXT: vle16.v v10, (a0)949; VLA-NEXT: vsetivli zero, 4, e16, m2, tu, ma950; VLA-NEXT: vslideup.vi v8, v10, 2951; VLA-NEXT: ret952;953; VLS-LABEL: insert_nxv8f16_v2f16_2:954; VLS: # %bb.0:955; VLS-NEXT: vsetivli zero, 2, e16, mf4, ta, ma956; VLS-NEXT: vle16.v v10, (a0)957; VLS-NEXT: vsetivli zero, 4, e16, m1, tu, ma958; VLS-NEXT: vslideup.vi v8, v10, 2959; VLS-NEXT: ret960 %sv = load <2 x half>, ptr %svp961 %v = call <vscale x 8 x half> @llvm.vector.insert.v2f16.nxv8f16(<vscale x 8 x half> %vec, <2 x half> %sv, i64 2)962 ret <vscale x 8 x half> %v963}964 965; We emit insert_subvectors of fixed vectors at index 0 into undefs as a966; copy_to_regclass or insert_subreg, depending on the register classes of the967; vector types. Make sure that we use the correct type and not the shrunken968; LMUL=1 type, otherwise we will end up with an invalid extract_subvector when969; converting it from scalable->fixed, e.g. we get this for VLEN=128:970;971; t14: nxv2i32 = insert_subvector poison:nxv2i32, t4, Constant:i64<0>972; t15: v8i32 = extract_subvector t14, Constant:i64<0>973define <4 x i32> @insert_extract_v8i32_v2i32_0(<2 x i32> %v) {974; CHECK-LABEL: insert_extract_v8i32_v2i32_0:975; CHECK: # %bb.0:976; CHECK-NEXT: ret977 %1 = call <8 x i32> @llvm.vector.insert.v2i32.v8i32(<8 x i32> poison, <2 x i32> %v, i64 0)978 %2 = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %1, i64 0)979 ret <4 x i32> %2980}981