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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,ZVFH3; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,ZVFH4; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,ZVFHMIN,ZVFHMINRV325; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,ZVFHMIN,ZVFHMINRV646;7; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+zfbfmin,+zvfbfmin,+f,+d,+experimental-xrivosvisni -verify-machineinstrs < %s | FileCheck %s --check-prefixes=VISNI8 9define <4 x i32> @insertelt_v4i32_0(<4 x i32> %a, i32 %y) {10; CHECK-LABEL: insertelt_v4i32_0:11; CHECK: # %bb.0:12; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma13; CHECK-NEXT: vmv.s.x v8, a014; CHECK-NEXT: ret15;16; VISNI-LABEL: insertelt_v4i32_0:17; VISNI: # %bb.0:18; VISNI-NEXT: vsetivli zero, 4, e32, m1, tu, ma19; VISNI-NEXT: vmv.s.x v8, a020; VISNI-NEXT: ret21 %b = insertelement <4 x i32> %a, i32 %y, i32 022 ret <4 x i32> %b23}24 25define <4 x i32> @insertelt_v4i32_3(<4 x i32> %a, i32 %y) {26; CHECK-LABEL: insertelt_v4i32_3:27; CHECK: # %bb.0:28; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma29; CHECK-NEXT: vmv.s.x v9, a030; CHECK-NEXT: vslideup.vi v8, v9, 331; CHECK-NEXT: ret32;33; VISNI-LABEL: insertelt_v4i32_3:34; VISNI: # %bb.0:35; VISNI-NEXT: vsetivli zero, 4, e32, m1, ta, ma36; VISNI-NEXT: ri.vinsert.v.x v8, a0, 337; VISNI-NEXT: ret38 %b = insertelement <4 x i32> %a, i32 %y, i32 339 ret <4 x i32> %b40}41 42define <4 x i32> @insertelt_v4i32_idx(<4 x i32> %a, i32 %y, i32 zeroext %idx) {43; CHECK-LABEL: insertelt_v4i32_idx:44; CHECK: # %bb.0:45; CHECK-NEXT: addi a2, a1, 146; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma47; CHECK-NEXT: vmv.s.x v9, a048; CHECK-NEXT: vsetvli zero, a2, e32, m1, tu, ma49; CHECK-NEXT: vslideup.vx v8, v9, a150; CHECK-NEXT: ret51;52; VISNI-LABEL: insertelt_v4i32_idx:53; VISNI: # %bb.0:54; VISNI-NEXT: addi a2, a1, 155; VISNI-NEXT: vsetivli zero, 4, e32, m1, ta, ma56; VISNI-NEXT: vmv.s.x v9, a057; VISNI-NEXT: vsetvli zero, a2, e32, m1, tu, ma58; VISNI-NEXT: vslideup.vx v8, v9, a159; VISNI-NEXT: ret60 %b = insertelement <4 x i32> %a, i32 %y, i32 %idx61 ret <4 x i32> %b62}63 64define <32 x i32> @insertelt_v32i32_0(<32 x i32> %a, i32 %y) {65; CHECK-LABEL: insertelt_v32i32_0:66; CHECK: # %bb.0:67; CHECK-NEXT: li a1, 3268; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma69; CHECK-NEXT: vmv.s.x v8, a070; CHECK-NEXT: ret71;72; VISNI-LABEL: insertelt_v32i32_0:73; VISNI: # %bb.0:74; VISNI-NEXT: li a1, 3275; VISNI-NEXT: vsetvli zero, a1, e32, m1, tu, ma76; VISNI-NEXT: vmv.s.x v8, a077; VISNI-NEXT: ret78 %b = insertelement <32 x i32> %a, i32 %y, i32 079 ret <32 x i32> %b80}81 82define <32 x i32> @insertelt_v32i32_4(<32 x i32> %a, i32 %y) {83; CHECK-LABEL: insertelt_v32i32_4:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetivli zero, 5, e32, m2, tu, ma86; CHECK-NEXT: vmv.s.x v16, a087; CHECK-NEXT: vslideup.vi v8, v16, 488; CHECK-NEXT: ret89;90; VISNI-LABEL: insertelt_v32i32_4:91; VISNI: # %bb.0:92; VISNI-NEXT: li a1, 3293; VISNI-NEXT: vsetvli zero, a1, e32, m2, ta, ma94; VISNI-NEXT: ri.vinsert.v.x v8, a0, 495; VISNI-NEXT: ret96 %b = insertelement <32 x i32> %a, i32 %y, i32 497 ret <32 x i32> %b98}99 100define <32 x i32> @insertelt_v32i32_31(<32 x i32> %a, i32 %y) {101; CHECK-LABEL: insertelt_v32i32_31:102; CHECK: # %bb.0:103; CHECK-NEXT: li a1, 32104; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma105; CHECK-NEXT: vmv.s.x v16, a0106; CHECK-NEXT: vslideup.vi v8, v16, 31107; CHECK-NEXT: ret108;109; VISNI-LABEL: insertelt_v32i32_31:110; VISNI: # %bb.0:111; VISNI-NEXT: li a1, 32112; VISNI-NEXT: vsetvli zero, a1, e32, m8, ta, ma113; VISNI-NEXT: ri.vinsert.v.x v8, a0, 31114; VISNI-NEXT: ret115 %b = insertelement <32 x i32> %a, i32 %y, i32 31116 ret <32 x i32> %b117}118 119define <32 x i32> @insertelt_v32i32_idx(<32 x i32> %a, i32 %y, i32 zeroext %idx) {120; CHECK-LABEL: insertelt_v32i32_idx:121; CHECK: # %bb.0:122; CHECK-NEXT: li a2, 32123; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma124; CHECK-NEXT: vmv.s.x v16, a0125; CHECK-NEXT: addi a0, a1, 1126; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma127; CHECK-NEXT: vslideup.vx v8, v16, a1128; CHECK-NEXT: ret129;130; VISNI-LABEL: insertelt_v32i32_idx:131; VISNI: # %bb.0:132; VISNI-NEXT: li a2, 32133; VISNI-NEXT: vsetvli zero, a2, e32, m1, ta, ma134; VISNI-NEXT: vmv.s.x v16, a0135; VISNI-NEXT: addi a0, a1, 1136; VISNI-NEXT: vsetvli zero, a0, e32, m8, tu, ma137; VISNI-NEXT: vslideup.vx v8, v16, a1138; VISNI-NEXT: ret139 %b = insertelement <32 x i32> %a, i32 %y, i32 %idx140 ret <32 x i32> %b141}142 143define <64 x i32> @insertelt_v64i32_0(<64 x i32> %a, i32 %y) {144; CHECK-LABEL: insertelt_v64i32_0:145; CHECK: # %bb.0:146; CHECK-NEXT: li a1, 32147; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma148; CHECK-NEXT: vmv.s.x v8, a0149; CHECK-NEXT: ret150;151; VISNI-LABEL: insertelt_v64i32_0:152; VISNI: # %bb.0:153; VISNI-NEXT: li a1, 32154; VISNI-NEXT: vsetvli zero, a1, e32, m1, tu, ma155; VISNI-NEXT: vmv.s.x v8, a0156; VISNI-NEXT: ret157 %b = insertelement <64 x i32> %a, i32 %y, i32 0158 ret <64 x i32> %b159}160 161define <64 x i32> @insertelt_v64i32_63(<64 x i32> %a, i32 %y) {162; CHECK-LABEL: insertelt_v64i32_63:163; CHECK: # %bb.0:164; CHECK-NEXT: li a1, 32165; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma166; CHECK-NEXT: vmv.s.x v24, a0167; CHECK-NEXT: vslideup.vi v16, v24, 31168; CHECK-NEXT: ret169;170; VISNI-LABEL: insertelt_v64i32_63:171; VISNI: # %bb.0:172; VISNI-NEXT: li a1, 32173; VISNI-NEXT: vsetvli zero, a1, e32, m8, ta, ma174; VISNI-NEXT: ri.vinsert.v.x v16, a0, 31175; VISNI-NEXT: ret176 %b = insertelement <64 x i32> %a, i32 %y, i32 63177 ret <64 x i32> %b178}179 180define <64 x i32> @insertelt_v64i32_idx(<64 x i32> %a, i32 %y, i32 zeroext %idx) {181; RV32-LABEL: insertelt_v64i32_idx:182; RV32: # %bb.0:183; RV32-NEXT: addi sp, sp, -384184; RV32-NEXT: .cfi_def_cfa_offset 384185; RV32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill186; RV32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill187; RV32-NEXT: .cfi_offset ra, -4188; RV32-NEXT: .cfi_offset s0, -8189; RV32-NEXT: addi s0, sp, 384190; RV32-NEXT: .cfi_def_cfa s0, 0191; RV32-NEXT: andi sp, sp, -128192; RV32-NEXT: andi a1, a1, 63193; RV32-NEXT: mv a2, sp194; RV32-NEXT: addi a3, sp, 128195; RV32-NEXT: li a4, 32196; RV32-NEXT: slli a1, a1, 2197; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma198; RV32-NEXT: vse32.v v16, (a3)199; RV32-NEXT: vse32.v v8, (a2)200; RV32-NEXT: add a1, a2, a1201; RV32-NEXT: sw a0, 0(a1)202; RV32-NEXT: vle32.v v8, (a2)203; RV32-NEXT: vle32.v v16, (a3)204; RV32-NEXT: addi sp, s0, -384205; RV32-NEXT: .cfi_def_cfa sp, 384206; RV32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload207; RV32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload208; RV32-NEXT: .cfi_restore ra209; RV32-NEXT: .cfi_restore s0210; RV32-NEXT: addi sp, sp, 384211; RV32-NEXT: .cfi_def_cfa_offset 0212; RV32-NEXT: ret213;214; RV64-LABEL: insertelt_v64i32_idx:215; RV64: # %bb.0:216; RV64-NEXT: addi sp, sp, -384217; RV64-NEXT: .cfi_def_cfa_offset 384218; RV64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill219; RV64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill220; RV64-NEXT: .cfi_offset ra, -8221; RV64-NEXT: .cfi_offset s0, -16222; RV64-NEXT: addi s0, sp, 384223; RV64-NEXT: .cfi_def_cfa s0, 0224; RV64-NEXT: andi sp, sp, -128225; RV64-NEXT: andi a1, a1, 63226; RV64-NEXT: mv a2, sp227; RV64-NEXT: addi a3, sp, 128228; RV64-NEXT: li a4, 32229; RV64-NEXT: slli a1, a1, 2230; RV64-NEXT: vsetvli zero, a4, e32, m8, ta, ma231; RV64-NEXT: vse32.v v16, (a3)232; RV64-NEXT: vse32.v v8, (a2)233; RV64-NEXT: add a1, a2, a1234; RV64-NEXT: sw a0, 0(a1)235; RV64-NEXT: vle32.v v8, (a2)236; RV64-NEXT: vle32.v v16, (a3)237; RV64-NEXT: addi sp, s0, -384238; RV64-NEXT: .cfi_def_cfa sp, 384239; RV64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload240; RV64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload241; RV64-NEXT: .cfi_restore ra242; RV64-NEXT: .cfi_restore s0243; RV64-NEXT: addi sp, sp, 384244; RV64-NEXT: .cfi_def_cfa_offset 0245; RV64-NEXT: ret246;247; VISNI-LABEL: insertelt_v64i32_idx:248; VISNI: # %bb.0:249; VISNI-NEXT: addi sp, sp, -384250; VISNI-NEXT: .cfi_def_cfa_offset 384251; VISNI-NEXT: sd ra, 376(sp) # 8-byte Folded Spill252; VISNI-NEXT: sd s0, 368(sp) # 8-byte Folded Spill253; VISNI-NEXT: .cfi_offset ra, -8254; VISNI-NEXT: .cfi_offset s0, -16255; VISNI-NEXT: addi s0, sp, 384256; VISNI-NEXT: .cfi_def_cfa s0, 0257; VISNI-NEXT: andi sp, sp, -128258; VISNI-NEXT: andi a1, a1, 63259; VISNI-NEXT: mv a2, sp260; VISNI-NEXT: addi a3, sp, 128261; VISNI-NEXT: li a4, 32262; VISNI-NEXT: slli a1, a1, 2263; VISNI-NEXT: vsetvli zero, a4, e32, m8, ta, ma264; VISNI-NEXT: vse32.v v16, (a3)265; VISNI-NEXT: vse32.v v8, (a2)266; VISNI-NEXT: add a1, a2, a1267; VISNI-NEXT: sw a0, 0(a1)268; VISNI-NEXT: vle32.v v8, (a2)269; VISNI-NEXT: vle32.v v16, (a3)270; VISNI-NEXT: addi sp, s0, -384271; VISNI-NEXT: .cfi_def_cfa sp, 384272; VISNI-NEXT: ld ra, 376(sp) # 8-byte Folded Reload273; VISNI-NEXT: ld s0, 368(sp) # 8-byte Folded Reload274; VISNI-NEXT: .cfi_restore ra275; VISNI-NEXT: .cfi_restore s0276; VISNI-NEXT: addi sp, sp, 384277; VISNI-NEXT: .cfi_def_cfa_offset 0278; VISNI-NEXT: ret279 %b = insertelement <64 x i32> %a, i32 %y, i32 %idx280 ret <64 x i32> %b281}282 283; FIXME: This codegen needs to be improved. These tests previously asserted284; type legalizing the i64 type on RV32.285 286define <4 x i64> @insertelt_v4i64(<4 x i64> %a, i64 %y) {287; RV32-LABEL: insertelt_v4i64:288; RV32: # %bb.0:289; RV32-NEXT: vsetivli zero, 2, e32, m2, ta, ma290; RV32-NEXT: vslide1down.vx v10, v8, a0291; RV32-NEXT: vslide1down.vx v10, v10, a1292; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma293; RV32-NEXT: vslideup.vi v8, v10, 3294; RV32-NEXT: ret295;296; RV64-LABEL: insertelt_v4i64:297; RV64: # %bb.0:298; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma299; RV64-NEXT: vmv.s.x v10, a0300; RV64-NEXT: vslideup.vi v8, v10, 3301; RV64-NEXT: ret302;303; VISNI-LABEL: insertelt_v4i64:304; VISNI: # %bb.0:305; VISNI-NEXT: vsetivli zero, 4, e64, m2, ta, ma306; VISNI-NEXT: ri.vinsert.v.x v8, a0, 3307; VISNI-NEXT: ret308 %b = insertelement <4 x i64> %a, i64 %y, i32 3309 ret <4 x i64> %b310}311 312define void @insertelt_v4i64_store(ptr %x, i64 %y) {313; RV32-LABEL: insertelt_v4i64_store:314; RV32: # %bb.0:315; RV32-NEXT: sw a1, 24(a0)316; RV32-NEXT: sw a2, 28(a0)317; RV32-NEXT: ret318;319; RV64-LABEL: insertelt_v4i64_store:320; RV64: # %bb.0:321; RV64-NEXT: sd a1, 24(a0)322; RV64-NEXT: ret323;324; VISNI-LABEL: insertelt_v4i64_store:325; VISNI: # %bb.0:326; VISNI-NEXT: sd a1, 24(a0)327; VISNI-NEXT: ret328 %a = load <4 x i64>, ptr %x329 %b = insertelement <4 x i64> %a, i64 %y, i32 3330 store <4 x i64> %b, ptr %x331 ret void332}333 334; This uses a non-power of 2 type so that it isn't an MVT.335; The align keeps the type legalizer from using a 256 bit load so we must split336; it. This some operations that weren't support for scalable vectors when337; this test was written.338define <3 x i64> @insertelt_v3i64(<3 x i64> %a, i64 %y) {339; RV32-LABEL: insertelt_v3i64:340; RV32: # %bb.0:341; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma342; RV32-NEXT: vslidedown.vi v9, v8, 3343; RV32-NEXT: vslidedown.vi v10, v8, 2344; RV32-NEXT: vmv.x.s a2, v8345; RV32-NEXT: vslidedown.vi v8, v8, 1346; RV32-NEXT: vmv.x.s a3, v9347; RV32-NEXT: vmv.x.s a4, v10348; RV32-NEXT: vmv.x.s a5, v8349; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma350; RV32-NEXT: vmv.v.x v8, a2351; RV32-NEXT: vslide1down.vx v8, v8, a5352; RV32-NEXT: vslide1down.vx v8, v8, a4353; RV32-NEXT: vslide1down.vx v8, v8, a3354; RV32-NEXT: vslide1down.vx v8, v8, a0355; RV32-NEXT: vslide1down.vx v8, v8, a1356; RV32-NEXT: vslidedown.vi v8, v8, 2357; RV32-NEXT: ret358;359; RV64-LABEL: insertelt_v3i64:360; RV64: # %bb.0:361; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma362; RV64-NEXT: vslidedown.vi v9, v8, 1363; RV64-NEXT: vmv.x.s a1, v8364; RV64-NEXT: vmv.x.s a2, v9365; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma366; RV64-NEXT: vmv.v.x v8, a1367; RV64-NEXT: vslide1down.vx v8, v8, a2368; RV64-NEXT: vslide1down.vx v8, v8, a0369; RV64-NEXT: vslidedown.vi v8, v8, 1370; RV64-NEXT: ret371;372; VISNI-LABEL: insertelt_v3i64:373; VISNI: # %bb.0:374; VISNI-NEXT: vsetivli zero, 1, e64, m1, ta, ma375; VISNI-NEXT: ri.vextract.x.v a1, v8, 1376; VISNI-NEXT: vmv.x.s a2, v8377; VISNI-NEXT: vsetivli zero, 4, e64, m2, ta, ma378; VISNI-NEXT: vmv.v.x v8, a2379; VISNI-NEXT: vslide1down.vx v8, v8, a1380; VISNI-NEXT: vslide1down.vx v8, v8, a0381; VISNI-NEXT: vslidedown.vi v8, v8, 1382; VISNI-NEXT: ret383 %b = insertelement <3 x i64> %a, i64 %y, i32 2384 ret <3 x i64> %b385}386 387define void @insertelt_v3i64_store(ptr %x, i64 %y) {388; RV32-LABEL: insertelt_v3i64_store:389; RV32: # %bb.0:390; RV32-NEXT: sw a1, 16(a0)391; RV32-NEXT: sw a2, 20(a0)392; RV32-NEXT: ret393;394; RV64-LABEL: insertelt_v3i64_store:395; RV64: # %bb.0:396; RV64-NEXT: sd a1, 16(a0)397; RV64-NEXT: ret398;399; VISNI-LABEL: insertelt_v3i64_store:400; VISNI: # %bb.0:401; VISNI-NEXT: sd a1, 16(a0)402; VISNI-NEXT: ret403 %a = load <3 x i64>, ptr %x, align 8404 %b = insertelement <3 x i64> %a, i64 %y, i32 2405 store <3 x i64> %b, ptr %x406 ret void407}408 409define <16 x i8> @insertelt_v16i8(<16 x i8> %a, i8 %y) {410; CHECK-LABEL: insertelt_v16i8:411; CHECK: # %bb.0:412; CHECK-NEXT: vsetivli zero, 15, e8, m1, tu, ma413; CHECK-NEXT: vmv.s.x v9, a0414; CHECK-NEXT: vslideup.vi v8, v9, 14415; CHECK-NEXT: ret416;417; VISNI-LABEL: insertelt_v16i8:418; VISNI: # %bb.0:419; VISNI-NEXT: vsetivli zero, 16, e8, m1, ta, ma420; VISNI-NEXT: ri.vinsert.v.x v8, a0, 14421; VISNI-NEXT: ret422 %b = insertelement <16 x i8> %a, i8 %y, i32 14423 ret <16 x i8> %b424}425 426define void @insertelt_v16i8_store(ptr %x, i8 %y) {427; CHECK-LABEL: insertelt_v16i8_store:428; CHECK: # %bb.0:429; CHECK-NEXT: sb a1, 14(a0)430; CHECK-NEXT: ret431;432; VISNI-LABEL: insertelt_v16i8_store:433; VISNI: # %bb.0:434; VISNI-NEXT: sb a1, 14(a0)435; VISNI-NEXT: ret436 %a = load <16 x i8>, ptr %x437 %b = insertelement <16 x i8> %a, i8 %y, i32 14438 store <16 x i8> %b, ptr %x439 ret void440}441 442define <32 x i16> @insertelt_v32i16(<32 x i16> %a, i16 %y, i32 %idx) {443; RV32-LABEL: insertelt_v32i16:444; RV32: # %bb.0:445; RV32-NEXT: li a2, 32446; RV32-NEXT: vsetvli zero, a2, e16, m1, ta, ma447; RV32-NEXT: vmv.s.x v12, a0448; RV32-NEXT: addi a0, a1, 1449; RV32-NEXT: vsetvli zero, a0, e16, m4, tu, ma450; RV32-NEXT: vslideup.vx v8, v12, a1451; RV32-NEXT: ret452;453; RV64-LABEL: insertelt_v32i16:454; RV64: # %bb.0:455; RV64-NEXT: li a2, 32456; RV64-NEXT: slli a1, a1, 32457; RV64-NEXT: vsetvli zero, a2, e16, m1, ta, ma458; RV64-NEXT: vmv.s.x v12, a0459; RV64-NEXT: srli a1, a1, 32460; RV64-NEXT: addi a0, a1, 1461; RV64-NEXT: vsetvli zero, a0, e16, m4, tu, ma462; RV64-NEXT: vslideup.vx v8, v12, a1463; RV64-NEXT: ret464;465; VISNI-LABEL: insertelt_v32i16:466; VISNI: # %bb.0:467; VISNI-NEXT: li a2, 32468; VISNI-NEXT: slli a1, a1, 32469; VISNI-NEXT: vsetvli zero, a2, e16, m1, ta, ma470; VISNI-NEXT: vmv.s.x v12, a0471; VISNI-NEXT: srli a1, a1, 32472; VISNI-NEXT: addi a0, a1, 1473; VISNI-NEXT: vsetvli zero, a0, e16, m4, tu, ma474; VISNI-NEXT: vslideup.vx v8, v12, a1475; VISNI-NEXT: ret476 %b = insertelement <32 x i16> %a, i16 %y, i32 %idx477 ret <32 x i16> %b478}479 480define void @insertelt_v32i16_store(ptr %x, i16 %y, i32 %idx) {481; CHECK-LABEL: insertelt_v32i16_store:482; CHECK: # %bb.0:483; CHECK-NEXT: andi a2, a2, 31484; CHECK-NEXT: slli a2, a2, 1485; CHECK-NEXT: add a0, a0, a2486; CHECK-NEXT: sh a1, 0(a0)487; CHECK-NEXT: ret488;489; VISNI-LABEL: insertelt_v32i16_store:490; VISNI: # %bb.0:491; VISNI-NEXT: andi a2, a2, 31492; VISNI-NEXT: slli a2, a2, 1493; VISNI-NEXT: add a0, a0, a2494; VISNI-NEXT: sh a1, 0(a0)495; VISNI-NEXT: ret496 %a = load <32 x i16>, ptr %x497 %b = insertelement <32 x i16> %a, i16 %y, i32 %idx498 store <32 x i16> %b, ptr %x499 ret void500}501 502define <8 x float> @insertelt_v8f32(<8 x float> %a, float %y, i32 %idx) {503; RV32-LABEL: insertelt_v8f32:504; RV32: # %bb.0:505; RV32-NEXT: vsetivli zero, 8, e32, m1, ta, ma506; RV32-NEXT: vfmv.s.f v10, fa0507; RV32-NEXT: addi a1, a0, 1508; RV32-NEXT: vsetvli zero, a1, e32, m2, tu, ma509; RV32-NEXT: vslideup.vx v8, v10, a0510; RV32-NEXT: ret511;512; RV64-LABEL: insertelt_v8f32:513; RV64: # %bb.0:514; RV64-NEXT: vsetivli zero, 8, e32, m1, ta, ma515; RV64-NEXT: vfmv.s.f v10, fa0516; RV64-NEXT: slli a0, a0, 32517; RV64-NEXT: srli a0, a0, 32518; RV64-NEXT: addi a1, a0, 1519; RV64-NEXT: vsetvli zero, a1, e32, m2, tu, ma520; RV64-NEXT: vslideup.vx v8, v10, a0521; RV64-NEXT: ret522;523; VISNI-LABEL: insertelt_v8f32:524; VISNI: # %bb.0:525; VISNI-NEXT: vsetivli zero, 8, e32, m1, ta, ma526; VISNI-NEXT: vfmv.s.f v10, fa0527; VISNI-NEXT: slli a0, a0, 32528; VISNI-NEXT: srli a0, a0, 32529; VISNI-NEXT: addi a1, a0, 1530; VISNI-NEXT: vsetvli zero, a1, e32, m2, tu, ma531; VISNI-NEXT: vslideup.vx v8, v10, a0532; VISNI-NEXT: ret533 %b = insertelement <8 x float> %a, float %y, i32 %idx534 ret <8 x float> %b535}536 537define void @insertelt_v8f32_store(ptr %x, float %y, i32 %idx) {538; CHECK-LABEL: insertelt_v8f32_store:539; CHECK: # %bb.0:540; CHECK-NEXT: andi a1, a1, 7541; CHECK-NEXT: slli a1, a1, 2542; CHECK-NEXT: add a0, a0, a1543; CHECK-NEXT: fsw fa0, 0(a0)544; CHECK-NEXT: ret545;546; VISNI-LABEL: insertelt_v8f32_store:547; VISNI: # %bb.0:548; VISNI-NEXT: andi a1, a1, 7549; VISNI-NEXT: slli a1, a1, 2550; VISNI-NEXT: add a0, a0, a1551; VISNI-NEXT: fsw fa0, 0(a0)552; VISNI-NEXT: ret553 %a = load <8 x float>, ptr %x554 %b = insertelement <8 x float> %a, float %y, i32 %idx555 store <8 x float> %b, ptr %x556 ret void557}558 559define <8 x i64> @insertelt_v8i64_0(<8 x i64> %a, ptr %x) {560; CHECK-LABEL: insertelt_v8i64_0:561; CHECK: # %bb.0:562; CHECK-NEXT: li a0, -1563; CHECK-NEXT: vsetivli zero, 8, e64, m1, tu, ma564; CHECK-NEXT: vmv.s.x v8, a0565; CHECK-NEXT: ret566;567; VISNI-LABEL: insertelt_v8i64_0:568; VISNI: # %bb.0:569; VISNI-NEXT: li a0, -1570; VISNI-NEXT: vsetivli zero, 8, e64, m1, tu, ma571; VISNI-NEXT: vmv.s.x v8, a0572; VISNI-NEXT: ret573 %b = insertelement <8 x i64> %a, i64 -1, i32 0574 ret <8 x i64> %b575}576 577define void @insertelt_v8i64_0_store(ptr %x) {578; RV32-LABEL: insertelt_v8i64_0_store:579; RV32: # %bb.0:580; RV32-NEXT: li a1, -1581; RV32-NEXT: sw a1, 0(a0)582; RV32-NEXT: sw a1, 4(a0)583; RV32-NEXT: ret584;585; RV64-LABEL: insertelt_v8i64_0_store:586; RV64: # %bb.0:587; RV64-NEXT: li a1, -1588; RV64-NEXT: sd a1, 0(a0)589; RV64-NEXT: ret590;591; VISNI-LABEL: insertelt_v8i64_0_store:592; VISNI: # %bb.0:593; VISNI-NEXT: li a1, -1594; VISNI-NEXT: sd a1, 0(a0)595; VISNI-NEXT: ret596 %a = load <8 x i64>, ptr %x597 %b = insertelement <8 x i64> %a, i64 -1, i32 0598 store <8 x i64> %b, ptr %x599 ret void600}601 602define <8 x i64> @insertelt_v8i64(<8 x i64> %a, i32 %idx) {603; RV32-LABEL: insertelt_v8i64:604; RV32: # %bb.0:605; RV32-NEXT: vsetivli zero, 8, e64, m1, ta, ma606; RV32-NEXT: vmv.v.i v12, -1607; RV32-NEXT: addi a1, a0, 1608; RV32-NEXT: vsetvli zero, a1, e64, m4, tu, ma609; RV32-NEXT: vslideup.vx v8, v12, a0610; RV32-NEXT: ret611;612; RV64-LABEL: insertelt_v8i64:613; RV64: # %bb.0:614; RV64-NEXT: vsetivli zero, 8, e64, m1, ta, ma615; RV64-NEXT: vmv.v.i v12, -1616; RV64-NEXT: slli a0, a0, 32617; RV64-NEXT: srli a0, a0, 32618; RV64-NEXT: addi a1, a0, 1619; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, ma620; RV64-NEXT: vslideup.vx v8, v12, a0621; RV64-NEXT: ret622;623; VISNI-LABEL: insertelt_v8i64:624; VISNI: # %bb.0:625; VISNI-NEXT: vsetivli zero, 8, e64, m1, ta, ma626; VISNI-NEXT: vmv.v.i v12, -1627; VISNI-NEXT: slli a0, a0, 32628; VISNI-NEXT: srli a0, a0, 32629; VISNI-NEXT: addi a1, a0, 1630; VISNI-NEXT: vsetvli zero, a1, e64, m4, tu, ma631; VISNI-NEXT: vslideup.vx v8, v12, a0632; VISNI-NEXT: ret633 %b = insertelement <8 x i64> %a, i64 -1, i32 %idx634 ret <8 x i64> %b635}636 637define void @insertelt_v8i64_store(ptr %x, i32 %idx) {638; RV32-LABEL: insertelt_v8i64_store:639; RV32: # %bb.0:640; RV32-NEXT: andi a1, a1, 7641; RV32-NEXT: slli a1, a1, 3642; RV32-NEXT: add a0, a0, a1643; RV32-NEXT: li a1, -1644; RV32-NEXT: sw a1, 0(a0)645; RV32-NEXT: sw a1, 4(a0)646; RV32-NEXT: ret647;648; RV64-LABEL: insertelt_v8i64_store:649; RV64: # %bb.0:650; RV64-NEXT: andi a1, a1, 7651; RV64-NEXT: slli a1, a1, 3652; RV64-NEXT: add a0, a0, a1653; RV64-NEXT: li a1, -1654; RV64-NEXT: sd a1, 0(a0)655; RV64-NEXT: ret656;657; VISNI-LABEL: insertelt_v8i64_store:658; VISNI: # %bb.0:659; VISNI-NEXT: andi a1, a1, 7660; VISNI-NEXT: slli a1, a1, 3661; VISNI-NEXT: add a0, a0, a1662; VISNI-NEXT: li a1, -1663; VISNI-NEXT: sd a1, 0(a0)664; VISNI-NEXT: ret665 %a = load <8 x i64>, ptr %x666 %b = insertelement <8 x i64> %a, i64 -1, i32 %idx667 store <8 x i64> %b, ptr %x668 ret void669}670 671define <8 x i64> @insertelt_c6_v8i64_0(<8 x i64> %a, ptr %x) {672; CHECK-LABEL: insertelt_c6_v8i64_0:673; CHECK: # %bb.0:674; CHECK-NEXT: li a0, 6675; CHECK-NEXT: vsetivli zero, 8, e64, m1, tu, ma676; CHECK-NEXT: vmv.s.x v8, a0677; CHECK-NEXT: ret678;679; VISNI-LABEL: insertelt_c6_v8i64_0:680; VISNI: # %bb.0:681; VISNI-NEXT: li a0, 6682; VISNI-NEXT: vsetivli zero, 8, e64, m1, tu, ma683; VISNI-NEXT: vmv.s.x v8, a0684; VISNI-NEXT: ret685 %b = insertelement <8 x i64> %a, i64 6, i32 0686 ret <8 x i64> %b687}688 689define void @insertelt_c6_v8i64_0_store(ptr %x) {690; RV32-LABEL: insertelt_c6_v8i64_0_store:691; RV32: # %bb.0:692; RV32-NEXT: li a1, 6693; RV32-NEXT: sw a1, 0(a0)694; RV32-NEXT: sw zero, 4(a0)695; RV32-NEXT: ret696;697; RV64-LABEL: insertelt_c6_v8i64_0_store:698; RV64: # %bb.0:699; RV64-NEXT: li a1, 6700; RV64-NEXT: sd a1, 0(a0)701; RV64-NEXT: ret702;703; VISNI-LABEL: insertelt_c6_v8i64_0_store:704; VISNI: # %bb.0:705; VISNI-NEXT: li a1, 6706; VISNI-NEXT: sd a1, 0(a0)707; VISNI-NEXT: ret708 %a = load <8 x i64>, ptr %x709 %b = insertelement <8 x i64> %a, i64 6, i32 0710 store <8 x i64> %b, ptr %x711 ret void712}713 714define <8 x i64> @insertelt_c6_v8i64(<8 x i64> %a, i32 %idx) {715; RV32-LABEL: insertelt_c6_v8i64:716; RV32: # %bb.0:717; RV32-NEXT: vsetivli zero, 8, e64, m1, ta, ma718; RV32-NEXT: vmv.v.i v12, 6719; RV32-NEXT: addi a1, a0, 1720; RV32-NEXT: vsetvli zero, a1, e64, m4, tu, ma721; RV32-NEXT: vslideup.vx v8, v12, a0722; RV32-NEXT: ret723;724; RV64-LABEL: insertelt_c6_v8i64:725; RV64: # %bb.0:726; RV64-NEXT: vsetivli zero, 8, e64, m1, ta, ma727; RV64-NEXT: vmv.v.i v12, 6728; RV64-NEXT: slli a0, a0, 32729; RV64-NEXT: srli a0, a0, 32730; RV64-NEXT: addi a1, a0, 1731; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, ma732; RV64-NEXT: vslideup.vx v8, v12, a0733; RV64-NEXT: ret734;735; VISNI-LABEL: insertelt_c6_v8i64:736; VISNI: # %bb.0:737; VISNI-NEXT: vsetivli zero, 8, e64, m1, ta, ma738; VISNI-NEXT: vmv.v.i v12, 6739; VISNI-NEXT: slli a0, a0, 32740; VISNI-NEXT: srli a0, a0, 32741; VISNI-NEXT: addi a1, a0, 1742; VISNI-NEXT: vsetvli zero, a1, e64, m4, tu, ma743; VISNI-NEXT: vslideup.vx v8, v12, a0744; VISNI-NEXT: ret745 %b = insertelement <8 x i64> %a, i64 6, i32 %idx746 ret <8 x i64> %b747}748 749define void @insertelt_c6_v8i64_store(ptr %x, i32 %idx) {750; RV32-LABEL: insertelt_c6_v8i64_store:751; RV32: # %bb.0:752; RV32-NEXT: andi a1, a1, 7753; RV32-NEXT: slli a1, a1, 3754; RV32-NEXT: add a0, a0, a1755; RV32-NEXT: li a1, 6756; RV32-NEXT: sw a1, 0(a0)757; RV32-NEXT: sw zero, 4(a0)758; RV32-NEXT: ret759;760; RV64-LABEL: insertelt_c6_v8i64_store:761; RV64: # %bb.0:762; RV64-NEXT: andi a1, a1, 7763; RV64-NEXT: slli a1, a1, 3764; RV64-NEXT: add a0, a0, a1765; RV64-NEXT: li a1, 6766; RV64-NEXT: sd a1, 0(a0)767; RV64-NEXT: ret768;769; VISNI-LABEL: insertelt_c6_v8i64_store:770; VISNI: # %bb.0:771; VISNI-NEXT: andi a1, a1, 7772; VISNI-NEXT: slli a1, a1, 3773; VISNI-NEXT: add a0, a0, a1774; VISNI-NEXT: li a1, 6775; VISNI-NEXT: sd a1, 0(a0)776; VISNI-NEXT: ret777 %a = load <8 x i64>, ptr %x778 %b = insertelement <8 x i64> %a, i64 6, i32 %idx779 store <8 x i64> %b, ptr %x780 ret void781}782 783; Test that using a insertelement at element 0 by a later operation doesn't784; crash the compiler.785define void @insertelt_c6_v8i64_0_add(ptr %x, ptr %y) {786; CHECK-LABEL: insertelt_c6_v8i64_0_add:787; CHECK: # %bb.0:788; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma789; CHECK-NEXT: vle64.v v8, (a0)790; CHECK-NEXT: vle64.v v12, (a1)791; CHECK-NEXT: li a1, 6792; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, ma793; CHECK-NEXT: vmv.s.x v8, a1794; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma795; CHECK-NEXT: vadd.vv v8, v8, v12796; CHECK-NEXT: vse64.v v8, (a0)797; CHECK-NEXT: ret798;799; VISNI-LABEL: insertelt_c6_v8i64_0_add:800; VISNI: # %bb.0:801; VISNI-NEXT: vsetivli zero, 8, e64, m4, ta, ma802; VISNI-NEXT: vle64.v v8, (a0)803; VISNI-NEXT: vle64.v v12, (a1)804; VISNI-NEXT: li a1, 6805; VISNI-NEXT: vsetvli zero, zero, e64, m4, tu, ma806; VISNI-NEXT: vmv.s.x v8, a1807; VISNI-NEXT: vsetvli zero, zero, e64, m4, ta, ma808; VISNI-NEXT: vadd.vv v8, v8, v12809; VISNI-NEXT: vse64.v v8, (a0)810; VISNI-NEXT: ret811 %a = load <8 x i64>, ptr %x812 %b = insertelement <8 x i64> %a, i64 6, i32 0813 %c = load <8 x i64>, ptr %y814 %d = add <8 x i64> %b, %c815 store <8 x i64> %d, ptr %x816 ret void817}818 819; The next batch of tests cover inserts into high LMUL vectors when the820; exact VLEM is known. FIXME: These can directly access the sub-registers821 822define <16 x i32> @insertelt_c0_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_range(2,2) {823; CHECK-LABEL: insertelt_c0_v16xi32_exact:824; CHECK: # %bb.0:825; CHECK-NEXT: vsetivli zero, 16, e32, m1, tu, ma826; CHECK-NEXT: vmv.s.x v8, a0827; CHECK-NEXT: ret828;829; VISNI-LABEL: insertelt_c0_v16xi32_exact:830; VISNI: # %bb.0:831; VISNI-NEXT: vsetivli zero, 16, e32, m1, tu, ma832; VISNI-NEXT: vmv.s.x v8, a0833; VISNI-NEXT: ret834 %v = insertelement <16 x i32> %vin, i32 %a, i32 0835 ret <16 x i32> %v836}837 838define <16 x i32> @insertelt_c1_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_range(2,2) {839; CHECK-LABEL: insertelt_c1_v16xi32_exact:840; CHECK: # %bb.0:841; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma842; CHECK-NEXT: vmv.s.x v12, a0843; CHECK-NEXT: vslideup.vi v8, v12, 1844; CHECK-NEXT: ret845;846; VISNI-LABEL: insertelt_c1_v16xi32_exact:847; VISNI: # %bb.0:848; VISNI-NEXT: vsetivli zero, 16, e32, m1, ta, ma849; VISNI-NEXT: ri.vinsert.v.x v8, a0, 1850; VISNI-NEXT: ret851 %v = insertelement <16 x i32> %vin, i32 %a, i32 1852 ret <16 x i32> %v853}854 855define <16 x i32> @insertelt_c2_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_range(2,2) {856; CHECK-LABEL: insertelt_c2_v16xi32_exact:857; CHECK: # %bb.0:858; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma859; CHECK-NEXT: vmv.s.x v12, a0860; CHECK-NEXT: vslideup.vi v8, v12, 2861; CHECK-NEXT: ret862;863; VISNI-LABEL: insertelt_c2_v16xi32_exact:864; VISNI: # %bb.0:865; VISNI-NEXT: vsetivli zero, 16, e32, m1, ta, ma866; VISNI-NEXT: ri.vinsert.v.x v8, a0, 2867; VISNI-NEXT: ret868 %v = insertelement <16 x i32> %vin, i32 %a, i32 2869 ret <16 x i32> %v870}871 872define <16 x i32> @insertelt_c3_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_range(2,2) {873; CHECK-LABEL: insertelt_c3_v16xi32_exact:874; CHECK: # %bb.0:875; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma876; CHECK-NEXT: vmv.s.x v12, a0877; CHECK-NEXT: vslideup.vi v8, v12, 3878; CHECK-NEXT: ret879;880; VISNI-LABEL: insertelt_c3_v16xi32_exact:881; VISNI: # %bb.0:882; VISNI-NEXT: vsetivli zero, 16, e32, m1, ta, ma883; VISNI-NEXT: ri.vinsert.v.x v8, a0, 3884; VISNI-NEXT: ret885 %v = insertelement <16 x i32> %vin, i32 %a, i32 3886 ret <16 x i32> %v887}888 889define <16 x i32> @insertelt_c12_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_range(2,2) {890; CHECK-LABEL: insertelt_c12_v16xi32_exact:891; CHECK: # %bb.0:892; CHECK-NEXT: vsetivli zero, 16, e32, m1, tu, ma893; CHECK-NEXT: vmv.s.x v11, a0894; CHECK-NEXT: ret895;896; VISNI-LABEL: insertelt_c12_v16xi32_exact:897; VISNI: # %bb.0:898; VISNI-NEXT: vsetivli zero, 16, e32, m1, tu, ma899; VISNI-NEXT: vmv.s.x v11, a0900; VISNI-NEXT: ret901 %v = insertelement <16 x i32> %vin, i32 %a, i32 12902 ret <16 x i32> %v903}904 905define <16 x i32> @insertelt_c13_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_range(2,2) {906; CHECK-LABEL: insertelt_c13_v16xi32_exact:907; CHECK: # %bb.0:908; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma909; CHECK-NEXT: vmv.s.x v12, a0910; CHECK-NEXT: vslideup.vi v11, v12, 1911; CHECK-NEXT: ret912;913; VISNI-LABEL: insertelt_c13_v16xi32_exact:914; VISNI: # %bb.0:915; VISNI-NEXT: vsetivli zero, 16, e32, m1, ta, ma916; VISNI-NEXT: ri.vinsert.v.x v11, a0, 1917; VISNI-NEXT: ret918 %v = insertelement <16 x i32> %vin, i32 %a, i32 13919 ret <16 x i32> %v920}921 922define <16 x i32> @insertelt_c14_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_range(2,2) {923; CHECK-LABEL: insertelt_c14_v16xi32_exact:924; CHECK: # %bb.0:925; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma926; CHECK-NEXT: vmv.s.x v12, a0927; CHECK-NEXT: vslideup.vi v11, v12, 2928; CHECK-NEXT: ret929;930; VISNI-LABEL: insertelt_c14_v16xi32_exact:931; VISNI: # %bb.0:932; VISNI-NEXT: vsetivli zero, 16, e32, m1, ta, ma933; VISNI-NEXT: ri.vinsert.v.x v11, a0, 2934; VISNI-NEXT: ret935 %v = insertelement <16 x i32> %vin, i32 %a, i32 14936 ret <16 x i32> %v937}938 939define <16 x i32> @insertelt_c15_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_range(2,2) {940; CHECK-LABEL: insertelt_c15_v16xi32_exact:941; CHECK: # %bb.0:942; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma943; CHECK-NEXT: vmv.s.x v12, a0944; CHECK-NEXT: vslideup.vi v11, v12, 3945; CHECK-NEXT: ret946;947; VISNI-LABEL: insertelt_c15_v16xi32_exact:948; VISNI: # %bb.0:949; VISNI-NEXT: vsetivli zero, 16, e32, m1, ta, ma950; VISNI-NEXT: ri.vinsert.v.x v11, a0, 3951; VISNI-NEXT: ret952 %v = insertelement <16 x i32> %vin, i32 %a, i32 15953 ret <16 x i32> %v954}955 956define <8 x i64> @insertelt_c4_v8xi64_exact(<8 x i64> %vin, i64 %a) vscale_range(2,2) {957; RV32-LABEL: insertelt_c4_v8xi64_exact:958; RV32: # %bb.0:959; RV32-NEXT: vsetivli zero, 2, e32, m1, tu, ma960; RV32-NEXT: vslide1down.vx v10, v10, a0961; RV32-NEXT: vslide1down.vx v10, v10, a1962; RV32-NEXT: ret963;964; RV64-LABEL: insertelt_c4_v8xi64_exact:965; RV64: # %bb.0:966; RV64-NEXT: vsetivli zero, 8, e64, m1, tu, ma967; RV64-NEXT: vmv.s.x v10, a0968; RV64-NEXT: ret969;970; VISNI-LABEL: insertelt_c4_v8xi64_exact:971; VISNI: # %bb.0:972; VISNI-NEXT: vsetivli zero, 8, e64, m1, tu, ma973; VISNI-NEXT: vmv.s.x v10, a0974; VISNI-NEXT: ret975 %v = insertelement <8 x i64> %vin, i64 %a, i32 4976 ret <8 x i64> %v977}978 979define <8 x i64> @insertelt_c5_v8xi64_exact(<8 x i64> %vin, i64 %a) vscale_range(2,2) {980; RV32-LABEL: insertelt_c5_v8xi64_exact:981; RV32: # %bb.0:982; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, ma983; RV32-NEXT: vslide1down.vx v12, v8, a0984; RV32-NEXT: vslide1down.vx v12, v12, a1985; RV32-NEXT: vsetivli zero, 2, e64, m1, tu, ma986; RV32-NEXT: vslideup.vi v10, v12, 1987; RV32-NEXT: ret988;989; RV64-LABEL: insertelt_c5_v8xi64_exact:990; RV64: # %bb.0:991; RV64-NEXT: vsetivli zero, 2, e64, m1, tu, ma992; RV64-NEXT: vmv.s.x v12, a0993; RV64-NEXT: vslideup.vi v10, v12, 1994; RV64-NEXT: ret995;996; VISNI-LABEL: insertelt_c5_v8xi64_exact:997; VISNI: # %bb.0:998; VISNI-NEXT: vsetivli zero, 8, e64, m1, ta, ma999; VISNI-NEXT: ri.vinsert.v.x v10, a0, 11000; VISNI-NEXT: ret1001 %v = insertelement <8 x i64> %vin, i64 %a, i32 51002 ret <8 x i64> %v1003}1004 1005define <4 x bfloat> @insertelt_v4bf16_0(<4 x bfloat> %a, bfloat %y) {1006; CHECK-LABEL: insertelt_v4bf16_0:1007; CHECK: # %bb.0:1008; CHECK-NEXT: fmv.x.h a0, fa01009; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma1010; CHECK-NEXT: vmv.s.x v8, a01011; CHECK-NEXT: ret1012;1013; VISNI-LABEL: insertelt_v4bf16_0:1014; VISNI: # %bb.0:1015; VISNI-NEXT: fmv.x.h a0, fa01016; VISNI-NEXT: vsetivli zero, 4, e16, m1, tu, ma1017; VISNI-NEXT: vmv.s.x v8, a01018; VISNI-NEXT: ret1019 %b = insertelement <4 x bfloat> %a, bfloat %y, i32 01020 ret <4 x bfloat> %b1021}1022 1023define <4 x bfloat> @insertelt_v4bf16_3(<4 x bfloat> %a, bfloat %y) {1024; CHECK-LABEL: insertelt_v4bf16_3:1025; CHECK: # %bb.0:1026; CHECK-NEXT: fmv.x.h a0, fa01027; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1028; CHECK-NEXT: vmv.s.x v9, a01029; CHECK-NEXT: vslideup.vi v8, v9, 31030; CHECK-NEXT: ret1031;1032; VISNI-LABEL: insertelt_v4bf16_3:1033; VISNI: # %bb.0:1034; VISNI-NEXT: fmv.x.h a0, fa01035; VISNI-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1036; VISNI-NEXT: ri.vinsert.v.x v8, a0, 31037; VISNI-NEXT: ret1038 %b = insertelement <4 x bfloat> %a, bfloat %y, i32 31039 ret <4 x bfloat> %b1040}1041 1042define <4 x bfloat> @insertelt_v4bf16_idx(<4 x bfloat> %a, bfloat %y, i32 zeroext %idx) {1043; CHECK-LABEL: insertelt_v4bf16_idx:1044; CHECK: # %bb.0:1045; CHECK-NEXT: addi a1, a0, 11046; CHECK-NEXT: fmv.x.h a2, fa01047; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma1048; CHECK-NEXT: vmv.s.x v9, a21049; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, ma1050; CHECK-NEXT: vslideup.vx v8, v9, a01051; CHECK-NEXT: ret1052;1053; VISNI-LABEL: insertelt_v4bf16_idx:1054; VISNI: # %bb.0:1055; VISNI-NEXT: addi a1, a0, 11056; VISNI-NEXT: fmv.x.h a2, fa01057; VISNI-NEXT: vsetivli zero, 4, e16, m1, ta, ma1058; VISNI-NEXT: vmv.s.x v9, a21059; VISNI-NEXT: vsetvli zero, a1, e16, mf2, tu, ma1060; VISNI-NEXT: vslideup.vx v8, v9, a01061; VISNI-NEXT: ret1062 %b = insertelement <4 x bfloat> %a, bfloat %y, i32 %idx1063 ret <4 x bfloat> %b1064}1065 1066define <4 x half> @insertelt_v4f16_0(<4 x half> %a, half %y) {1067; ZVFH-LABEL: insertelt_v4f16_0:1068; ZVFH: # %bb.0:1069; ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma1070; ZVFH-NEXT: vfmv.s.f v8, fa01071; ZVFH-NEXT: ret1072;1073; ZVFHMIN-LABEL: insertelt_v4f16_0:1074; ZVFHMIN: # %bb.0:1075; ZVFHMIN-NEXT: fmv.x.h a0, fa01076; ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma1077; ZVFHMIN-NEXT: vmv.s.x v8, a01078; ZVFHMIN-NEXT: ret1079;1080; VISNI-LABEL: insertelt_v4f16_0:1081; VISNI: # %bb.0:1082; VISNI-NEXT: vsetivli zero, 4, e16, m1, tu, ma1083; VISNI-NEXT: vfmv.s.f v8, fa01084; VISNI-NEXT: ret1085 %b = insertelement <4 x half> %a, half %y, i32 01086 ret <4 x half> %b1087}1088 1089define <4 x half> @insertelt_v4f16_3(<4 x half> %a, half %y) {1090; ZVFH-LABEL: insertelt_v4f16_3:1091; ZVFH: # %bb.0:1092; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1093; ZVFH-NEXT: vfmv.s.f v9, fa01094; ZVFH-NEXT: vslideup.vi v8, v9, 31095; ZVFH-NEXT: ret1096;1097; ZVFHMIN-LABEL: insertelt_v4f16_3:1098; ZVFHMIN: # %bb.0:1099; ZVFHMIN-NEXT: fmv.x.h a0, fa01100; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1101; ZVFHMIN-NEXT: vmv.s.x v9, a01102; ZVFHMIN-NEXT: vslideup.vi v8, v9, 31103; ZVFHMIN-NEXT: ret1104;1105; VISNI-LABEL: insertelt_v4f16_3:1106; VISNI: # %bb.0:1107; VISNI-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1108; VISNI-NEXT: vfmv.s.f v9, fa01109; VISNI-NEXT: vslideup.vi v8, v9, 31110; VISNI-NEXT: ret1111 %b = insertelement <4 x half> %a, half %y, i32 31112 ret <4 x half> %b1113}1114 1115define <4 x half> @insertelt_v4f16_idx(<4 x half> %a, half %y, i32 zeroext %idx) {1116; ZVFH-LABEL: insertelt_v4f16_idx:1117; ZVFH: # %bb.0:1118; ZVFH-NEXT: addi a1, a0, 11119; ZVFH-NEXT: vsetivli zero, 4, e16, m1, ta, ma1120; ZVFH-NEXT: vfmv.s.f v9, fa01121; ZVFH-NEXT: vsetvli zero, a1, e16, mf2, tu, ma1122; ZVFH-NEXT: vslideup.vx v8, v9, a01123; ZVFH-NEXT: ret1124;1125; ZVFHMIN-LABEL: insertelt_v4f16_idx:1126; ZVFHMIN: # %bb.0:1127; ZVFHMIN-NEXT: addi a1, a0, 11128; ZVFHMIN-NEXT: fmv.x.h a2, fa01129; ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, ta, ma1130; ZVFHMIN-NEXT: vmv.s.x v9, a21131; ZVFHMIN-NEXT: vsetvli zero, a1, e16, mf2, tu, ma1132; ZVFHMIN-NEXT: vslideup.vx v8, v9, a01133; ZVFHMIN-NEXT: ret1134;1135; VISNI-LABEL: insertelt_v4f16_idx:1136; VISNI: # %bb.0:1137; VISNI-NEXT: addi a1, a0, 11138; VISNI-NEXT: vsetivli zero, 4, e16, m1, ta, ma1139; VISNI-NEXT: vfmv.s.f v9, fa01140; VISNI-NEXT: vsetvli zero, a1, e16, mf2, tu, ma1141; VISNI-NEXT: vslideup.vx v8, v9, a01142; VISNI-NEXT: ret1143 %b = insertelement <4 x half> %a, half %y, i32 %idx1144 ret <4 x half> %b1145}1146 1147define <2 x i8> @pr169017(<4 x i16> %vecinit, <2 x i8> %dst_vec) {1148; CHECK-LABEL: pr169017:1149; CHECK: # %bb.0: # %entry1150; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma1151; CHECK-NEXT: vmv.x.s a0, v81152; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, ma1153; CHECK-NEXT: vmv.s.x v9, a01154; CHECK-NEXT: vmv1r.v v8, v91155; CHECK-NEXT: ret1156;1157; VISNI-LABEL: pr169017:1158; VISNI: # %bb.0: # %entry1159; VISNI-NEXT: vsetivli zero, 1, e64, m1, ta, ma1160; VISNI-NEXT: vmv.x.s a0, v81161; VISNI-NEXT: vsetvli zero, zero, e8, mf8, tu, ma1162; VISNI-NEXT: vmv.s.x v9, a01163; VISNI-NEXT: vmv1r.v v8, v91164; VISNI-NEXT: ret1165entry:1166 %cast = bitcast <4 x i16> %vecinit to i641167 %trunc = trunc i64 %cast to i81168 %2 = insertelement <2 x i8> %dst_vec, i8 %trunc, i64 01169 ret <2 x i8> %21170}1171 1172;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1173; ZVFHMINRV32: {{.*}}1174; ZVFHMINRV64: {{.*}}1175