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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-ONLY3; RUN: llc -mtriple=riscv32 -mattr=+v,+zba,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32VB4; RUN: llc -mtriple=riscv32 -mattr=+v,+zba,+zbb,+zbkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32VB-PACK5; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V,RV64V-ONLY6; RUN: llc -mtriple=riscv64 -mattr=+v,+rva22u64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V,RVA22U647; RUN: llc -mtriple=riscv64 -mattr=+v,+rva22u64,+zbkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V,RVA22U64-PACK8; RUN: llc -mtriple=riscv64 -mattr=+zve32x,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVE329 10define void @buildvec_vid_v16i8(ptr %x) {11; CHECK-LABEL: buildvec_vid_v16i8:12; CHECK: # %bb.0:13; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma14; CHECK-NEXT: vid.v v815; CHECK-NEXT: vse8.v v8, (a0)16; CHECK-NEXT: ret17 store <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, ptr %x18 ret void19}20 21define void @buildvec_vid_undefelts_v16i8(ptr %x) {22; CHECK-LABEL: buildvec_vid_undefelts_v16i8:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma25; CHECK-NEXT: vid.v v826; CHECK-NEXT: vse8.v v8, (a0)27; CHECK-NEXT: ret28 store <16 x i8> <i8 0, i8 1, i8 2, i8 poison, i8 4, i8 poison, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, ptr %x29 ret void30}31 32; TODO: Could do VID then insertelement on missing elements33define void @buildvec_notquite_vid_v16i8(ptr %x) {34; CHECK-LABEL: buildvec_notquite_vid_v16i8:35; CHECK: # %bb.0:36; CHECK-NEXT: lui a1, %hi(.LCPI2_0)37; CHECK-NEXT: addi a1, a1, %lo(.LCPI2_0)38; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma39; CHECK-NEXT: vle8.v v8, (a1)40; CHECK-NEXT: vse8.v v8, (a0)41; CHECK-NEXT: ret42 store <16 x i8> <i8 0, i8 1, i8 3, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, ptr %x43 ret void44}45 46define void @buildvec_vid_plus_imm_v16i8(ptr %x) {47; CHECK-LABEL: buildvec_vid_plus_imm_v16i8:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma50; CHECK-NEXT: vid.v v851; CHECK-NEXT: vadd.vi v8, v8, 252; CHECK-NEXT: vse8.v v8, (a0)53; CHECK-NEXT: ret54 store <16 x i8> <i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17>, ptr %x55 ret void56}57 58define void @buildvec_vid_plus_nonimm_v16i8(ptr %x) {59; CHECK-LABEL: buildvec_vid_plus_nonimm_v16i8:60; CHECK: # %bb.0:61; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma62; CHECK-NEXT: vid.v v863; CHECK-NEXT: li a1, 10064; CHECK-NEXT: vadd.vx v8, v8, a165; CHECK-NEXT: vse8.v v8, (a0)66; CHECK-NEXT: ret67 store <16 x i8> <i8 100, i8 101, i8 102, i8 103, i8 104, i8 105, i8 106, i8 107, i8 108, i8 109, i8 110, i8 111, i8 112, i8 113, i8 114, i8 115>, ptr %x68 ret void69}70 71define void @buildvec_vid_mpy_imm_v16i8(ptr %x) {72; CHECK-LABEL: buildvec_vid_mpy_imm_v16i8:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma75; CHECK-NEXT: vid.v v876; CHECK-NEXT: li a1, 377; CHECK-NEXT: vmul.vx v8, v8, a178; CHECK-NEXT: vse8.v v8, (a0)79; CHECK-NEXT: ret80 store <16 x i8> <i8 0, i8 3, i8 6, i8 9, i8 12, i8 15, i8 18, i8 21, i8 24, i8 27, i8 30, i8 33, i8 36, i8 39, i8 42, i8 45>, ptr %x81 ret void82}83 84define <4 x i8> @buildvec_vid_step2_add0_v4i8() {85; CHECK-LABEL: buildvec_vid_step2_add0_v4i8:86; CHECK: # %bb.0:87; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma88; CHECK-NEXT: vid.v v889; CHECK-NEXT: vadd.vv v8, v8, v890; CHECK-NEXT: ret91 ret <4 x i8> <i8 0, i8 2, i8 4, i8 6>92}93 94define <4 x i8> @buildvec_vid_step2_add0_v4i8_undef0() {95; CHECK-LABEL: buildvec_vid_step2_add0_v4i8_undef0:96; CHECK: # %bb.0:97; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma98; CHECK-NEXT: vid.v v899; CHECK-NEXT: vadd.vv v8, v8, v8100; CHECK-NEXT: ret101 ret <4 x i8> <i8 poison, i8 2, i8 4, i8 6>102}103 104define <4 x i8> @buildvec_vid_step2_add0_v4i8_undef1() {105; CHECK-LABEL: buildvec_vid_step2_add0_v4i8_undef1:106; CHECK: # %bb.0:107; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma108; CHECK-NEXT: vid.v v8109; CHECK-NEXT: vadd.vv v8, v8, v8110; CHECK-NEXT: ret111 ret <4 x i8> <i8 poison, i8 poison, i8 4, i8 6>112}113 114define <4 x i8> @buildvec_vid_step2_add0_v4i8_undef2() {115; CHECK-LABEL: buildvec_vid_step2_add0_v4i8_undef2:116; CHECK: # %bb.0:117; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma118; CHECK-NEXT: vid.v v8119; CHECK-NEXT: vadd.vv v8, v8, v8120; CHECK-NEXT: ret121 ret <4 x i8> <i8 0, i8 poison, i8 poison, i8 6>122}123 124define <4 x i8> @buildvec_vid_step2_add1_v4i8() {125; CHECK-LABEL: buildvec_vid_step2_add1_v4i8:126; CHECK: # %bb.0:127; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma128; CHECK-NEXT: vid.v v8129; CHECK-NEXT: vadd.vv v8, v8, v8130; CHECK-NEXT: vadd.vi v8, v8, 1131; CHECK-NEXT: ret132 ret <4 x i8> <i8 1, i8 3, i8 5, i8 7>133}134 135define <4 x i8> @buildvec_vid_step2_add1_v4i8_undef0() {136; CHECK-LABEL: buildvec_vid_step2_add1_v4i8_undef0:137; CHECK: # %bb.0:138; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma139; CHECK-NEXT: vid.v v8140; CHECK-NEXT: vadd.vv v8, v8, v8141; CHECK-NEXT: vadd.vi v8, v8, 1142; CHECK-NEXT: ret143 ret <4 x i8> <i8 poison, i8 3, i8 5, i8 7>144}145 146define <4 x i8> @buildvec_vid_step2_add1_v4i8_undef1() {147; CHECK-LABEL: buildvec_vid_step2_add1_v4i8_undef1:148; CHECK: # %bb.0:149; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma150; CHECK-NEXT: vid.v v8151; CHECK-NEXT: vadd.vv v8, v8, v8152; CHECK-NEXT: vadd.vi v8, v8, 1153; CHECK-NEXT: ret154 ret <4 x i8> <i8 poison, i8 poison, i8 5, i8 7>155}156 157define <4 x i8> @buildvec_vid_step2_add1_v4i8_undef2() {158; CHECK-LABEL: buildvec_vid_step2_add1_v4i8_undef2:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma161; CHECK-NEXT: vid.v v8162; CHECK-NEXT: vadd.vv v8, v8, v8163; CHECK-NEXT: vadd.vi v8, v8, 1164; CHECK-NEXT: ret165 ret <4 x i8> <i8 1, i8 poison, i8 poison, i8 7>166}167 168define <4 x i8> @buildvec_vid_stepn1_add0_v4i8() {169; CHECK-LABEL: buildvec_vid_stepn1_add0_v4i8:170; CHECK: # %bb.0:171; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma172; CHECK-NEXT: vid.v v8173; CHECK-NEXT: vrsub.vi v8, v8, 0174; CHECK-NEXT: ret175 ret <4 x i8> <i8 0, i8 -1, i8 -2, i8 -3>176}177 178define <4 x i8> @buildvec_vid_stepn1_add0_v4i8_undef0() {179; CHECK-LABEL: buildvec_vid_stepn1_add0_v4i8_undef0:180; CHECK: # %bb.0:181; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma182; CHECK-NEXT: vid.v v8183; CHECK-NEXT: vrsub.vi v8, v8, 0184; CHECK-NEXT: ret185 ret <4 x i8> <i8 poison, i8 -1, i8 -2, i8 -3>186}187 188define <4 x i8> @buildvec_vid_stepn1_add0_v4i8_undef1() {189; CHECK-LABEL: buildvec_vid_stepn1_add0_v4i8_undef1:190; CHECK: # %bb.0:191; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma192; CHECK-NEXT: vid.v v8193; CHECK-NEXT: vrsub.vi v8, v8, 0194; CHECK-NEXT: ret195 ret <4 x i8> <i8 poison, i8 poison, i8 -2, i8 -3>196}197 198define <4 x i8> @buildvec_vid_stepn1_add0_v4i8_undef2() {199; CHECK-LABEL: buildvec_vid_stepn1_add0_v4i8_undef2:200; CHECK: # %bb.0:201; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma202; CHECK-NEXT: vid.v v8203; CHECK-NEXT: vrsub.vi v8, v8, 0204; CHECK-NEXT: ret205 ret <4 x i8> <i8 0, i8 poison, i8 poison, i8 -3>206}207 208define <4 x i8> @buildvec_vid_stepn2_add0_v4i8() {209; CHECK-LABEL: buildvec_vid_stepn2_add0_v4i8:210; CHECK: # %bb.0:211; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma212; CHECK-NEXT: vid.v v8213; CHECK-NEXT: vadd.vv v8, v8, v8214; CHECK-NEXT: vrsub.vi v8, v8, 0215; CHECK-NEXT: ret216 ret <4 x i8> <i8 0, i8 -2, i8 -4, i8 -6>217}218 219define <4 x i8> @buildvec_vid_stepn2_add0_v4i8_undef0() {220; CHECK-LABEL: buildvec_vid_stepn2_add0_v4i8_undef0:221; CHECK: # %bb.0:222; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma223; CHECK-NEXT: vid.v v8224; CHECK-NEXT: vadd.vv v8, v8, v8225; CHECK-NEXT: vrsub.vi v8, v8, 0226; CHECK-NEXT: ret227 ret <4 x i8> <i8 poison, i8 -2, i8 -4, i8 -6>228}229 230define <4 x i8> @buildvec_vid_stepn2_add0_v4i8_undef1() {231; CHECK-LABEL: buildvec_vid_stepn2_add0_v4i8_undef1:232; CHECK: # %bb.0:233; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma234; CHECK-NEXT: vid.v v8235; CHECK-NEXT: vadd.vv v8, v8, v8236; CHECK-NEXT: vrsub.vi v8, v8, 0237; CHECK-NEXT: ret238 ret <4 x i8> <i8 poison, i8 poison, i8 -4, i8 -6>239}240 241define <4 x i8> @buildvec_vid_stepn2_add0_v4i8_undef2() {242; CHECK-LABEL: buildvec_vid_stepn2_add0_v4i8_undef2:243; CHECK: # %bb.0:244; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma245; CHECK-NEXT: vmv.v.i v8, -6246; CHECK-NEXT: ret247 ret <4 x i8> <i8 poison, i8 poison, i8 poison, i8 -6>248}249 250define <4 x i8> @buildvec_vid_stepn2_add3_v4i8() {251; CHECK-LABEL: buildvec_vid_stepn2_add3_v4i8:252; CHECK: # %bb.0:253; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma254; CHECK-NEXT: vid.v v8255; CHECK-NEXT: vadd.vv v8, v8, v8256; CHECK-NEXT: vrsub.vi v8, v8, 3257; CHECK-NEXT: ret258 ret <4 x i8> <i8 3, i8 1, i8 -1, i8 -3>259}260 261define <4 x i8> @buildvec_vid_stepn3_add3_v4i8() {262; CHECK-LABEL: buildvec_vid_stepn3_add3_v4i8:263; CHECK: # %bb.0:264; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma265; CHECK-NEXT: vmv.v.i v9, 3266; CHECK-NEXT: vid.v v8267; CHECK-NEXT: li a0, -3268; CHECK-NEXT: vmadd.vx v8, a0, v9269; CHECK-NEXT: ret270 ret <4 x i8> <i8 3, i8 0, i8 -3, i8 -6>271}272 273define void @buildvec_vid_stepn3_addn3_v4i32(ptr %z0, ptr %z1, ptr %z2, ptr %z3) {274; CHECK-LABEL: buildvec_vid_stepn3_addn3_v4i32:275; CHECK: # %bb.0:276; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma277; CHECK-NEXT: vmv.v.i v8, -3278; CHECK-NEXT: vid.v v9279; CHECK-NEXT: li a4, -3280; CHECK-NEXT: vmadd.vx v9, a4, v8281; CHECK-NEXT: vse32.v v9, (a0)282; CHECK-NEXT: vse32.v v9, (a1)283; CHECK-NEXT: vse32.v v9, (a2)284; CHECK-NEXT: vse32.v v9, (a3)285; CHECK-NEXT: ret286 store <4 x i32> <i32 -3, i32 -6, i32 -9, i32 -12>, ptr %z0287 store <4 x i32> <i32 poison, i32 -6, i32 -9, i32 -12>, ptr %z1288 store <4 x i32> <i32 poison, i32 poison, i32 -9, i32 -12>, ptr %z2289 store <4 x i32> <i32 -3, i32 poison, i32 poison, i32 -12>, ptr %z3290 ret void291}292 293define <4 x i64> @buildvec_vid_step1_add0_v4i64() {294; RV32-LABEL: buildvec_vid_step1_add0_v4i64:295; RV32: # %bb.0:296; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma297; RV32-NEXT: vid.v v8298; RV32-NEXT: ret299;300; RV64V-LABEL: buildvec_vid_step1_add0_v4i64:301; RV64V: # %bb.0:302; RV64V-NEXT: vsetivli zero, 4, e64, m2, ta, ma303; RV64V-NEXT: vid.v v8304; RV64V-NEXT: ret305;306; RV64ZVE32-LABEL: buildvec_vid_step1_add0_v4i64:307; RV64ZVE32: # %bb.0:308; RV64ZVE32-NEXT: li a1, 3309; RV64ZVE32-NEXT: li a2, 2310; RV64ZVE32-NEXT: li a3, 1311; RV64ZVE32-NEXT: sd zero, 0(a0)312; RV64ZVE32-NEXT: sd a3, 8(a0)313; RV64ZVE32-NEXT: sd a2, 16(a0)314; RV64ZVE32-NEXT: sd a1, 24(a0)315; RV64ZVE32-NEXT: ret316 ret <4 x i64> <i64 0, i64 1, i64 2, i64 3>317}318 319define <4 x i64> @buildvec_vid_step2_add0_v4i64() {320; RV32-LABEL: buildvec_vid_step2_add0_v4i64:321; RV32: # %bb.0:322; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma323; RV32-NEXT: vid.v v8324; RV32-NEXT: vadd.vv v8, v8, v8325; RV32-NEXT: ret326;327; RV64V-LABEL: buildvec_vid_step2_add0_v4i64:328; RV64V: # %bb.0:329; RV64V-NEXT: vsetivli zero, 4, e64, m2, ta, ma330; RV64V-NEXT: vid.v v8331; RV64V-NEXT: vadd.vv v8, v8, v8332; RV64V-NEXT: ret333;334; RV64ZVE32-LABEL: buildvec_vid_step2_add0_v4i64:335; RV64ZVE32: # %bb.0:336; RV64ZVE32-NEXT: li a1, 6337; RV64ZVE32-NEXT: li a2, 4338; RV64ZVE32-NEXT: li a3, 2339; RV64ZVE32-NEXT: sd zero, 0(a0)340; RV64ZVE32-NEXT: sd a3, 8(a0)341; RV64ZVE32-NEXT: sd a2, 16(a0)342; RV64ZVE32-NEXT: sd a1, 24(a0)343; RV64ZVE32-NEXT: ret344 ret <4 x i64> <i64 0, i64 2, i64 4, i64 6>345}346 347define <4 x i8> @buildvec_no_vid_v4i8_0() {348; CHECK-LABEL: buildvec_no_vid_v4i8_0:349; CHECK: # %bb.0:350; CHECK-NEXT: lui a0, 28768351; CHECK-NEXT: addi a0, a0, 769352; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma353; CHECK-NEXT: vmv.s.x v8, a0354; CHECK-NEXT: ret355 ret <4 x i8> <i8 1, i8 3, i8 6, i8 7>356}357 358define <4 x i8> @buildvec_no_vid_v4i8_1() {359; CHECK-LABEL: buildvec_no_vid_v4i8_1:360; CHECK: # %bb.0:361; CHECK-NEXT: lui a0, 28752362; CHECK-NEXT: addi a0, a0, 512363; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma364; CHECK-NEXT: vmv.s.x v8, a0365; CHECK-NEXT: ret366 ret <4 x i8> <i8 poison, i8 2, i8 5, i8 7>367}368 369define <4 x i8> @buildvec_no_vid_v4i8_2() {370; CHECK-LABEL: buildvec_no_vid_v4i8_2:371; CHECK: # %bb.0:372; CHECK-NEXT: lui a0, 32768373; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma374; CHECK-NEXT: vmv.s.x v8, a0375; CHECK-NEXT: ret376 ret <4 x i8> <i8 0, i8 poison, i8 poison, i8 8>377}378 379define <4 x i8> @buildvec_no_vid_v4i8_3() {380; CHECK-LABEL: buildvec_no_vid_v4i8_3:381; CHECK: # %bb.0:382; CHECK-NEXT: lui a0, 28672383; CHECK-NEXT: addi a0, a0, 255384; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma385; CHECK-NEXT: vmv.s.x v8, a0386; CHECK-NEXT: ret387 ret <4 x i8> <i8 -1, i8 poison, i8 poison, i8 7>388}389 390define <4 x i8> @buildvec_no_vid_v4i8_4() {391; CHECK-LABEL: buildvec_no_vid_v4i8_4:392; CHECK: # %bb.0:393; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma394; CHECK-NEXT: vmv.v.i v8, -2395; CHECK-NEXT: ret396 ret <4 x i8> <i8 -2, i8 poison, i8 poison, i8 poison>397}398 399define <4 x i8> @buildvec_no_vid_v4i8_5() {400; CHECK-LABEL: buildvec_no_vid_v4i8_5:401; CHECK: # %bb.0:402; CHECK-NEXT: lui a0, 1032144403; CHECK-NEXT: addi a0, a0, -257404; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma405; CHECK-NEXT: vmv.s.x v8, a0406; CHECK-NEXT: ret407 ret <4 x i8> <i8 -1, i8 -2, i8 -4, i8 -5>408}409 410define void @buildvec_dominant0_v8i16(ptr %x) {411; CHECK-LABEL: buildvec_dominant0_v8i16:412; CHECK: # %bb.0:413; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma414; CHECK-NEXT: vmv.s.x v8, zero415; CHECK-NEXT: vmv.v.i v9, 8416; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma417; CHECK-NEXT: vslideup.vi v9, v8, 3418; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma419; CHECK-NEXT: vse16.v v9, (a0)420; CHECK-NEXT: ret421 store <8 x i16> <i16 8, i16 8, i16 poison, i16 0, i16 8, i16 poison, i16 8, i16 8>, ptr %x422 ret void423}424 425define void @buildvec_dominant0_v8i16_with_end_element(ptr %x) {426; CHECK-LABEL: buildvec_dominant0_v8i16_with_end_element:427; CHECK: # %bb.0:428; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma429; CHECK-NEXT: vmv.v.i v8, 8430; CHECK-NEXT: li a1, 3431; CHECK-NEXT: vslide1down.vx v8, v8, a1432; CHECK-NEXT: vse16.v v8, (a0)433; CHECK-NEXT: ret434 store <8 x i16> <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 3>, ptr %x435 ret void436}437 438define void @buildvec_dominant0_v8i16_with_tail(ptr %x) {439; CHECK-LABEL: buildvec_dominant0_v8i16_with_tail:440; CHECK: # %bb.0:441; CHECK-NEXT: lui a1, %hi(.LCPI35_0)442; CHECK-NEXT: addi a1, a1, %lo(.LCPI35_0)443; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma444; CHECK-NEXT: vle16.v v8, (a1)445; CHECK-NEXT: vse16.v v8, (a0)446; CHECK-NEXT: ret447 store <8 x i16> <i16 8, i16 8, i16 8, i16 8, i16 8, i16 poison, i16 2, i16 3>, ptr %x448 ret void449}450 451 452define void @buildvec_dominant1_v8i16(ptr %x) {453; CHECK-LABEL: buildvec_dominant1_v8i16:454; CHECK: # %bb.0:455; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma456; CHECK-NEXT: vmv.v.i v8, 8457; CHECK-NEXT: vse16.v v8, (a0)458; CHECK-NEXT: ret459 store <8 x i16> <i16 poison, i16 8, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison>, ptr %x460 ret void461}462 463define <2 x i8> @buildvec_dominant0_v2i8() {464; CHECK-LABEL: buildvec_dominant0_v2i8:465; CHECK: # %bb.0:466; CHECK-NEXT: ret467 ret <2 x i8> <i8 poison, i8 poison>468}469 470define <2 x i8> @buildvec_dominant1_v2i8() {471; RV32-LABEL: buildvec_dominant1_v2i8:472; RV32: # %bb.0:473; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma474; RV32-NEXT: vmv.v.i v8, -1475; RV32-NEXT: ret476;477; RV64V-LABEL: buildvec_dominant1_v2i8:478; RV64V: # %bb.0:479; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma480; RV64V-NEXT: vmv.v.i v8, -1481; RV64V-NEXT: ret482;483; RV64ZVE32-LABEL: buildvec_dominant1_v2i8:484; RV64ZVE32: # %bb.0:485; RV64ZVE32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma486; RV64ZVE32-NEXT: vmv.v.i v8, -1487; RV64ZVE32-NEXT: ret488 ret <2 x i8> <i8 poison, i8 -1>489}490 491define <2 x i8> @buildvec_dominant2_v2i8() {492; RV32-LABEL: buildvec_dominant2_v2i8:493; RV32: # %bb.0:494; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma495; RV32-NEXT: vid.v v8496; RV32-NEXT: vrsub.vi v8, v8, 0497; RV32-NEXT: ret498;499; RV64V-LABEL: buildvec_dominant2_v2i8:500; RV64V: # %bb.0:501; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma502; RV64V-NEXT: vid.v v8503; RV64V-NEXT: vrsub.vi v8, v8, 0504; RV64V-NEXT: ret505;506; RV64ZVE32-LABEL: buildvec_dominant2_v2i8:507; RV64ZVE32: # %bb.0:508; RV64ZVE32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma509; RV64ZVE32-NEXT: vid.v v8510; RV64ZVE32-NEXT: vrsub.vi v8, v8, 0511; RV64ZVE32-NEXT: ret512 ret <2 x i8> <i8 0, i8 -1>513}514 515define void @buildvec_dominant0_v2i32(ptr %x) {516; RV32-LABEL: buildvec_dominant0_v2i32:517; RV32: # %bb.0:518; RV32-NEXT: lui a1, %hi(.LCPI40_0)519; RV32-NEXT: addi a1, a1, %lo(.LCPI40_0)520; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma521; RV32-NEXT: vle32.v v8, (a1)522; RV32-NEXT: vse32.v v8, (a0)523; RV32-NEXT: ret524;525; RV64V-LABEL: buildvec_dominant0_v2i32:526; RV64V: # %bb.0:527; RV64V-NEXT: lui a1, %hi(.LCPI40_0)528; RV64V-NEXT: ld a1, %lo(.LCPI40_0)(a1)529; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma530; RV64V-NEXT: vmv.v.i v8, -1531; RV64V-NEXT: vsetvli zero, zero, e64, m1, tu, ma532; RV64V-NEXT: vmv.s.x v8, a1533; RV64V-NEXT: vse64.v v8, (a0)534; RV64V-NEXT: ret535;536; RV64ZVE32-LABEL: buildvec_dominant0_v2i32:537; RV64ZVE32: # %bb.0:538; RV64ZVE32-NEXT: lui a1, %hi(.LCPI40_0)539; RV64ZVE32-NEXT: ld a1, %lo(.LCPI40_0)(a1)540; RV64ZVE32-NEXT: li a2, -1541; RV64ZVE32-NEXT: sd a1, 0(a0)542; RV64ZVE32-NEXT: sd a2, 8(a0)543; RV64ZVE32-NEXT: ret544 store <2 x i64> <i64 2049638230412172402, i64 -1>, ptr %x545 ret void546}547 548define void @buildvec_dominant1_optsize_v2i32(ptr %x) optsize {549; RV32-LABEL: buildvec_dominant1_optsize_v2i32:550; RV32: # %bb.0:551; RV32-NEXT: lui a1, %hi(.LCPI41_0)552; RV32-NEXT: addi a1, a1, %lo(.LCPI41_0)553; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma554; RV32-NEXT: vle32.v v8, (a1)555; RV32-NEXT: vse32.v v8, (a0)556; RV32-NEXT: ret557;558; RV64V-LABEL: buildvec_dominant1_optsize_v2i32:559; RV64V: # %bb.0:560; RV64V-NEXT: lui a1, %hi(.LCPI41_0)561; RV64V-NEXT: addi a1, a1, %lo(.LCPI41_0)562; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma563; RV64V-NEXT: vle64.v v8, (a1)564; RV64V-NEXT: vse64.v v8, (a0)565; RV64V-NEXT: ret566;567; RV64ZVE32-LABEL: buildvec_dominant1_optsize_v2i32:568; RV64ZVE32: # %bb.0:569; RV64ZVE32-NEXT: lui a1, %hi(.LCPI41_0)570; RV64ZVE32-NEXT: ld a1, %lo(.LCPI41_0)(a1)571; RV64ZVE32-NEXT: li a2, -1572; RV64ZVE32-NEXT: sd a1, 0(a0)573; RV64ZVE32-NEXT: sd a2, 8(a0)574; RV64ZVE32-NEXT: ret575 store <2 x i64> <i64 2049638230412172402, i64 -1>, ptr %x576 ret void577}578 579define void @buildvec_seq_v8i8_v4i16(ptr %x) {580; CHECK-LABEL: buildvec_seq_v8i8_v4i16:581; CHECK: # %bb.0:582; CHECK-NEXT: li a1, 513583; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma584; CHECK-NEXT: vmv.v.x v8, a1585; CHECK-NEXT: vse8.v v8, (a0)586; CHECK-NEXT: ret587 store <8 x i8> <i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 poison, i8 2>, ptr %x588 ret void589}590 591define void @buildvec_seq_v8i8_v2i32(ptr %x) {592; RV32-LABEL: buildvec_seq_v8i8_v2i32:593; RV32: # %bb.0:594; RV32-NEXT: lui a1, 48595; RV32-NEXT: addi a1, a1, 513596; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma597; RV32-NEXT: vmv.v.x v8, a1598; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma599; RV32-NEXT: vse8.v v8, (a0)600; RV32-NEXT: ret601;602; RV64V-LABEL: buildvec_seq_v8i8_v2i32:603; RV64V: # %bb.0:604; RV64V-NEXT: lui a1, 48605; RV64V-NEXT: addi a1, a1, 513606; RV64V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma607; RV64V-NEXT: vmv.v.x v8, a1608; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma609; RV64V-NEXT: vse8.v v8, (a0)610; RV64V-NEXT: ret611;612; RV64ZVE32-LABEL: buildvec_seq_v8i8_v2i32:613; RV64ZVE32: # %bb.0:614; RV64ZVE32-NEXT: lui a1, 48615; RV64ZVE32-NEXT: addi a1, a1, 513616; RV64ZVE32-NEXT: vsetivli zero, 2, e32, m1, ta, ma617; RV64ZVE32-NEXT: vmv.v.x v8, a1618; RV64ZVE32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma619; RV64ZVE32-NEXT: vse8.v v8, (a0)620; RV64ZVE32-NEXT: ret621 store <8 x i8> <i8 1, i8 2, i8 3, i8 poison, i8 1, i8 2, i8 3, i8 poison>, ptr %x622 ret void623}624 625define void @buildvec_seq_v16i8_v2i64(ptr %x) {626; RV32-LABEL: buildvec_seq_v16i8_v2i64:627; RV32: # %bb.0:628; RV32-NEXT: lui a1, %hi(.LCPI44_0)629; RV32-NEXT: addi a1, a1, %lo(.LCPI44_0)630; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma631; RV32-NEXT: vle8.v v8, (a1)632; RV32-NEXT: vse8.v v8, (a0)633; RV32-NEXT: ret634;635; RV64V-LABEL: buildvec_seq_v16i8_v2i64:636; RV64V: # %bb.0:637; RV64V-NEXT: lui a1, %hi(.LCPI44_0)638; RV64V-NEXT: ld a1, %lo(.LCPI44_0)(a1)639; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma640; RV64V-NEXT: vmv.v.x v8, a1641; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma642; RV64V-NEXT: vse8.v v8, (a0)643; RV64V-NEXT: ret644;645; RV64ZVE32-LABEL: buildvec_seq_v16i8_v2i64:646; RV64ZVE32: # %bb.0:647; RV64ZVE32-NEXT: lui a1, %hi(.LCPI44_0)648; RV64ZVE32-NEXT: addi a1, a1, %lo(.LCPI44_0)649; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, ma650; RV64ZVE32-NEXT: vle8.v v8, (a1)651; RV64ZVE32-NEXT: vse8.v v8, (a0)652; RV64ZVE32-NEXT: ret653 store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr %x654 ret void655}656 657define void @buildvec_seq2_v16i8_v2i64(ptr %x) {658; RV32-LABEL: buildvec_seq2_v16i8_v2i64:659; RV32: # %bb.0:660; RV32-NEXT: lui a1, 528432661; RV32-NEXT: addi a1, a1, 513662; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma663; RV32-NEXT: vmv.v.x v8, a1664; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma665; RV32-NEXT: vse8.v v8, (a0)666; RV32-NEXT: ret667;668; RV64V-LABEL: buildvec_seq2_v16i8_v2i64:669; RV64V: # %bb.0:670; RV64V-NEXT: lui a1, 528432671; RV64V-NEXT: addi a1, a1, 513672; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma673; RV64V-NEXT: vmv.v.x v8, a1674; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma675; RV64V-NEXT: vse8.v v8, (a0)676; RV64V-NEXT: ret677;678; RV64ZVE32-LABEL: buildvec_seq2_v16i8_v2i64:679; RV64ZVE32: # %bb.0:680; RV64ZVE32-NEXT: lui a1, %hi(.LCPI45_0)681; RV64ZVE32-NEXT: addi a1, a1, %lo(.LCPI45_0)682; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, ma683; RV64ZVE32-NEXT: vle8.v v8, (a1)684; RV64ZVE32-NEXT: vse8.v v8, (a0)685; RV64ZVE32-NEXT: ret686 store <16 x i8> <i8 1, i8 2, i8 3, i8 129, i8 -1, i8 -1, i8 -1, i8 -1, i8 1, i8 2, i8 3, i8 129, i8 -1, i8 -1, i8 -1, i8 -1>, ptr %x687 ret void688}689 690define void @buildvec_seq_v9i8(ptr %x) {691; CHECK-LABEL: buildvec_seq_v9i8:692; CHECK: # %bb.0:693; CHECK-NEXT: li a1, 73694; CHECK-NEXT: vsetivli zero, 9, e8, m1, ta, ma695; CHECK-NEXT: vmv.v.i v8, 3696; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma697; CHECK-NEXT: vmv.s.x v0, a1698; CHECK-NEXT: li a1, 146699; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma700; CHECK-NEXT: vmerge.vim v8, v8, 1, v0701; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma702; CHECK-NEXT: vmv.s.x v0, a1703; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma704; CHECK-NEXT: vmerge.vim v8, v8, 2, v0705; CHECK-NEXT: vse8.v v8, (a0)706; CHECK-NEXT: ret707 store <9 x i8> <i8 1, i8 2, i8 3, i8 1, i8 2, i8 3, i8 1, i8 2, i8 3>, ptr %x708 ret void709}710 711define void @buildvec_seq_v4i16_v2i32(ptr %x) {712; CHECK-LABEL: buildvec_seq_v4i16_v2i32:713; CHECK: # %bb.0:714; CHECK-NEXT: li a1, -127715; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma716; CHECK-NEXT: vmv.v.x v8, a1717; CHECK-NEXT: vse16.v v8, (a0)718; CHECK-NEXT: ret719 store <4 x i16> <i16 -127, i16 -1, i16 -127, i16 -1>, ptr %x720 ret void721}722 723define void @buildvec_vid_step1o2_v4i32(ptr %z0, ptr %z1, ptr %z2, ptr %z3, ptr %z4, ptr %z5, ptr %z6) {724; CHECK-LABEL: buildvec_vid_step1o2_v4i32:725; CHECK: # %bb.0:726; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma727; CHECK-NEXT: vmv.v.i v8, 1728; CHECK-NEXT: vmv.s.x v9, zero729; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma730; CHECK-NEXT: vslideup.vi v8, v9, 1731; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma732; CHECK-NEXT: vid.v v9733; CHECK-NEXT: vsrl.vi v9, v9, 1734; CHECK-NEXT: vse32.v v9, (a0)735; CHECK-NEXT: vse32.v v9, (a1)736; CHECK-NEXT: vse32.v v9, (a2)737; CHECK-NEXT: vse32.v v9, (a3)738; CHECK-NEXT: vse32.v v9, (a4)739; CHECK-NEXT: vmv.v.i v9, 0740; CHECK-NEXT: li a0, 1741; CHECK-NEXT: vslide1down.vx v9, v9, a0742; CHECK-NEXT: vse32.v v8, (a5)743; CHECK-NEXT: vse32.v v9, (a6)744; CHECK-NEXT: ret745 store <4 x i32> <i32 0, i32 0, i32 1, i32 1>, ptr %z0746 store <4 x i32> <i32 0, i32 0, i32 1, i32 poison>, ptr %z1747 store <4 x i32> <i32 0, i32 poison, i32 1, i32 1>, ptr %z2748 store <4 x i32> <i32 poison, i32 0, i32 poison, i32 1>, ptr %z3749 store <4 x i32> <i32 0, i32 poison, i32 1, i32 poison>, ptr %z4750 ; We don't catch this one751 store <4 x i32> <i32 poison, i32 0, i32 1, i32 1>, ptr %z5752 ; We catch this one but as VID/3 rather than VID/2753 store <4 x i32> <i32 0, i32 0, i32 poison, i32 1>, ptr %z6754 ret void755}756 757define void @buildvec_vid_step1o2_add3_v4i16(ptr %z0, ptr %z1, ptr %z2, ptr %z3, ptr %z4, ptr %z5, ptr %z6) {758; CHECK-LABEL: buildvec_vid_step1o2_add3_v4i16:759; CHECK: # %bb.0:760; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma761; CHECK-NEXT: vid.v v8762; CHECK-NEXT: vmv.v.i v9, 3763; CHECK-NEXT: vsrl.vi v8, v8, 1764; CHECK-NEXT: vadd.vi v8, v8, 3765; CHECK-NEXT: vse16.v v8, (a0)766; CHECK-NEXT: vse16.v v8, (a1)767; CHECK-NEXT: vse16.v v8, (a2)768; CHECK-NEXT: vse16.v v8, (a3)769; CHECK-NEXT: vse16.v v8, (a4)770; CHECK-NEXT: vmv.v.i v8, 4771; CHECK-NEXT: li a0, 4772; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma773; CHECK-NEXT: vslideup.vi v8, v9, 1774; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma775; CHECK-NEXT: vslide1down.vx v9, v9, a0776; CHECK-NEXT: vse16.v v8, (a5)777; CHECK-NEXT: vse16.v v9, (a6)778; CHECK-NEXT: ret779 store <4 x i16> <i16 3, i16 3, i16 4, i16 4>, ptr %z0780 store <4 x i16> <i16 3, i16 3, i16 4, i16 poison>, ptr %z1781 store <4 x i16> <i16 3, i16 poison, i16 4, i16 4>, ptr %z2782 store <4 x i16> <i16 poison, i16 3, i16 poison, i16 4>, ptr %z3783 store <4 x i16> <i16 3, i16 poison, i16 4, i16 poison>, ptr %z4784 ; We don't catch this one785 store <4 x i16> <i16 poison, i16 3, i16 4, i16 4>, ptr %z5786 ; We catch this one but as VID/3 rather than VID/2787 store <4 x i16> <i16 3, i16 3, i16 poison, i16 4>, ptr %z6788 ret void789}790 791define void @buildvec_vid_stepn1o4_addn5_v8i8(ptr %z0) {792; CHECK-LABEL: buildvec_vid_stepn1o4_addn5_v8i8:793; CHECK: # %bb.0:794; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma795; CHECK-NEXT: vid.v v8796; CHECK-NEXT: vsrl.vi v8, v8, 2797; CHECK-NEXT: vrsub.vi v8, v8, -5798; CHECK-NEXT: vse8.v v8, (a0)799; CHECK-NEXT: ret800 store <8 x i8> <i8 -5, i8 -5, i8 -5, i8 -5, i8 -6, i8 -6, i8 -6, i8 -6>, ptr %z0801 ret void802}803 804define void @buildvec_vid_mpy_imm_v8i16(ptr %x) {805; CHECK-LABEL: buildvec_vid_mpy_imm_v8i16:806; CHECK: # %bb.0:807; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma808; CHECK-NEXT: vid.v v8809; CHECK-NEXT: li a1, 17810; CHECK-NEXT: vmul.vx v8, v8, a1811; CHECK-NEXT: vse16.v v8, (a0)812; CHECK-NEXT: ret813 store <8 x i16> <i16 0, i16 17, i16 34, i16 51, i16 68, i16 85, i16 102, i16 119>, ptr %x814 ret void815}816 817define void @buildvec_vid_shl_imm_v8i16(ptr %x) {818; CHECK-LABEL: buildvec_vid_shl_imm_v8i16:819; CHECK: # %bb.0:820; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma821; CHECK-NEXT: vid.v v8822; CHECK-NEXT: vsll.vi v8, v8, 9823; CHECK-NEXT: vse16.v v8, (a0)824; CHECK-NEXT: ret825 store <8 x i16> <i16 0, i16 512, i16 1024, i16 1536, i16 2048, i16 2560, i16 3072, i16 3584>, ptr %x826 ret void827}828 829define <4 x i32> @splat_c3_v4i32(<4 x i32> %v) {830; CHECK-LABEL: splat_c3_v4i32:831; CHECK: # %bb.0:832; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma833; CHECK-NEXT: vrgather.vi v9, v8, 3834; CHECK-NEXT: vmv.v.v v8, v9835; CHECK-NEXT: ret836 %x = extractelement <4 x i32> %v, i32 3837 %ins = insertelement <4 x i32> poison, i32 %x, i32 0838 %splat = shufflevector <4 x i32> %ins, <4 x i32> poison, <4 x i32> zeroinitializer839 ret <4 x i32> %splat840}841 842define <4 x i32> @splat_idx_v4i32(<4 x i32> %v, i64 %idx) {843; CHECK-LABEL: splat_idx_v4i32:844; CHECK: # %bb.0:845; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma846; CHECK-NEXT: vrgather.vx v9, v8, a0847; CHECK-NEXT: vmv.v.v v8, v9848; CHECK-NEXT: ret849 %x = extractelement <4 x i32> %v, i64 %idx850 %ins = insertelement <4 x i32> poison, i32 %x, i32 0851 %splat = shufflevector <4 x i32> %ins, <4 x i32> poison, <4 x i32> zeroinitializer852 ret <4 x i32> %splat853}854 855define <8 x i16> @splat_c4_v8i16(<8 x i16> %v) {856; CHECK-LABEL: splat_c4_v8i16:857; CHECK: # %bb.0:858; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma859; CHECK-NEXT: vrgather.vi v9, v8, 4860; CHECK-NEXT: vmv.v.v v8, v9861; CHECK-NEXT: ret862 %x = extractelement <8 x i16> %v, i32 4863 %ins = insertelement <8 x i16> poison, i16 %x, i32 0864 %splat = shufflevector <8 x i16> %ins, <8 x i16> poison, <8 x i32> zeroinitializer865 ret <8 x i16> %splat866}867 868define <8 x i16> @splat_idx_v8i16(<8 x i16> %v, i64 %idx) {869; CHECK-LABEL: splat_idx_v8i16:870; CHECK: # %bb.0:871; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma872; CHECK-NEXT: vrgather.vx v9, v8, a0873; CHECK-NEXT: vmv.v.v v8, v9874; CHECK-NEXT: ret875 %x = extractelement <8 x i16> %v, i64 %idx876 %ins = insertelement <8 x i16> poison, i16 %x, i32 0877 %splat = shufflevector <8 x i16> %ins, <8 x i16> poison, <8 x i32> zeroinitializer878 ret <8 x i16> %splat879}880 881define <4 x i8> @buildvec_not_vid_v4i8_1() {882; CHECK-LABEL: buildvec_not_vid_v4i8_1:883; CHECK: # %bb.0:884; CHECK-NEXT: lui a0, 12320885; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma886; CHECK-NEXT: vmv.s.x v8, a0887; CHECK-NEXT: ret888 ret <4 x i8> <i8 0, i8 0, i8 2, i8 3>889}890 891define <4 x i8> @buildvec_not_vid_v4i8_2() {892; CHECK-LABEL: buildvec_not_vid_v4i8_2:893; CHECK: # %bb.0:894; CHECK-NEXT: lui a0, 16895; CHECK-NEXT: addi a0, a0, 771896; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma897; CHECK-NEXT: vmv.s.x v8, a0898; CHECK-NEXT: ret899 ret <4 x i8> <i8 3, i8 3, i8 1, i8 0>900}901 902; We match this as a VID sequence (-3 / 8) + 5 but choose not to introduce903; division to compute it.904define <16 x i8> @buildvec_not_vid_v16i8() {905; CHECK-LABEL: buildvec_not_vid_v16i8:906; CHECK: # %bb.0:907; CHECK-NEXT: vsetivli zero, 7, e8, m1, ta, ma908; CHECK-NEXT: vmv.v.i v9, 3909; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma910; CHECK-NEXT: vmv.v.i v8, 0911; CHECK-NEXT: vsetivli zero, 7, e8, m1, tu, ma912; CHECK-NEXT: vslideup.vi v8, v9, 6913; CHECK-NEXT: ret914 ret <16 x i8> <i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 3, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 0>915}916 917define <512 x i8> @buildvec_vid_v512i8_indices_overflow() vscale_range(16, 1024) {918; CHECK-LABEL: buildvec_vid_v512i8_indices_overflow:919; CHECK: # %bb.0:920; CHECK-NEXT: li a0, 512921; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma922; CHECK-NEXT: vid.v v8923; CHECK-NEXT: ret924 ret <512 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39, i8 40, i8 41, i8 42, i8 43, i8 44, i8 45, i8 46, i8 47, i8 48, i8 49, i8 50, i8 51, i8 52, i8 53, i8 54, i8 55, i8 56, i8 57, i8 58, i8 59, i8 60, i8 61, i8 62, i8 63, i8 64, i8 65, i8 66, i8 67, i8 68, i8 69, i8 70, i8 71, i8 72, i8 73, i8 74, i8 75, i8 76, i8 77, i8 78, i8 79, i8 80, i8 81, i8 82, i8 83, i8 84, i8 85, i8 86, i8 87, i8 88, i8 89, i8 90, i8 91, i8 92, i8 93, i8 94, i8 95, i8 96, i8 97, i8 98, i8 99, i8 100, i8 101, i8 102, i8 103, i8 104, i8 105, i8 106, i8 107, i8 108, i8 109, i8 110, i8 111, i8 112, i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 128, i8 129, i8 130, i8 131, i8 132, i8 133, i8 134, i8 135, i8 136, i8 137, i8 138, i8 139, i8 140, i8 141, i8 142, i8 143, i8 144, i8 145, i8 146, i8 147, i8 148, i8 149, i8 150, i8 151, i8 152, i8 153, i8 154, i8 155, i8 156, i8 157, i8 158, i8 159, i8 160, i8 161, i8 162, i8 163, i8 164, i8 165, i8 166, i8 167, i8 168, i8 169, i8 170, i8 171, i8 172, i8 173, i8 174, i8 175, i8 176, i8 177, i8 178, i8 179, i8 180, i8 181, i8 182, i8 183, i8 184, i8 185, i8 186, i8 187, i8 188, i8 189, i8 190, i8 191, i8 192, i8 193, i8 194, i8 195, i8 196, i8 197, i8 198, i8 199, i8 200, i8 201, i8 202, i8 203, i8 204, i8 205, i8 206, i8 207, i8 208, i8 209, i8 210, i8 211, i8 212, i8 213, i8 214, i8 215, i8 216, i8 217, i8 218, i8 219, i8 220, i8 221, i8 222, i8 223, i8 224, i8 225, i8 226, i8 227, i8 228, i8 229, i8 230, i8 231, i8 232, i8 233, i8 234, i8 235, i8 236, i8 237, i8 238, i8 239, i8 240, i8 241, i8 242, i8 243, i8 244, i8 245, i8 246, i8 247, i8 248, i8 249, i8 250, i8 251, i8 252, i8 253, i8 254, i8 255, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39, i8 40, i8 41, i8 42, i8 43, i8 44, i8 45, i8 46, i8 47, i8 48, i8 49, i8 50, i8 51, i8 52, i8 53, i8 54, i8 55, i8 56, i8 57, i8 58, i8 59, i8 60, i8 61, i8 62, i8 63, i8 64, i8 65, i8 66, i8 67, i8 68, i8 69, i8 70, i8 71, i8 72, i8 73, i8 74, i8 75, i8 76, i8 77, i8 78, i8 79, i8 80, i8 81, i8 82, i8 83, i8 84, i8 85, i8 86, i8 87, i8 88, i8 89, i8 90, i8 91, i8 92, i8 93, i8 94, i8 95, i8 96, i8 97, i8 98, i8 99, i8 100, i8 101, i8 102, i8 103, i8 104, i8 105, i8 106, i8 107, i8 108, i8 109, i8 110, i8 111, i8 112, i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 128, i8 129, i8 130, i8 131, i8 132, i8 133, i8 134, i8 135, i8 136, i8 137, i8 138, i8 139, i8 140, i8 141, i8 142, i8 143, i8 144, i8 145, i8 146, i8 147, i8 148, i8 149, i8 150, i8 151, i8 152, i8 153, i8 154, i8 155, i8 156, i8 157, i8 158, i8 159, i8 160, i8 161, i8 162, i8 163, i8 164, i8 165, i8 166, i8 167, i8 168, i8 169, i8 170, i8 171, i8 172, i8 173, i8 174, i8 175, i8 176, i8 177, i8 178, i8 179, i8 180, i8 181, i8 182, i8 183, i8 184, i8 185, i8 186, i8 187, i8 188, i8 189, i8 190, i8 191, i8 192, i8 193, i8 194, i8 195, i8 196, i8 197, i8 198, i8 199, i8 200, i8 201, i8 202, i8 203, i8 204, i8 205, i8 206, i8 207, i8 208, i8 209, i8 210, i8 211, i8 212, i8 213, i8 214, i8 215, i8 216, i8 217, i8 218, i8 219, i8 220, i8 221, i8 222, i8 223, i8 224, i8 225, i8 226, i8 227, i8 228, i8 229, i8 230, i8 231, i8 232, i8 233, i8 234, i8 235, i8 236, i8 237, i8 238, i8 239, i8 240, i8 241, i8 242, i8 243, i8 244, i8 245, i8 246, i8 247, i8 248, i8 249, i8 250, i8 251, i8 252, i8 253, i8 254, i8 255>925}926 927define <512 x i8> @buildvec_not_vid_v512i8_indices_overflow_1() vscale_range(16, 1024) {928; RV32-LABEL: buildvec_not_vid_v512i8_indices_overflow_1:929; RV32: # %bb.0:930; RV32-NEXT: li a0, 512931; RV32-NEXT: vsetivli zero, 16, e32, mf2, ta, ma932; RV32-NEXT: vid.v v8933; RV32-NEXT: vsrl.vi v8, v8, 3934; RV32-NEXT: vadd.vi v0, v8, -1935; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma936; RV32-NEXT: vmv.v.i v8, 1937; RV32-NEXT: vmerge.vim v8, v8, 0, v0938; RV32-NEXT: ret939;940; RV64V-LABEL: buildvec_not_vid_v512i8_indices_overflow_1:941; RV64V: # %bb.0:942; RV64V-NEXT: li a0, 512943; RV64V-NEXT: vsetivli zero, 8, e64, m1, ta, ma944; RV64V-NEXT: vid.v v8945; RV64V-NEXT: vsrl.vi v8, v8, 2946; RV64V-NEXT: vadd.vi v0, v8, -1947; RV64V-NEXT: vsetvli zero, a0, e8, m4, ta, ma948; RV64V-NEXT: vmv.v.i v8, 1949; RV64V-NEXT: vmerge.vim v8, v8, 0, v0950; RV64V-NEXT: ret951;952; RV64ZVE32-LABEL: buildvec_not_vid_v512i8_indices_overflow_1:953; RV64ZVE32: # %bb.0:954; RV64ZVE32-NEXT: li a0, 512955; RV64ZVE32-NEXT: vsetivli zero, 16, e32, m1, ta, ma956; RV64ZVE32-NEXT: vid.v v8957; RV64ZVE32-NEXT: vsrl.vi v8, v8, 3958; RV64ZVE32-NEXT: vadd.vi v0, v8, -1959; RV64ZVE32-NEXT: vsetvli zero, a0, e8, m4, ta, ma960; RV64ZVE32-NEXT: vmv.v.i v8, 1961; RV64ZVE32-NEXT: vmerge.vim v8, v8, 0, v0962; RV64ZVE32-NEXT: ret963 ret <512 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>964}965 966define <512 x i8> @buildvec_not_vid_v512i8_indices_overflow_2() vscale_range(16, 1024) {967; RV32-LABEL: buildvec_not_vid_v512i8_indices_overflow_2:968; RV32: # %bb.0:969; RV32-NEXT: vsetivli zero, 16, e32, mf2, ta, ma970; RV32-NEXT: vmv.v.i v0, 15971; RV32-NEXT: vmv.v.i v12, 0972; RV32-NEXT: li a0, 512973; RV32-NEXT: li a1, 240974; RV32-NEXT: vmerge.vim v13, v12, -1, v0975; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma976; RV32-NEXT: vmv.v.i v8, 3977; RV32-NEXT: vmv1r.v v0, v13978; RV32-NEXT: vmerge.vim v8, v8, 0, v0979; RV32-NEXT: vsetvli zero, zero, e16, m8, ta, ma980; RV32-NEXT: vmv.s.x v0, a1981; RV32-NEXT: li a1, 15982; RV32-NEXT: vsetivli zero, 16, e32, mf2, ta, ma983; RV32-NEXT: vmerge.vim v13, v12, -1, v0984; RV32-NEXT: slli a1, a1, 8985; RV32-NEXT: vmv1r.v v0, v13986; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma987; RV32-NEXT: vmerge.vim v8, v8, 1, v0988; RV32-NEXT: vsetvli zero, zero, e16, m8, ta, ma989; RV32-NEXT: vmv.s.x v0, a1990; RV32-NEXT: vsetivli zero, 16, e32, mf2, ta, ma991; RV32-NEXT: vmerge.vim v12, v12, -1, v0992; RV32-NEXT: vmv1r.v v0, v12993; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma994; RV32-NEXT: vmerge.vim v8, v8, 2, v0995; RV32-NEXT: ret996;997; RV64V-LABEL: buildvec_not_vid_v512i8_indices_overflow_2:998; RV64V: # %bb.0:999; RV64V-NEXT: vsetivli zero, 8, e64, m1, ta, ma1000; RV64V-NEXT: vmv.v.i v0, 31001; RV64V-NEXT: vmv.v.i v12, 01002; RV64V-NEXT: li a0, 5121003; RV64V-NEXT: vmerge.vim v13, v12, -1, v01004; RV64V-NEXT: vsetvli zero, a0, e8, m4, ta, ma1005; RV64V-NEXT: vmv.v.i v8, 31006; RV64V-NEXT: vmv1r.v v0, v131007; RV64V-NEXT: vmerge.vim v8, v8, 0, v01008; RV64V-NEXT: vsetivli zero, 8, e64, m1, ta, ma1009; RV64V-NEXT: vmv.v.i v0, 121010; RV64V-NEXT: vmerge.vim v13, v12, -1, v01011; RV64V-NEXT: li a1, 481012; RV64V-NEXT: vmv.v.v v0, v131013; RV64V-NEXT: vsetvli zero, a0, e8, m4, ta, ma1014; RV64V-NEXT: vmerge.vim v8, v8, 1, v01015; RV64V-NEXT: vmv.s.x v0, a11016; RV64V-NEXT: vsetivli zero, 8, e64, m1, ta, ma1017; RV64V-NEXT: vmerge.vim v12, v12, -1, v01018; RV64V-NEXT: vmv.v.v v0, v121019; RV64V-NEXT: vsetvli zero, a0, e8, m4, ta, ma1020; RV64V-NEXT: vmerge.vim v8, v8, 2, v01021; RV64V-NEXT: ret1022;1023; RV64ZVE32-LABEL: buildvec_not_vid_v512i8_indices_overflow_2:1024; RV64ZVE32: # %bb.0:1025; RV64ZVE32-NEXT: vsetivli zero, 16, e32, m1, ta, ma1026; RV64ZVE32-NEXT: vmv.v.i v0, 151027; RV64ZVE32-NEXT: vmv.v.i v12, 01028; RV64ZVE32-NEXT: li a0, 5121029; RV64ZVE32-NEXT: li a1, 2401030; RV64ZVE32-NEXT: vmerge.vim v13, v12, -1, v01031; RV64ZVE32-NEXT: vsetvli zero, a0, e8, m4, ta, ma1032; RV64ZVE32-NEXT: vmv.v.i v8, 31033; RV64ZVE32-NEXT: vmv1r.v v0, v131034; RV64ZVE32-NEXT: vmerge.vim v8, v8, 0, v01035; RV64ZVE32-NEXT: vsetvli zero, zero, e16, m8, ta, ma1036; RV64ZVE32-NEXT: vmv.s.x v0, a11037; RV64ZVE32-NEXT: li a1, 151038; RV64ZVE32-NEXT: vsetivli zero, 16, e32, m1, ta, ma1039; RV64ZVE32-NEXT: vmerge.vim v13, v12, -1, v01040; RV64ZVE32-NEXT: slli a1, a1, 81041; RV64ZVE32-NEXT: vmv.v.v v0, v131042; RV64ZVE32-NEXT: vsetvli zero, a0, e8, m4, ta, ma1043; RV64ZVE32-NEXT: vmerge.vim v8, v8, 1, v01044; RV64ZVE32-NEXT: vsetvli zero, zero, e16, m8, ta, ma1045; RV64ZVE32-NEXT: vmv.s.x v0, a11046; RV64ZVE32-NEXT: vsetivli zero, 16, e32, m1, ta, ma1047; RV64ZVE32-NEXT: vmerge.vim v12, v12, -1, v01048; RV64ZVE32-NEXT: vmv.v.v v0, v121049; RV64ZVE32-NEXT: vsetvli zero, a0, e8, m4, ta, ma1050; RV64ZVE32-NEXT: vmerge.vim v8, v8, 2, v01051; RV64ZVE32-NEXT: ret1052 ret <512 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>1053}1054 1055define <8 x i32> @prefix_overwrite(<8 x i32> %vin, i32 %a, i32 %b, i32 %c, i32 %d) {1056; CHECK-LABEL: prefix_overwrite:1057; CHECK: # %bb.0:1058; CHECK-NEXT: vsetivli zero, 8, e32, m1, tu, ma1059; CHECK-NEXT: vmv.s.x v10, a11060; CHECK-NEXT: vmv.s.x v8, a01061; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma1062; CHECK-NEXT: vslideup.vi v8, v10, 11063; CHECK-NEXT: vmv.s.x v10, a21064; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma1065; CHECK-NEXT: vslideup.vi v8, v10, 21066; CHECK-NEXT: vmv.s.x v10, a31067; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma1068; CHECK-NEXT: vslideup.vi v8, v10, 31069; CHECK-NEXT: ret1070 %v0 = insertelement <8 x i32> %vin, i32 %a, i32 01071 %v1 = insertelement <8 x i32> %v0, i32 %b, i32 11072 %v2 = insertelement <8 x i32> %v1, i32 %c, i32 21073 %v3 = insertelement <8 x i32> %v2, i32 %d, i32 31074 ret <8 x i32> %v31075}1076 1077define <8 x i32> @suffix_overwrite(<8 x i32> %vin, i32 %a, i32 %b, i32 %c, i32 %d) {1078; CHECK-LABEL: suffix_overwrite:1079; CHECK: # %bb.0:1080; CHECK-NEXT: vsetivli zero, 5, e32, m2, tu, ma1081; CHECK-NEXT: vmv.s.x v10, a01082; CHECK-NEXT: vslideup.vi v8, v10, 41083; CHECK-NEXT: vmv.s.x v10, a11084; CHECK-NEXT: vsetivli zero, 6, e32, m2, tu, ma1085; CHECK-NEXT: vslideup.vi v8, v10, 51086; CHECK-NEXT: vmv.s.x v10, a21087; CHECK-NEXT: vsetivli zero, 7, e32, m2, tu, ma1088; CHECK-NEXT: vslideup.vi v8, v10, 61089; CHECK-NEXT: vmv.s.x v10, a31090; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1091; CHECK-NEXT: vslideup.vi v8, v10, 71092; CHECK-NEXT: ret1093 %v0 = insertelement <8 x i32> %vin, i32 %a, i32 41094 %v1 = insertelement <8 x i32> %v0, i32 %b, i32 51095 %v2 = insertelement <8 x i32> %v1, i32 %c, i32 61096 %v3 = insertelement <8 x i32> %v2, i32 %d, i32 71097 ret <8 x i32> %v31098}1099 1100define <4 x i64> @v4xi64_exact(i64 %a, i64 %b, i64 %c, i64 %d) vscale_range(2,2) {1101; RV32-LABEL: v4xi64_exact:1102; RV32: # %bb.0:1103; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma1104; RV32-NEXT: vmv.v.x v8, a41105; RV32-NEXT: vmv.v.x v9, a01106; RV32-NEXT: vslide1down.vx v8, v8, a51107; RV32-NEXT: vslide1down.vx v10, v9, a11108; RV32-NEXT: vslide1down.vx v8, v8, a61109; RV32-NEXT: vslide1down.vx v9, v8, a71110; RV32-NEXT: vslide1down.vx v8, v10, a21111; RV32-NEXT: vslide1down.vx v8, v8, a31112; RV32-NEXT: ret1113;1114; RV64V-LABEL: v4xi64_exact:1115; RV64V: # %bb.0:1116; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma1117; RV64V-NEXT: vmv.v.x v8, a21118; RV64V-NEXT: vslide1down.vx v9, v8, a31119; RV64V-NEXT: vmv.v.x v8, a01120; RV64V-NEXT: vslide1down.vx v8, v8, a11121; RV64V-NEXT: ret1122;1123; RV64ZVE32-LABEL: v4xi64_exact:1124; RV64ZVE32: # %bb.0:1125; RV64ZVE32-NEXT: sd a1, 0(a0)1126; RV64ZVE32-NEXT: sd a2, 8(a0)1127; RV64ZVE32-NEXT: sd a3, 16(a0)1128; RV64ZVE32-NEXT: sd a4, 24(a0)1129; RV64ZVE32-NEXT: ret1130 %v1 = insertelement <4 x i64> poison, i64 %a, i32 01131 %v2 = insertelement <4 x i64> %v1, i64 %b, i32 11132 %v3 = insertelement <4 x i64> %v2, i64 %c, i32 21133 %v4 = insertelement <4 x i64> %v3, i64 %d, i32 31134 ret <4 x i64> %v41135}1136 1137define <8 x i64> @v8xi64_exact(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h) vscale_range(2,2) {1138; RV32-LABEL: v8xi64_exact:1139; RV32: # %bb.0:1140; RV32-NEXT: addi sp, sp, -161141; RV32-NEXT: .cfi_def_cfa_offset 161142; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill1143; RV32-NEXT: .cfi_offset s0, -41144; RV32-NEXT: lw t0, 44(sp)1145; RV32-NEXT: lw t1, 40(sp)1146; RV32-NEXT: lw t2, 36(sp)1147; RV32-NEXT: lw t3, 32(sp)1148; RV32-NEXT: lw t4, 28(sp)1149; RV32-NEXT: lw t5, 24(sp)1150; RV32-NEXT: lw t6, 20(sp)1151; RV32-NEXT: lw s0, 16(sp)1152; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma1153; RV32-NEXT: vmv.v.x v8, a41154; RV32-NEXT: vmv.v.x v9, a01155; RV32-NEXT: vslide1down.vx v8, v8, a51156; RV32-NEXT: vslide1down.vx v9, v9, a11157; RV32-NEXT: vslide1down.vx v8, v8, a61158; RV32-NEXT: vslide1down.vx v10, v9, a21159; RV32-NEXT: vslide1down.vx v9, v8, a71160; RV32-NEXT: vslide1down.vx v8, v10, a31161; RV32-NEXT: vmv.v.x v10, s01162; RV32-NEXT: vslide1down.vx v10, v10, t61163; RV32-NEXT: vslide1down.vx v10, v10, t51164; RV32-NEXT: vslide1down.vx v10, v10, t41165; RV32-NEXT: vmv.v.x v11, t31166; RV32-NEXT: vslide1down.vx v11, v11, t21167; RV32-NEXT: vslide1down.vx v11, v11, t11168; RV32-NEXT: vslide1down.vx v11, v11, t01169; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload1170; RV32-NEXT: .cfi_restore s01171; RV32-NEXT: addi sp, sp, 161172; RV32-NEXT: .cfi_def_cfa_offset 01173; RV32-NEXT: ret1174;1175; RV64V-LABEL: v8xi64_exact:1176; RV64V: # %bb.0:1177; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma1178; RV64V-NEXT: vmv.v.x v8, a21179; RV64V-NEXT: vmv.v.x v10, a01180; RV64V-NEXT: vslide1down.vx v9, v8, a31181; RV64V-NEXT: vslide1down.vx v8, v10, a11182; RV64V-NEXT: vmv.v.x v10, a41183; RV64V-NEXT: vslide1down.vx v10, v10, a51184; RV64V-NEXT: vmv.v.x v11, a61185; RV64V-NEXT: vslide1down.vx v11, v11, a71186; RV64V-NEXT: ret1187;1188; RV64ZVE32-LABEL: v8xi64_exact:1189; RV64ZVE32: # %bb.0:1190; RV64ZVE32-NEXT: ld t0, 0(sp)1191; RV64ZVE32-NEXT: sd a5, 32(a0)1192; RV64ZVE32-NEXT: sd a6, 40(a0)1193; RV64ZVE32-NEXT: sd a7, 48(a0)1194; RV64ZVE32-NEXT: sd t0, 56(a0)1195; RV64ZVE32-NEXT: sd a1, 0(a0)1196; RV64ZVE32-NEXT: sd a2, 8(a0)1197; RV64ZVE32-NEXT: sd a3, 16(a0)1198; RV64ZVE32-NEXT: sd a4, 24(a0)1199; RV64ZVE32-NEXT: ret1200 %v1 = insertelement <8 x i64> poison, i64 %a, i32 01201 %v2 = insertelement <8 x i64> %v1, i64 %b, i32 11202 %v3 = insertelement <8 x i64> %v2, i64 %c, i32 21203 %v4 = insertelement <8 x i64> %v3, i64 %d, i32 31204 %v5 = insertelement <8 x i64> %v4, i64 %e, i32 41205 %v6 = insertelement <8 x i64> %v5, i64 %f, i32 51206 %v7 = insertelement <8 x i64> %v6, i64 %g, i32 61207 %v8 = insertelement <8 x i64> %v7, i64 %h, i32 71208 ret <8 x i64> %v81209}1210 1211define <8 x i64> @v8xi64_exact_equal_halves(i64 %a, i64 %b, i64 %c, i64 %d) vscale_range(2,2) {1212; RV32-LABEL: v8xi64_exact_equal_halves:1213; RV32: # %bb.0:1214; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma1215; RV32-NEXT: vmv.v.x v8, a41216; RV32-NEXT: vmv.v.x v9, a01217; RV32-NEXT: vslide1down.vx v8, v8, a51218; RV32-NEXT: vslide1down.vx v10, v9, a11219; RV32-NEXT: vslide1down.vx v8, v8, a61220; RV32-NEXT: vslide1down.vx v9, v8, a71221; RV32-NEXT: vslide1down.vx v8, v10, a21222; RV32-NEXT: vslide1down.vx v8, v8, a31223; RV32-NEXT: vmv.v.v v10, v81224; RV32-NEXT: vmv.v.v v11, v91225; RV32-NEXT: ret1226;1227; RV64V-LABEL: v8xi64_exact_equal_halves:1228; RV64V: # %bb.0:1229; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma1230; RV64V-NEXT: vmv.v.x v8, a21231; RV64V-NEXT: vslide1down.vx v9, v8, a31232; RV64V-NEXT: vmv.v.x v8, a01233; RV64V-NEXT: vslide1down.vx v8, v8, a11234; RV64V-NEXT: vmv.v.v v10, v81235; RV64V-NEXT: vmv.v.v v11, v91236; RV64V-NEXT: ret1237;1238; RV64ZVE32-LABEL: v8xi64_exact_equal_halves:1239; RV64ZVE32: # %bb.0:1240; RV64ZVE32-NEXT: sd a1, 32(a0)1241; RV64ZVE32-NEXT: sd a2, 40(a0)1242; RV64ZVE32-NEXT: sd a3, 48(a0)1243; RV64ZVE32-NEXT: sd a4, 56(a0)1244; RV64ZVE32-NEXT: sd a1, 0(a0)1245; RV64ZVE32-NEXT: sd a2, 8(a0)1246; RV64ZVE32-NEXT: sd a3, 16(a0)1247; RV64ZVE32-NEXT: sd a4, 24(a0)1248; RV64ZVE32-NEXT: ret1249 %v1 = insertelement <8 x i64> poison, i64 %a, i32 01250 %v2 = insertelement <8 x i64> %v1, i64 %b, i32 11251 %v3 = insertelement <8 x i64> %v2, i64 %c, i32 21252 %v4 = insertelement <8 x i64> %v3, i64 %d, i32 31253 %v5 = insertelement <8 x i64> %v4, i64 %a, i32 41254 %v6 = insertelement <8 x i64> %v5, i64 %b, i32 51255 %v7 = insertelement <8 x i64> %v6, i64 %c, i32 61256 %v8 = insertelement <8 x i64> %v7, i64 %d, i32 71257 ret <8 x i64> %v81258}1259 1260define <8 x i64> @v8xi64_exact_undef_suffix(i64 %a, i64 %b, i64 %c, i64 %d) vscale_range(2,2) {1261; RV32-LABEL: v8xi64_exact_undef_suffix:1262; RV32: # %bb.0:1263; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma1264; RV32-NEXT: vmv.v.x v8, a41265; RV32-NEXT: vmv.v.x v9, a01266; RV32-NEXT: vslide1down.vx v8, v8, a51267; RV32-NEXT: vslide1down.vx v10, v9, a11268; RV32-NEXT: vslide1down.vx v8, v8, a61269; RV32-NEXT: vslide1down.vx v9, v8, a71270; RV32-NEXT: vslide1down.vx v8, v10, a21271; RV32-NEXT: vslide1down.vx v8, v8, a31272; RV32-NEXT: ret1273;1274; RV64V-LABEL: v8xi64_exact_undef_suffix:1275; RV64V: # %bb.0:1276; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma1277; RV64V-NEXT: vmv.v.x v8, a21278; RV64V-NEXT: vslide1down.vx v9, v8, a31279; RV64V-NEXT: vmv.v.x v8, a01280; RV64V-NEXT: vslide1down.vx v8, v8, a11281; RV64V-NEXT: ret1282;1283; RV64ZVE32-LABEL: v8xi64_exact_undef_suffix:1284; RV64ZVE32: # %bb.0:1285; RV64ZVE32-NEXT: sd a1, 0(a0)1286; RV64ZVE32-NEXT: sd a2, 8(a0)1287; RV64ZVE32-NEXT: sd a3, 16(a0)1288; RV64ZVE32-NEXT: sd a4, 24(a0)1289; RV64ZVE32-NEXT: ret1290 %v1 = insertelement <8 x i64> poison, i64 %a, i32 01291 %v2 = insertelement <8 x i64> %v1, i64 %b, i32 11292 %v3 = insertelement <8 x i64> %v2, i64 %c, i32 21293 %v4 = insertelement <8 x i64> %v3, i64 %d, i32 31294 ret <8 x i64> %v41295}1296 1297define <8 x i64> @v8xi64_exact_undef_prefix(i64 %a, i64 %b, i64 %c, i64 %d) vscale_range(2,2) {1298; RV32-LABEL: v8xi64_exact_undef_prefix:1299; RV32: # %bb.0:1300; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma1301; RV32-NEXT: vmv.v.x v8, a41302; RV32-NEXT: vmv.v.x v9, a01303; RV32-NEXT: vslide1down.vx v8, v8, a51304; RV32-NEXT: vslide1down.vx v9, v9, a11305; RV32-NEXT: vslide1down.vx v8, v8, a61306; RV32-NEXT: vslide1down.vx v11, v8, a71307; RV32-NEXT: vslide1down.vx v8, v9, a21308; RV32-NEXT: vslide1down.vx v10, v8, a31309; RV32-NEXT: ret1310;1311; RV64V-LABEL: v8xi64_exact_undef_prefix:1312; RV64V: # %bb.0:1313; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma1314; RV64V-NEXT: vmv.v.x v8, a21315; RV64V-NEXT: vslide1down.vx v11, v8, a31316; RV64V-NEXT: vmv.v.x v8, a01317; RV64V-NEXT: vslide1down.vx v10, v8, a11318; RV64V-NEXT: ret1319;1320; RV64ZVE32-LABEL: v8xi64_exact_undef_prefix:1321; RV64ZVE32: # %bb.0:1322; RV64ZVE32-NEXT: sd a1, 32(a0)1323; RV64ZVE32-NEXT: sd a2, 40(a0)1324; RV64ZVE32-NEXT: sd a3, 48(a0)1325; RV64ZVE32-NEXT: sd a4, 56(a0)1326; RV64ZVE32-NEXT: ret1327 %v1 = insertelement <8 x i64> poison, i64 %a, i32 41328 %v2 = insertelement <8 x i64> %v1, i64 %b, i32 51329 %v3 = insertelement <8 x i64> %v2, i64 %c, i32 61330 %v4 = insertelement <8 x i64> %v3, i64 %d, i32 71331 ret <8 x i64> %v41332}1333 1334 1335define <16 x i8> @buildvec_v16i8_loads_contigous(ptr %p) {1336; RV32-ONLY-LABEL: buildvec_v16i8_loads_contigous:1337; RV32-ONLY: # %bb.0:1338; RV32-ONLY-NEXT: addi sp, sp, -161339; RV32-ONLY-NEXT: .cfi_def_cfa_offset 161340; RV32-ONLY-NEXT: sw s0, 12(sp) # 4-byte Folded Spill1341; RV32-ONLY-NEXT: .cfi_offset s0, -41342; RV32-ONLY-NEXT: lbu a1, 0(a0)1343; RV32-ONLY-NEXT: lbu a2, 1(a0)1344; RV32-ONLY-NEXT: lbu a3, 2(a0)1345; RV32-ONLY-NEXT: lbu a4, 3(a0)1346; RV32-ONLY-NEXT: lbu a5, 4(a0)1347; RV32-ONLY-NEXT: lbu a6, 5(a0)1348; RV32-ONLY-NEXT: lbu a7, 6(a0)1349; RV32-ONLY-NEXT: lbu t0, 7(a0)1350; RV32-ONLY-NEXT: lbu t1, 8(a0)1351; RV32-ONLY-NEXT: lbu t2, 9(a0)1352; RV32-ONLY-NEXT: lbu t3, 10(a0)1353; RV32-ONLY-NEXT: lbu t4, 11(a0)1354; RV32-ONLY-NEXT: li t5, 2551355; RV32-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma1356; RV32-ONLY-NEXT: vmv.s.x v0, t51357; RV32-ONLY-NEXT: lbu t5, 12(a0)1358; RV32-ONLY-NEXT: lbu t6, 13(a0)1359; RV32-ONLY-NEXT: lbu s0, 14(a0)1360; RV32-ONLY-NEXT: lbu a0, 15(a0)1361; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu1362; RV32-ONLY-NEXT: vmv.v.x v8, t11363; RV32-ONLY-NEXT: vmv.v.x v9, a11364; RV32-ONLY-NEXT: vslide1down.vx v8, v8, t21365; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a21366; RV32-ONLY-NEXT: vslide1down.vx v8, v8, t31367; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a31368; RV32-ONLY-NEXT: vslide1down.vx v8, v8, t41369; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a41370; RV32-ONLY-NEXT: vslide1down.vx v8, v8, t51371; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a51372; RV32-ONLY-NEXT: vslide1down.vx v8, v8, t61373; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a61374; RV32-ONLY-NEXT: vslide1down.vx v8, v8, s01375; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a71376; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a01377; RV32-ONLY-NEXT: vslide1down.vx v9, v9, t01378; RV32-ONLY-NEXT: vslidedown.vi v8, v9, 8, v0.t1379; RV32-ONLY-NEXT: lw s0, 12(sp) # 4-byte Folded Reload1380; RV32-ONLY-NEXT: .cfi_restore s01381; RV32-ONLY-NEXT: addi sp, sp, 161382; RV32-ONLY-NEXT: .cfi_def_cfa_offset 01383; RV32-ONLY-NEXT: ret1384;1385; RV32VB-LABEL: buildvec_v16i8_loads_contigous:1386; RV32VB: # %bb.0:1387; RV32VB-NEXT: lbu a1, 0(a0)1388; RV32VB-NEXT: lbu a2, 1(a0)1389; RV32VB-NEXT: lbu a3, 2(a0)1390; RV32VB-NEXT: lbu a4, 3(a0)1391; RV32VB-NEXT: lbu a5, 4(a0)1392; RV32VB-NEXT: lbu a6, 5(a0)1393; RV32VB-NEXT: lbu a7, 6(a0)1394; RV32VB-NEXT: lbu t0, 7(a0)1395; RV32VB-NEXT: slli a2, a2, 81396; RV32VB-NEXT: slli a3, a3, 161397; RV32VB-NEXT: slli a4, a4, 241398; RV32VB-NEXT: slli a6, a6, 81399; RV32VB-NEXT: or a1, a1, a21400; RV32VB-NEXT: or a3, a4, a31401; RV32VB-NEXT: or a2, a5, a61402; RV32VB-NEXT: lbu a4, 8(a0)1403; RV32VB-NEXT: lbu a5, 9(a0)1404; RV32VB-NEXT: lbu a6, 10(a0)1405; RV32VB-NEXT: lbu t1, 11(a0)1406; RV32VB-NEXT: slli a7, a7, 161407; RV32VB-NEXT: slli t0, t0, 241408; RV32VB-NEXT: slli a5, a5, 81409; RV32VB-NEXT: slli a6, a6, 161410; RV32VB-NEXT: slli t1, t1, 241411; RV32VB-NEXT: or a7, t0, a71412; RV32VB-NEXT: or a4, a4, a51413; RV32VB-NEXT: or a5, t1, a61414; RV32VB-NEXT: lbu a6, 13(a0)1415; RV32VB-NEXT: lbu t0, 12(a0)1416; RV32VB-NEXT: lbu t1, 14(a0)1417; RV32VB-NEXT: lbu a0, 15(a0)1418; RV32VB-NEXT: slli a6, a6, 81419; RV32VB-NEXT: or a6, t0, a61420; RV32VB-NEXT: slli t1, t1, 161421; RV32VB-NEXT: slli a0, a0, 241422; RV32VB-NEXT: or a0, a0, t11423; RV32VB-NEXT: or a1, a1, a31424; RV32VB-NEXT: or a2, a2, a71425; RV32VB-NEXT: or a4, a4, a51426; RV32VB-NEXT: or a0, a6, a01427; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma1428; RV32VB-NEXT: vmv.v.x v8, a11429; RV32VB-NEXT: vslide1down.vx v8, v8, a21430; RV32VB-NEXT: vslide1down.vx v8, v8, a41431; RV32VB-NEXT: vslide1down.vx v8, v8, a01432; RV32VB-NEXT: ret1433;1434; RV32VB-PACK-LABEL: buildvec_v16i8_loads_contigous:1435; RV32VB-PACK: # %bb.0:1436; RV32VB-PACK-NEXT: lbu a1, 0(a0)1437; RV32VB-PACK-NEXT: lbu a2, 1(a0)1438; RV32VB-PACK-NEXT: lbu a3, 2(a0)1439; RV32VB-PACK-NEXT: lbu a4, 3(a0)1440; RV32VB-PACK-NEXT: lbu a5, 4(a0)1441; RV32VB-PACK-NEXT: lbu a6, 5(a0)1442; RV32VB-PACK-NEXT: lbu a7, 6(a0)1443; RV32VB-PACK-NEXT: lbu t0, 7(a0)1444; RV32VB-PACK-NEXT: packh a1, a1, a21445; RV32VB-PACK-NEXT: lbu a2, 8(a0)1446; RV32VB-PACK-NEXT: lbu t1, 9(a0)1447; RV32VB-PACK-NEXT: lbu t2, 10(a0)1448; RV32VB-PACK-NEXT: lbu t3, 11(a0)1449; RV32VB-PACK-NEXT: packh a3, a3, a41450; RV32VB-PACK-NEXT: packh a4, a5, a61451; RV32VB-PACK-NEXT: packh a5, a7, t01452; RV32VB-PACK-NEXT: lbu a6, 12(a0)1453; RV32VB-PACK-NEXT: lbu a7, 13(a0)1454; RV32VB-PACK-NEXT: lbu t0, 14(a0)1455; RV32VB-PACK-NEXT: lbu a0, 15(a0)1456; RV32VB-PACK-NEXT: packh a2, a2, t11457; RV32VB-PACK-NEXT: packh t1, t2, t31458; RV32VB-PACK-NEXT: packh a6, a6, a71459; RV32VB-PACK-NEXT: packh a0, t0, a01460; RV32VB-PACK-NEXT: pack a1, a1, a31461; RV32VB-PACK-NEXT: pack a3, a4, a51462; RV32VB-PACK-NEXT: pack a2, a2, t11463; RV32VB-PACK-NEXT: pack a0, a6, a01464; RV32VB-PACK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1465; RV32VB-PACK-NEXT: vmv.v.x v8, a11466; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a31467; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a21468; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a01469; RV32VB-PACK-NEXT: ret1470;1471; RV64V-ONLY-LABEL: buildvec_v16i8_loads_contigous:1472; RV64V-ONLY: # %bb.0:1473; RV64V-ONLY-NEXT: addi sp, sp, -161474; RV64V-ONLY-NEXT: .cfi_def_cfa_offset 161475; RV64V-ONLY-NEXT: sd s0, 8(sp) # 8-byte Folded Spill1476; RV64V-ONLY-NEXT: .cfi_offset s0, -81477; RV64V-ONLY-NEXT: lbu a1, 0(a0)1478; RV64V-ONLY-NEXT: lbu a2, 1(a0)1479; RV64V-ONLY-NEXT: lbu a3, 2(a0)1480; RV64V-ONLY-NEXT: lbu a4, 3(a0)1481; RV64V-ONLY-NEXT: lbu a5, 4(a0)1482; RV64V-ONLY-NEXT: lbu a6, 5(a0)1483; RV64V-ONLY-NEXT: lbu a7, 6(a0)1484; RV64V-ONLY-NEXT: lbu t0, 7(a0)1485; RV64V-ONLY-NEXT: lbu t1, 8(a0)1486; RV64V-ONLY-NEXT: lbu t2, 9(a0)1487; RV64V-ONLY-NEXT: lbu t3, 10(a0)1488; RV64V-ONLY-NEXT: lbu t4, 11(a0)1489; RV64V-ONLY-NEXT: li t5, 2551490; RV64V-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma1491; RV64V-ONLY-NEXT: vmv.s.x v0, t51492; RV64V-ONLY-NEXT: lbu t5, 12(a0)1493; RV64V-ONLY-NEXT: lbu t6, 13(a0)1494; RV64V-ONLY-NEXT: lbu s0, 14(a0)1495; RV64V-ONLY-NEXT: lbu a0, 15(a0)1496; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu1497; RV64V-ONLY-NEXT: vmv.v.x v8, t11498; RV64V-ONLY-NEXT: vmv.v.x v9, a11499; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, t21500; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a21501; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, t31502; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a31503; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, t41504; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a41505; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, t51506; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a51507; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, t61508; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a61509; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, s01510; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a71511; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a01512; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, t01513; RV64V-ONLY-NEXT: vslidedown.vi v8, v9, 8, v0.t1514; RV64V-ONLY-NEXT: ld s0, 8(sp) # 8-byte Folded Reload1515; RV64V-ONLY-NEXT: .cfi_restore s01516; RV64V-ONLY-NEXT: addi sp, sp, 161517; RV64V-ONLY-NEXT: .cfi_def_cfa_offset 01518; RV64V-ONLY-NEXT: ret1519;1520; RVA22U64-LABEL: buildvec_v16i8_loads_contigous:1521; RVA22U64: # %bb.0:1522; RVA22U64-NEXT: lbu a6, 0(a0)1523; RVA22U64-NEXT: lbu a2, 1(a0)1524; RVA22U64-NEXT: lbu a3, 2(a0)1525; RVA22U64-NEXT: lbu a4, 3(a0)1526; RVA22U64-NEXT: lbu a5, 4(a0)1527; RVA22U64-NEXT: lbu a1, 5(a0)1528; RVA22U64-NEXT: lbu a7, 6(a0)1529; RVA22U64-NEXT: lbu t0, 7(a0)1530; RVA22U64-NEXT: slli a2, a2, 81531; RVA22U64-NEXT: slli a3, a3, 161532; RVA22U64-NEXT: slli a4, a4, 241533; RVA22U64-NEXT: slli a5, a5, 321534; RVA22U64-NEXT: slli a1, a1, 401535; RVA22U64-NEXT: or a6, a6, a21536; RVA22U64-NEXT: or t2, a4, a31537; RVA22U64-NEXT: or t1, a1, a51538; RVA22U64-NEXT: lbu a4, 8(a0)1539; RVA22U64-NEXT: lbu a5, 9(a0)1540; RVA22U64-NEXT: lbu a2, 10(a0)1541; RVA22U64-NEXT: lbu a1, 11(a0)1542; RVA22U64-NEXT: slli a7, a7, 481543; RVA22U64-NEXT: slli t0, t0, 561544; RVA22U64-NEXT: slli a5, a5, 81545; RVA22U64-NEXT: slli a2, a2, 161546; RVA22U64-NEXT: slli a1, a1, 241547; RVA22U64-NEXT: or a7, t0, a71548; RVA22U64-NEXT: or a4, a4, a51549; RVA22U64-NEXT: or a1, a1, a21550; RVA22U64-NEXT: lbu a2, 12(a0)1551; RVA22U64-NEXT: lbu a5, 13(a0)1552; RVA22U64-NEXT: lbu a3, 14(a0)1553; RVA22U64-NEXT: lbu a0, 15(a0)1554; RVA22U64-NEXT: slli a2, a2, 321555; RVA22U64-NEXT: slli a5, a5, 401556; RVA22U64-NEXT: or a2, a2, a51557; RVA22U64-NEXT: slli a3, a3, 481558; RVA22U64-NEXT: slli a0, a0, 561559; RVA22U64-NEXT: or a0, a0, a31560; RVA22U64-NEXT: or a3, a6, t21561; RVA22U64-NEXT: or a5, a7, t11562; RVA22U64-NEXT: or a1, a1, a41563; RVA22U64-NEXT: or a0, a0, a21564; RVA22U64-NEXT: or a3, a3, a51565; RVA22U64-NEXT: or a0, a0, a11566; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma1567; RVA22U64-NEXT: vmv.v.x v8, a31568; RVA22U64-NEXT: vslide1down.vx v8, v8, a01569; RVA22U64-NEXT: ret1570;1571; RVA22U64-PACK-LABEL: buildvec_v16i8_loads_contigous:1572; RVA22U64-PACK: # %bb.0:1573; RVA22U64-PACK-NEXT: lbu a1, 0(a0)1574; RVA22U64-PACK-NEXT: lbu a2, 1(a0)1575; RVA22U64-PACK-NEXT: lbu a6, 2(a0)1576; RVA22U64-PACK-NEXT: lbu a7, 3(a0)1577; RVA22U64-PACK-NEXT: lbu t0, 4(a0)1578; RVA22U64-PACK-NEXT: lbu a3, 5(a0)1579; RVA22U64-PACK-NEXT: lbu a4, 6(a0)1580; RVA22U64-PACK-NEXT: lbu a5, 7(a0)1581; RVA22U64-PACK-NEXT: packh t1, a1, a21582; RVA22U64-PACK-NEXT: lbu t2, 8(a0)1583; RVA22U64-PACK-NEXT: lbu t3, 9(a0)1584; RVA22U64-PACK-NEXT: lbu t4, 10(a0)1585; RVA22U64-PACK-NEXT: lbu a1, 11(a0)1586; RVA22U64-PACK-NEXT: packh a6, a6, a71587; RVA22U64-PACK-NEXT: packh a7, t0, a31588; RVA22U64-PACK-NEXT: packh t0, a4, a51589; RVA22U64-PACK-NEXT: lbu a5, 12(a0)1590; RVA22U64-PACK-NEXT: lbu a3, 13(a0)1591; RVA22U64-PACK-NEXT: lbu a2, 14(a0)1592; RVA22U64-PACK-NEXT: lbu a0, 15(a0)1593; RVA22U64-PACK-NEXT: packh a4, t2, t31594; RVA22U64-PACK-NEXT: packh a1, t4, a11595; RVA22U64-PACK-NEXT: packh a3, a5, a31596; RVA22U64-PACK-NEXT: packh a0, a2, a01597; RVA22U64-PACK-NEXT: packw a2, t1, a61598; RVA22U64-PACK-NEXT: packw a5, a7, t01599; RVA22U64-PACK-NEXT: packw a1, a4, a11600; RVA22U64-PACK-NEXT: packw a0, a3, a01601; RVA22U64-PACK-NEXT: pack a2, a2, a51602; RVA22U64-PACK-NEXT: pack a0, a1, a01603; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma1604; RVA22U64-PACK-NEXT: vmv.v.x v8, a21605; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a01606; RVA22U64-PACK-NEXT: ret1607;1608; RV64ZVE32-LABEL: buildvec_v16i8_loads_contigous:1609; RV64ZVE32: # %bb.0:1610; RV64ZVE32-NEXT: addi sp, sp, -161611; RV64ZVE32-NEXT: .cfi_def_cfa_offset 161612; RV64ZVE32-NEXT: sd s0, 8(sp) # 8-byte Folded Spill1613; RV64ZVE32-NEXT: .cfi_offset s0, -81614; RV64ZVE32-NEXT: lbu a1, 0(a0)1615; RV64ZVE32-NEXT: lbu a2, 1(a0)1616; RV64ZVE32-NEXT: lbu a3, 2(a0)1617; RV64ZVE32-NEXT: lbu a4, 3(a0)1618; RV64ZVE32-NEXT: lbu a5, 4(a0)1619; RV64ZVE32-NEXT: lbu a6, 5(a0)1620; RV64ZVE32-NEXT: lbu a7, 6(a0)1621; RV64ZVE32-NEXT: lbu t0, 7(a0)1622; RV64ZVE32-NEXT: lbu t1, 8(a0)1623; RV64ZVE32-NEXT: lbu t2, 9(a0)1624; RV64ZVE32-NEXT: lbu t3, 10(a0)1625; RV64ZVE32-NEXT: lbu t4, 11(a0)1626; RV64ZVE32-NEXT: li t5, 2551627; RV64ZVE32-NEXT: vsetivli zero, 1, e16, m1, ta, ma1628; RV64ZVE32-NEXT: vmv.s.x v0, t51629; RV64ZVE32-NEXT: lbu t5, 12(a0)1630; RV64ZVE32-NEXT: lbu t6, 13(a0)1631; RV64ZVE32-NEXT: lbu s0, 14(a0)1632; RV64ZVE32-NEXT: lbu a0, 15(a0)1633; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, mu1634; RV64ZVE32-NEXT: vmv.v.x v8, t11635; RV64ZVE32-NEXT: vmv.v.x v9, a11636; RV64ZVE32-NEXT: vslide1down.vx v8, v8, t21637; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a21638; RV64ZVE32-NEXT: vslide1down.vx v8, v8, t31639; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a31640; RV64ZVE32-NEXT: vslide1down.vx v8, v8, t41641; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a41642; RV64ZVE32-NEXT: vslide1down.vx v8, v8, t51643; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a51644; RV64ZVE32-NEXT: vslide1down.vx v8, v8, t61645; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a61646; RV64ZVE32-NEXT: vslide1down.vx v8, v8, s01647; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a71648; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a01649; RV64ZVE32-NEXT: vslide1down.vx v9, v9, t01650; RV64ZVE32-NEXT: vslidedown.vi v8, v9, 8, v0.t1651; RV64ZVE32-NEXT: ld s0, 8(sp) # 8-byte Folded Reload1652; RV64ZVE32-NEXT: .cfi_restore s01653; RV64ZVE32-NEXT: addi sp, sp, 161654; RV64ZVE32-NEXT: .cfi_def_cfa_offset 01655; RV64ZVE32-NEXT: ret1656 %p2 = getelementptr i8, ptr %p, i32 11657 %p3 = getelementptr i8, ptr %p, i32 21658 %p4 = getelementptr i8, ptr %p, i32 31659 %p5 = getelementptr i8, ptr %p, i32 41660 %p6 = getelementptr i8, ptr %p, i32 51661 %p7 = getelementptr i8, ptr %p, i32 61662 %p8 = getelementptr i8, ptr %p, i32 71663 %p9 = getelementptr i8, ptr %p, i32 81664 %p10 = getelementptr i8, ptr %p, i32 91665 %p11 = getelementptr i8, ptr %p, i32 101666 %p12 = getelementptr i8, ptr %p, i32 111667 %p13 = getelementptr i8, ptr %p, i32 121668 %p14 = getelementptr i8, ptr %p, i32 131669 %p15 = getelementptr i8, ptr %p, i32 141670 %p16 = getelementptr i8, ptr %p, i32 151671 1672 %ld1 = load i8, ptr %p1673 %ld2 = load i8, ptr %p21674 %ld3 = load i8, ptr %p31675 %ld4 = load i8, ptr %p41676 %ld5 = load i8, ptr %p51677 %ld6 = load i8, ptr %p61678 %ld7 = load i8, ptr %p71679 %ld8 = load i8, ptr %p81680 %ld9 = load i8, ptr %p91681 %ld10 = load i8, ptr %p101682 %ld11 = load i8, ptr %p111683 %ld12 = load i8, ptr %p121684 %ld13 = load i8, ptr %p131685 %ld14 = load i8, ptr %p141686 %ld15 = load i8, ptr %p151687 %ld16 = load i8, ptr %p161688 1689 %v1 = insertelement <16 x i8> poison, i8 %ld1, i32 01690 %v2 = insertelement <16 x i8> %v1, i8 %ld2, i32 11691 %v3 = insertelement <16 x i8> %v2, i8 %ld3, i32 21692 %v4 = insertelement <16 x i8> %v3, i8 %ld4, i32 31693 %v5 = insertelement <16 x i8> %v4, i8 %ld5, i32 41694 %v6 = insertelement <16 x i8> %v5, i8 %ld6, i32 51695 %v7 = insertelement <16 x i8> %v6, i8 %ld7, i32 61696 %v8 = insertelement <16 x i8> %v7, i8 %ld8, i32 71697 %v9 = insertelement <16 x i8> %v8, i8 %ld9, i32 81698 %v10 = insertelement <16 x i8> %v9, i8 %ld10, i32 91699 %v11 = insertelement <16 x i8> %v10, i8 %ld11, i32 101700 %v12 = insertelement <16 x i8> %v11, i8 %ld12, i32 111701 %v13 = insertelement <16 x i8> %v12, i8 %ld13, i32 121702 %v14 = insertelement <16 x i8> %v13, i8 %ld14, i32 131703 %v15 = insertelement <16 x i8> %v14, i8 %ld15, i32 141704 %v16 = insertelement <16 x i8> %v15, i8 %ld16, i32 151705 ret <16 x i8> %v161706}1707 1708 1709define <16 x i8> @buildvec_v16i8_loads_gather(ptr %p) {1710; RV32-ONLY-LABEL: buildvec_v16i8_loads_gather:1711; RV32-ONLY: # %bb.0:1712; RV32-ONLY-NEXT: addi sp, sp, -161713; RV32-ONLY-NEXT: .cfi_def_cfa_offset 161714; RV32-ONLY-NEXT: sw s0, 12(sp) # 4-byte Folded Spill1715; RV32-ONLY-NEXT: .cfi_offset s0, -41716; RV32-ONLY-NEXT: lbu a1, 0(a0)1717; RV32-ONLY-NEXT: lbu a2, 1(a0)1718; RV32-ONLY-NEXT: lbu a3, 22(a0)1719; RV32-ONLY-NEXT: lbu a4, 31(a0)1720; RV32-ONLY-NEXT: lbu a5, 623(a0)1721; RV32-ONLY-NEXT: lbu a6, 44(a0)1722; RV32-ONLY-NEXT: lbu a7, 55(a0)1723; RV32-ONLY-NEXT: lbu t0, 75(a0)1724; RV32-ONLY-NEXT: lbu t1, 82(a0)1725; RV32-ONLY-NEXT: lbu t2, 154(a0)1726; RV32-ONLY-NEXT: lbu t3, 161(a0)1727; RV32-ONLY-NEXT: lbu t4, 163(a0)1728; RV32-ONLY-NEXT: li t5, 2551729; RV32-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma1730; RV32-ONLY-NEXT: vmv.s.x v0, t51731; RV32-ONLY-NEXT: lbu t5, 93(a0)1732; RV32-ONLY-NEXT: lbu t6, 105(a0)1733; RV32-ONLY-NEXT: lbu s0, 124(a0)1734; RV32-ONLY-NEXT: lbu a0, 144(a0)1735; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu1736; RV32-ONLY-NEXT: vmv.v.x v8, t11737; RV32-ONLY-NEXT: vmv.v.x v9, a11738; RV32-ONLY-NEXT: vslide1down.vx v8, v8, t51739; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a21740; RV32-ONLY-NEXT: vslide1down.vx v8, v8, t61741; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a31742; RV32-ONLY-NEXT: vslide1down.vx v8, v8, t31743; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a41744; RV32-ONLY-NEXT: vslide1down.vx v8, v8, s01745; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a61746; RV32-ONLY-NEXT: vslide1down.vx v8, v8, t41747; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a71748; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a01749; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a51750; RV32-ONLY-NEXT: vslide1down.vx v8, v8, t21751; RV32-ONLY-NEXT: vslide1down.vx v9, v9, t01752; RV32-ONLY-NEXT: vslidedown.vi v8, v9, 8, v0.t1753; RV32-ONLY-NEXT: lw s0, 12(sp) # 4-byte Folded Reload1754; RV32-ONLY-NEXT: .cfi_restore s01755; RV32-ONLY-NEXT: addi sp, sp, 161756; RV32-ONLY-NEXT: .cfi_def_cfa_offset 01757; RV32-ONLY-NEXT: ret1758;1759; RV32VB-LABEL: buildvec_v16i8_loads_gather:1760; RV32VB: # %bb.0:1761; RV32VB-NEXT: lbu a1, 0(a0)1762; RV32VB-NEXT: lbu a2, 1(a0)1763; RV32VB-NEXT: lbu a3, 22(a0)1764; RV32VB-NEXT: lbu a4, 31(a0)1765; RV32VB-NEXT: lbu a5, 623(a0)1766; RV32VB-NEXT: lbu a6, 44(a0)1767; RV32VB-NEXT: lbu a7, 55(a0)1768; RV32VB-NEXT: lbu t0, 75(a0)1769; RV32VB-NEXT: lbu t1, 82(a0)1770; RV32VB-NEXT: slli a2, a2, 81771; RV32VB-NEXT: slli a3, a3, 161772; RV32VB-NEXT: slli a4, a4, 241773; RV32VB-NEXT: slli a7, a7, 81774; RV32VB-NEXT: or a1, a1, a21775; RV32VB-NEXT: or a3, a4, a31776; RV32VB-NEXT: or a2, a6, a71777; RV32VB-NEXT: lbu a4, 93(a0)1778; RV32VB-NEXT: lbu a6, 105(a0)1779; RV32VB-NEXT: lbu a7, 124(a0)1780; RV32VB-NEXT: lbu t2, 144(a0)1781; RV32VB-NEXT: slli a5, a5, 161782; RV32VB-NEXT: slli t0, t0, 241783; RV32VB-NEXT: slli a4, a4, 81784; RV32VB-NEXT: or a5, t0, a51785; RV32VB-NEXT: or a4, t1, a41786; RV32VB-NEXT: lbu t0, 161(a0)1787; RV32VB-NEXT: lbu t1, 154(a0)1788; RV32VB-NEXT: lbu a0, 163(a0)1789; RV32VB-NEXT: slli a6, a6, 161790; RV32VB-NEXT: slli t0, t0, 241791; RV32VB-NEXT: or a6, t0, a61792; RV32VB-NEXT: slli a0, a0, 81793; RV32VB-NEXT: or a0, a7, a01794; RV32VB-NEXT: slli t2, t2, 161795; RV32VB-NEXT: slli t1, t1, 241796; RV32VB-NEXT: or a7, t1, t21797; RV32VB-NEXT: or a1, a1, a31798; RV32VB-NEXT: or a2, a2, a51799; RV32VB-NEXT: or a3, a4, a61800; RV32VB-NEXT: or a0, a0, a71801; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma1802; RV32VB-NEXT: vmv.v.x v8, a11803; RV32VB-NEXT: vslide1down.vx v8, v8, a21804; RV32VB-NEXT: vslide1down.vx v8, v8, a31805; RV32VB-NEXT: vslide1down.vx v8, v8, a01806; RV32VB-NEXT: ret1807;1808; RV32VB-PACK-LABEL: buildvec_v16i8_loads_gather:1809; RV32VB-PACK: # %bb.0:1810; RV32VB-PACK-NEXT: lbu a1, 0(a0)1811; RV32VB-PACK-NEXT: lbu a2, 1(a0)1812; RV32VB-PACK-NEXT: lbu a3, 22(a0)1813; RV32VB-PACK-NEXT: lbu a4, 31(a0)1814; RV32VB-PACK-NEXT: lbu a5, 623(a0)1815; RV32VB-PACK-NEXT: lbu a6, 44(a0)1816; RV32VB-PACK-NEXT: lbu a7, 55(a0)1817; RV32VB-PACK-NEXT: lbu t0, 75(a0)1818; RV32VB-PACK-NEXT: lbu t1, 82(a0)1819; RV32VB-PACK-NEXT: packh a1, a1, a21820; RV32VB-PACK-NEXT: lbu a2, 154(a0)1821; RV32VB-PACK-NEXT: lbu t2, 161(a0)1822; RV32VB-PACK-NEXT: lbu t3, 163(a0)1823; RV32VB-PACK-NEXT: packh a3, a3, a41824; RV32VB-PACK-NEXT: packh a4, a6, a71825; RV32VB-PACK-NEXT: packh a5, a5, t01826; RV32VB-PACK-NEXT: lbu a6, 93(a0)1827; RV32VB-PACK-NEXT: lbu a7, 105(a0)1828; RV32VB-PACK-NEXT: lbu t0, 124(a0)1829; RV32VB-PACK-NEXT: lbu a0, 144(a0)1830; RV32VB-PACK-NEXT: packh a6, t1, a61831; RV32VB-PACK-NEXT: packh a7, a7, t21832; RV32VB-PACK-NEXT: packh t0, t0, t31833; RV32VB-PACK-NEXT: packh a0, a0, a21834; RV32VB-PACK-NEXT: pack a1, a1, a31835; RV32VB-PACK-NEXT: pack a2, a4, a51836; RV32VB-PACK-NEXT: pack a3, a6, a71837; RV32VB-PACK-NEXT: pack a0, t0, a01838; RV32VB-PACK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1839; RV32VB-PACK-NEXT: vmv.v.x v8, a11840; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a21841; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a31842; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a01843; RV32VB-PACK-NEXT: ret1844;1845; RV64V-ONLY-LABEL: buildvec_v16i8_loads_gather:1846; RV64V-ONLY: # %bb.0:1847; RV64V-ONLY-NEXT: addi sp, sp, -161848; RV64V-ONLY-NEXT: .cfi_def_cfa_offset 161849; RV64V-ONLY-NEXT: sd s0, 8(sp) # 8-byte Folded Spill1850; RV64V-ONLY-NEXT: .cfi_offset s0, -81851; RV64V-ONLY-NEXT: lbu a1, 0(a0)1852; RV64V-ONLY-NEXT: lbu a2, 1(a0)1853; RV64V-ONLY-NEXT: lbu a3, 22(a0)1854; RV64V-ONLY-NEXT: lbu a4, 31(a0)1855; RV64V-ONLY-NEXT: lbu a5, 623(a0)1856; RV64V-ONLY-NEXT: lbu a6, 44(a0)1857; RV64V-ONLY-NEXT: lbu a7, 55(a0)1858; RV64V-ONLY-NEXT: lbu t0, 75(a0)1859; RV64V-ONLY-NEXT: lbu t1, 82(a0)1860; RV64V-ONLY-NEXT: lbu t2, 154(a0)1861; RV64V-ONLY-NEXT: lbu t3, 161(a0)1862; RV64V-ONLY-NEXT: lbu t4, 163(a0)1863; RV64V-ONLY-NEXT: li t5, 2551864; RV64V-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma1865; RV64V-ONLY-NEXT: vmv.s.x v0, t51866; RV64V-ONLY-NEXT: lbu t5, 93(a0)1867; RV64V-ONLY-NEXT: lbu t6, 105(a0)1868; RV64V-ONLY-NEXT: lbu s0, 124(a0)1869; RV64V-ONLY-NEXT: lbu a0, 144(a0)1870; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu1871; RV64V-ONLY-NEXT: vmv.v.x v8, t11872; RV64V-ONLY-NEXT: vmv.v.x v9, a11873; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, t51874; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a21875; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, t61876; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a31877; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, t31878; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a41879; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, s01880; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a61881; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, t41882; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a71883; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a01884; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a51885; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, t21886; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, t01887; RV64V-ONLY-NEXT: vslidedown.vi v8, v9, 8, v0.t1888; RV64V-ONLY-NEXT: ld s0, 8(sp) # 8-byte Folded Reload1889; RV64V-ONLY-NEXT: .cfi_restore s01890; RV64V-ONLY-NEXT: addi sp, sp, 161891; RV64V-ONLY-NEXT: .cfi_def_cfa_offset 01892; RV64V-ONLY-NEXT: ret1893;1894; RVA22U64-LABEL: buildvec_v16i8_loads_gather:1895; RVA22U64: # %bb.0:1896; RVA22U64-NEXT: lbu a7, 0(a0)1897; RVA22U64-NEXT: lbu a2, 1(a0)1898; RVA22U64-NEXT: lbu a3, 22(a0)1899; RVA22U64-NEXT: lbu a4, 31(a0)1900; RVA22U64-NEXT: lbu a6, 623(a0)1901; RVA22U64-NEXT: lbu a5, 44(a0)1902; RVA22U64-NEXT: lbu a1, 55(a0)1903; RVA22U64-NEXT: lbu t0, 75(a0)1904; RVA22U64-NEXT: lbu t1, 82(a0)1905; RVA22U64-NEXT: slli a2, a2, 81906; RVA22U64-NEXT: slli a3, a3, 161907; RVA22U64-NEXT: slli a4, a4, 241908; RVA22U64-NEXT: slli a5, a5, 321909; RVA22U64-NEXT: slli a1, a1, 401910; RVA22U64-NEXT: or a7, a7, a21911; RVA22U64-NEXT: or t3, a4, a31912; RVA22U64-NEXT: or t2, a1, a51913; RVA22U64-NEXT: lbu a4, 93(a0)1914; RVA22U64-NEXT: lbu t4, 105(a0)1915; RVA22U64-NEXT: lbu a2, 124(a0)1916; RVA22U64-NEXT: lbu t5, 144(a0)1917; RVA22U64-NEXT: slli a6, a6, 481918; RVA22U64-NEXT: slli t0, t0, 561919; RVA22U64-NEXT: slli a4, a4, 81920; RVA22U64-NEXT: or a3, t0, a61921; RVA22U64-NEXT: or a4, t1, a41922; RVA22U64-NEXT: lbu a5, 161(a0)1923; RVA22U64-NEXT: lbu a1, 154(a0)1924; RVA22U64-NEXT: lbu a0, 163(a0)1925; RVA22U64-NEXT: slli t4, t4, 161926; RVA22U64-NEXT: slli a5, a5, 241927; RVA22U64-NEXT: or a5, a5, t41928; RVA22U64-NEXT: slli a2, a2, 321929; RVA22U64-NEXT: slli a0, a0, 401930; RVA22U64-NEXT: or a0, a0, a21931; RVA22U64-NEXT: slli t5, t5, 481932; RVA22U64-NEXT: slli a1, a1, 561933; RVA22U64-NEXT: or a1, a1, t51934; RVA22U64-NEXT: or a2, a7, t31935; RVA22U64-NEXT: or a3, a3, t21936; RVA22U64-NEXT: or a4, a4, a51937; RVA22U64-NEXT: or a0, a0, a11938; RVA22U64-NEXT: or a2, a2, a31939; RVA22U64-NEXT: or a0, a0, a41940; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma1941; RVA22U64-NEXT: vmv.v.x v8, a21942; RVA22U64-NEXT: vslide1down.vx v8, v8, a01943; RVA22U64-NEXT: ret1944;1945; RVA22U64-PACK-LABEL: buildvec_v16i8_loads_gather:1946; RVA22U64-PACK: # %bb.0:1947; RVA22U64-PACK-NEXT: addi sp, sp, -161948; RVA22U64-PACK-NEXT: .cfi_def_cfa_offset 161949; RVA22U64-PACK-NEXT: sd s0, 8(sp) # 8-byte Folded Spill1950; RVA22U64-PACK-NEXT: .cfi_offset s0, -81951; RVA22U64-PACK-NEXT: lbu a1, 0(a0)1952; RVA22U64-PACK-NEXT: lbu a2, 1(a0)1953; RVA22U64-PACK-NEXT: lbu a6, 22(a0)1954; RVA22U64-PACK-NEXT: lbu a7, 31(a0)1955; RVA22U64-PACK-NEXT: lbu t0, 623(a0)1956; RVA22U64-PACK-NEXT: lbu t3, 44(a0)1957; RVA22U64-PACK-NEXT: lbu t4, 55(a0)1958; RVA22U64-PACK-NEXT: lbu t5, 75(a0)1959; RVA22U64-PACK-NEXT: lbu t1, 82(a0)1960; RVA22U64-PACK-NEXT: packh t2, a1, a21961; RVA22U64-PACK-NEXT: lbu t6, 154(a0)1962; RVA22U64-PACK-NEXT: lbu s0, 161(a0)1963; RVA22U64-PACK-NEXT: lbu a3, 163(a0)1964; RVA22U64-PACK-NEXT: packh a6, a6, a71965; RVA22U64-PACK-NEXT: packh a7, t3, t41966; RVA22U64-PACK-NEXT: packh a2, t0, t51967; RVA22U64-PACK-NEXT: lbu a4, 93(a0)1968; RVA22U64-PACK-NEXT: lbu a5, 105(a0)1969; RVA22U64-PACK-NEXT: lbu a1, 124(a0)1970; RVA22U64-PACK-NEXT: lbu a0, 144(a0)1971; RVA22U64-PACK-NEXT: packh a4, t1, a41972; RVA22U64-PACK-NEXT: packh a5, a5, s01973; RVA22U64-PACK-NEXT: packh a1, a1, a31974; RVA22U64-PACK-NEXT: packh a0, a0, t61975; RVA22U64-PACK-NEXT: packw a3, t2, a61976; RVA22U64-PACK-NEXT: packw a2, a7, a21977; RVA22U64-PACK-NEXT: packw a4, a4, a51978; RVA22U64-PACK-NEXT: packw a0, a1, a01979; RVA22U64-PACK-NEXT: pack a1, a3, a21980; RVA22U64-PACK-NEXT: pack a0, a4, a01981; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma1982; RVA22U64-PACK-NEXT: vmv.v.x v8, a11983; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a01984; RVA22U64-PACK-NEXT: ld s0, 8(sp) # 8-byte Folded Reload1985; RVA22U64-PACK-NEXT: .cfi_restore s01986; RVA22U64-PACK-NEXT: addi sp, sp, 161987; RVA22U64-PACK-NEXT: .cfi_def_cfa_offset 01988; RVA22U64-PACK-NEXT: ret1989;1990; RV64ZVE32-LABEL: buildvec_v16i8_loads_gather:1991; RV64ZVE32: # %bb.0:1992; RV64ZVE32-NEXT: addi sp, sp, -161993; RV64ZVE32-NEXT: .cfi_def_cfa_offset 161994; RV64ZVE32-NEXT: sd s0, 8(sp) # 8-byte Folded Spill1995; RV64ZVE32-NEXT: .cfi_offset s0, -81996; RV64ZVE32-NEXT: lbu a1, 0(a0)1997; RV64ZVE32-NEXT: lbu a2, 1(a0)1998; RV64ZVE32-NEXT: lbu a3, 22(a0)1999; RV64ZVE32-NEXT: lbu a4, 31(a0)2000; RV64ZVE32-NEXT: lbu a5, 623(a0)2001; RV64ZVE32-NEXT: lbu a6, 44(a0)2002; RV64ZVE32-NEXT: lbu a7, 55(a0)2003; RV64ZVE32-NEXT: lbu t0, 75(a0)2004; RV64ZVE32-NEXT: lbu t1, 82(a0)2005; RV64ZVE32-NEXT: lbu t2, 154(a0)2006; RV64ZVE32-NEXT: lbu t3, 161(a0)2007; RV64ZVE32-NEXT: lbu t4, 163(a0)2008; RV64ZVE32-NEXT: li t5, 2552009; RV64ZVE32-NEXT: vsetivli zero, 1, e16, m1, ta, ma2010; RV64ZVE32-NEXT: vmv.s.x v0, t52011; RV64ZVE32-NEXT: lbu t5, 93(a0)2012; RV64ZVE32-NEXT: lbu t6, 105(a0)2013; RV64ZVE32-NEXT: lbu s0, 124(a0)2014; RV64ZVE32-NEXT: lbu a0, 144(a0)2015; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, mu2016; RV64ZVE32-NEXT: vmv.v.x v8, t12017; RV64ZVE32-NEXT: vmv.v.x v9, a12018; RV64ZVE32-NEXT: vslide1down.vx v8, v8, t52019; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a22020; RV64ZVE32-NEXT: vslide1down.vx v8, v8, t62021; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a32022; RV64ZVE32-NEXT: vslide1down.vx v8, v8, t32023; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a42024; RV64ZVE32-NEXT: vslide1down.vx v8, v8, s02025; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a62026; RV64ZVE32-NEXT: vslide1down.vx v8, v8, t42027; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a72028; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a02029; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a52030; RV64ZVE32-NEXT: vslide1down.vx v8, v8, t22031; RV64ZVE32-NEXT: vslide1down.vx v9, v9, t02032; RV64ZVE32-NEXT: vslidedown.vi v8, v9, 8, v0.t2033; RV64ZVE32-NEXT: ld s0, 8(sp) # 8-byte Folded Reload2034; RV64ZVE32-NEXT: .cfi_restore s02035; RV64ZVE32-NEXT: addi sp, sp, 162036; RV64ZVE32-NEXT: .cfi_def_cfa_offset 02037; RV64ZVE32-NEXT: ret2038 %p2 = getelementptr i8, ptr %p, i32 12039 %p3 = getelementptr i8, ptr %p, i32 222040 %p4 = getelementptr i8, ptr %p, i32 312041 %p5 = getelementptr i8, ptr %p, i32 442042 %p6 = getelementptr i8, ptr %p, i32 552043 %p7 = getelementptr i8, ptr %p, i32 6232044 %p8 = getelementptr i8, ptr %p, i32 752045 %p9 = getelementptr i8, ptr %p, i32 822046 %p10 = getelementptr i8, ptr %p, i32 932047 %p11 = getelementptr i8, ptr %p, i32 1052048 %p12 = getelementptr i8, ptr %p, i32 1612049 %p13 = getelementptr i8, ptr %p, i32 1242050 %p14 = getelementptr i8, ptr %p, i32 1632051 %p15 = getelementptr i8, ptr %p, i32 1442052 %p16 = getelementptr i8, ptr %p, i32 1542053 2054 %ld1 = load i8, ptr %p2055 %ld2 = load i8, ptr %p22056 %ld3 = load i8, ptr %p32057 %ld4 = load i8, ptr %p42058 %ld5 = load i8, ptr %p52059 %ld6 = load i8, ptr %p62060 %ld7 = load i8, ptr %p72061 %ld8 = load i8, ptr %p82062 %ld9 = load i8, ptr %p92063 %ld10 = load i8, ptr %p102064 %ld11 = load i8, ptr %p112065 %ld12 = load i8, ptr %p122066 %ld13 = load i8, ptr %p132067 %ld14 = load i8, ptr %p142068 %ld15 = load i8, ptr %p152069 %ld16 = load i8, ptr %p162070 2071 %v1 = insertelement <16 x i8> poison, i8 %ld1, i32 02072 %v2 = insertelement <16 x i8> %v1, i8 %ld2, i32 12073 %v3 = insertelement <16 x i8> %v2, i8 %ld3, i32 22074 %v4 = insertelement <16 x i8> %v3, i8 %ld4, i32 32075 %v5 = insertelement <16 x i8> %v4, i8 %ld5, i32 42076 %v6 = insertelement <16 x i8> %v5, i8 %ld6, i32 52077 %v7 = insertelement <16 x i8> %v6, i8 %ld7, i32 62078 %v8 = insertelement <16 x i8> %v7, i8 %ld8, i32 72079 %v9 = insertelement <16 x i8> %v8, i8 %ld9, i32 82080 %v10 = insertelement <16 x i8> %v9, i8 %ld10, i32 92081 %v11 = insertelement <16 x i8> %v10, i8 %ld11, i32 102082 %v12 = insertelement <16 x i8> %v11, i8 %ld12, i32 112083 %v13 = insertelement <16 x i8> %v12, i8 %ld13, i32 122084 %v14 = insertelement <16 x i8> %v13, i8 %ld14, i32 132085 %v15 = insertelement <16 x i8> %v14, i8 %ld15, i32 142086 %v16 = insertelement <16 x i8> %v15, i8 %ld16, i32 152087 ret <16 x i8> %v162088}2089 2090define <16 x i8> @buildvec_v16i8_undef_low_half(ptr %p) {2091; RV32-ONLY-LABEL: buildvec_v16i8_undef_low_half:2092; RV32-ONLY: # %bb.0:2093; RV32-ONLY-NEXT: lbu a1, 82(a0)2094; RV32-ONLY-NEXT: lbu a2, 93(a0)2095; RV32-ONLY-NEXT: lbu a3, 105(a0)2096; RV32-ONLY-NEXT: lbu a4, 124(a0)2097; RV32-ONLY-NEXT: lbu a5, 144(a0)2098; RV32-ONLY-NEXT: lbu a6, 154(a0)2099; RV32-ONLY-NEXT: lbu a7, 161(a0)2100; RV32-ONLY-NEXT: lbu a0, 163(a0)2101; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, ma2102; RV32-ONLY-NEXT: vmv.v.x v8, a12103; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a22104; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a32105; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a72106; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a42107; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a02108; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a52109; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a62110; RV32-ONLY-NEXT: ret2111;2112; RV32VB-LABEL: buildvec_v16i8_undef_low_half:2113; RV32VB: # %bb.0:2114; RV32VB-NEXT: lbu a1, 93(a0)2115; RV32VB-NEXT: lbu a2, 82(a0)2116; RV32VB-NEXT: lbu a3, 105(a0)2117; RV32VB-NEXT: lbu a4, 124(a0)2118; RV32VB-NEXT: slli a1, a1, 82119; RV32VB-NEXT: or a1, a2, a12120; RV32VB-NEXT: lbu a2, 161(a0)2121; RV32VB-NEXT: lbu a5, 144(a0)2122; RV32VB-NEXT: lbu a6, 154(a0)2123; RV32VB-NEXT: lbu a0, 163(a0)2124; RV32VB-NEXT: slli a3, a3, 162125; RV32VB-NEXT: slli a2, a2, 242126; RV32VB-NEXT: or a2, a2, a32127; RV32VB-NEXT: slli a0, a0, 82128; RV32VB-NEXT: or a0, a4, a02129; RV32VB-NEXT: slli a5, a5, 162130; RV32VB-NEXT: slli a6, a6, 242131; RV32VB-NEXT: or a3, a6, a52132; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma2133; RV32VB-NEXT: vmv.v.i v8, 02134; RV32VB-NEXT: or a1, a1, a22135; RV32VB-NEXT: or a0, a0, a32136; RV32VB-NEXT: vslide1down.vx v8, v8, zero2137; RV32VB-NEXT: vslide1down.vx v8, v8, a12138; RV32VB-NEXT: vslide1down.vx v8, v8, a02139; RV32VB-NEXT: ret2140;2141; RV32VB-PACK-LABEL: buildvec_v16i8_undef_low_half:2142; RV32VB-PACK: # %bb.0:2143; RV32VB-PACK-NEXT: lbu a1, 82(a0)2144; RV32VB-PACK-NEXT: lbu a2, 93(a0)2145; RV32VB-PACK-NEXT: lbu a3, 105(a0)2146; RV32VB-PACK-NEXT: lbu a4, 124(a0)2147; RV32VB-PACK-NEXT: lbu a5, 161(a0)2148; RV32VB-PACK-NEXT: lbu a6, 163(a0)2149; RV32VB-PACK-NEXT: lbu a7, 144(a0)2150; RV32VB-PACK-NEXT: lbu a0, 154(a0)2151; RV32VB-PACK-NEXT: packh a1, a1, a22152; RV32VB-PACK-NEXT: packh a2, a3, a52153; RV32VB-PACK-NEXT: packh a3, a4, a62154; RV32VB-PACK-NEXT: packh a0, a7, a02155; RV32VB-PACK-NEXT: pack a1, a1, a22156; RV32VB-PACK-NEXT: packh a2, a0, a02157; RV32VB-PACK-NEXT: pack a2, a2, a22158; RV32VB-PACK-NEXT: vsetivli zero, 4, e32, m1, ta, ma2159; RV32VB-PACK-NEXT: vmv.v.x v8, a22160; RV32VB-PACK-NEXT: pack a0, a3, a02161; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a22162; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a12163; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a02164; RV32VB-PACK-NEXT: ret2165;2166; RV64V-ONLY-LABEL: buildvec_v16i8_undef_low_half:2167; RV64V-ONLY: # %bb.0:2168; RV64V-ONLY-NEXT: lbu a1, 82(a0)2169; RV64V-ONLY-NEXT: lbu a2, 93(a0)2170; RV64V-ONLY-NEXT: lbu a3, 105(a0)2171; RV64V-ONLY-NEXT: lbu a4, 124(a0)2172; RV64V-ONLY-NEXT: lbu a5, 144(a0)2173; RV64V-ONLY-NEXT: lbu a6, 154(a0)2174; RV64V-ONLY-NEXT: lbu a7, 161(a0)2175; RV64V-ONLY-NEXT: lbu a0, 163(a0)2176; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, ma2177; RV64V-ONLY-NEXT: vmv.v.x v8, a12178; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a22179; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a32180; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a72181; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a42182; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a02183; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a52184; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a62185; RV64V-ONLY-NEXT: ret2186;2187; RVA22U64-LABEL: buildvec_v16i8_undef_low_half:2188; RVA22U64: # %bb.0:2189; RVA22U64-NEXT: lbu a1, 93(a0)2190; RVA22U64-NEXT: lbu a2, 82(a0)2191; RVA22U64-NEXT: lbu a3, 105(a0)2192; RVA22U64-NEXT: lbu a4, 124(a0)2193; RVA22U64-NEXT: slli a1, a1, 82194; RVA22U64-NEXT: or a6, a2, a12195; RVA22U64-NEXT: lbu a2, 161(a0)2196; RVA22U64-NEXT: lbu a5, 144(a0)2197; RVA22U64-NEXT: lbu a1, 154(a0)2198; RVA22U64-NEXT: lbu a0, 163(a0)2199; RVA22U64-NEXT: slli a3, a3, 162200; RVA22U64-NEXT: slli a2, a2, 242201; RVA22U64-NEXT: or a2, a2, a32202; RVA22U64-NEXT: slli a4, a4, 322203; RVA22U64-NEXT: slli a0, a0, 402204; RVA22U64-NEXT: or a0, a0, a42205; RVA22U64-NEXT: slli a5, a5, 482206; RVA22U64-NEXT: slli a1, a1, 562207; RVA22U64-NEXT: or a1, a1, a52208; RVA22U64-NEXT: or a2, a6, a22209; RVA22U64-NEXT: or a0, a0, a12210; RVA22U64-NEXT: or a0, a0, a22211; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma2212; RVA22U64-NEXT: vmv.v.i v8, 02213; RVA22U64-NEXT: vslide1down.vx v8, v8, a02214; RVA22U64-NEXT: ret2215;2216; RVA22U64-PACK-LABEL: buildvec_v16i8_undef_low_half:2217; RVA22U64-PACK: # %bb.0:2218; RVA22U64-PACK-NEXT: lbu a6, 82(a0)2219; RVA22U64-PACK-NEXT: lbu a7, 93(a0)2220; RVA22U64-PACK-NEXT: lbu t0, 105(a0)2221; RVA22U64-PACK-NEXT: lbu a4, 124(a0)2222; RVA22U64-PACK-NEXT: lbu a5, 161(a0)2223; RVA22U64-PACK-NEXT: lbu a1, 163(a0)2224; RVA22U64-PACK-NEXT: lbu a2, 144(a0)2225; RVA22U64-PACK-NEXT: lbu a0, 154(a0)2226; RVA22U64-PACK-NEXT: packh a3, a6, a72227; RVA22U64-PACK-NEXT: packh a5, t0, a52228; RVA22U64-PACK-NEXT: packh a1, a4, a12229; RVA22U64-PACK-NEXT: packh a0, a2, a02230; RVA22U64-PACK-NEXT: packw a2, a3, a52231; RVA22U64-PACK-NEXT: packh a3, a0, a02232; RVA22U64-PACK-NEXT: packw a3, a3, a32233; RVA22U64-PACK-NEXT: pack a3, a3, a32234; RVA22U64-PACK-NEXT: packw a0, a1, a02235; RVA22U64-PACK-NEXT: pack a0, a2, a02236; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma2237; RVA22U64-PACK-NEXT: vmv.v.x v8, a32238; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a02239; RVA22U64-PACK-NEXT: ret2240;2241; RV64ZVE32-LABEL: buildvec_v16i8_undef_low_half:2242; RV64ZVE32: # %bb.0:2243; RV64ZVE32-NEXT: lbu a1, 82(a0)2244; RV64ZVE32-NEXT: lbu a2, 93(a0)2245; RV64ZVE32-NEXT: lbu a3, 105(a0)2246; RV64ZVE32-NEXT: lbu a4, 124(a0)2247; RV64ZVE32-NEXT: lbu a5, 144(a0)2248; RV64ZVE32-NEXT: lbu a6, 154(a0)2249; RV64ZVE32-NEXT: lbu a7, 161(a0)2250; RV64ZVE32-NEXT: lbu a0, 163(a0)2251; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, ma2252; RV64ZVE32-NEXT: vmv.v.x v8, a12253; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a22254; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a32255; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a72256; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a42257; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a02258; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a52259; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a62260; RV64ZVE32-NEXT: ret2261 %p9 = getelementptr i8, ptr %p, i32 822262 %p10 = getelementptr i8, ptr %p, i32 932263 %p11 = getelementptr i8, ptr %p, i32 1052264 %p12 = getelementptr i8, ptr %p, i32 1612265 %p13 = getelementptr i8, ptr %p, i32 1242266 %p14 = getelementptr i8, ptr %p, i32 1632267 %p15 = getelementptr i8, ptr %p, i32 1442268 %p16 = getelementptr i8, ptr %p, i32 1542269 2270 %ld9 = load i8, ptr %p92271 %ld10 = load i8, ptr %p102272 %ld11 = load i8, ptr %p112273 %ld12 = load i8, ptr %p122274 %ld13 = load i8, ptr %p132275 %ld14 = load i8, ptr %p142276 %ld15 = load i8, ptr %p152277 %ld16 = load i8, ptr %p162278 2279 %v9 = insertelement <16 x i8> poison, i8 %ld9, i32 82280 %v10 = insertelement <16 x i8> %v9, i8 %ld10, i32 92281 %v11 = insertelement <16 x i8> %v10, i8 %ld11, i32 102282 %v12 = insertelement <16 x i8> %v11, i8 %ld12, i32 112283 %v13 = insertelement <16 x i8> %v12, i8 %ld13, i32 122284 %v14 = insertelement <16 x i8> %v13, i8 %ld14, i32 132285 %v15 = insertelement <16 x i8> %v14, i8 %ld15, i32 142286 %v16 = insertelement <16 x i8> %v15, i8 %ld16, i32 152287 ret <16 x i8> %v162288}2289 2290define <16 x i8> @buildvec_v16i8_undef_high_half(ptr %p) {2291; RV32-ONLY-LABEL: buildvec_v16i8_undef_high_half:2292; RV32-ONLY: # %bb.0:2293; RV32-ONLY-NEXT: lbu a1, 0(a0)2294; RV32-ONLY-NEXT: lbu a2, 1(a0)2295; RV32-ONLY-NEXT: lbu a3, 22(a0)2296; RV32-ONLY-NEXT: lbu a4, 31(a0)2297; RV32-ONLY-NEXT: lbu a5, 623(a0)2298; RV32-ONLY-NEXT: lbu a6, 44(a0)2299; RV32-ONLY-NEXT: lbu a7, 55(a0)2300; RV32-ONLY-NEXT: lbu a0, 75(a0)2301; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, ma2302; RV32-ONLY-NEXT: vmv.v.x v8, a12303; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a22304; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a32305; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a42306; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a62307; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a72308; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a52309; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a02310; RV32-ONLY-NEXT: vslidedown.vi v8, v8, 82311; RV32-ONLY-NEXT: ret2312;2313; RV32VB-LABEL: buildvec_v16i8_undef_high_half:2314; RV32VB: # %bb.0:2315; RV32VB-NEXT: lbu a1, 1(a0)2316; RV32VB-NEXT: lbu a2, 0(a0)2317; RV32VB-NEXT: lbu a3, 22(a0)2318; RV32VB-NEXT: lbu a4, 31(a0)2319; RV32VB-NEXT: slli a1, a1, 82320; RV32VB-NEXT: or a1, a2, a12321; RV32VB-NEXT: lbu a2, 44(a0)2322; RV32VB-NEXT: lbu a5, 55(a0)2323; RV32VB-NEXT: slli a3, a3, 162324; RV32VB-NEXT: slli a4, a4, 242325; RV32VB-NEXT: or a3, a4, a32326; RV32VB-NEXT: lbu a4, 623(a0)2327; RV32VB-NEXT: lbu a0, 75(a0)2328; RV32VB-NEXT: slli a5, a5, 82329; RV32VB-NEXT: or a2, a2, a52330; RV32VB-NEXT: slli a4, a4, 162331; RV32VB-NEXT: slli a0, a0, 242332; RV32VB-NEXT: or a0, a0, a42333; RV32VB-NEXT: or a1, a1, a32334; RV32VB-NEXT: or a0, a2, a02335; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma2336; RV32VB-NEXT: vmv.v.x v8, a12337; RV32VB-NEXT: vslide1down.vx v8, v8, a02338; RV32VB-NEXT: vslide1down.vx v8, v8, zero2339; RV32VB-NEXT: vslide1down.vx v8, v8, zero2340; RV32VB-NEXT: ret2341;2342; RV32VB-PACK-LABEL: buildvec_v16i8_undef_high_half:2343; RV32VB-PACK: # %bb.0:2344; RV32VB-PACK-NEXT: lbu a1, 0(a0)2345; RV32VB-PACK-NEXT: lbu a2, 1(a0)2346; RV32VB-PACK-NEXT: lbu a3, 22(a0)2347; RV32VB-PACK-NEXT: lbu a4, 31(a0)2348; RV32VB-PACK-NEXT: lbu a5, 623(a0)2349; RV32VB-PACK-NEXT: lbu a6, 44(a0)2350; RV32VB-PACK-NEXT: lbu a7, 55(a0)2351; RV32VB-PACK-NEXT: lbu a0, 75(a0)2352; RV32VB-PACK-NEXT: packh a1, a1, a22353; RV32VB-PACK-NEXT: packh a2, a3, a42354; RV32VB-PACK-NEXT: packh a3, a6, a72355; RV32VB-PACK-NEXT: packh a0, a5, a02356; RV32VB-PACK-NEXT: pack a1, a1, a22357; RV32VB-PACK-NEXT: packh a2, a0, a02358; RV32VB-PACK-NEXT: pack a0, a3, a02359; RV32VB-PACK-NEXT: vsetivli zero, 4, e32, m1, ta, ma2360; RV32VB-PACK-NEXT: vmv.v.x v8, a12361; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a02362; RV32VB-PACK-NEXT: pack a0, a2, a22363; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a02364; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a02365; RV32VB-PACK-NEXT: ret2366;2367; RV64V-ONLY-LABEL: buildvec_v16i8_undef_high_half:2368; RV64V-ONLY: # %bb.0:2369; RV64V-ONLY-NEXT: lbu a1, 0(a0)2370; RV64V-ONLY-NEXT: lbu a2, 1(a0)2371; RV64V-ONLY-NEXT: lbu a3, 22(a0)2372; RV64V-ONLY-NEXT: lbu a4, 31(a0)2373; RV64V-ONLY-NEXT: lbu a5, 623(a0)2374; RV64V-ONLY-NEXT: lbu a6, 44(a0)2375; RV64V-ONLY-NEXT: lbu a7, 55(a0)2376; RV64V-ONLY-NEXT: lbu a0, 75(a0)2377; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, ma2378; RV64V-ONLY-NEXT: vmv.v.x v8, a12379; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a22380; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a32381; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a42382; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a62383; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a72384; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a52385; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a02386; RV64V-ONLY-NEXT: vslidedown.vi v8, v8, 82387; RV64V-ONLY-NEXT: ret2388;2389; RVA22U64-LABEL: buildvec_v16i8_undef_high_half:2390; RVA22U64: # %bb.0:2391; RVA22U64-NEXT: lbu a1, 1(a0)2392; RVA22U64-NEXT: lbu a2, 0(a0)2393; RVA22U64-NEXT: lbu a3, 22(a0)2394; RVA22U64-NEXT: lbu a4, 31(a0)2395; RVA22U64-NEXT: slli a1, a1, 82396; RVA22U64-NEXT: or a1, a1, a22397; RVA22U64-NEXT: lbu a2, 44(a0)2398; RVA22U64-NEXT: lbu a5, 55(a0)2399; RVA22U64-NEXT: slli a3, a3, 162400; RVA22U64-NEXT: slli a4, a4, 242401; RVA22U64-NEXT: or a3, a3, a42402; RVA22U64-NEXT: lbu a4, 623(a0)2403; RVA22U64-NEXT: lbu a0, 75(a0)2404; RVA22U64-NEXT: slli a2, a2, 322405; RVA22U64-NEXT: slli a5, a5, 402406; RVA22U64-NEXT: or a2, a2, a52407; RVA22U64-NEXT: slli a4, a4, 482408; RVA22U64-NEXT: slli a0, a0, 562409; RVA22U64-NEXT: or a0, a0, a42410; RVA22U64-NEXT: or a1, a1, a32411; RVA22U64-NEXT: or a0, a0, a22412; RVA22U64-NEXT: or a0, a0, a12413; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma2414; RVA22U64-NEXT: vmv.v.x v8, a02415; RVA22U64-NEXT: vslide1down.vx v8, v8, zero2416; RVA22U64-NEXT: ret2417;2418; RVA22U64-PACK-LABEL: buildvec_v16i8_undef_high_half:2419; RVA22U64-PACK: # %bb.0:2420; RVA22U64-PACK-NEXT: lbu a6, 0(a0)2421; RVA22U64-PACK-NEXT: lbu a7, 1(a0)2422; RVA22U64-PACK-NEXT: lbu t0, 22(a0)2423; RVA22U64-PACK-NEXT: lbu a4, 31(a0)2424; RVA22U64-PACK-NEXT: lbu a5, 623(a0)2425; RVA22U64-PACK-NEXT: lbu a1, 44(a0)2426; RVA22U64-PACK-NEXT: lbu a2, 55(a0)2427; RVA22U64-PACK-NEXT: lbu a0, 75(a0)2428; RVA22U64-PACK-NEXT: packh a3, a6, a72429; RVA22U64-PACK-NEXT: packh a4, t0, a42430; RVA22U64-PACK-NEXT: packh a1, a1, a22431; RVA22U64-PACK-NEXT: packh a0, a5, a02432; RVA22U64-PACK-NEXT: packw a2, a3, a42433; RVA22U64-PACK-NEXT: packh a3, a0, a02434; RVA22U64-PACK-NEXT: packw a3, a3, a32435; RVA22U64-PACK-NEXT: packw a0, a1, a02436; RVA22U64-PACK-NEXT: pack a0, a2, a02437; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma2438; RVA22U64-PACK-NEXT: vmv.v.x v8, a02439; RVA22U64-PACK-NEXT: pack a0, a3, a32440; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a02441; RVA22U64-PACK-NEXT: ret2442;2443; RV64ZVE32-LABEL: buildvec_v16i8_undef_high_half:2444; RV64ZVE32: # %bb.0:2445; RV64ZVE32-NEXT: lbu a1, 0(a0)2446; RV64ZVE32-NEXT: lbu a2, 1(a0)2447; RV64ZVE32-NEXT: lbu a3, 22(a0)2448; RV64ZVE32-NEXT: lbu a4, 31(a0)2449; RV64ZVE32-NEXT: lbu a5, 623(a0)2450; RV64ZVE32-NEXT: lbu a6, 44(a0)2451; RV64ZVE32-NEXT: lbu a7, 55(a0)2452; RV64ZVE32-NEXT: lbu a0, 75(a0)2453; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, ma2454; RV64ZVE32-NEXT: vmv.v.x v8, a12455; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a22456; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a32457; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a42458; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a62459; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a72460; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a52461; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a02462; RV64ZVE32-NEXT: vslidedown.vi v8, v8, 82463; RV64ZVE32-NEXT: ret2464 %p2 = getelementptr i8, ptr %p, i32 12465 %p3 = getelementptr i8, ptr %p, i32 222466 %p4 = getelementptr i8, ptr %p, i32 312467 %p5 = getelementptr i8, ptr %p, i32 442468 %p6 = getelementptr i8, ptr %p, i32 552469 %p7 = getelementptr i8, ptr %p, i32 6232470 %p8 = getelementptr i8, ptr %p, i32 752471 2472 %ld1 = load i8, ptr %p2473 %ld2 = load i8, ptr %p22474 %ld3 = load i8, ptr %p32475 %ld4 = load i8, ptr %p42476 %ld5 = load i8, ptr %p52477 %ld6 = load i8, ptr %p62478 %ld7 = load i8, ptr %p72479 %ld8 = load i8, ptr %p82480 2481 %v1 = insertelement <16 x i8> poison, i8 %ld1, i32 02482 %v2 = insertelement <16 x i8> %v1, i8 %ld2, i32 12483 %v3 = insertelement <16 x i8> %v2, i8 %ld3, i32 22484 %v4 = insertelement <16 x i8> %v3, i8 %ld4, i32 32485 %v5 = insertelement <16 x i8> %v4, i8 %ld5, i32 42486 %v6 = insertelement <16 x i8> %v5, i8 %ld6, i32 52487 %v7 = insertelement <16 x i8> %v6, i8 %ld7, i32 62488 %v8 = insertelement <16 x i8> %v7, i8 %ld8, i32 72489 ret <16 x i8> %v82490}2491 2492define <16 x i8> @buildvec_v16i8_undef_edges(ptr %p) {2493; RV32-ONLY-LABEL: buildvec_v16i8_undef_edges:2494; RV32-ONLY: # %bb.0:2495; RV32-ONLY-NEXT: lbu a1, 623(a0)2496; RV32-ONLY-NEXT: lbu a2, 31(a0)2497; RV32-ONLY-NEXT: lbu a3, 44(a0)2498; RV32-ONLY-NEXT: lbu a4, 55(a0)2499; RV32-ONLY-NEXT: lbu a5, 75(a0)2500; RV32-ONLY-NEXT: li a6, 2552501; RV32-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma2502; RV32-ONLY-NEXT: vmv.s.x v0, a62503; RV32-ONLY-NEXT: lbu a6, 82(a0)2504; RV32-ONLY-NEXT: lbu a7, 93(a0)2505; RV32-ONLY-NEXT: lbu t0, 105(a0)2506; RV32-ONLY-NEXT: lbu a0, 161(a0)2507; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu2508; RV32-ONLY-NEXT: vmv.v.x v8, a62509; RV32-ONLY-NEXT: vmv.v.x v9, a22510; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a72511; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a32512; RV32-ONLY-NEXT: vslide1down.vx v8, v8, t02513; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a42514; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a02515; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a12516; RV32-ONLY-NEXT: vslidedown.vi v8, v8, 42517; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a52518; RV32-ONLY-NEXT: vslidedown.vi v8, v9, 8, v0.t2519; RV32-ONLY-NEXT: ret2520;2521; RV32VB-LABEL: buildvec_v16i8_undef_edges:2522; RV32VB: # %bb.0:2523; RV32VB-NEXT: lbu a1, 623(a0)2524; RV32VB-NEXT: lbu a2, 55(a0)2525; RV32VB-NEXT: lbu a3, 31(a0)2526; RV32VB-NEXT: lbu a4, 75(a0)2527; RV32VB-NEXT: lbu a5, 44(a0)2528; RV32VB-NEXT: slli a2, a2, 82529; RV32VB-NEXT: slli a1, a1, 162530; RV32VB-NEXT: slli a4, a4, 242531; RV32VB-NEXT: or a2, a5, a22532; RV32VB-NEXT: or a1, a4, a12533; RV32VB-NEXT: lbu a4, 93(a0)2534; RV32VB-NEXT: lbu a5, 82(a0)2535; RV32VB-NEXT: lbu a6, 105(a0)2536; RV32VB-NEXT: lbu a0, 161(a0)2537; RV32VB-NEXT: slli a4, a4, 82538; RV32VB-NEXT: or a4, a5, a42539; RV32VB-NEXT: slli a6, a6, 162540; RV32VB-NEXT: slli a0, a0, 242541; RV32VB-NEXT: or a0, a0, a62542; RV32VB-NEXT: slli a3, a3, 242543; RV32VB-NEXT: or a1, a2, a12544; RV32VB-NEXT: or a0, a4, a02545; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma2546; RV32VB-NEXT: vmv.v.x v8, a32547; RV32VB-NEXT: vslide1down.vx v8, v8, a12548; RV32VB-NEXT: vslide1down.vx v8, v8, a02549; RV32VB-NEXT: vslide1down.vx v8, v8, zero2550; RV32VB-NEXT: ret2551;2552; RV32VB-PACK-LABEL: buildvec_v16i8_undef_edges:2553; RV32VB-PACK: # %bb.0:2554; RV32VB-PACK-NEXT: lbu a1, 623(a0)2555; RV32VB-PACK-NEXT: lbu a2, 31(a0)2556; RV32VB-PACK-NEXT: lbu a3, 44(a0)2557; RV32VB-PACK-NEXT: lbu a4, 55(a0)2558; RV32VB-PACK-NEXT: lbu a5, 75(a0)2559; RV32VB-PACK-NEXT: lbu a6, 82(a0)2560; RV32VB-PACK-NEXT: lbu a7, 93(a0)2561; RV32VB-PACK-NEXT: lbu t0, 105(a0)2562; RV32VB-PACK-NEXT: lbu a0, 161(a0)2563; RV32VB-PACK-NEXT: packh a3, a3, a42564; RV32VB-PACK-NEXT: packh a1, a1, a52565; RV32VB-PACK-NEXT: packh a4, a6, a72566; RV32VB-PACK-NEXT: packh a0, t0, a02567; RV32VB-PACK-NEXT: packh a5, a0, a02568; RV32VB-PACK-NEXT: packh a2, a0, a22569; RV32VB-PACK-NEXT: pack a2, a5, a22570; RV32VB-PACK-NEXT: pack a1, a3, a12571; RV32VB-PACK-NEXT: pack a0, a4, a02572; RV32VB-PACK-NEXT: vsetivli zero, 4, e32, m1, ta, ma2573; RV32VB-PACK-NEXT: vmv.v.x v8, a22574; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a12575; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a02576; RV32VB-PACK-NEXT: pack a0, a5, a52577; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a02578; RV32VB-PACK-NEXT: ret2579;2580; RV64V-ONLY-LABEL: buildvec_v16i8_undef_edges:2581; RV64V-ONLY: # %bb.0:2582; RV64V-ONLY-NEXT: lbu a1, 623(a0)2583; RV64V-ONLY-NEXT: lbu a2, 31(a0)2584; RV64V-ONLY-NEXT: lbu a3, 44(a0)2585; RV64V-ONLY-NEXT: lbu a4, 55(a0)2586; RV64V-ONLY-NEXT: lbu a5, 75(a0)2587; RV64V-ONLY-NEXT: li a6, 2552588; RV64V-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma2589; RV64V-ONLY-NEXT: vmv.s.x v0, a62590; RV64V-ONLY-NEXT: lbu a6, 82(a0)2591; RV64V-ONLY-NEXT: lbu a7, 93(a0)2592; RV64V-ONLY-NEXT: lbu t0, 105(a0)2593; RV64V-ONLY-NEXT: lbu a0, 161(a0)2594; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu2595; RV64V-ONLY-NEXT: vmv.v.x v8, a62596; RV64V-ONLY-NEXT: vmv.v.x v9, a22597; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a72598; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a32599; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, t02600; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a42601; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a02602; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a12603; RV64V-ONLY-NEXT: vslidedown.vi v8, v8, 42604; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a52605; RV64V-ONLY-NEXT: vslidedown.vi v8, v9, 8, v0.t2606; RV64V-ONLY-NEXT: ret2607;2608; RVA22U64-LABEL: buildvec_v16i8_undef_edges:2609; RVA22U64: # %bb.0:2610; RVA22U64-NEXT: lbu a1, 623(a0)2611; RVA22U64-NEXT: lbu a2, 44(a0)2612; RVA22U64-NEXT: lbu a3, 55(a0)2613; RVA22U64-NEXT: lbu a6, 31(a0)2614; RVA22U64-NEXT: lbu a5, 75(a0)2615; RVA22U64-NEXT: slli a2, a2, 322616; RVA22U64-NEXT: slli a3, a3, 402617; RVA22U64-NEXT: slli a1, a1, 482618; RVA22U64-NEXT: slli a5, a5, 562619; RVA22U64-NEXT: or a2, a2, a32620; RVA22U64-NEXT: or a1, a1, a52621; RVA22U64-NEXT: lbu a3, 93(a0)2622; RVA22U64-NEXT: lbu a5, 82(a0)2623; RVA22U64-NEXT: lbu a4, 105(a0)2624; RVA22U64-NEXT: lbu a0, 161(a0)2625; RVA22U64-NEXT: slli a3, a3, 82626; RVA22U64-NEXT: or a3, a3, a52627; RVA22U64-NEXT: slli a4, a4, 162628; RVA22U64-NEXT: slli a0, a0, 242629; RVA22U64-NEXT: or a0, a0, a42630; RVA22U64-NEXT: slli a6, a6, 242631; RVA22U64-NEXT: or a1, a1, a22632; RVA22U64-NEXT: add.uw a1, a6, a12633; RVA22U64-NEXT: or a0, a0, a32634; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma2635; RVA22U64-NEXT: vmv.v.x v8, a12636; RVA22U64-NEXT: vslide1down.vx v8, v8, a02637; RVA22U64-NEXT: ret2638;2639; RVA22U64-PACK-LABEL: buildvec_v16i8_undef_edges:2640; RVA22U64-PACK: # %bb.0:2641; RVA22U64-PACK-NEXT: lbu a7, 623(a0)2642; RVA22U64-PACK-NEXT: lbu a6, 31(a0)2643; RVA22U64-PACK-NEXT: lbu t0, 44(a0)2644; RVA22U64-PACK-NEXT: lbu a4, 55(a0)2645; RVA22U64-PACK-NEXT: lbu a5, 75(a0)2646; RVA22U64-PACK-NEXT: lbu a2, 82(a0)2647; RVA22U64-PACK-NEXT: lbu a1, 93(a0)2648; RVA22U64-PACK-NEXT: lbu a3, 105(a0)2649; RVA22U64-PACK-NEXT: lbu a0, 161(a0)2650; RVA22U64-PACK-NEXT: packh a4, t0, a42651; RVA22U64-PACK-NEXT: packh a5, a7, a52652; RVA22U64-PACK-NEXT: packh a1, a2, a12653; RVA22U64-PACK-NEXT: packh a0, a3, a02654; RVA22U64-PACK-NEXT: packh a2, a0, a02655; RVA22U64-PACK-NEXT: packh a3, a0, a62656; RVA22U64-PACK-NEXT: packw a3, a2, a32657; RVA22U64-PACK-NEXT: packw a2, a2, a22658; RVA22U64-PACK-NEXT: packw a4, a4, a52659; RVA22U64-PACK-NEXT: packw a0, a1, a02660; RVA22U64-PACK-NEXT: pack a1, a3, a42661; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma2662; RVA22U64-PACK-NEXT: vmv.v.x v8, a12663; RVA22U64-PACK-NEXT: pack a0, a0, a22664; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a02665; RVA22U64-PACK-NEXT: ret2666;2667; RV64ZVE32-LABEL: buildvec_v16i8_undef_edges:2668; RV64ZVE32: # %bb.0:2669; RV64ZVE32-NEXT: lbu a1, 623(a0)2670; RV64ZVE32-NEXT: lbu a2, 31(a0)2671; RV64ZVE32-NEXT: lbu a3, 44(a0)2672; RV64ZVE32-NEXT: lbu a4, 55(a0)2673; RV64ZVE32-NEXT: lbu a5, 75(a0)2674; RV64ZVE32-NEXT: li a6, 2552675; RV64ZVE32-NEXT: vsetivli zero, 1, e16, m1, ta, ma2676; RV64ZVE32-NEXT: vmv.s.x v0, a62677; RV64ZVE32-NEXT: lbu a6, 82(a0)2678; RV64ZVE32-NEXT: lbu a7, 93(a0)2679; RV64ZVE32-NEXT: lbu t0, 105(a0)2680; RV64ZVE32-NEXT: lbu a0, 161(a0)2681; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, mu2682; RV64ZVE32-NEXT: vmv.v.x v8, a62683; RV64ZVE32-NEXT: vmv.v.x v9, a22684; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a72685; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a32686; RV64ZVE32-NEXT: vslide1down.vx v8, v8, t02687; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a42688; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a02689; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a12690; RV64ZVE32-NEXT: vslidedown.vi v8, v8, 42691; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a52692; RV64ZVE32-NEXT: vslidedown.vi v8, v9, 8, v0.t2693; RV64ZVE32-NEXT: ret2694 %p4 = getelementptr i8, ptr %p, i32 312695 %p5 = getelementptr i8, ptr %p, i32 442696 %p6 = getelementptr i8, ptr %p, i32 552697 %p7 = getelementptr i8, ptr %p, i32 6232698 %p8 = getelementptr i8, ptr %p, i32 752699 %p9 = getelementptr i8, ptr %p, i32 822700 %p10 = getelementptr i8, ptr %p, i32 932701 %p11 = getelementptr i8, ptr %p, i32 1052702 %p12 = getelementptr i8, ptr %p, i32 1612703 2704 %ld4 = load i8, ptr %p42705 %ld5 = load i8, ptr %p52706 %ld6 = load i8, ptr %p62707 %ld7 = load i8, ptr %p72708 %ld8 = load i8, ptr %p82709 %ld9 = load i8, ptr %p92710 %ld10 = load i8, ptr %p102711 %ld11 = load i8, ptr %p112712 %ld12 = load i8, ptr %p122713 2714 %v4 = insertelement <16 x i8> poison, i8 %ld4, i32 32715 %v5 = insertelement <16 x i8> %v4, i8 %ld5, i32 42716 %v6 = insertelement <16 x i8> %v5, i8 %ld6, i32 52717 %v7 = insertelement <16 x i8> %v6, i8 %ld7, i32 62718 %v8 = insertelement <16 x i8> %v7, i8 %ld8, i32 72719 %v9 = insertelement <16 x i8> %v8, i8 %ld9, i32 82720 %v10 = insertelement <16 x i8> %v9, i8 %ld10, i32 92721 %v11 = insertelement <16 x i8> %v10, i8 %ld11, i32 102722 %v12 = insertelement <16 x i8> %v11, i8 %ld12, i32 112723 ret <16 x i8> %v122724}2725 2726define <16 x i8> @buildvec_v16i8_loads_undef_scattered(ptr %p) {2727; RV32-ONLY-LABEL: buildvec_v16i8_loads_undef_scattered:2728; RV32-ONLY: # %bb.0:2729; RV32-ONLY-NEXT: lbu a1, 0(a0)2730; RV32-ONLY-NEXT: lbu a2, 1(a0)2731; RV32-ONLY-NEXT: lbu a3, 44(a0)2732; RV32-ONLY-NEXT: lbu a4, 55(a0)2733; RV32-ONLY-NEXT: lbu a5, 75(a0)2734; RV32-ONLY-NEXT: lbu a6, 82(a0)2735; RV32-ONLY-NEXT: lbu a7, 93(a0)2736; RV32-ONLY-NEXT: lbu t0, 124(a0)2737; RV32-ONLY-NEXT: li t1, 2552738; RV32-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma2739; RV32-ONLY-NEXT: vmv.s.x v0, t12740; RV32-ONLY-NEXT: lbu t1, 144(a0)2741; RV32-ONLY-NEXT: lbu a0, 154(a0)2742; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu2743; RV32-ONLY-NEXT: vmv.v.x v8, a62744; RV32-ONLY-NEXT: vmv.v.x v9, a12745; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a72746; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a22747; RV32-ONLY-NEXT: vslidedown.vi v8, v8, 22748; RV32-ONLY-NEXT: vslidedown.vi v9, v9, 22749; RV32-ONLY-NEXT: vslide1down.vx v8, v8, t02750; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a32751; RV32-ONLY-NEXT: vslidedown.vi v8, v8, 12752; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a42753; RV32-ONLY-NEXT: vslide1down.vx v8, v8, t12754; RV32-ONLY-NEXT: vslidedown.vi v9, v9, 12755; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a02756; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a52757; RV32-ONLY-NEXT: vslidedown.vi v8, v9, 8, v0.t2758; RV32-ONLY-NEXT: ret2759;2760; RV32VB-LABEL: buildvec_v16i8_loads_undef_scattered:2761; RV32VB: # %bb.0:2762; RV32VB-NEXT: lbu a1, 1(a0)2763; RV32VB-NEXT: lbu a2, 0(a0)2764; RV32VB-NEXT: lbu a3, 44(a0)2765; RV32VB-NEXT: lbu a4, 55(a0)2766; RV32VB-NEXT: slli a1, a1, 82767; RV32VB-NEXT: or a1, a2, a12768; RV32VB-NEXT: lbu a2, 75(a0)2769; RV32VB-NEXT: lbu a5, 82(a0)2770; RV32VB-NEXT: lbu a6, 93(a0)2771; RV32VB-NEXT: lbu a7, 124(a0)2772; RV32VB-NEXT: slli a4, a4, 82773; RV32VB-NEXT: or a3, a3, a42774; RV32VB-NEXT: lbu a4, 144(a0)2775; RV32VB-NEXT: lbu a0, 154(a0)2776; RV32VB-NEXT: slli a6, a6, 82777; RV32VB-NEXT: or a5, a5, a62778; RV32VB-NEXT: slli a4, a4, 162779; RV32VB-NEXT: slli a0, a0, 242780; RV32VB-NEXT: or a0, a0, a42781; RV32VB-NEXT: slli a2, a2, 242782; RV32VB-NEXT: or a2, a3, a22783; RV32VB-NEXT: or a0, a7, a02784; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma2785; RV32VB-NEXT: vmv.v.x v8, a12786; RV32VB-NEXT: vslide1down.vx v8, v8, a22787; RV32VB-NEXT: vslide1down.vx v8, v8, a52788; RV32VB-NEXT: vslide1down.vx v8, v8, a02789; RV32VB-NEXT: ret2790;2791; RV32VB-PACK-LABEL: buildvec_v16i8_loads_undef_scattered:2792; RV32VB-PACK: # %bb.0:2793; RV32VB-PACK-NEXT: lbu a1, 0(a0)2794; RV32VB-PACK-NEXT: lbu a2, 1(a0)2795; RV32VB-PACK-NEXT: lbu a3, 44(a0)2796; RV32VB-PACK-NEXT: lbu a4, 55(a0)2797; RV32VB-PACK-NEXT: lbu a5, 82(a0)2798; RV32VB-PACK-NEXT: lbu a6, 93(a0)2799; RV32VB-PACK-NEXT: packh a1, a1, a22800; RV32VB-PACK-NEXT: lbu a2, 144(a0)2801; RV32VB-PACK-NEXT: lbu a7, 154(a0)2802; RV32VB-PACK-NEXT: packh a3, a3, a42803; RV32VB-PACK-NEXT: lbu a4, 75(a0)2804; RV32VB-PACK-NEXT: lbu a0, 124(a0)2805; RV32VB-PACK-NEXT: packh a5, a5, a62806; RV32VB-PACK-NEXT: packh a2, a2, a72807; RV32VB-PACK-NEXT: packh a4, a0, a42808; RV32VB-PACK-NEXT: pack a3, a3, a42809; RV32VB-PACK-NEXT: packh a4, a0, a02810; RV32VB-PACK-NEXT: packh a0, a0, a02811; RV32VB-PACK-NEXT: pack a0, a0, a22812; RV32VB-PACK-NEXT: pack a1, a1, a42813; RV32VB-PACK-NEXT: vsetivli zero, 4, e32, m1, ta, ma2814; RV32VB-PACK-NEXT: vmv.v.x v8, a12815; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a32816; RV32VB-PACK-NEXT: pack a1, a5, a42817; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a12818; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a02819; RV32VB-PACK-NEXT: ret2820;2821; RV64V-ONLY-LABEL: buildvec_v16i8_loads_undef_scattered:2822; RV64V-ONLY: # %bb.0:2823; RV64V-ONLY-NEXT: lbu a1, 0(a0)2824; RV64V-ONLY-NEXT: lbu a2, 1(a0)2825; RV64V-ONLY-NEXT: lbu a3, 44(a0)2826; RV64V-ONLY-NEXT: lbu a4, 55(a0)2827; RV64V-ONLY-NEXT: lbu a5, 75(a0)2828; RV64V-ONLY-NEXT: lbu a6, 82(a0)2829; RV64V-ONLY-NEXT: lbu a7, 93(a0)2830; RV64V-ONLY-NEXT: lbu t0, 124(a0)2831; RV64V-ONLY-NEXT: li t1, 2552832; RV64V-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma2833; RV64V-ONLY-NEXT: vmv.s.x v0, t12834; RV64V-ONLY-NEXT: lbu t1, 144(a0)2835; RV64V-ONLY-NEXT: lbu a0, 154(a0)2836; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu2837; RV64V-ONLY-NEXT: vmv.v.x v8, a62838; RV64V-ONLY-NEXT: vmv.v.x v9, a12839; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a72840; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a22841; RV64V-ONLY-NEXT: vslidedown.vi v8, v8, 22842; RV64V-ONLY-NEXT: vslidedown.vi v9, v9, 22843; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, t02844; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a32845; RV64V-ONLY-NEXT: vslidedown.vi v8, v8, 12846; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a42847; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, t12848; RV64V-ONLY-NEXT: vslidedown.vi v9, v9, 12849; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a02850; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a52851; RV64V-ONLY-NEXT: vslidedown.vi v8, v9, 8, v0.t2852; RV64V-ONLY-NEXT: ret2853;2854; RVA22U64-LABEL: buildvec_v16i8_loads_undef_scattered:2855; RVA22U64: # %bb.0:2856; RVA22U64-NEXT: lbu a1, 1(a0)2857; RVA22U64-NEXT: lbu a2, 0(a0)2858; RVA22U64-NEXT: lbu a3, 44(a0)2859; RVA22U64-NEXT: lbu a4, 55(a0)2860; RVA22U64-NEXT: slli a1, a1, 82861; RVA22U64-NEXT: or a6, a2, a12862; RVA22U64-NEXT: lbu a7, 75(a0)2863; RVA22U64-NEXT: lbu a5, 82(a0)2864; RVA22U64-NEXT: lbu a1, 93(a0)2865; RVA22U64-NEXT: lbu a2, 124(a0)2866; RVA22U64-NEXT: slli a3, a3, 322867; RVA22U64-NEXT: slli a4, a4, 402868; RVA22U64-NEXT: or a3, a3, a42869; RVA22U64-NEXT: lbu a4, 144(a0)2870; RVA22U64-NEXT: lbu a0, 154(a0)2871; RVA22U64-NEXT: slli a1, a1, 82872; RVA22U64-NEXT: or a1, a1, a52873; RVA22U64-NEXT: slli a4, a4, 482874; RVA22U64-NEXT: slli a0, a0, 562875; RVA22U64-NEXT: or a0, a0, a42876; RVA22U64-NEXT: slli a7, a7, 562877; RVA22U64-NEXT: or a3, a7, a32878; RVA22U64-NEXT: slli a2, a2, 322879; RVA22U64-NEXT: or a0, a0, a22880; RVA22U64-NEXT: or a2, a6, a32881; RVA22U64-NEXT: or a0, a0, a12882; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma2883; RVA22U64-NEXT: vmv.v.x v8, a22884; RVA22U64-NEXT: vslide1down.vx v8, v8, a02885; RVA22U64-NEXT: ret2886;2887; RVA22U64-PACK-LABEL: buildvec_v16i8_loads_undef_scattered:2888; RVA22U64-PACK: # %bb.0:2889; RVA22U64-PACK-NEXT: lbu a1, 0(a0)2890; RVA22U64-PACK-NEXT: lbu a2, 1(a0)2891; RVA22U64-PACK-NEXT: lbu a6, 44(a0)2892; RVA22U64-PACK-NEXT: lbu a7, 55(a0)2893; RVA22U64-PACK-NEXT: lbu t1, 82(a0)2894; RVA22U64-PACK-NEXT: lbu a3, 93(a0)2895; RVA22U64-PACK-NEXT: packh t0, a1, a22896; RVA22U64-PACK-NEXT: lbu a2, 144(a0)2897; RVA22U64-PACK-NEXT: lbu a4, 154(a0)2898; RVA22U64-PACK-NEXT: packh a1, a6, a72899; RVA22U64-PACK-NEXT: lbu a5, 75(a0)2900; RVA22U64-PACK-NEXT: lbu a0, 124(a0)2901; RVA22U64-PACK-NEXT: packh a3, t1, a32902; RVA22U64-PACK-NEXT: packh a2, a2, a42903; RVA22U64-PACK-NEXT: packh a4, a0, a52904; RVA22U64-PACK-NEXT: packw a1, a1, a42905; RVA22U64-PACK-NEXT: packh a4, a0, a02906; RVA22U64-PACK-NEXT: packh a0, a0, a02907; RVA22U64-PACK-NEXT: packw a5, t0, a42908; RVA22U64-PACK-NEXT: packw a0, a0, a22909; RVA22U64-PACK-NEXT: packw a2, a3, a42910; RVA22U64-PACK-NEXT: pack a1, a5, a12911; RVA22U64-PACK-NEXT: pack a0, a2, a02912; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma2913; RVA22U64-PACK-NEXT: vmv.v.x v8, a12914; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a02915; RVA22U64-PACK-NEXT: ret2916;2917; RV64ZVE32-LABEL: buildvec_v16i8_loads_undef_scattered:2918; RV64ZVE32: # %bb.0:2919; RV64ZVE32-NEXT: lbu a1, 0(a0)2920; RV64ZVE32-NEXT: lbu a2, 1(a0)2921; RV64ZVE32-NEXT: lbu a3, 44(a0)2922; RV64ZVE32-NEXT: lbu a4, 55(a0)2923; RV64ZVE32-NEXT: lbu a5, 75(a0)2924; RV64ZVE32-NEXT: lbu a6, 82(a0)2925; RV64ZVE32-NEXT: lbu a7, 93(a0)2926; RV64ZVE32-NEXT: lbu t0, 124(a0)2927; RV64ZVE32-NEXT: li t1, 2552928; RV64ZVE32-NEXT: vsetivli zero, 1, e16, m1, ta, ma2929; RV64ZVE32-NEXT: vmv.s.x v0, t12930; RV64ZVE32-NEXT: lbu t1, 144(a0)2931; RV64ZVE32-NEXT: lbu a0, 154(a0)2932; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, mu2933; RV64ZVE32-NEXT: vmv.v.x v8, a62934; RV64ZVE32-NEXT: vmv.v.x v9, a12935; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a72936; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a22937; RV64ZVE32-NEXT: vslidedown.vi v8, v8, 22938; RV64ZVE32-NEXT: vslidedown.vi v9, v9, 22939; RV64ZVE32-NEXT: vslide1down.vx v8, v8, t02940; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a32941; RV64ZVE32-NEXT: vslidedown.vi v8, v8, 12942; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a42943; RV64ZVE32-NEXT: vslide1down.vx v8, v8, t12944; RV64ZVE32-NEXT: vslidedown.vi v9, v9, 12945; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a02946; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a52947; RV64ZVE32-NEXT: vslidedown.vi v8, v9, 8, v0.t2948; RV64ZVE32-NEXT: ret2949 %p2 = getelementptr i8, ptr %p, i32 12950 %p3 = getelementptr i8, ptr %p, i32 222951 %p4 = getelementptr i8, ptr %p, i32 312952 %p5 = getelementptr i8, ptr %p, i32 442953 %p6 = getelementptr i8, ptr %p, i32 552954 %p7 = getelementptr i8, ptr %p, i32 6232955 %p8 = getelementptr i8, ptr %p, i32 752956 %p9 = getelementptr i8, ptr %p, i32 822957 %p10 = getelementptr i8, ptr %p, i32 932958 %p11 = getelementptr i8, ptr %p, i32 1052959 %p12 = getelementptr i8, ptr %p, i32 1612960 %p13 = getelementptr i8, ptr %p, i32 1242961 %p14 = getelementptr i8, ptr %p, i32 1632962 %p15 = getelementptr i8, ptr %p, i32 1442963 %p16 = getelementptr i8, ptr %p, i32 1542964 2965 %ld1 = load i8, ptr %p2966 %ld2 = load i8, ptr %p22967 %ld3 = load i8, ptr %p32968 %ld4 = load i8, ptr %p42969 %ld5 = load i8, ptr %p52970 %ld6 = load i8, ptr %p62971 %ld7 = load i8, ptr %p72972 %ld8 = load i8, ptr %p82973 %ld9 = load i8, ptr %p92974 %ld10 = load i8, ptr %p102975 %ld11 = load i8, ptr %p112976 %ld12 = load i8, ptr %p122977 %ld13 = load i8, ptr %p132978 %ld14 = load i8, ptr %p142979 %ld15 = load i8, ptr %p152980 %ld16 = load i8, ptr %p162981 2982 %v1 = insertelement <16 x i8> poison, i8 %ld1, i32 02983 %v2 = insertelement <16 x i8> %v1, i8 %ld2, i32 12984 %v3 = insertelement <16 x i8> %v2, i8 poison, i32 22985 %v4 = insertelement <16 x i8> %v3, i8 poison, i32 32986 %v5 = insertelement <16 x i8> %v4, i8 %ld5, i32 42987 %v6 = insertelement <16 x i8> %v5, i8 %ld6, i32 52988 %v7 = insertelement <16 x i8> %v6, i8 poison, i32 62989 %v8 = insertelement <16 x i8> %v7, i8 %ld8, i32 72990 %v9 = insertelement <16 x i8> %v8, i8 %ld9, i32 82991 %v10 = insertelement <16 x i8> %v9, i8 %ld10, i32 92992 %v11 = insertelement <16 x i8> %v10, i8 poison, i32 102993 %v12 = insertelement <16 x i8> %v11, i8 poison, i32 112994 %v13 = insertelement <16 x i8> %v12, i8 %ld13, i32 122995 %v14 = insertelement <16 x i8> %v13, i8 poison, i32 132996 %v15 = insertelement <16 x i8> %v14, i8 %ld15, i32 142997 %v16 = insertelement <16 x i8> %v15, i8 %ld16, i32 152998 ret <16 x i8> %v162999}3000 3001define <8 x i8> @buildvec_v8i8_pack(i8 %e1, i8 %e2, i8 %e3, i8 %e4, i8 %e5, i8 %e6, i8 %e7, i8 %e8) {3002; RV32-ONLY-LABEL: buildvec_v8i8_pack:3003; RV32-ONLY: # %bb.0:3004; RV32-ONLY-NEXT: vsetivli zero, 8, e8, mf2, ta, mu3005; RV32-ONLY-NEXT: vmv.v.x v8, a43006; RV32-ONLY-NEXT: vmv.v.x v9, a03007; RV32-ONLY-NEXT: vmv.v.i v0, 153008; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a53009; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a13010; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a63011; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a23012; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a73013; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a33014; RV32-ONLY-NEXT: vslidedown.vi v8, v9, 4, v0.t3015; RV32-ONLY-NEXT: ret3016;3017; RV32VB-LABEL: buildvec_v8i8_pack:3018; RV32VB: # %bb.0:3019; RV32VB-NEXT: slli a7, a7, 243020; RV32VB-NEXT: zext.b a6, a63021; RV32VB-NEXT: zext.b a4, a43022; RV32VB-NEXT: zext.b a5, a53023; RV32VB-NEXT: slli a3, a3, 243024; RV32VB-NEXT: zext.b a2, a23025; RV32VB-NEXT: zext.b a0, a03026; RV32VB-NEXT: zext.b a1, a13027; RV32VB-NEXT: slli a6, a6, 163028; RV32VB-NEXT: slli a5, a5, 83029; RV32VB-NEXT: slli a2, a2, 163030; RV32VB-NEXT: slli a1, a1, 83031; RV32VB-NEXT: or a6, a7, a63032; RV32VB-NEXT: or a4, a4, a53033; RV32VB-NEXT: or a2, a3, a23034; RV32VB-NEXT: or a0, a0, a13035; RV32VB-NEXT: or a1, a4, a63036; RV32VB-NEXT: or a0, a0, a23037; RV32VB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma3038; RV32VB-NEXT: vmv.v.x v8, a03039; RV32VB-NEXT: vslide1down.vx v8, v8, a13040; RV32VB-NEXT: ret3041;3042; RV32VB-PACK-LABEL: buildvec_v8i8_pack:3043; RV32VB-PACK: # %bb.0:3044; RV32VB-PACK-NEXT: packh a6, a6, a73045; RV32VB-PACK-NEXT: packh a4, a4, a53046; RV32VB-PACK-NEXT: packh a2, a2, a33047; RV32VB-PACK-NEXT: packh a0, a0, a13048; RV32VB-PACK-NEXT: pack a1, a4, a63049; RV32VB-PACK-NEXT: pack a0, a0, a23050; RV32VB-PACK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma3051; RV32VB-PACK-NEXT: vmv.v.x v8, a03052; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a13053; RV32VB-PACK-NEXT: ret3054;3055; RV64V-ONLY-LABEL: buildvec_v8i8_pack:3056; RV64V-ONLY: # %bb.0:3057; RV64V-ONLY-NEXT: vsetivli zero, 8, e8, mf2, ta, mu3058; RV64V-ONLY-NEXT: vmv.v.x v8, a43059; RV64V-ONLY-NEXT: vmv.v.x v9, a03060; RV64V-ONLY-NEXT: vmv.v.i v0, 153061; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a53062; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a13063; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a63064; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a23065; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a73066; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a33067; RV64V-ONLY-NEXT: vslidedown.vi v8, v9, 4, v0.t3068; RV64V-ONLY-NEXT: ret3069;3070; RVA22U64-LABEL: buildvec_v8i8_pack:3071; RVA22U64: # %bb.0:3072; RVA22U64-NEXT: zext.b t0, a43073; RVA22U64-NEXT: zext.b a5, a53074; RVA22U64-NEXT: slli a7, a7, 563075; RVA22U64-NEXT: zext.b a4, a63076; RVA22U64-NEXT: zext.b a2, a23077; RVA22U64-NEXT: zext.b a3, a33078; RVA22U64-NEXT: zext.b a0, a03079; RVA22U64-NEXT: zext.b a1, a13080; RVA22U64-NEXT: slli t0, t0, 323081; RVA22U64-NEXT: slli a5, a5, 403082; RVA22U64-NEXT: slli a4, a4, 483083; RVA22U64-NEXT: slli a2, a2, 163084; RVA22U64-NEXT: slli a3, a3, 243085; RVA22U64-NEXT: slli a1, a1, 83086; RVA22U64-NEXT: or a5, a5, t03087; RVA22U64-NEXT: or a4, a7, a43088; RVA22U64-NEXT: or a2, a2, a33089; RVA22U64-NEXT: or a0, a0, a13090; RVA22U64-NEXT: or a4, a4, a53091; RVA22U64-NEXT: or a0, a0, a23092; RVA22U64-NEXT: or a0, a0, a43093; RVA22U64-NEXT: vsetivli zero, 1, e64, m1, ta, ma3094; RVA22U64-NEXT: vmv.s.x v8, a03095; RVA22U64-NEXT: ret3096;3097; RVA22U64-PACK-LABEL: buildvec_v8i8_pack:3098; RVA22U64-PACK: # %bb.0:3099; RVA22U64-PACK-NEXT: packh a6, a6, a73100; RVA22U64-PACK-NEXT: packh a4, a4, a53101; RVA22U64-PACK-NEXT: packh a2, a2, a33102; RVA22U64-PACK-NEXT: packh a0, a0, a13103; RVA22U64-PACK-NEXT: packw a1, a4, a63104; RVA22U64-PACK-NEXT: packw a0, a0, a23105; RVA22U64-PACK-NEXT: pack a0, a0, a13106; RVA22U64-PACK-NEXT: vsetivli zero, 1, e64, m1, ta, ma3107; RVA22U64-PACK-NEXT: vmv.s.x v8, a03108; RVA22U64-PACK-NEXT: ret3109;3110; RV64ZVE32-LABEL: buildvec_v8i8_pack:3111; RV64ZVE32: # %bb.0:3112; RV64ZVE32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu3113; RV64ZVE32-NEXT: vmv.v.x v8, a43114; RV64ZVE32-NEXT: vmv.v.x v9, a03115; RV64ZVE32-NEXT: vmv.v.i v0, 153116; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a53117; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a13118; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a63119; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a23120; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a73121; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a33122; RV64ZVE32-NEXT: vslidedown.vi v8, v9, 4, v0.t3123; RV64ZVE32-NEXT: ret3124 %v1 = insertelement <8 x i8> poison, i8 %e1, i32 03125 %v2 = insertelement <8 x i8> %v1, i8 %e2, i32 13126 %v3 = insertelement <8 x i8> %v2, i8 %e3, i32 23127 %v4 = insertelement <8 x i8> %v3, i8 %e4, i32 33128 %v5 = insertelement <8 x i8> %v4, i8 %e5, i32 43129 %v6 = insertelement <8 x i8> %v5, i8 %e6, i32 53130 %v7 = insertelement <8 x i8> %v6, i8 %e7, i32 63131 %v8 = insertelement <8 x i8> %v7, i8 %e8, i32 73132 ret <8 x i8> %v83133}3134 3135define <6 x i8> @buildvec_v6i8_pack(i8 %e1, i8 %e2, i8 %e3, i8 %e4, i8 %e5, i8 %e6) {3136; RV32-ONLY-LABEL: buildvec_v6i8_pack:3137; RV32-ONLY: # %bb.0:3138; RV32-ONLY-NEXT: vsetivli zero, 8, e8, mf2, ta, ma3139; RV32-ONLY-NEXT: vmv.v.x v8, a03140; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a13141; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a23142; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a33143; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a43144; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a53145; RV32-ONLY-NEXT: vslidedown.vi v8, v8, 23146; RV32-ONLY-NEXT: ret3147;3148; RV32VB-LABEL: buildvec_v6i8_pack:3149; RV32VB: # %bb.0:3150; RV32VB-NEXT: slli a3, a3, 243151; RV32VB-NEXT: zext.b a2, a23152; RV32VB-NEXT: zext.b a0, a03153; RV32VB-NEXT: zext.b a1, a13154; RV32VB-NEXT: zext.b a4, a43155; RV32VB-NEXT: zext.b a5, a53156; RV32VB-NEXT: slli a2, a2, 163157; RV32VB-NEXT: slli a1, a1, 83158; RV32VB-NEXT: slli a5, a5, 83159; RV32VB-NEXT: or a2, a3, a23160; RV32VB-NEXT: or a0, a0, a13161; RV32VB-NEXT: or a0, a0, a23162; RV32VB-NEXT: or a4, a4, a53163; RV32VB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma3164; RV32VB-NEXT: vmv.v.x v8, a03165; RV32VB-NEXT: vslide1down.vx v8, v8, a43166; RV32VB-NEXT: ret3167;3168; RV32VB-PACK-LABEL: buildvec_v6i8_pack:3169; RV32VB-PACK: # %bb.0:3170; RV32VB-PACK-NEXT: packh a2, a2, a33171; RV32VB-PACK-NEXT: packh a0, a0, a13172; RV32VB-PACK-NEXT: packh a1, a4, a53173; RV32VB-PACK-NEXT: packh a3, a0, a03174; RV32VB-PACK-NEXT: pack a0, a0, a23175; RV32VB-PACK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma3176; RV32VB-PACK-NEXT: vmv.v.x v8, a03177; RV32VB-PACK-NEXT: pack a0, a1, a33178; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a03179; RV32VB-PACK-NEXT: ret3180;3181; RV64V-ONLY-LABEL: buildvec_v6i8_pack:3182; RV64V-ONLY: # %bb.0:3183; RV64V-ONLY-NEXT: vsetivli zero, 8, e8, mf2, ta, ma3184; RV64V-ONLY-NEXT: vmv.v.x v8, a03185; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a13186; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a23187; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a33188; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a43189; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a53190; RV64V-ONLY-NEXT: vslidedown.vi v8, v8, 23191; RV64V-ONLY-NEXT: ret3192;3193; RVA22U64-LABEL: buildvec_v6i8_pack:3194; RVA22U64: # %bb.0:3195; RVA22U64-NEXT: zext.b a2, a23196; RVA22U64-NEXT: zext.b a3, a33197; RVA22U64-NEXT: zext.b a0, a03198; RVA22U64-NEXT: zext.b a1, a13199; RVA22U64-NEXT: zext.b a4, a43200; RVA22U64-NEXT: zext.b a5, a53201; RVA22U64-NEXT: slli a2, a2, 163202; RVA22U64-NEXT: slli a3, a3, 243203; RVA22U64-NEXT: slli a1, a1, 83204; RVA22U64-NEXT: slli a4, a4, 323205; RVA22U64-NEXT: slli a5, a5, 403206; RVA22U64-NEXT: or a2, a2, a33207; RVA22U64-NEXT: or a0, a0, a13208; RVA22U64-NEXT: or a0, a0, a23209; RVA22U64-NEXT: or a4, a4, a53210; RVA22U64-NEXT: or a0, a0, a43211; RVA22U64-NEXT: vsetivli zero, 1, e64, m1, ta, ma3212; RVA22U64-NEXT: vmv.s.x v8, a03213; RVA22U64-NEXT: ret3214;3215; RVA22U64-PACK-LABEL: buildvec_v6i8_pack:3216; RVA22U64-PACK: # %bb.0:3217; RVA22U64-PACK-NEXT: packh a2, a2, a33218; RVA22U64-PACK-NEXT: packh a0, a0, a13219; RVA22U64-PACK-NEXT: packh a1, a4, a53220; RVA22U64-PACK-NEXT: packh a3, a0, a03221; RVA22U64-PACK-NEXT: packw a0, a0, a23222; RVA22U64-PACK-NEXT: packw a1, a1, a33223; RVA22U64-PACK-NEXT: pack a0, a0, a13224; RVA22U64-PACK-NEXT: vsetivli zero, 1, e64, m1, ta, ma3225; RVA22U64-PACK-NEXT: vmv.s.x v8, a03226; RVA22U64-PACK-NEXT: ret3227;3228; RV64ZVE32-LABEL: buildvec_v6i8_pack:3229; RV64ZVE32: # %bb.0:3230; RV64ZVE32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma3231; RV64ZVE32-NEXT: vmv.v.x v8, a03232; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a13233; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a23234; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a33235; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a43236; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a53237; RV64ZVE32-NEXT: vslidedown.vi v8, v8, 23238; RV64ZVE32-NEXT: ret3239 %v1 = insertelement <6 x i8> poison, i8 %e1, i32 03240 %v2 = insertelement <6 x i8> %v1, i8 %e2, i32 13241 %v3 = insertelement <6 x i8> %v2, i8 %e3, i32 23242 %v4 = insertelement <6 x i8> %v3, i8 %e4, i32 33243 %v5 = insertelement <6 x i8> %v4, i8 %e5, i32 43244 %v6 = insertelement <6 x i8> %v5, i8 %e6, i32 53245 ret <6 x i8> %v63246}3247 3248define <4 x i16> @buildvec_v4i16_pack(i16 %e1, i16 %e2, i16 %e3, i16 %e4) {3249; RV32-ONLY-LABEL: buildvec_v4i16_pack:3250; RV32-ONLY: # %bb.0:3251; RV32-ONLY-NEXT: vsetivli zero, 4, e16, mf2, ta, ma3252; RV32-ONLY-NEXT: vmv.v.x v8, a03253; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a13254; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a23255; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a33256; RV32-ONLY-NEXT: ret3257;3258; RV32VB-LABEL: buildvec_v4i16_pack:3259; RV32VB: # %bb.0:3260; RV32VB-NEXT: slli a3, a3, 163261; RV32VB-NEXT: zext.h a2, a23262; RV32VB-NEXT: slli a1, a1, 163263; RV32VB-NEXT: zext.h a0, a03264; RV32VB-NEXT: or a2, a2, a33265; RV32VB-NEXT: or a0, a0, a13266; RV32VB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma3267; RV32VB-NEXT: vmv.v.x v8, a03268; RV32VB-NEXT: vslide1down.vx v8, v8, a23269; RV32VB-NEXT: ret3270;3271; RV32VB-PACK-LABEL: buildvec_v4i16_pack:3272; RV32VB-PACK: # %bb.0:3273; RV32VB-PACK-NEXT: pack a2, a2, a33274; RV32VB-PACK-NEXT: pack a0, a0, a13275; RV32VB-PACK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma3276; RV32VB-PACK-NEXT: vmv.v.x v8, a03277; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a23278; RV32VB-PACK-NEXT: ret3279;3280; RV64V-ONLY-LABEL: buildvec_v4i16_pack:3281; RV64V-ONLY: # %bb.0:3282; RV64V-ONLY-NEXT: vsetivli zero, 4, e16, mf2, ta, ma3283; RV64V-ONLY-NEXT: vmv.v.x v8, a03284; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a13285; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a23286; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a33287; RV64V-ONLY-NEXT: ret3288;3289; RVA22U64-LABEL: buildvec_v4i16_pack:3290; RVA22U64: # %bb.0:3291; RVA22U64-NEXT: slli a3, a3, 483292; RVA22U64-NEXT: slli a2, a2, 483293; RVA22U64-NEXT: zext.h a0, a03294; RVA22U64-NEXT: slli a1, a1, 483295; RVA22U64-NEXT: srli a2, a2, 163296; RVA22U64-NEXT: srli a1, a1, 323297; RVA22U64-NEXT: or a2, a2, a33298; RVA22U64-NEXT: or a0, a0, a13299; RVA22U64-NEXT: or a0, a0, a23300; RVA22U64-NEXT: vsetivli zero, 1, e64, m1, ta, ma3301; RVA22U64-NEXT: vmv.s.x v8, a03302; RVA22U64-NEXT: ret3303;3304; RVA22U64-PACK-LABEL: buildvec_v4i16_pack:3305; RVA22U64-PACK: # %bb.0:3306; RVA22U64-PACK-NEXT: packw a2, a2, a33307; RVA22U64-PACK-NEXT: packw a0, a0, a13308; RVA22U64-PACK-NEXT: pack a0, a0, a23309; RVA22U64-PACK-NEXT: vsetivli zero, 1, e64, m1, ta, ma3310; RVA22U64-PACK-NEXT: vmv.s.x v8, a03311; RVA22U64-PACK-NEXT: ret3312;3313; RV64ZVE32-LABEL: buildvec_v4i16_pack:3314; RV64ZVE32: # %bb.0:3315; RV64ZVE32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma3316; RV64ZVE32-NEXT: vmv.v.x v8, a03317; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a13318; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a23319; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a33320; RV64ZVE32-NEXT: ret3321 %v1 = insertelement <4 x i16> poison, i16 %e1, i32 03322 %v2 = insertelement <4 x i16> %v1, i16 %e2, i32 13323 %v3 = insertelement <4 x i16> %v2, i16 %e3, i32 23324 %v4 = insertelement <4 x i16> %v3, i16 %e4, i32 33325 ret <4 x i16> %v43326}3327 3328define <2 x i32> @buildvec_v2i32_pack(i32 %e1, i32 %e2) {3329; RV32-LABEL: buildvec_v2i32_pack:3330; RV32: # %bb.0:3331; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma3332; RV32-NEXT: vmv.v.x v8, a03333; RV32-NEXT: vslide1down.vx v8, v8, a13334; RV32-NEXT: ret3335;3336; RV64V-ONLY-LABEL: buildvec_v2i32_pack:3337; RV64V-ONLY: # %bb.0:3338; RV64V-ONLY-NEXT: vsetivli zero, 2, e32, mf2, ta, ma3339; RV64V-ONLY-NEXT: vmv.v.x v8, a03340; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a13341; RV64V-ONLY-NEXT: ret3342;3343; RVA22U64-LABEL: buildvec_v2i32_pack:3344; RVA22U64: # %bb.0:3345; RVA22U64-NEXT: slli a1, a1, 323346; RVA22U64-NEXT: add.uw a0, a0, a13347; RVA22U64-NEXT: vsetivli zero, 1, e64, m1, ta, ma3348; RVA22U64-NEXT: vmv.s.x v8, a03349; RVA22U64-NEXT: ret3350;3351; RVA22U64-PACK-LABEL: buildvec_v2i32_pack:3352; RVA22U64-PACK: # %bb.0:3353; RVA22U64-PACK-NEXT: pack a0, a0, a13354; RVA22U64-PACK-NEXT: vsetivli zero, 1, e64, m1, ta, ma3355; RVA22U64-PACK-NEXT: vmv.s.x v8, a03356; RVA22U64-PACK-NEXT: ret3357;3358; RV64ZVE32-LABEL: buildvec_v2i32_pack:3359; RV64ZVE32: # %bb.0:3360; RV64ZVE32-NEXT: vsetivli zero, 2, e32, m1, ta, ma3361; RV64ZVE32-NEXT: vmv.v.x v8, a03362; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a13363; RV64ZVE32-NEXT: ret3364 %v1 = insertelement <2 x i32> poison, i32 %e1, i32 03365 %v2 = insertelement <2 x i32> %v1, i32 %e2, i32 13366 ret <2 x i32> %v23367}3368 3369define <1 x i16> @buildvec_v1i16_pack(i16 %e1) {3370; CHECK-LABEL: buildvec_v1i16_pack:3371; CHECK: # %bb.0:3372; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma3373; CHECK-NEXT: vmv.s.x v8, a03374; CHECK-NEXT: ret3375 %v1 = insertelement <1 x i16> poison, i16 %e1, i32 03376 ret <1 x i16> %v13377}3378 3379define <1 x i32> @buildvec_v1i32_pack(i32 %e1) {3380; CHECK-LABEL: buildvec_v1i32_pack:3381; CHECK: # %bb.0:3382; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma3383; CHECK-NEXT: vmv.s.x v8, a03384; CHECK-NEXT: ret3385 %v1 = insertelement <1 x i32> poison, i32 %e1, i32 03386 ret <1 x i32> %v13387}3388 3389define <4 x i32> @buildvec_vslide1up(i32 %e1, i32 %e2) {3390; CHECK-LABEL: buildvec_vslide1up:3391; CHECK: # %bb.0:3392; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma3393; CHECK-NEXT: vmv.v.x v8, a03394; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma3395; CHECK-NEXT: vmv.s.x v8, a13396; CHECK-NEXT: ret3397 %v1 = insertelement <4 x i32> poison, i32 %e2, i32 03398 %v2 = insertelement <4 x i32> %v1, i32 %e1, i32 13399 %v3 = insertelement <4 x i32> %v2, i32 %e1, i32 23400 %v4 = insertelement <4 x i32> %v3, i32 %e1, i32 33401 ret <4 x i32> %v43402}3403 3404define <4 x i1> @buildvec_i1_splat(i1 %e1) {3405; CHECK-LABEL: buildvec_i1_splat:3406; CHECK: # %bb.0:3407; CHECK-NEXT: andi a0, a0, 13408; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma3409; CHECK-NEXT: vmv.v.x v8, a03410; CHECK-NEXT: vmsne.vi v0, v8, 03411; CHECK-NEXT: ret3412 %v1 = insertelement <4 x i1> poison, i1 %e1, i32 03413 %v2 = insertelement <4 x i1> %v1, i1 %e1, i32 13414 %v3 = insertelement <4 x i1> %v2, i1 %e1, i32 23415 %v4 = insertelement <4 x i1> %v3, i1 %e1, i32 33416 ret <4 x i1> %v43417}3418 3419define <4 x i32> @buildvec_vredsum_slideup(<8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> %arg2, <8 x i32> %arg3) nounwind {3420; RV32-LABEL: buildvec_vredsum_slideup:3421; RV32: # %bb.0:3422; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma3423; RV32-NEXT: vmv.s.x v16, zero3424; RV32-NEXT: vredsum.vs v8, v8, v163425; RV32-NEXT: vredsum.vs v9, v10, v163426; RV32-NEXT: vredsum.vs v10, v12, v163427; RV32-NEXT: vredsum.vs v11, v14, v163428; RV32-NEXT: vsetivli zero, 4, e32, m1, tu, ma3429; RV32-NEXT: vslideup.vi v10, v11, 13430; RV32-NEXT: vslideup.vi v9, v10, 13431; RV32-NEXT: vslideup.vi v8, v9, 13432; RV32-NEXT: ret3433;3434; RV64V-ONLY-LABEL: buildvec_vredsum_slideup:3435; RV64V-ONLY: # %bb.0:3436; RV64V-ONLY-NEXT: vsetivli zero, 8, e32, m2, ta, ma3437; RV64V-ONLY-NEXT: vmv.s.x v16, zero3438; RV64V-ONLY-NEXT: vredsum.vs v8, v8, v163439; RV64V-ONLY-NEXT: vredsum.vs v9, v10, v163440; RV64V-ONLY-NEXT: vredsum.vs v10, v12, v163441; RV64V-ONLY-NEXT: vredsum.vs v11, v14, v163442; RV64V-ONLY-NEXT: vsetivli zero, 4, e32, m1, tu, ma3443; RV64V-ONLY-NEXT: vslideup.vi v10, v11, 13444; RV64V-ONLY-NEXT: vslideup.vi v9, v10, 13445; RV64V-ONLY-NEXT: vslideup.vi v8, v9, 13446; RV64V-ONLY-NEXT: ret3447;3448; RVA22U64-LABEL: buildvec_vredsum_slideup:3449; RVA22U64: # %bb.0:3450; RVA22U64-NEXT: vsetivli zero, 8, e32, m2, ta, ma3451; RVA22U64-NEXT: vmv.s.x v16, zero3452; RVA22U64-NEXT: vredsum.vs v8, v8, v163453; RVA22U64-NEXT: vredsum.vs v9, v10, v163454; RVA22U64-NEXT: vredsum.vs v10, v12, v163455; RVA22U64-NEXT: vredsum.vs v11, v14, v163456; RVA22U64-NEXT: vmv.x.s a0, v83457; RVA22U64-NEXT: vmv.x.s a1, v93458; RVA22U64-NEXT: vmv.x.s a2, v103459; RVA22U64-NEXT: slli a1, a1, 323460; RVA22U64-NEXT: add.uw a0, a0, a13461; RVA22U64-NEXT: vmv.x.s a1, v113462; RVA22U64-NEXT: slli a1, a1, 323463; RVA22U64-NEXT: add.uw a1, a2, a13464; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma3465; RVA22U64-NEXT: vmv.v.x v8, a03466; RVA22U64-NEXT: vslide1down.vx v8, v8, a13467; RVA22U64-NEXT: ret3468;3469; RVA22U64-PACK-LABEL: buildvec_vredsum_slideup:3470; RVA22U64-PACK: # %bb.0:3471; RVA22U64-PACK-NEXT: vsetivli zero, 8, e32, m2, ta, ma3472; RVA22U64-PACK-NEXT: vmv.s.x v16, zero3473; RVA22U64-PACK-NEXT: vredsum.vs v8, v8, v163474; RVA22U64-PACK-NEXT: vredsum.vs v9, v10, v163475; RVA22U64-PACK-NEXT: vredsum.vs v10, v12, v163476; RVA22U64-PACK-NEXT: vredsum.vs v11, v14, v163477; RVA22U64-PACK-NEXT: vmv.x.s a0, v83478; RVA22U64-PACK-NEXT: vmv.x.s a1, v93479; RVA22U64-PACK-NEXT: vmv.x.s a2, v103480; RVA22U64-PACK-NEXT: pack a0, a0, a13481; RVA22U64-PACK-NEXT: vmv.x.s a1, v113482; RVA22U64-PACK-NEXT: pack a1, a2, a13483; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma3484; RVA22U64-PACK-NEXT: vmv.v.x v8, a03485; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a13486; RVA22U64-PACK-NEXT: ret3487;3488; RV64ZVE32-LABEL: buildvec_vredsum_slideup:3489; RV64ZVE32: # %bb.0:3490; RV64ZVE32-NEXT: vsetivli zero, 8, e32, m2, ta, ma3491; RV64ZVE32-NEXT: vmv.s.x v16, zero3492; RV64ZVE32-NEXT: vredsum.vs v8, v8, v163493; RV64ZVE32-NEXT: vredsum.vs v9, v10, v163494; RV64ZVE32-NEXT: vredsum.vs v10, v12, v163495; RV64ZVE32-NEXT: vredsum.vs v11, v14, v163496; RV64ZVE32-NEXT: vsetivli zero, 4, e32, m1, tu, ma3497; RV64ZVE32-NEXT: vslideup.vi v10, v11, 13498; RV64ZVE32-NEXT: vslideup.vi v9, v10, 13499; RV64ZVE32-NEXT: vslideup.vi v8, v9, 13500; RV64ZVE32-NEXT: ret3501 %247 = tail call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %arg0)3502 %248 = insertelement <4 x i32> poison, i32 %247, i64 03503 %250 = tail call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %arg1)3504 %251 = insertelement <4 x i32> %248, i32 %250, i64 13505 %252 = tail call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %arg2)3506 %253 = insertelement <4 x i32> %251, i32 %252, i64 23507 %254 = tail call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %arg3)3508 %255 = insertelement <4 x i32> %253, i32 %254, i64 33509 ret <4 x i32> %2553510}3511 3512define <4 x i32> @buildvec_vredmax_slideup(<8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> %arg2, <8 x i32> %arg3) nounwind {3513; RV32-LABEL: buildvec_vredmax_slideup:3514; RV32: # %bb.0:3515; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma3516; RV32-NEXT: vredmaxu.vs v8, v8, v83517; RV32-NEXT: vredmaxu.vs v9, v10, v103518; RV32-NEXT: vredmaxu.vs v10, v12, v123519; RV32-NEXT: vredmaxu.vs v11, v14, v143520; RV32-NEXT: vsetivli zero, 4, e32, m1, tu, ma3521; RV32-NEXT: vslideup.vi v10, v11, 13522; RV32-NEXT: vslideup.vi v9, v10, 13523; RV32-NEXT: vslideup.vi v8, v9, 13524; RV32-NEXT: ret3525;3526; RV64V-ONLY-LABEL: buildvec_vredmax_slideup:3527; RV64V-ONLY: # %bb.0:3528; RV64V-ONLY-NEXT: vsetivli zero, 8, e32, m2, ta, ma3529; RV64V-ONLY-NEXT: vredmaxu.vs v8, v8, v83530; RV64V-ONLY-NEXT: vredmaxu.vs v9, v10, v103531; RV64V-ONLY-NEXT: vredmaxu.vs v10, v12, v123532; RV64V-ONLY-NEXT: vredmaxu.vs v11, v14, v143533; RV64V-ONLY-NEXT: vsetivli zero, 4, e32, m1, tu, ma3534; RV64V-ONLY-NEXT: vslideup.vi v10, v11, 13535; RV64V-ONLY-NEXT: vslideup.vi v9, v10, 13536; RV64V-ONLY-NEXT: vslideup.vi v8, v9, 13537; RV64V-ONLY-NEXT: ret3538;3539; RVA22U64-LABEL: buildvec_vredmax_slideup:3540; RVA22U64: # %bb.0:3541; RVA22U64-NEXT: vsetivli zero, 8, e32, m2, ta, ma3542; RVA22U64-NEXT: vredmaxu.vs v8, v8, v83543; RVA22U64-NEXT: vredmaxu.vs v9, v10, v103544; RVA22U64-NEXT: vredmaxu.vs v10, v12, v123545; RVA22U64-NEXT: vredmaxu.vs v11, v14, v143546; RVA22U64-NEXT: vmv.x.s a0, v83547; RVA22U64-NEXT: vmv.x.s a1, v93548; RVA22U64-NEXT: vmv.x.s a2, v103549; RVA22U64-NEXT: slli a1, a1, 323550; RVA22U64-NEXT: add.uw a0, a0, a13551; RVA22U64-NEXT: vmv.x.s a1, v113552; RVA22U64-NEXT: slli a1, a1, 323553; RVA22U64-NEXT: add.uw a1, a2, a13554; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma3555; RVA22U64-NEXT: vmv.v.x v8, a03556; RVA22U64-NEXT: vslide1down.vx v8, v8, a13557; RVA22U64-NEXT: ret3558;3559; RVA22U64-PACK-LABEL: buildvec_vredmax_slideup:3560; RVA22U64-PACK: # %bb.0:3561; RVA22U64-PACK-NEXT: vsetivli zero, 8, e32, m2, ta, ma3562; RVA22U64-PACK-NEXT: vredmaxu.vs v8, v8, v83563; RVA22U64-PACK-NEXT: vredmaxu.vs v9, v10, v103564; RVA22U64-PACK-NEXT: vredmaxu.vs v10, v12, v123565; RVA22U64-PACK-NEXT: vredmaxu.vs v11, v14, v143566; RVA22U64-PACK-NEXT: vmv.x.s a0, v83567; RVA22U64-PACK-NEXT: vmv.x.s a1, v93568; RVA22U64-PACK-NEXT: vmv.x.s a2, v103569; RVA22U64-PACK-NEXT: pack a0, a0, a13570; RVA22U64-PACK-NEXT: vmv.x.s a1, v113571; RVA22U64-PACK-NEXT: pack a1, a2, a13572; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma3573; RVA22U64-PACK-NEXT: vmv.v.x v8, a03574; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a13575; RVA22U64-PACK-NEXT: ret3576;3577; RV64ZVE32-LABEL: buildvec_vredmax_slideup:3578; RV64ZVE32: # %bb.0:3579; RV64ZVE32-NEXT: vsetivli zero, 8, e32, m2, ta, ma3580; RV64ZVE32-NEXT: vredmaxu.vs v8, v8, v83581; RV64ZVE32-NEXT: vredmaxu.vs v9, v10, v103582; RV64ZVE32-NEXT: vredmaxu.vs v10, v12, v123583; RV64ZVE32-NEXT: vredmaxu.vs v11, v14, v143584; RV64ZVE32-NEXT: vsetivli zero, 4, e32, m1, tu, ma3585; RV64ZVE32-NEXT: vslideup.vi v10, v11, 13586; RV64ZVE32-NEXT: vslideup.vi v9, v10, 13587; RV64ZVE32-NEXT: vslideup.vi v8, v9, 13588; RV64ZVE32-NEXT: ret3589 %247 = tail call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %arg0)3590 %248 = insertelement <4 x i32> poison, i32 %247, i64 03591 %250 = tail call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %arg1)3592 %251 = insertelement <4 x i32> %248, i32 %250, i64 13593 %252 = tail call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %arg2)3594 %253 = insertelement <4 x i32> %251, i32 %252, i64 23595 %254 = tail call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %arg3)3596 %255 = insertelement <4 x i32> %253, i32 %254, i64 33597 ret <4 x i32> %2553598}3599 3600define <16 x i16> @PR159294(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {3601; RV32-ONLY-LABEL: PR159294:3602; RV32-ONLY: # %bb.0: # %entry3603; RV32-ONLY-NEXT: vsetivli zero, 1, e32, m1, ta, ma3604; RV32-ONLY-NEXT: vmv.x.s a0, v83605; RV32-ONLY-NEXT: vmv.x.s a1, v93606; RV32-ONLY-NEXT: vmv.x.s a2, v103607; RV32-ONLY-NEXT: vsetivli zero, 16, e16, m2, ta, ma3608; RV32-ONLY-NEXT: vmv.v.x v8, a23609; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a03610; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a13611; RV32-ONLY-NEXT: vslidedown.vi v8, v8, 133612; RV32-ONLY-NEXT: ret3613;3614; RV32VB-LABEL: PR159294:3615; RV32VB: # %bb.0: # %entry3616; RV32VB-NEXT: vsetivli zero, 8, e32, m2, ta, ma3617; RV32VB-NEXT: vmv.x.s a0, v83618; RV32VB-NEXT: vmv.x.s a1, v103619; RV32VB-NEXT: slli a0, a0, 163620; RV32VB-NEXT: zext.h a1, a13621; RV32VB-NEXT: or a0, a1, a03622; RV32VB-NEXT: vmv.x.s a1, v93623; RV32VB-NEXT: vmv.v.i v8, 03624; RV32VB-NEXT: zext.h a1, a13625; RV32VB-NEXT: vsetvli zero, zero, e32, m2, tu, ma3626; RV32VB-NEXT: vmv.s.x v8, a03627; RV32VB-NEXT: vmv.s.x v10, a13628; RV32VB-NEXT: vsetivli zero, 2, e32, m1, tu, ma3629; RV32VB-NEXT: vslideup.vi v8, v10, 13630; RV32VB-NEXT: ret3631;3632; RV32VB-PACK-LABEL: PR159294:3633; RV32VB-PACK: # %bb.0: # %entry3634; RV32VB-PACK-NEXT: vsetivli zero, 8, e32, m2, ta, ma3635; RV32VB-PACK-NEXT: vmv.x.s a0, v83636; RV32VB-PACK-NEXT: vmv.x.s a1, v103637; RV32VB-PACK-NEXT: vmv.x.s a2, v93638; RV32VB-PACK-NEXT: pack a0, a1, a03639; RV32VB-PACK-NEXT: pack a1, a0, a03640; RV32VB-PACK-NEXT: vmv.v.x v8, a13641; RV32VB-PACK-NEXT: pack a1, a2, a03642; RV32VB-PACK-NEXT: vsetvli zero, zero, e32, m2, tu, ma3643; RV32VB-PACK-NEXT: vmv.s.x v8, a03644; RV32VB-PACK-NEXT: vmv.s.x v10, a13645; RV32VB-PACK-NEXT: vsetivli zero, 2, e32, m1, tu, ma3646; RV32VB-PACK-NEXT: vslideup.vi v8, v10, 13647; RV32VB-PACK-NEXT: ret3648;3649; RV64V-ONLY-LABEL: PR159294:3650; RV64V-ONLY: # %bb.0: # %entry3651; RV64V-ONLY-NEXT: vsetivli zero, 1, e32, m1, ta, ma3652; RV64V-ONLY-NEXT: vmv.x.s a0, v83653; RV64V-ONLY-NEXT: vmv.x.s a1, v93654; RV64V-ONLY-NEXT: vmv.x.s a2, v103655; RV64V-ONLY-NEXT: vsetivli zero, 16, e16, m2, ta, ma3656; RV64V-ONLY-NEXT: vmv.v.x v8, a23657; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a03658; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a13659; RV64V-ONLY-NEXT: vslidedown.vi v8, v8, 133660; RV64V-ONLY-NEXT: ret3661;3662; RVA22U64-LABEL: PR159294:3663; RVA22U64: # %bb.0: # %entry3664; RVA22U64-NEXT: vsetivli zero, 8, e32, m2, ta, ma3665; RVA22U64-NEXT: vmv.x.s a0, v83666; RVA22U64-NEXT: vmv.x.s a1, v103667; RVA22U64-NEXT: slli a0, a0, 163668; RVA22U64-NEXT: zext.h a1, a13669; RVA22U64-NEXT: or a0, a0, a13670; RVA22U64-NEXT: vmv.x.s a1, v93671; RVA22U64-NEXT: vmv.v.i v8, 03672; RVA22U64-NEXT: zext.h a1, a13673; RVA22U64-NEXT: vsetvli zero, zero, e32, m2, tu, ma3674; RVA22U64-NEXT: vmv.s.x v8, a03675; RVA22U64-NEXT: vmv.s.x v10, a13676; RVA22U64-NEXT: vsetivli zero, 2, e32, m1, tu, ma3677; RVA22U64-NEXT: vslideup.vi v8, v10, 13678; RVA22U64-NEXT: ret3679;3680; RVA22U64-PACK-LABEL: PR159294:3681; RVA22U64-PACK: # %bb.0: # %entry3682; RVA22U64-PACK-NEXT: vsetivli zero, 8, e32, m2, ta, ma3683; RVA22U64-PACK-NEXT: vmv.x.s a0, v83684; RVA22U64-PACK-NEXT: vmv.x.s a1, v103685; RVA22U64-PACK-NEXT: vmv.x.s a2, v93686; RVA22U64-PACK-NEXT: packw a0, a1, a03687; RVA22U64-PACK-NEXT: packw a1, a0, a03688; RVA22U64-PACK-NEXT: vmv.v.x v8, a13689; RVA22U64-PACK-NEXT: packw a1, a2, a03690; RVA22U64-PACK-NEXT: vsetvli zero, zero, e32, m2, tu, ma3691; RVA22U64-PACK-NEXT: vmv.s.x v8, a03692; RVA22U64-PACK-NEXT: vmv.s.x v10, a13693; RVA22U64-PACK-NEXT: vsetivli zero, 2, e32, m1, tu, ma3694; RVA22U64-PACK-NEXT: vslideup.vi v8, v10, 13695; RVA22U64-PACK-NEXT: ret3696;3697; RV64ZVE32-LABEL: PR159294:3698; RV64ZVE32: # %bb.0: # %entry3699; RV64ZVE32-NEXT: vsetivli zero, 1, e32, m1, ta, ma3700; RV64ZVE32-NEXT: vmv.x.s a0, v83701; RV64ZVE32-NEXT: vmv.x.s a1, v93702; RV64ZVE32-NEXT: vmv.x.s a2, v103703; RV64ZVE32-NEXT: vsetivli zero, 16, e16, m2, ta, ma3704; RV64ZVE32-NEXT: vmv.v.x v8, a23705; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a03706; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a13707; RV64ZVE32-NEXT: vslidedown.vi v8, v8, 133708; RV64ZVE32-NEXT: ret3709entry:3710 %vecext3 = extractelement <2 x i32> %a, i32 03711 %conv4 = trunc i32 %vecext3 to i163712 %vecinit5 = insertelement <16 x i16> <i16 0, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison>, i16 %conv4, i32 13713 %vecext7 = extractelement <2 x i32> %b, i32 03714 %conv8 = trunc i32 %vecext7 to i163715 %vecinit9 = insertelement <16 x i16> %vecinit5, i16 %conv8, i32 23716 %vecext59 = extractelement <2 x i32> %c, i32 03717 %conv60 = trunc i32 %vecext59 to i163718 %vecinit61 = insertelement <16 x i16> %vecinit9, i16 %conv60, i32 03719 ret <16 x i16> %vecinit613720}3721 3722define <16 x i32> @PR159294_zext(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {3723; RV32-LABEL: PR159294_zext:3724; RV32: # %bb.0: # %entry3725; RV32-NEXT: vsetivli zero, 1, e16, m1, ta, ma3726; RV32-NEXT: vmv.x.s a0, v83727; RV32-NEXT: vmv.x.s a1, v93728; RV32-NEXT: vmv.x.s a2, v103729; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma3730; RV32-NEXT: vmv.v.x v8, a23731; RV32-NEXT: lui a2, 163732; RV32-NEXT: vslide1down.vx v8, v8, a03733; RV32-NEXT: vslide1down.vx v8, v8, a13734; RV32-NEXT: vslidedown.vi v8, v8, 133735; RV32-NEXT: addi a2, a2, -13736; RV32-NEXT: vand.vx v8, v8, a23737; RV32-NEXT: ret3738;3739; RV64V-ONLY-LABEL: PR159294_zext:3740; RV64V-ONLY: # %bb.0: # %entry3741; RV64V-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma3742; RV64V-ONLY-NEXT: vmv.x.s a0, v83743; RV64V-ONLY-NEXT: lui a1, 163744; RV64V-ONLY-NEXT: vmv.x.s a2, v93745; RV64V-ONLY-NEXT: vmv.x.s a3, v103746; RV64V-ONLY-NEXT: addi a1, a1, -13747; RV64V-ONLY-NEXT: and a0, a0, a13748; RV64V-ONLY-NEXT: and a2, a2, a13749; RV64V-ONLY-NEXT: and a1, a3, a13750; RV64V-ONLY-NEXT: vsetivli zero, 16, e32, m4, ta, ma3751; RV64V-ONLY-NEXT: vmv.v.x v8, a13752; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a03753; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a23754; RV64V-ONLY-NEXT: vslidedown.vi v8, v8, 133755; RV64V-ONLY-NEXT: ret3756;3757; RVA22U64-LABEL: PR159294_zext:3758; RVA22U64: # %bb.0: # %entry3759; RVA22U64-NEXT: vsetivli zero, 1, e16, m1, ta, ma3760; RVA22U64-NEXT: vmv.x.s a0, v83761; RVA22U64-NEXT: vmv.x.s a1, v103762; RVA22U64-NEXT: slli a0, a0, 483763; RVA22U64-NEXT: zext.h a1, a13764; RVA22U64-NEXT: srli a0, a0, 163765; RVA22U64-NEXT: or a0, a0, a13766; RVA22U64-NEXT: vmv.x.s a1, v93767; RVA22U64-NEXT: vsetivli zero, 8, e64, m4, ta, ma3768; RVA22U64-NEXT: vmv.v.i v8, 03769; RVA22U64-NEXT: zext.h a1, a13770; RVA22U64-NEXT: vsetvli zero, zero, e64, m4, tu, ma3771; RVA22U64-NEXT: vmv.s.x v8, a03772; RVA22U64-NEXT: vmv.s.x v12, a13773; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, tu, ma3774; RVA22U64-NEXT: vslideup.vi v8, v12, 13775; RVA22U64-NEXT: ret3776;3777; RVA22U64-PACK-LABEL: PR159294_zext:3778; RVA22U64-PACK: # %bb.0: # %entry3779; RVA22U64-PACK-NEXT: vsetivli zero, 1, e16, m2, ta, ma3780; RVA22U64-PACK-NEXT: vmv1r.v v12, v93781; RVA22U64-PACK-NEXT: vmv.x.s a0, v83782; RVA22U64-PACK-NEXT: vmv.x.s a1, v103783; RVA22U64-PACK-NEXT: pack a2, a0, a03784; RVA22U64-PACK-NEXT: vsetivli zero, 8, e64, m4, ta, ma3785; RVA22U64-PACK-NEXT: vmv.v.x v8, a23786; RVA22U64-PACK-NEXT: vsetvli zero, zero, e16, m1, ta, ma3787; RVA22U64-PACK-NEXT: vmv.x.s a2, v123788; RVA22U64-PACK-NEXT: zext.h a0, a03789; RVA22U64-PACK-NEXT: zext.h a1, a13790; RVA22U64-PACK-NEXT: zext.h a2, a23791; RVA22U64-PACK-NEXT: pack a0, a1, a03792; RVA22U64-PACK-NEXT: pack a1, a2, a03793; RVA22U64-PACK-NEXT: vsetvli zero, zero, e64, m4, tu, ma3794; RVA22U64-PACK-NEXT: vmv.s.x v8, a03795; RVA22U64-PACK-NEXT: vmv.s.x v12, a13796; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, tu, ma3797; RVA22U64-PACK-NEXT: vslideup.vi v8, v12, 13798; RVA22U64-PACK-NEXT: ret3799;3800; RV64ZVE32-LABEL: PR159294_zext:3801; RV64ZVE32: # %bb.0: # %entry3802; RV64ZVE32-NEXT: vsetivli zero, 1, e16, m1, ta, ma3803; RV64ZVE32-NEXT: vmv.x.s a0, v83804; RV64ZVE32-NEXT: lui a1, 163805; RV64ZVE32-NEXT: vmv.x.s a2, v93806; RV64ZVE32-NEXT: vmv.x.s a3, v103807; RV64ZVE32-NEXT: addi a1, a1, -13808; RV64ZVE32-NEXT: and a0, a0, a13809; RV64ZVE32-NEXT: and a2, a2, a13810; RV64ZVE32-NEXT: and a1, a3, a13811; RV64ZVE32-NEXT: vsetivli zero, 16, e32, m4, ta, ma3812; RV64ZVE32-NEXT: vmv.v.x v8, a13813; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a03814; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a23815; RV64ZVE32-NEXT: vslidedown.vi v8, v8, 133816; RV64ZVE32-NEXT: ret3817entry:3818 %vecext3 = extractelement <2 x i16> %a, i32 03819 %conv4 = zext i16 %vecext3 to i323820 %vecinit5 = insertelement <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, i32 %conv4, i32 13821 %vecext7 = extractelement <2 x i16> %b, i32 03822 %conv8 = zext i16 %vecext7 to i323823 %vecinit9 = insertelement <16 x i32> %vecinit5, i32 %conv8, i32 23824 %vecext59 = extractelement <2 x i16> %c, i32 03825 %conv60 = zext i16 %vecext59 to i323826 %vecinit61 = insertelement <16 x i32> %vecinit9, i32 %conv60, i32 03827 ret <16 x i32> %vecinit613828}3829 3830define <16 x i32> @PR159294_sext(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {3831; RV32-LABEL: PR159294_sext:3832; RV32: # %bb.0: # %entry3833; RV32-NEXT: vsetivli zero, 1, e16, m1, ta, ma3834; RV32-NEXT: vmv.x.s a0, v83835; RV32-NEXT: vmv.x.s a1, v93836; RV32-NEXT: vmv.x.s a2, v103837; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma3838; RV32-NEXT: vmv.v.x v8, a23839; RV32-NEXT: vslide1down.vx v8, v8, a03840; RV32-NEXT: vslide1down.vx v8, v8, a13841; RV32-NEXT: vslidedown.vi v8, v8, 133842; RV32-NEXT: ret3843;3844; RV64V-ONLY-LABEL: PR159294_sext:3845; RV64V-ONLY: # %bb.0: # %entry3846; RV64V-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma3847; RV64V-ONLY-NEXT: vmv.x.s a0, v83848; RV64V-ONLY-NEXT: vmv.x.s a1, v93849; RV64V-ONLY-NEXT: vmv.x.s a2, v103850; RV64V-ONLY-NEXT: vsetivli zero, 16, e32, m4, ta, ma3851; RV64V-ONLY-NEXT: vmv.v.x v8, a23852; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a03853; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a13854; RV64V-ONLY-NEXT: vslidedown.vi v8, v8, 133855; RV64V-ONLY-NEXT: ret3856;3857; RVA22U64-LABEL: PR159294_sext:3858; RVA22U64: # %bb.0: # %entry3859; RVA22U64-NEXT: vsetivli zero, 1, e16, m1, ta, ma3860; RVA22U64-NEXT: vmv.x.s a0, v83861; RVA22U64-NEXT: vmv.x.s a1, v103862; RVA22U64-NEXT: slli a0, a0, 323863; RVA22U64-NEXT: add.uw a0, a1, a03864; RVA22U64-NEXT: vmv.x.s a1, v93865; RVA22U64-NEXT: vsetivli zero, 8, e64, m4, ta, ma3866; RVA22U64-NEXT: vmv.v.i v8, 03867; RVA22U64-NEXT: zext.w a1, a13868; RVA22U64-NEXT: vsetvli zero, zero, e64, m4, tu, ma3869; RVA22U64-NEXT: vmv.s.x v8, a03870; RVA22U64-NEXT: vmv.s.x v12, a13871; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, tu, ma3872; RVA22U64-NEXT: vslideup.vi v8, v12, 13873; RVA22U64-NEXT: ret3874;3875; RVA22U64-PACK-LABEL: PR159294_sext:3876; RVA22U64-PACK: # %bb.0: # %entry3877; RVA22U64-PACK-NEXT: vsetivli zero, 1, e16, m1, ta, ma3878; RVA22U64-PACK-NEXT: vmv.x.s a0, v83879; RVA22U64-PACK-NEXT: vmv.x.s a1, v103880; RVA22U64-PACK-NEXT: vmv.x.s a2, v93881; RVA22U64-PACK-NEXT: pack a0, a1, a03882; RVA22U64-PACK-NEXT: pack a1, a0, a03883; RVA22U64-PACK-NEXT: vsetivli zero, 8, e64, m4, ta, ma3884; RVA22U64-PACK-NEXT: vmv.v.x v8, a13885; RVA22U64-PACK-NEXT: pack a1, a2, a03886; RVA22U64-PACK-NEXT: vsetvli zero, zero, e64, m4, tu, ma3887; RVA22U64-PACK-NEXT: vmv.s.x v8, a03888; RVA22U64-PACK-NEXT: vmv.s.x v12, a13889; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, tu, ma3890; RVA22U64-PACK-NEXT: vslideup.vi v8, v12, 13891; RVA22U64-PACK-NEXT: ret3892;3893; RV64ZVE32-LABEL: PR159294_sext:3894; RV64ZVE32: # %bb.0: # %entry3895; RV64ZVE32-NEXT: vsetivli zero, 1, e16, m1, ta, ma3896; RV64ZVE32-NEXT: vmv.x.s a0, v83897; RV64ZVE32-NEXT: vmv.x.s a1, v93898; RV64ZVE32-NEXT: vmv.x.s a2, v103899; RV64ZVE32-NEXT: vsetivli zero, 16, e32, m4, ta, ma3900; RV64ZVE32-NEXT: vmv.v.x v8, a23901; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a03902; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a13903; RV64ZVE32-NEXT: vslidedown.vi v8, v8, 133904; RV64ZVE32-NEXT: ret3905entry:3906 %vecext3 = extractelement <2 x i16> %a, i32 03907 %conv4 = sext i16 %vecext3 to i323908 %vecinit5 = insertelement <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, i32 %conv4, i32 13909 %vecext7 = extractelement <2 x i16> %b, i32 03910 %conv8 = sext i16 %vecext7 to i323911 %vecinit9 = insertelement <16 x i32> %vecinit5, i32 %conv8, i32 23912 %vecext59 = extractelement <2 x i16> %c, i32 03913 %conv60 = sext i16 %vecext59 to i323914 %vecinit61 = insertelement <16 x i32> %vecinit9, i32 %conv60, i32 03915 ret <16 x i32> %vecinit613916}3917;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:3918; RV64: {{.*}}3919