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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define i8 @explode_2xi8(<2 x i8> %v) {6; CHECK-LABEL: explode_2xi8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma9; CHECK-NEXT: vmv.s.x v9, zero10; CHECK-NEXT: vredxor.vs v8, v8, v911; CHECK-NEXT: vmv.x.s a0, v812; CHECK-NEXT: ret13 %e0 = extractelement <2 x i8> %v, i32 014 %e1 = extractelement <2 x i8> %v, i32 115 %add0 = xor i8 %e0, %e116 ret i8 %add017}18 19define i8 @explode_4xi8(<4 x i8> %v) {20; CHECK-LABEL: explode_4xi8:21; CHECK: # %bb.0:22; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma23; CHECK-NEXT: vslidedown.vi v9, v8, 224; CHECK-NEXT: vmv.x.s a0, v925; CHECK-NEXT: vslidedown.vi v9, v8, 326; CHECK-NEXT: vmv.x.s a1, v927; CHECK-NEXT: vmv.s.x v9, zero28; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma29; CHECK-NEXT: vredxor.vs v8, v8, v930; CHECK-NEXT: vmv.x.s a2, v831; CHECK-NEXT: add a0, a0, a132; CHECK-NEXT: add a0, a2, a033; CHECK-NEXT: ret34 %e0 = extractelement <4 x i8> %v, i32 035 %e1 = extractelement <4 x i8> %v, i32 136 %e2 = extractelement <4 x i8> %v, i32 237 %e3 = extractelement <4 x i8> %v, i32 338 %add0 = xor i8 %e0, %e139 %add1 = add i8 %add0, %e240 %add2 = add i8 %add1, %e341 ret i8 %add242}43 44 45define i8 @explode_8xi8(<8 x i8> %v) {46; CHECK-LABEL: explode_8xi8:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma49; CHECK-NEXT: vslidedown.vi v9, v8, 250; CHECK-NEXT: vmv.x.s a0, v951; CHECK-NEXT: vslidedown.vi v9, v8, 352; CHECK-NEXT: vmv.x.s a1, v953; CHECK-NEXT: vslidedown.vi v9, v8, 454; CHECK-NEXT: vmv.x.s a2, v955; CHECK-NEXT: vslidedown.vi v9, v8, 556; CHECK-NEXT: vmv.x.s a3, v957; CHECK-NEXT: vslidedown.vi v9, v8, 658; CHECK-NEXT: vmv.x.s a4, v959; CHECK-NEXT: vslidedown.vi v9, v8, 760; CHECK-NEXT: vmv.x.s a5, v961; CHECK-NEXT: vmv.s.x v9, zero62; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma63; CHECK-NEXT: vredxor.vs v8, v8, v964; CHECK-NEXT: vmv.x.s a6, v865; CHECK-NEXT: add a0, a0, a166; CHECK-NEXT: add a2, a2, a367; CHECK-NEXT: add a0, a6, a068; CHECK-NEXT: add a2, a2, a469; CHECK-NEXT: add a0, a0, a270; CHECK-NEXT: add a0, a0, a571; CHECK-NEXT: ret72 %e0 = extractelement <8 x i8> %v, i32 073 %e1 = extractelement <8 x i8> %v, i32 174 %e2 = extractelement <8 x i8> %v, i32 275 %e3 = extractelement <8 x i8> %v, i32 376 %e4 = extractelement <8 x i8> %v, i32 477 %e5 = extractelement <8 x i8> %v, i32 578 %e6 = extractelement <8 x i8> %v, i32 679 %e7 = extractelement <8 x i8> %v, i32 780 %add0 = xor i8 %e0, %e181 %add1 = add i8 %add0, %e282 %add2 = add i8 %add1, %e383 %add3 = add i8 %add2, %e484 %add4 = add i8 %add3, %e585 %add5 = add i8 %add4, %e686 %add6 = add i8 %add5, %e787 ret i8 %add688}89 90define i8 @explode_16xi8(<16 x i8> %v) {91; CHECK-LABEL: explode_16xi8:92; CHECK: # %bb.0:93; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma94; CHECK-NEXT: vslidedown.vi v9, v8, 295; CHECK-NEXT: vmv.x.s a0, v996; CHECK-NEXT: vslidedown.vi v9, v8, 397; CHECK-NEXT: vmv.x.s a1, v998; CHECK-NEXT: vslidedown.vi v9, v8, 499; CHECK-NEXT: vmv.x.s a2, v9100; CHECK-NEXT: vslidedown.vi v9, v8, 5101; CHECK-NEXT: vmv.x.s a3, v9102; CHECK-NEXT: vslidedown.vi v9, v8, 6103; CHECK-NEXT: vmv.x.s a4, v9104; CHECK-NEXT: vslidedown.vi v9, v8, 7105; CHECK-NEXT: vmv.x.s a5, v9106; CHECK-NEXT: vslidedown.vi v9, v8, 8107; CHECK-NEXT: vmv.x.s a6, v9108; CHECK-NEXT: vslidedown.vi v9, v8, 9109; CHECK-NEXT: vmv.x.s a7, v9110; CHECK-NEXT: vslidedown.vi v9, v8, 10111; CHECK-NEXT: vmv.x.s t0, v9112; CHECK-NEXT: vslidedown.vi v9, v8, 11113; CHECK-NEXT: vmv.x.s t1, v9114; CHECK-NEXT: vslidedown.vi v9, v8, 12115; CHECK-NEXT: vmv.x.s t2, v9116; CHECK-NEXT: vslidedown.vi v9, v8, 13117; CHECK-NEXT: vmv.x.s t3, v9118; CHECK-NEXT: vslidedown.vi v9, v8, 14119; CHECK-NEXT: vmv.x.s t4, v9120; CHECK-NEXT: vslidedown.vi v9, v8, 15121; CHECK-NEXT: vmv.x.s t5, v9122; CHECK-NEXT: vmv.s.x v9, zero123; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma124; CHECK-NEXT: vredxor.vs v8, v8, v9125; CHECK-NEXT: vmv.x.s t6, v8126; CHECK-NEXT: add a0, a0, a1127; CHECK-NEXT: add a2, a2, a3128; CHECK-NEXT: add a5, a5, a6129; CHECK-NEXT: add t1, t1, t2130; CHECK-NEXT: add a0, t6, a0131; CHECK-NEXT: add a2, a2, a4132; CHECK-NEXT: add a5, a5, a7133; CHECK-NEXT: add t1, t1, t3134; CHECK-NEXT: add a0, a0, a2135; CHECK-NEXT: add a5, a5, t0136; CHECK-NEXT: add t1, t1, t4137; CHECK-NEXT: add a0, a0, a5138; CHECK-NEXT: add t1, t1, t5139; CHECK-NEXT: add a0, a0, t1140; CHECK-NEXT: ret141 %e0 = extractelement <16 x i8> %v, i32 0142 %e1 = extractelement <16 x i8> %v, i32 1143 %e2 = extractelement <16 x i8> %v, i32 2144 %e3 = extractelement <16 x i8> %v, i32 3145 %e4 = extractelement <16 x i8> %v, i32 4146 %e5 = extractelement <16 x i8> %v, i32 5147 %e6 = extractelement <16 x i8> %v, i32 6148 %e7 = extractelement <16 x i8> %v, i32 7149 %e8 = extractelement <16 x i8> %v, i32 8150 %e9 = extractelement <16 x i8> %v, i32 9151 %e10 = extractelement <16 x i8> %v, i32 10152 %e11 = extractelement <16 x i8> %v, i32 11153 %e12 = extractelement <16 x i8> %v, i32 12154 %e13 = extractelement <16 x i8> %v, i32 13155 %e14 = extractelement <16 x i8> %v, i32 14156 %e15 = extractelement <16 x i8> %v, i32 15157 %add0 = xor i8 %e0, %e1158 %add1 = add i8 %add0, %e2159 %add2 = add i8 %add1, %e3160 %add3 = add i8 %add2, %e4161 %add4 = add i8 %add3, %e5162 %add5 = add i8 %add4, %e6163 %add6 = add i8 %add5, %e7164 %add7 = add i8 %add6, %e8165 %add8 = add i8 %add7, %e9166 %add9 = add i8 %add8, %e10167 %add10 = add i8 %add9, %e11168 %add11 = add i8 %add10, %e12169 %add12 = add i8 %add11, %e13170 %add13 = add i8 %add12, %e14171 %add14 = add i8 %add13, %e15172 ret i8 %add14173}174 175define i16 @explode_2xi16(<2 x i16> %v) {176; CHECK-LABEL: explode_2xi16:177; CHECK: # %bb.0:178; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma179; CHECK-NEXT: vmv.s.x v9, zero180; CHECK-NEXT: vredxor.vs v8, v8, v9181; CHECK-NEXT: vmv.x.s a0, v8182; CHECK-NEXT: ret183 %e0 = extractelement <2 x i16> %v, i32 0184 %e1 = extractelement <2 x i16> %v, i32 1185 %add0 = xor i16 %e0, %e1186 ret i16 %add0187}188 189define i16 @explode_4xi16(<4 x i16> %v) {190; CHECK-LABEL: explode_4xi16:191; CHECK: # %bb.0:192; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma193; CHECK-NEXT: vslidedown.vi v9, v8, 2194; CHECK-NEXT: vmv.x.s a0, v9195; CHECK-NEXT: vslidedown.vi v9, v8, 3196; CHECK-NEXT: vmv.x.s a1, v9197; CHECK-NEXT: vmv.s.x v9, zero198; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma199; CHECK-NEXT: vredxor.vs v8, v8, v9200; CHECK-NEXT: vmv.x.s a2, v8201; CHECK-NEXT: add a0, a0, a1202; CHECK-NEXT: add a0, a2, a0203; CHECK-NEXT: ret204 %e0 = extractelement <4 x i16> %v, i32 0205 %e1 = extractelement <4 x i16> %v, i32 1206 %e2 = extractelement <4 x i16> %v, i32 2207 %e3 = extractelement <4 x i16> %v, i32 3208 %add0 = xor i16 %e0, %e1209 %add1 = add i16 %add0, %e2210 %add2 = add i16 %add1, %e3211 ret i16 %add2212}213 214 215define i16 @explode_8xi16(<8 x i16> %v) {216; CHECK-LABEL: explode_8xi16:217; CHECK: # %bb.0:218; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma219; CHECK-NEXT: vslidedown.vi v9, v8, 2220; CHECK-NEXT: vmv.x.s a0, v9221; CHECK-NEXT: vslidedown.vi v9, v8, 3222; CHECK-NEXT: vmv.x.s a1, v9223; CHECK-NEXT: vslidedown.vi v9, v8, 4224; CHECK-NEXT: vmv.x.s a2, v9225; CHECK-NEXT: vslidedown.vi v9, v8, 5226; CHECK-NEXT: vmv.x.s a3, v9227; CHECK-NEXT: vslidedown.vi v9, v8, 6228; CHECK-NEXT: vmv.x.s a4, v9229; CHECK-NEXT: vslidedown.vi v9, v8, 7230; CHECK-NEXT: vmv.x.s a5, v9231; CHECK-NEXT: vmv.s.x v9, zero232; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma233; CHECK-NEXT: vredxor.vs v8, v8, v9234; CHECK-NEXT: vmv.x.s a6, v8235; CHECK-NEXT: add a0, a0, a1236; CHECK-NEXT: add a2, a2, a3237; CHECK-NEXT: add a0, a6, a0238; CHECK-NEXT: add a2, a2, a4239; CHECK-NEXT: add a0, a0, a2240; CHECK-NEXT: add a0, a0, a5241; CHECK-NEXT: ret242 %e0 = extractelement <8 x i16> %v, i32 0243 %e1 = extractelement <8 x i16> %v, i32 1244 %e2 = extractelement <8 x i16> %v, i32 2245 %e3 = extractelement <8 x i16> %v, i32 3246 %e4 = extractelement <8 x i16> %v, i32 4247 %e5 = extractelement <8 x i16> %v, i32 5248 %e6 = extractelement <8 x i16> %v, i32 6249 %e7 = extractelement <8 x i16> %v, i32 7250 %add0 = xor i16 %e0, %e1251 %add1 = add i16 %add0, %e2252 %add2 = add i16 %add1, %e3253 %add3 = add i16 %add2, %e4254 %add4 = add i16 %add3, %e5255 %add5 = add i16 %add4, %e6256 %add6 = add i16 %add5, %e7257 ret i16 %add6258}259 260define i16 @explode_16xi16(<16 x i16> %v) {261; CHECK-LABEL: explode_16xi16:262; CHECK: # %bb.0:263; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, ma264; CHECK-NEXT: vslidedown.vi v10, v8, 8265; CHECK-NEXT: vmv.x.s a0, v10266; CHECK-NEXT: vslidedown.vi v10, v8, 9267; CHECK-NEXT: vmv.x.s a1, v10268; CHECK-NEXT: vslidedown.vi v10, v8, 10269; CHECK-NEXT: vmv.x.s a2, v10270; CHECK-NEXT: vslidedown.vi v10, v8, 11271; CHECK-NEXT: vmv.x.s a3, v10272; CHECK-NEXT: vslidedown.vi v10, v8, 12273; CHECK-NEXT: vmv.x.s a4, v10274; CHECK-NEXT: vslidedown.vi v10, v8, 13275; CHECK-NEXT: vmv.x.s a5, v10276; CHECK-NEXT: vslidedown.vi v10, v8, 14277; CHECK-NEXT: vmv.x.s a6, v10278; CHECK-NEXT: vslidedown.vi v10, v8, 15279; CHECK-NEXT: vmv.x.s a7, v10280; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma281; CHECK-NEXT: vslidedown.vi v9, v8, 2282; CHECK-NEXT: vslidedown.vi v10, v8, 3283; CHECK-NEXT: vmv.x.s t0, v9284; CHECK-NEXT: vslidedown.vi v9, v8, 4285; CHECK-NEXT: vmv.x.s t1, v10286; CHECK-NEXT: vslidedown.vi v10, v8, 5287; CHECK-NEXT: vmv.x.s t2, v9288; CHECK-NEXT: vslidedown.vi v9, v8, 6289; CHECK-NEXT: vmv.x.s t3, v10290; CHECK-NEXT: vslidedown.vi v10, v8, 7291; CHECK-NEXT: vmv.x.s t4, v9292; CHECK-NEXT: vmv.s.x v9, zero293; CHECK-NEXT: vmv.x.s t5, v10294; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma295; CHECK-NEXT: vredxor.vs v8, v8, v9296; CHECK-NEXT: vmv.x.s t6, v8297; CHECK-NEXT: add t0, t0, t1298; CHECK-NEXT: add t2, t2, t3299; CHECK-NEXT: add a0, t5, a0300; CHECK-NEXT: add a3, a3, a4301; CHECK-NEXT: add t0, t6, t0302; CHECK-NEXT: add t2, t2, t4303; CHECK-NEXT: add a0, a0, a1304; CHECK-NEXT: add a3, a3, a5305; CHECK-NEXT: add t0, t0, t2306; CHECK-NEXT: add a0, a0, a2307; CHECK-NEXT: add a3, a3, a6308; CHECK-NEXT: add a0, t0, a0309; CHECK-NEXT: add a3, a3, a7310; CHECK-NEXT: add a0, a0, a3311; CHECK-NEXT: ret312 %e0 = extractelement <16 x i16> %v, i32 0313 %e1 = extractelement <16 x i16> %v, i32 1314 %e2 = extractelement <16 x i16> %v, i32 2315 %e3 = extractelement <16 x i16> %v, i32 3316 %e4 = extractelement <16 x i16> %v, i32 4317 %e5 = extractelement <16 x i16> %v, i32 5318 %e6 = extractelement <16 x i16> %v, i32 6319 %e7 = extractelement <16 x i16> %v, i32 7320 %e8 = extractelement <16 x i16> %v, i32 8321 %e9 = extractelement <16 x i16> %v, i32 9322 %e10 = extractelement <16 x i16> %v, i32 10323 %e11 = extractelement <16 x i16> %v, i32 11324 %e12 = extractelement <16 x i16> %v, i32 12325 %e13 = extractelement <16 x i16> %v, i32 13326 %e14 = extractelement <16 x i16> %v, i32 14327 %e15 = extractelement <16 x i16> %v, i32 15328 %add0 = xor i16 %e0, %e1329 %add1 = add i16 %add0, %e2330 %add2 = add i16 %add1, %e3331 %add3 = add i16 %add2, %e4332 %add4 = add i16 %add3, %e5333 %add5 = add i16 %add4, %e6334 %add6 = add i16 %add5, %e7335 %add7 = add i16 %add6, %e8336 %add8 = add i16 %add7, %e9337 %add9 = add i16 %add8, %e10338 %add10 = add i16 %add9, %e11339 %add11 = add i16 %add10, %e12340 %add12 = add i16 %add11, %e13341 %add13 = add i16 %add12, %e14342 %add14 = add i16 %add13, %e15343 ret i16 %add14344}345 346define i32 @explode_2xi32(<2 x i32> %v) {347; CHECK-LABEL: explode_2xi32:348; CHECK: # %bb.0:349; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma350; CHECK-NEXT: vmv.s.x v9, zero351; CHECK-NEXT: vredxor.vs v8, v8, v9352; CHECK-NEXT: vmv.x.s a0, v8353; CHECK-NEXT: ret354 %e0 = extractelement <2 x i32> %v, i32 0355 %e1 = extractelement <2 x i32> %v, i32 1356 %add0 = xor i32 %e0, %e1357 ret i32 %add0358}359 360define i32 @explode_4xi32(<4 x i32> %v) {361; RV32-LABEL: explode_4xi32:362; RV32: # %bb.0:363; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma364; RV32-NEXT: vslidedown.vi v9, v8, 2365; RV32-NEXT: vmv.x.s a0, v9366; RV32-NEXT: vslidedown.vi v9, v8, 3367; RV32-NEXT: vmv.x.s a1, v9368; RV32-NEXT: vmv.s.x v9, zero369; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma370; RV32-NEXT: vredxor.vs v8, v8, v9371; RV32-NEXT: vmv.x.s a2, v8372; RV32-NEXT: add a0, a0, a1373; RV32-NEXT: add a0, a2, a0374; RV32-NEXT: ret375;376; RV64-LABEL: explode_4xi32:377; RV64: # %bb.0:378; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma379; RV64-NEXT: vslidedown.vi v9, v8, 2380; RV64-NEXT: vmv.x.s a0, v9381; RV64-NEXT: vslidedown.vi v9, v8, 3382; RV64-NEXT: vmv.x.s a1, v9383; RV64-NEXT: vmv.s.x v9, zero384; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma385; RV64-NEXT: vredxor.vs v8, v8, v9386; RV64-NEXT: vmv.x.s a2, v8387; RV64-NEXT: add a0, a0, a1388; RV64-NEXT: addw a0, a2, a0389; RV64-NEXT: ret390 %e0 = extractelement <4 x i32> %v, i32 0391 %e1 = extractelement <4 x i32> %v, i32 1392 %e2 = extractelement <4 x i32> %v, i32 2393 %e3 = extractelement <4 x i32> %v, i32 3394 %add0 = xor i32 %e0, %e1395 %add1 = add i32 %add0, %e2396 %add2 = add i32 %add1, %e3397 ret i32 %add2398}399 400 401define i32 @explode_8xi32(<8 x i32> %v) {402; RV32-LABEL: explode_8xi32:403; RV32: # %bb.0:404; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma405; RV32-NEXT: vslidedown.vi v10, v8, 4406; RV32-NEXT: vmv.x.s a0, v10407; RV32-NEXT: vslidedown.vi v10, v8, 5408; RV32-NEXT: vmv.x.s a1, v10409; RV32-NEXT: vslidedown.vi v10, v8, 6410; RV32-NEXT: vmv.x.s a2, v10411; RV32-NEXT: vslidedown.vi v10, v8, 7412; RV32-NEXT: vmv.x.s a3, v10413; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma414; RV32-NEXT: vslidedown.vi v9, v8, 2415; RV32-NEXT: vslidedown.vi v10, v8, 3416; RV32-NEXT: vmv.x.s a4, v9417; RV32-NEXT: vmv.s.x v9, zero418; RV32-NEXT: vmv.x.s a5, v10419; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma420; RV32-NEXT: vredxor.vs v8, v8, v9421; RV32-NEXT: vmv.x.s a6, v8422; RV32-NEXT: add a4, a4, a5423; RV32-NEXT: add a0, a0, a1424; RV32-NEXT: add a4, a6, a4425; RV32-NEXT: add a0, a0, a2426; RV32-NEXT: add a0, a4, a0427; RV32-NEXT: add a0, a0, a3428; RV32-NEXT: ret429;430; RV64-LABEL: explode_8xi32:431; RV64: # %bb.0:432; RV64-NEXT: vsetivli zero, 1, e32, m2, ta, ma433; RV64-NEXT: vslidedown.vi v10, v8, 4434; RV64-NEXT: vmv.x.s a0, v10435; RV64-NEXT: vslidedown.vi v10, v8, 5436; RV64-NEXT: vmv.x.s a1, v10437; RV64-NEXT: vslidedown.vi v10, v8, 6438; RV64-NEXT: vmv.x.s a2, v10439; RV64-NEXT: vslidedown.vi v10, v8, 7440; RV64-NEXT: vmv.x.s a3, v10441; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma442; RV64-NEXT: vslidedown.vi v9, v8, 2443; RV64-NEXT: vslidedown.vi v10, v8, 3444; RV64-NEXT: vmv.x.s a4, v9445; RV64-NEXT: vmv.s.x v9, zero446; RV64-NEXT: vmv.x.s a5, v10447; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma448; RV64-NEXT: vredxor.vs v8, v8, v9449; RV64-NEXT: vmv.x.s a6, v8450; RV64-NEXT: add a4, a4, a5451; RV64-NEXT: add a0, a0, a1452; RV64-NEXT: add a4, a6, a4453; RV64-NEXT: add a0, a0, a2454; RV64-NEXT: add a0, a4, a0455; RV64-NEXT: addw a0, a0, a3456; RV64-NEXT: ret457 %e0 = extractelement <8 x i32> %v, i32 0458 %e1 = extractelement <8 x i32> %v, i32 1459 %e2 = extractelement <8 x i32> %v, i32 2460 %e3 = extractelement <8 x i32> %v, i32 3461 %e4 = extractelement <8 x i32> %v, i32 4462 %e5 = extractelement <8 x i32> %v, i32 5463 %e6 = extractelement <8 x i32> %v, i32 6464 %e7 = extractelement <8 x i32> %v, i32 7465 %add0 = xor i32 %e0, %e1466 %add1 = add i32 %add0, %e2467 %add2 = add i32 %add1, %e3468 %add3 = add i32 %add2, %e4469 %add4 = add i32 %add3, %e5470 %add5 = add i32 %add4, %e6471 %add6 = add i32 %add5, %e7472 ret i32 %add6473}474 475define i32 @explode_16xi32(<16 x i32> %v) {476; RV32-LABEL: explode_16xi32:477; RV32: # %bb.0:478; RV32-NEXT: addi sp, sp, -128479; RV32-NEXT: .cfi_def_cfa_offset 128480; RV32-NEXT: sw ra, 124(sp) # 4-byte Folded Spill481; RV32-NEXT: sw s0, 120(sp) # 4-byte Folded Spill482; RV32-NEXT: .cfi_offset ra, -4483; RV32-NEXT: .cfi_offset s0, -8484; RV32-NEXT: addi s0, sp, 128485; RV32-NEXT: .cfi_def_cfa s0, 0486; RV32-NEXT: andi sp, sp, -64487; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma488; RV32-NEXT: vslidedown.vi v12, v8, 4489; RV32-NEXT: vmv.x.s a0, v12490; RV32-NEXT: vslidedown.vi v12, v8, 5491; RV32-NEXT: vmv.x.s a1, v12492; RV32-NEXT: vslidedown.vi v12, v8, 6493; RV32-NEXT: vmv.x.s a2, v12494; RV32-NEXT: vslidedown.vi v12, v8, 7495; RV32-NEXT: vmv.x.s a3, v12496; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma497; RV32-NEXT: vslidedown.vi v12, v8, 2498; RV32-NEXT: vslidedown.vi v13, v8, 3499; RV32-NEXT: mv a4, sp500; RV32-NEXT: vmv.x.s a5, v12501; RV32-NEXT: vmv.s.x v12, zero502; RV32-NEXT: vmv.x.s a6, v13503; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma504; RV32-NEXT: vse32.v v8, (a4)505; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma506; RV32-NEXT: vredxor.vs v8, v8, v12507; RV32-NEXT: lw a4, 32(sp)508; RV32-NEXT: lw a7, 36(sp)509; RV32-NEXT: lw t0, 40(sp)510; RV32-NEXT: lw t1, 44(sp)511; RV32-NEXT: lw t2, 48(sp)512; RV32-NEXT: lw t3, 52(sp)513; RV32-NEXT: lw t4, 56(sp)514; RV32-NEXT: lw t5, 60(sp)515; RV32-NEXT: vmv.x.s t6, v8516; RV32-NEXT: add a5, a5, a6517; RV32-NEXT: add a0, a0, a1518; RV32-NEXT: add a5, t6, a5519; RV32-NEXT: add a0, a0, a2520; RV32-NEXT: add a0, a5, a0521; RV32-NEXT: add a3, a3, a4522; RV32-NEXT: add a7, a7, t0523; RV32-NEXT: add t2, t2, t3524; RV32-NEXT: add a0, a0, a3525; RV32-NEXT: add a7, a7, t1526; RV32-NEXT: add t2, t2, t4527; RV32-NEXT: add a0, a0, a7528; RV32-NEXT: add t2, t2, t5529; RV32-NEXT: add a0, a0, t2530; RV32-NEXT: addi sp, s0, -128531; RV32-NEXT: .cfi_def_cfa sp, 128532; RV32-NEXT: lw ra, 124(sp) # 4-byte Folded Reload533; RV32-NEXT: lw s0, 120(sp) # 4-byte Folded Reload534; RV32-NEXT: .cfi_restore ra535; RV32-NEXT: .cfi_restore s0536; RV32-NEXT: addi sp, sp, 128537; RV32-NEXT: .cfi_def_cfa_offset 0538; RV32-NEXT: ret539;540; RV64-LABEL: explode_16xi32:541; RV64: # %bb.0:542; RV64-NEXT: addi sp, sp, -128543; RV64-NEXT: .cfi_def_cfa_offset 128544; RV64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill545; RV64-NEXT: sd s0, 112(sp) # 8-byte Folded Spill546; RV64-NEXT: .cfi_offset ra, -8547; RV64-NEXT: .cfi_offset s0, -16548; RV64-NEXT: addi s0, sp, 128549; RV64-NEXT: .cfi_def_cfa s0, 0550; RV64-NEXT: andi sp, sp, -64551; RV64-NEXT: vsetivli zero, 1, e32, m2, ta, ma552; RV64-NEXT: vslidedown.vi v12, v8, 4553; RV64-NEXT: vmv.x.s a0, v12554; RV64-NEXT: vslidedown.vi v12, v8, 5555; RV64-NEXT: vmv.x.s a1, v12556; RV64-NEXT: vslidedown.vi v12, v8, 6557; RV64-NEXT: vmv.x.s a2, v12558; RV64-NEXT: vslidedown.vi v12, v8, 7559; RV64-NEXT: vmv.x.s a3, v12560; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma561; RV64-NEXT: vslidedown.vi v12, v8, 2562; RV64-NEXT: vslidedown.vi v13, v8, 3563; RV64-NEXT: mv a4, sp564; RV64-NEXT: vmv.x.s a5, v12565; RV64-NEXT: vmv.s.x v12, zero566; RV64-NEXT: vmv.x.s a6, v13567; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma568; RV64-NEXT: vse32.v v8, (a4)569; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma570; RV64-NEXT: vredxor.vs v8, v8, v12571; RV64-NEXT: lw a4, 32(sp)572; RV64-NEXT: lw a7, 36(sp)573; RV64-NEXT: lw t0, 40(sp)574; RV64-NEXT: lw t1, 44(sp)575; RV64-NEXT: lw t2, 48(sp)576; RV64-NEXT: lw t3, 52(sp)577; RV64-NEXT: lw t4, 56(sp)578; RV64-NEXT: lw t5, 60(sp)579; RV64-NEXT: vmv.x.s t6, v8580; RV64-NEXT: add a5, a5, a6581; RV64-NEXT: add a0, a0, a1582; RV64-NEXT: add a5, t6, a5583; RV64-NEXT: add a0, a0, a2584; RV64-NEXT: add a0, a5, a0585; RV64-NEXT: add a3, a3, a4586; RV64-NEXT: add a7, a7, t0587; RV64-NEXT: add t2, t2, t3588; RV64-NEXT: add a0, a0, a3589; RV64-NEXT: add a7, a7, t1590; RV64-NEXT: add t2, t2, t4591; RV64-NEXT: add a0, a0, a7592; RV64-NEXT: add t2, t2, t5593; RV64-NEXT: addw a0, a0, t2594; RV64-NEXT: addi sp, s0, -128595; RV64-NEXT: .cfi_def_cfa sp, 128596; RV64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload597; RV64-NEXT: ld s0, 112(sp) # 8-byte Folded Reload598; RV64-NEXT: .cfi_restore ra599; RV64-NEXT: .cfi_restore s0600; RV64-NEXT: addi sp, sp, 128601; RV64-NEXT: .cfi_def_cfa_offset 0602; RV64-NEXT: ret603 %e0 = extractelement <16 x i32> %v, i32 0604 %e1 = extractelement <16 x i32> %v, i32 1605 %e2 = extractelement <16 x i32> %v, i32 2606 %e3 = extractelement <16 x i32> %v, i32 3607 %e4 = extractelement <16 x i32> %v, i32 4608 %e5 = extractelement <16 x i32> %v, i32 5609 %e6 = extractelement <16 x i32> %v, i32 6610 %e7 = extractelement <16 x i32> %v, i32 7611 %e8 = extractelement <16 x i32> %v, i32 8612 %e9 = extractelement <16 x i32> %v, i32 9613 %e10 = extractelement <16 x i32> %v, i32 10614 %e11 = extractelement <16 x i32> %v, i32 11615 %e12 = extractelement <16 x i32> %v, i32 12616 %e13 = extractelement <16 x i32> %v, i32 13617 %e14 = extractelement <16 x i32> %v, i32 14618 %e15 = extractelement <16 x i32> %v, i32 15619 %add0 = xor i32 %e0, %e1620 %add1 = add i32 %add0, %e2621 %add2 = add i32 %add1, %e3622 %add3 = add i32 %add2, %e4623 %add4 = add i32 %add3, %e5624 %add5 = add i32 %add4, %e6625 %add6 = add i32 %add5, %e7626 %add7 = add i32 %add6, %e8627 %add8 = add i32 %add7, %e9628 %add9 = add i32 %add8, %e10629 %add10 = add i32 %add9, %e11630 %add11 = add i32 %add10, %e12631 %add12 = add i32 %add11, %e13632 %add13 = add i32 %add12, %e14633 %add14 = add i32 %add13, %e15634 ret i32 %add14635}636 637define i64 @explode_2xi64(<2 x i64> %v) {638; RV32-LABEL: explode_2xi64:639; RV32: # %bb.0:640; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma641; RV32-NEXT: vmv.s.x v9, zero642; RV32-NEXT: li a1, 32643; RV32-NEXT: vredxor.vs v8, v8, v9644; RV32-NEXT: vmv.x.s a0, v8645; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma646; RV32-NEXT: vsrl.vx v8, v8, a1647; RV32-NEXT: vmv.x.s a1, v8648; RV32-NEXT: ret649;650; RV64-LABEL: explode_2xi64:651; RV64: # %bb.0:652; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma653; RV64-NEXT: vmv.s.x v9, zero654; RV64-NEXT: vredxor.vs v8, v8, v9655; RV64-NEXT: vmv.x.s a0, v8656; RV64-NEXT: ret657 %e0 = extractelement <2 x i64> %v, i32 0658 %e1 = extractelement <2 x i64> %v, i32 1659 %add0 = xor i64 %e0, %e1660 ret i64 %add0661}662 663define i64 @explode_4xi64(<4 x i64> %v) {664; RV32-LABEL: explode_4xi64:665; RV32: # %bb.0:666; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, ma667; RV32-NEXT: vslidedown.vi v10, v8, 2668; RV32-NEXT: li a0, 32669; RV32-NEXT: vmv.s.x v12, zero670; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma671; RV32-NEXT: vredxor.vs v12, v8, v12672; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, ma673; RV32-NEXT: vslidedown.vi v8, v8, 3674; RV32-NEXT: vmv.x.s a1, v10675; RV32-NEXT: vsrl.vx v10, v10, a0676; RV32-NEXT: vmv.x.s a2, v8677; RV32-NEXT: vsrl.vx v8, v8, a0678; RV32-NEXT: vmv.x.s a3, v10679; RV32-NEXT: vmv.x.s a4, v8680; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma681; RV32-NEXT: vsrl.vx v8, v12, a0682; RV32-NEXT: vmv.x.s a0, v12683; RV32-NEXT: vmv.x.s a5, v8684; RV32-NEXT: add a1, a0, a1685; RV32-NEXT: sltu a6, a1, a0686; RV32-NEXT: add a3, a5, a3687; RV32-NEXT: add a0, a1, a2688; RV32-NEXT: add a3, a3, a6689; RV32-NEXT: add a3, a3, a4690; RV32-NEXT: sltu a1, a0, a1691; RV32-NEXT: add a1, a3, a1692; RV32-NEXT: ret693;694; RV64-LABEL: explode_4xi64:695; RV64: # %bb.0:696; RV64-NEXT: vsetivli zero, 1, e64, m2, ta, ma697; RV64-NEXT: vslidedown.vi v10, v8, 2698; RV64-NEXT: vmv.x.s a0, v10699; RV64-NEXT: vslidedown.vi v10, v8, 3700; RV64-NEXT: vmv.x.s a1, v10701; RV64-NEXT: vmv.s.x v9, zero702; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma703; RV64-NEXT: vredxor.vs v8, v8, v9704; RV64-NEXT: vmv.x.s a2, v8705; RV64-NEXT: add a0, a0, a1706; RV64-NEXT: add a0, a2, a0707; RV64-NEXT: ret708 %e0 = extractelement <4 x i64> %v, i32 0709 %e1 = extractelement <4 x i64> %v, i32 1710 %e2 = extractelement <4 x i64> %v, i32 2711 %e3 = extractelement <4 x i64> %v, i32 3712 %add0 = xor i64 %e0, %e1713 %add1 = add i64 %add0, %e2714 %add2 = add i64 %add1, %e3715 ret i64 %add2716}717 718 719define i64 @explode_8xi64(<8 x i64> %v) {720; RV32-LABEL: explode_8xi64:721; RV32: # %bb.0:722; RV32-NEXT: vsetivli zero, 1, e64, m4, ta, ma723; RV32-NEXT: vslidedown.vi v12, v8, 2724; RV32-NEXT: li a0, 32725; RV32-NEXT: vslidedown.vi v16, v8, 3726; RV32-NEXT: vmv.x.s a2, v12727; RV32-NEXT: vsrl.vx v12, v12, a0728; RV32-NEXT: vmv.x.s a1, v12729; RV32-NEXT: vslidedown.vi v12, v8, 4730; RV32-NEXT: vmv.x.s a4, v16731; RV32-NEXT: vsrl.vx v16, v16, a0732; RV32-NEXT: vmv.x.s a3, v16733; RV32-NEXT: vslidedown.vi v16, v8, 5734; RV32-NEXT: vmv.x.s a5, v12735; RV32-NEXT: vsrl.vx v12, v12, a0736; RV32-NEXT: vmv.x.s a6, v12737; RV32-NEXT: vslidedown.vi v12, v8, 6738; RV32-NEXT: vmv.x.s a7, v16739; RV32-NEXT: vsrl.vx v16, v16, a0740; RV32-NEXT: vmv.x.s t0, v16741; RV32-NEXT: vmv.s.x v16, zero742; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma743; RV32-NEXT: vredxor.vs v16, v8, v16744; RV32-NEXT: vsetivli zero, 1, e64, m4, ta, ma745; RV32-NEXT: vslidedown.vi v8, v8, 7746; RV32-NEXT: vmv.x.s t1, v12747; RV32-NEXT: vsrl.vx v12, v12, a0748; RV32-NEXT: vmv.x.s t2, v8749; RV32-NEXT: vsrl.vx v8, v8, a0750; RV32-NEXT: vmv.x.s t3, v12751; RV32-NEXT: vmv.x.s t4, v8752; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma753; RV32-NEXT: vsrl.vx v8, v16, a0754; RV32-NEXT: vmv.x.s a0, v16755; RV32-NEXT: vmv.x.s t5, v8756; RV32-NEXT: add a2, a0, a2757; RV32-NEXT: sltu a0, a2, a0758; RV32-NEXT: add a1, t5, a1759; RV32-NEXT: add a4, a2, a4760; RV32-NEXT: add a0, a1, a0761; RV32-NEXT: sltu a1, a4, a2762; RV32-NEXT: add a5, a4, a5763; RV32-NEXT: add a0, a0, a3764; RV32-NEXT: add a1, a1, a6765; RV32-NEXT: sltu a2, a5, a4766; RV32-NEXT: add a7, a5, a7767; RV32-NEXT: add a0, a0, a1768; RV32-NEXT: add a2, a2, t0769; RV32-NEXT: sltu a1, a7, a5770; RV32-NEXT: add t1, a7, t1771; RV32-NEXT: add a2, a0, a2772; RV32-NEXT: add a1, a1, t3773; RV32-NEXT: sltu a3, t1, a7774; RV32-NEXT: add a0, t1, t2775; RV32-NEXT: add a1, a2, a1776; RV32-NEXT: add a3, a3, t4777; RV32-NEXT: add a1, a1, a3778; RV32-NEXT: sltu a2, a0, t1779; RV32-NEXT: add a1, a1, a2780; RV32-NEXT: ret781;782; RV64-LABEL: explode_8xi64:783; RV64: # %bb.0:784; RV64-NEXT: addi sp, sp, -128785; RV64-NEXT: .cfi_def_cfa_offset 128786; RV64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill787; RV64-NEXT: sd s0, 112(sp) # 8-byte Folded Spill788; RV64-NEXT: .cfi_offset ra, -8789; RV64-NEXT: .cfi_offset s0, -16790; RV64-NEXT: addi s0, sp, 128791; RV64-NEXT: .cfi_def_cfa s0, 0792; RV64-NEXT: andi sp, sp, -64793; RV64-NEXT: vsetivli zero, 1, e64, m2, ta, ma794; RV64-NEXT: vslidedown.vi v12, v8, 2795; RV64-NEXT: vmv.x.s a0, v12796; RV64-NEXT: vslidedown.vi v12, v8, 3797; RV64-NEXT: mv a1, sp798; RV64-NEXT: vmv.x.s a2, v12799; RV64-NEXT: vmv.s.x v12, zero800; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma801; RV64-NEXT: vse64.v v8, (a1)802; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma803; RV64-NEXT: vredxor.vs v8, v8, v12804; RV64-NEXT: ld a1, 32(sp)805; RV64-NEXT: ld a3, 40(sp)806; RV64-NEXT: ld a4, 48(sp)807; RV64-NEXT: ld a5, 56(sp)808; RV64-NEXT: vmv.x.s a6, v8809; RV64-NEXT: add a0, a0, a2810; RV64-NEXT: add a0, a6, a0811; RV64-NEXT: add a0, a0, a1812; RV64-NEXT: add a3, a3, a4813; RV64-NEXT: add a0, a0, a3814; RV64-NEXT: add a0, a0, a5815; RV64-NEXT: addi sp, s0, -128816; RV64-NEXT: .cfi_def_cfa sp, 128817; RV64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload818; RV64-NEXT: ld s0, 112(sp) # 8-byte Folded Reload819; RV64-NEXT: .cfi_restore ra820; RV64-NEXT: .cfi_restore s0821; RV64-NEXT: addi sp, sp, 128822; RV64-NEXT: .cfi_def_cfa_offset 0823; RV64-NEXT: ret824 %e0 = extractelement <8 x i64> %v, i32 0825 %e1 = extractelement <8 x i64> %v, i32 1826 %e2 = extractelement <8 x i64> %v, i32 2827 %e3 = extractelement <8 x i64> %v, i32 3828 %e4 = extractelement <8 x i64> %v, i32 4829 %e5 = extractelement <8 x i64> %v, i32 5830 %e6 = extractelement <8 x i64> %v, i32 6831 %e7 = extractelement <8 x i64> %v, i32 7832 %add0 = xor i64 %e0, %e1833 %add1 = add i64 %add0, %e2834 %add2 = add i64 %add1, %e3835 %add3 = add i64 %add2, %e4836 %add4 = add i64 %add3, %e5837 %add5 = add i64 %add4, %e6838 %add6 = add i64 %add5, %e7839 ret i64 %add6840}841 842define i64 @explode_16xi64(<16 x i64> %v) {843; RV32-LABEL: explode_16xi64:844; RV32: # %bb.0:845; RV32-NEXT: addi sp, sp, -64846; RV32-NEXT: .cfi_def_cfa_offset 64847; RV32-NEXT: sw s0, 60(sp) # 4-byte Folded Spill848; RV32-NEXT: sw s1, 56(sp) # 4-byte Folded Spill849; RV32-NEXT: sw s2, 52(sp) # 4-byte Folded Spill850; RV32-NEXT: sw s3, 48(sp) # 4-byte Folded Spill851; RV32-NEXT: sw s4, 44(sp) # 4-byte Folded Spill852; RV32-NEXT: sw s5, 40(sp) # 4-byte Folded Spill853; RV32-NEXT: sw s6, 36(sp) # 4-byte Folded Spill854; RV32-NEXT: sw s7, 32(sp) # 4-byte Folded Spill855; RV32-NEXT: sw s8, 28(sp) # 4-byte Folded Spill856; RV32-NEXT: sw s9, 24(sp) # 4-byte Folded Spill857; RV32-NEXT: sw s10, 20(sp) # 4-byte Folded Spill858; RV32-NEXT: sw s11, 16(sp) # 4-byte Folded Spill859; RV32-NEXT: .cfi_offset s0, -4860; RV32-NEXT: .cfi_offset s1, -8861; RV32-NEXT: .cfi_offset s2, -12862; RV32-NEXT: .cfi_offset s3, -16863; RV32-NEXT: .cfi_offset s4, -20864; RV32-NEXT: .cfi_offset s5, -24865; RV32-NEXT: .cfi_offset s6, -28866; RV32-NEXT: .cfi_offset s7, -32867; RV32-NEXT: .cfi_offset s8, -36868; RV32-NEXT: .cfi_offset s9, -40869; RV32-NEXT: .cfi_offset s10, -44870; RV32-NEXT: .cfi_offset s11, -48871; RV32-NEXT: csrr a0, vlenb872; RV32-NEXT: sub sp, sp, a0873; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 1 * vlenb874; RV32-NEXT: vsetivli zero, 1, e64, m8, ta, ma875; RV32-NEXT: vslidedown.vi v24, v8, 2876; RV32-NEXT: li a0, 32877; RV32-NEXT: vslidedown.vi v0, v8, 3878; RV32-NEXT: vslidedown.vi v16, v8, 4879; RV32-NEXT: vmv.x.s a1, v24880; RV32-NEXT: vsrl.vx v24, v24, a0881; RV32-NEXT: vmv.x.s a2, v24882; RV32-NEXT: vslidedown.vi v24, v8, 5883; RV32-NEXT: vmv.x.s a3, v0884; RV32-NEXT: vsrl.vx v0, v0, a0885; RV32-NEXT: vmv.x.s a4, v0886; RV32-NEXT: vslidedown.vi v0, v8, 6887; RV32-NEXT: vmv.x.s a5, v16888; RV32-NEXT: vsrl.vx v16, v16, a0889; RV32-NEXT: vmv.x.s a6, v16890; RV32-NEXT: vslidedown.vi v16, v8, 7891; RV32-NEXT: vmv.x.s a7, v24892; RV32-NEXT: vsrl.vx v24, v24, a0893; RV32-NEXT: vmv.x.s t0, v24894; RV32-NEXT: vslidedown.vi v24, v8, 8895; RV32-NEXT: vmv.x.s t1, v0896; RV32-NEXT: vsrl.vx v0, v0, a0897; RV32-NEXT: vmv.x.s t2, v0898; RV32-NEXT: vslidedown.vi v0, v8, 9899; RV32-NEXT: vmv.x.s t3, v16900; RV32-NEXT: vsrl.vx v16, v16, a0901; RV32-NEXT: vmv.x.s t4, v16902; RV32-NEXT: vslidedown.vi v16, v8, 10903; RV32-NEXT: vmv.x.s t5, v24904; RV32-NEXT: vsrl.vx v24, v24, a0905; RV32-NEXT: vmv.x.s t6, v24906; RV32-NEXT: vslidedown.vi v24, v8, 11907; RV32-NEXT: vmv.x.s s0, v0908; RV32-NEXT: vsrl.vx v0, v0, a0909; RV32-NEXT: vmv.x.s s1, v0910; RV32-NEXT: vslidedown.vi v0, v8, 12911; RV32-NEXT: vmv.x.s s2, v16912; RV32-NEXT: vsrl.vx v16, v16, a0913; RV32-NEXT: vmv.x.s s3, v16914; RV32-NEXT: vslidedown.vi v16, v8, 13915; RV32-NEXT: vmv.x.s s4, v24916; RV32-NEXT: vsrl.vx v24, v24, a0917; RV32-NEXT: vmv.x.s s5, v24918; RV32-NEXT: vslidedown.vi v24, v8, 14919; RV32-NEXT: vmv.x.s s6, v0920; RV32-NEXT: vsrl.vx v0, v0, a0921; RV32-NEXT: vmv.x.s s7, v0922; RV32-NEXT: vmv.s.x v7, zero923; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma924; RV32-NEXT: vredxor.vs v7, v8, v7925; RV32-NEXT: addi s8, sp, 16926; RV32-NEXT: vs1r.v v7, (s8) # vscale x 8-byte Folded Spill927; RV32-NEXT: vsetivli zero, 1, e64, m8, ta, ma928; RV32-NEXT: vslidedown.vi v8, v8, 15929; RV32-NEXT: vmv.x.s s8, v16930; RV32-NEXT: vsrl.vx v16, v16, a0931; RV32-NEXT: vmv.x.s s9, v16932; RV32-NEXT: vsrl.vx v0, v24, a0933; RV32-NEXT: addi s10, sp, 16934; RV32-NEXT: vl1r.v v17, (s10) # vscale x 8-byte Folded Reload935; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma936; RV32-NEXT: vsrl.vx v16, v17, a0937; RV32-NEXT: vmv.x.s s10, v17938; RV32-NEXT: vmv.x.s s11, v16939; RV32-NEXT: vsetivli zero, 1, e64, m8, ta, ma940; RV32-NEXT: vsrl.vx v16, v8, a0941; RV32-NEXT: add a2, s11, a2942; RV32-NEXT: add a1, s10, a1943; RV32-NEXT: sltu a0, a1, s10944; RV32-NEXT: add a0, a2, a0945; RV32-NEXT: add a0, a0, a4946; RV32-NEXT: add a3, a1, a3947; RV32-NEXT: sltu a1, a3, a1948; RV32-NEXT: add a1, a1, a6949; RV32-NEXT: add a0, a0, a1950; RV32-NEXT: add a5, a3, a5951; RV32-NEXT: sltu a1, a5, a3952; RV32-NEXT: add a1, a1, t0953; RV32-NEXT: add a0, a0, a1954; RV32-NEXT: add a7, a5, a7955; RV32-NEXT: sltu a1, a7, a5956; RV32-NEXT: add a1, a1, t2957; RV32-NEXT: add a0, a0, a1958; RV32-NEXT: add t1, a7, t1959; RV32-NEXT: sltu a1, t1, a7960; RV32-NEXT: add a1, a1, t4961; RV32-NEXT: add a0, a0, a1962; RV32-NEXT: add t3, t1, t3963; RV32-NEXT: sltu a1, t3, t1964; RV32-NEXT: add a1, a1, t6965; RV32-NEXT: add a0, a0, a1966; RV32-NEXT: add t5, t3, t5967; RV32-NEXT: sltu a1, t5, t3968; RV32-NEXT: add a1, a1, s1969; RV32-NEXT: add a0, a0, a1970; RV32-NEXT: add s0, t5, s0971; RV32-NEXT: sltu a1, s0, t5972; RV32-NEXT: add a1, a1, s3973; RV32-NEXT: add a0, a0, a1974; RV32-NEXT: add s2, s0, s2975; RV32-NEXT: sltu a1, s2, s0976; RV32-NEXT: add a1, a1, s5977; RV32-NEXT: add a0, a0, a1978; RV32-NEXT: add s4, s2, s4979; RV32-NEXT: sltu a1, s4, s2980; RV32-NEXT: add a1, a1, s7981; RV32-NEXT: add a0, a0, a1982; RV32-NEXT: add s6, s4, s6983; RV32-NEXT: sltu a1, s6, s4984; RV32-NEXT: add a1, a1, s9985; RV32-NEXT: add a0, a0, a1986; RV32-NEXT: vmv.x.s a1, v0987; RV32-NEXT: add s8, s6, s8988; RV32-NEXT: sltu a2, s8, s6989; RV32-NEXT: add a1, a2, a1990; RV32-NEXT: vmv.x.s a2, v24991; RV32-NEXT: add a0, a0, a1992; RV32-NEXT: vmv.x.s a1, v16993; RV32-NEXT: add a2, s8, a2994; RV32-NEXT: sltu a3, a2, s8995; RV32-NEXT: add a1, a3, a1996; RV32-NEXT: add a1, a0, a1997; RV32-NEXT: vmv.x.s a0, v8998; RV32-NEXT: add a0, a2, a0999; RV32-NEXT: sltu a2, a0, a21000; RV32-NEXT: add a1, a1, a21001; RV32-NEXT: csrr a2, vlenb1002; RV32-NEXT: add sp, sp, a21003; RV32-NEXT: .cfi_def_cfa sp, 641004; RV32-NEXT: lw s0, 60(sp) # 4-byte Folded Reload1005; RV32-NEXT: lw s1, 56(sp) # 4-byte Folded Reload1006; RV32-NEXT: lw s2, 52(sp) # 4-byte Folded Reload1007; RV32-NEXT: lw s3, 48(sp) # 4-byte Folded Reload1008; RV32-NEXT: lw s4, 44(sp) # 4-byte Folded Reload1009; RV32-NEXT: lw s5, 40(sp) # 4-byte Folded Reload1010; RV32-NEXT: lw s6, 36(sp) # 4-byte Folded Reload1011; RV32-NEXT: lw s7, 32(sp) # 4-byte Folded Reload1012; RV32-NEXT: lw s8, 28(sp) # 4-byte Folded Reload1013; RV32-NEXT: lw s9, 24(sp) # 4-byte Folded Reload1014; RV32-NEXT: lw s10, 20(sp) # 4-byte Folded Reload1015; RV32-NEXT: lw s11, 16(sp) # 4-byte Folded Reload1016; RV32-NEXT: .cfi_restore s01017; RV32-NEXT: .cfi_restore s11018; RV32-NEXT: .cfi_restore s21019; RV32-NEXT: .cfi_restore s31020; RV32-NEXT: .cfi_restore s41021; RV32-NEXT: .cfi_restore s51022; RV32-NEXT: .cfi_restore s61023; RV32-NEXT: .cfi_restore s71024; RV32-NEXT: .cfi_restore s81025; RV32-NEXT: .cfi_restore s91026; RV32-NEXT: .cfi_restore s101027; RV32-NEXT: .cfi_restore s111028; RV32-NEXT: addi sp, sp, 641029; RV32-NEXT: .cfi_def_cfa_offset 01030; RV32-NEXT: ret1031;1032; RV64-LABEL: explode_16xi64:1033; RV64: # %bb.0:1034; RV64-NEXT: addi sp, sp, -2561035; RV64-NEXT: .cfi_def_cfa_offset 2561036; RV64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill1037; RV64-NEXT: sd s0, 240(sp) # 8-byte Folded Spill1038; RV64-NEXT: .cfi_offset ra, -81039; RV64-NEXT: .cfi_offset s0, -161040; RV64-NEXT: addi s0, sp, 2561041; RV64-NEXT: .cfi_def_cfa s0, 01042; RV64-NEXT: andi sp, sp, -1281043; RV64-NEXT: vsetivli zero, 1, e64, m2, ta, ma1044; RV64-NEXT: vslidedown.vi v16, v8, 21045; RV64-NEXT: vmv.x.s a0, v161046; RV64-NEXT: vslidedown.vi v16, v8, 31047; RV64-NEXT: mv a1, sp1048; RV64-NEXT: vmv.x.s a2, v161049; RV64-NEXT: vmv.s.x v16, zero1050; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma1051; RV64-NEXT: vse64.v v8, (a1)1052; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma1053; RV64-NEXT: vredxor.vs v8, v8, v161054; RV64-NEXT: ld a1, 32(sp)1055; RV64-NEXT: ld a3, 40(sp)1056; RV64-NEXT: ld a4, 48(sp)1057; RV64-NEXT: ld a5, 56(sp)1058; RV64-NEXT: ld a6, 64(sp)1059; RV64-NEXT: ld a7, 72(sp)1060; RV64-NEXT: ld t0, 80(sp)1061; RV64-NEXT: ld t1, 88(sp)1062; RV64-NEXT: ld t2, 96(sp)1063; RV64-NEXT: ld t3, 104(sp)1064; RV64-NEXT: ld t4, 112(sp)1065; RV64-NEXT: ld t5, 120(sp)1066; RV64-NEXT: vmv.x.s t6, v81067; RV64-NEXT: add a0, a0, a21068; RV64-NEXT: add a0, t6, a01069; RV64-NEXT: add a0, a0, a11070; RV64-NEXT: add a3, a3, a41071; RV64-NEXT: add a5, a5, a61072; RV64-NEXT: add t0, t0, t11073; RV64-NEXT: add a0, a0, a31074; RV64-NEXT: add a5, a5, a71075; RV64-NEXT: add t0, t0, t21076; RV64-NEXT: add a0, a0, a51077; RV64-NEXT: add t0, t0, t31078; RV64-NEXT: add a0, a0, t01079; RV64-NEXT: add t4, t4, t51080; RV64-NEXT: add a0, a0, t41081; RV64-NEXT: addi sp, s0, -2561082; RV64-NEXT: .cfi_def_cfa sp, 2561083; RV64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload1084; RV64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload1085; RV64-NEXT: .cfi_restore ra1086; RV64-NEXT: .cfi_restore s01087; RV64-NEXT: addi sp, sp, 2561088; RV64-NEXT: .cfi_def_cfa_offset 01089; RV64-NEXT: ret1090 %e0 = extractelement <16 x i64> %v, i32 01091 %e1 = extractelement <16 x i64> %v, i32 11092 %e2 = extractelement <16 x i64> %v, i32 21093 %e3 = extractelement <16 x i64> %v, i32 31094 %e4 = extractelement <16 x i64> %v, i32 41095 %e5 = extractelement <16 x i64> %v, i32 51096 %e6 = extractelement <16 x i64> %v, i32 61097 %e7 = extractelement <16 x i64> %v, i32 71098 %e8 = extractelement <16 x i64> %v, i32 81099 %e9 = extractelement <16 x i64> %v, i32 91100 %e10 = extractelement <16 x i64> %v, i32 101101 %e11 = extractelement <16 x i64> %v, i32 111102 %e12 = extractelement <16 x i64> %v, i32 121103 %e13 = extractelement <16 x i64> %v, i32 131104 %e14 = extractelement <16 x i64> %v, i32 141105 %e15 = extractelement <16 x i64> %v, i32 151106 %add0 = xor i64 %e0, %e11107 %add1 = add i64 %add0, %e21108 %add2 = add i64 %add1, %e31109 %add3 = add i64 %add2, %e41110 %add4 = add i64 %add3, %e51111 %add5 = add i64 %add4, %e61112 %add6 = add i64 %add5, %e71113 %add7 = add i64 %add6, %e81114 %add8 = add i64 %add7, %e91115 %add9 = add i64 %add8, %e101116 %add10 = add i64 %add9, %e111117 %add11 = add i64 %add10, %e121118 %add12 = add i64 %add11, %e131119 %add13 = add i64 %add12, %e141120 %add14 = add i64 %add13, %e151121 ret i64 %add141122}1123 1124define i32 @explode_16xi32_exact_vlen(<16 x i32> %v) vscale_range(2, 2) {1125; RV32-LABEL: explode_16xi32_exact_vlen:1126; RV32: # %bb.0:1127; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma1128; RV32-NEXT: vslidedown.vi v12, v8, 21129; RV32-NEXT: vmv.x.s a0, v121130; RV32-NEXT: vslidedown.vi v12, v8, 31131; RV32-NEXT: vmv.x.s a1, v91132; RV32-NEXT: vmv.x.s a2, v121133; RV32-NEXT: vslidedown.vi v12, v9, 11134; RV32-NEXT: vmv.x.s a3, v121135; RV32-NEXT: vslidedown.vi v12, v9, 21136; RV32-NEXT: vmv.x.s a4, v121137; RV32-NEXT: vslidedown.vi v9, v9, 31138; RV32-NEXT: vmv.x.s a5, v101139; RV32-NEXT: vmv.x.s a6, v91140; RV32-NEXT: vslidedown.vi v9, v10, 11141; RV32-NEXT: vmv.x.s a7, v91142; RV32-NEXT: vslidedown.vi v9, v10, 21143; RV32-NEXT: vmv.x.s t0, v91144; RV32-NEXT: vslidedown.vi v9, v10, 31145; RV32-NEXT: vmv.x.s t1, v111146; RV32-NEXT: vmv.x.s t2, v91147; RV32-NEXT: vslidedown.vi v9, v11, 11148; RV32-NEXT: vmv.x.s t3, v91149; RV32-NEXT: vslidedown.vi v9, v11, 21150; RV32-NEXT: vmv.x.s t4, v91151; RV32-NEXT: vslidedown.vi v9, v11, 31152; RV32-NEXT: vmv.x.s t5, v91153; RV32-NEXT: vmv.s.x v9, zero1154; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1155; RV32-NEXT: vredxor.vs v8, v8, v91156; RV32-NEXT: vmv.x.s t6, v81157; RV32-NEXT: add a0, a0, a21158; RV32-NEXT: add a1, a1, a31159; RV32-NEXT: add a5, a6, a51160; RV32-NEXT: add t1, t2, t11161; RV32-NEXT: add a0, t6, a01162; RV32-NEXT: add a1, a1, a41163; RV32-NEXT: add a5, a5, a71164; RV32-NEXT: add t1, t1, t31165; RV32-NEXT: add a0, a0, a11166; RV32-NEXT: add a5, a5, t01167; RV32-NEXT: add t1, t1, t41168; RV32-NEXT: add a0, a0, a51169; RV32-NEXT: add t1, t1, t51170; RV32-NEXT: add a0, a0, t11171; RV32-NEXT: ret1172;1173; RV64-LABEL: explode_16xi32_exact_vlen:1174; RV64: # %bb.0:1175; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma1176; RV64-NEXT: vslidedown.vi v12, v8, 21177; RV64-NEXT: vmv.x.s a0, v121178; RV64-NEXT: vslidedown.vi v12, v8, 31179; RV64-NEXT: vmv.x.s a1, v91180; RV64-NEXT: vmv.x.s a2, v121181; RV64-NEXT: vslidedown.vi v12, v9, 11182; RV64-NEXT: vmv.x.s a3, v121183; RV64-NEXT: vslidedown.vi v12, v9, 21184; RV64-NEXT: vmv.x.s a4, v121185; RV64-NEXT: vslidedown.vi v9, v9, 31186; RV64-NEXT: vmv.x.s a5, v101187; RV64-NEXT: vmv.x.s a6, v91188; RV64-NEXT: vslidedown.vi v9, v10, 11189; RV64-NEXT: vmv.x.s a7, v91190; RV64-NEXT: vslidedown.vi v9, v10, 21191; RV64-NEXT: vmv.x.s t0, v91192; RV64-NEXT: vslidedown.vi v9, v10, 31193; RV64-NEXT: vmv.x.s t1, v111194; RV64-NEXT: vmv.x.s t2, v91195; RV64-NEXT: vslidedown.vi v9, v11, 11196; RV64-NEXT: vmv.x.s t3, v91197; RV64-NEXT: vslidedown.vi v9, v11, 21198; RV64-NEXT: vmv.x.s t4, v91199; RV64-NEXT: vslidedown.vi v9, v11, 31200; RV64-NEXT: vmv.x.s t5, v91201; RV64-NEXT: vmv.s.x v9, zero1202; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1203; RV64-NEXT: vredxor.vs v8, v8, v91204; RV64-NEXT: vmv.x.s t6, v81205; RV64-NEXT: add a0, a0, a21206; RV64-NEXT: add a1, a1, a31207; RV64-NEXT: add a5, a6, a51208; RV64-NEXT: add t1, t2, t11209; RV64-NEXT: add a0, t6, a01210; RV64-NEXT: add a1, a1, a41211; RV64-NEXT: add a5, a5, a71212; RV64-NEXT: add t1, t1, t31213; RV64-NEXT: add a0, a0, a11214; RV64-NEXT: add a5, a5, t01215; RV64-NEXT: add t1, t1, t41216; RV64-NEXT: add a0, a0, a51217; RV64-NEXT: add t1, t1, t51218; RV64-NEXT: addw a0, a0, t11219; RV64-NEXT: ret1220 %e0 = extractelement <16 x i32> %v, i32 01221 %e1 = extractelement <16 x i32> %v, i32 11222 %e2 = extractelement <16 x i32> %v, i32 21223 %e3 = extractelement <16 x i32> %v, i32 31224 %e4 = extractelement <16 x i32> %v, i32 41225 %e5 = extractelement <16 x i32> %v, i32 51226 %e6 = extractelement <16 x i32> %v, i32 61227 %e7 = extractelement <16 x i32> %v, i32 71228 %e8 = extractelement <16 x i32> %v, i32 81229 %e9 = extractelement <16 x i32> %v, i32 91230 %e10 = extractelement <16 x i32> %v, i32 101231 %e11 = extractelement <16 x i32> %v, i32 111232 %e12 = extractelement <16 x i32> %v, i32 121233 %e13 = extractelement <16 x i32> %v, i32 131234 %e14 = extractelement <16 x i32> %v, i32 141235 %e15 = extractelement <16 x i32> %v, i32 151236 %add0 = xor i32 %e0, %e11237 %add1 = add i32 %add0, %e21238 %add2 = add i32 %add1, %e31239 %add3 = add i32 %add2, %e41240 %add4 = add i32 %add3, %e51241 %add5 = add i32 %add4, %e61242 %add6 = add i32 %add5, %e71243 %add7 = add i32 %add6, %e81244 %add8 = add i32 %add7, %e91245 %add9 = add i32 %add8, %e101246 %add10 = add i32 %add9, %e111247 %add11 = add i32 %add10, %e121248 %add12 = add i32 %add11, %e131249 %add13 = add i32 %add12, %e141250 %add14 = add i32 %add13, %e151251 ret i32 %add141252}1253