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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV32 %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64 %s4 5define void @gather_const_v16i8(ptr %x) {6; CHECK-LABEL: gather_const_v16i8:7; CHECK: # %bb.0:8; CHECK-NEXT: lbu a1, 12(a0)9; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma10; CHECK-NEXT: vmv.v.x v8, a111; CHECK-NEXT: vse8.v v8, (a0)12; CHECK-NEXT: ret13 %a = load <16 x i8>, ptr %x14 %b = extractelement <16 x i8> %a, i32 1215 %c = insertelement <16 x i8> poison, i8 %b, i32 016 %d = shufflevector <16 x i8> %c, <16 x i8> poison, <16 x i32> zeroinitializer17 store <16 x i8> %d, ptr %x18 ret void19}20 21define void @gather_const_v8i16(ptr %x) {22; CHECK-LABEL: gather_const_v8i16:23; CHECK: # %bb.0:24; CHECK-NEXT: lh a1, 10(a0)25; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma26; CHECK-NEXT: vmv.v.x v8, a127; CHECK-NEXT: vse16.v v8, (a0)28; CHECK-NEXT: ret29 %a = load <8 x i16>, ptr %x30 %b = extractelement <8 x i16> %a, i32 531 %c = insertelement <8 x i16> poison, i16 %b, i32 032 %d = shufflevector <8 x i16> %c, <8 x i16> poison, <8 x i32> zeroinitializer33 store <8 x i16> %d, ptr %x34 ret void35}36 37define void @gather_const_v4i32(ptr %x) {38; CHECK-LABEL: gather_const_v4i32:39; CHECK: # %bb.0:40; CHECK-NEXT: lw a1, 12(a0)41; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma42; CHECK-NEXT: vmv.v.x v8, a143; CHECK-NEXT: vse32.v v8, (a0)44; CHECK-NEXT: ret45 %a = load <4 x i32>, ptr %x46 %b = extractelement <4 x i32> %a, i32 347 %c = insertelement <4 x i32> poison, i32 %b, i32 048 %d = shufflevector <4 x i32> %c, <4 x i32> poison, <4 x i32> zeroinitializer49 store <4 x i32> %d, ptr %x50 ret void51}52 53define void @gather_const_v2i64(ptr %x) {54; RV32-LABEL: gather_const_v2i64:55; RV32: # %bb.0:56; RV32-NEXT: addi a1, a0, 857; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma58; RV32-NEXT: vlse64.v v8, (a1), zero59; RV32-NEXT: vse64.v v8, (a0)60; RV32-NEXT: ret61;62; RV64-LABEL: gather_const_v2i64:63; RV64: # %bb.0:64; RV64-NEXT: ld a1, 8(a0)65; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma66; RV64-NEXT: vmv.v.x v8, a167; RV64-NEXT: vse64.v v8, (a0)68; RV64-NEXT: ret69 %a = load <2 x i64>, ptr %x70 %b = extractelement <2 x i64> %a, i32 171 %c = insertelement <2 x i64> poison, i64 %b, i32 072 %d = shufflevector <2 x i64> %c, <2 x i64> poison, <2 x i32> zeroinitializer73 store <2 x i64> %d, ptr %x74 ret void75}76 77define void @gather_const_v64i8(ptr %x) {78; CHECK-LABEL: gather_const_v64i8:79; CHECK: # %bb.0:80; CHECK-NEXT: lbu a1, 32(a0)81; CHECK-NEXT: li a2, 6482; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma83; CHECK-NEXT: vmv.v.x v8, a184; CHECK-NEXT: vse8.v v8, (a0)85; CHECK-NEXT: ret86 %a = load <64 x i8>, ptr %x87 %b = extractelement <64 x i8> %a, i32 3288 %c = insertelement <64 x i8> poison, i8 %b, i32 089 %d = shufflevector <64 x i8> %c, <64 x i8> poison, <64 x i32> zeroinitializer90 store <64 x i8> %d, ptr %x91 ret void92}93 94define void @gather_const_v16i16(ptr %x) {95; CHECK-LABEL: gather_const_v16i16:96; CHECK: # %bb.0:97; CHECK-NEXT: lh a1, 50(a0)98; CHECK-NEXT: li a2, 3299; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma100; CHECK-NEXT: vmv.v.x v8, a1101; CHECK-NEXT: vse16.v v8, (a0)102; CHECK-NEXT: ret103 %a = load <32 x i16>, ptr %x104 %b = extractelement <32 x i16> %a, i32 25105 %c = insertelement <32 x i16> poison, i16 %b, i32 0106 %d = shufflevector <32 x i16> %c, <32 x i16> poison, <32 x i32> zeroinitializer107 store <32 x i16> %d, ptr %x108 ret void109}110 111define void @gather_const_v16i32(ptr %x) {112; CHECK-LABEL: gather_const_v16i32:113; CHECK: # %bb.0:114; CHECK-NEXT: lw a1, 36(a0)115; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma116; CHECK-NEXT: vmv.v.x v8, a1117; CHECK-NEXT: vse32.v v8, (a0)118; CHECK-NEXT: ret119 %a = load <16 x i32>, ptr %x120 %b = extractelement <16 x i32> %a, i32 9121 %c = insertelement <16 x i32> poison, i32 %b, i32 0122 %d = shufflevector <16 x i32> %c, <16 x i32> poison, <16 x i32> zeroinitializer123 store <16 x i32> %d, ptr %x124 ret void125}126 127define void @gather_const_v8i64(ptr %x) {128; RV32-LABEL: gather_const_v8i64:129; RV32: # %bb.0:130; RV32-NEXT: addi a1, a0, 24131; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma132; RV32-NEXT: vlse64.v v8, (a1), zero133; RV32-NEXT: vse64.v v8, (a0)134; RV32-NEXT: ret135;136; RV64-LABEL: gather_const_v8i64:137; RV64: # %bb.0:138; RV64-NEXT: ld a1, 24(a0)139; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma140; RV64-NEXT: vmv.v.x v8, a1141; RV64-NEXT: vse64.v v8, (a0)142; RV64-NEXT: ret143 %a = load <8 x i64>, ptr %x144 %b = extractelement <8 x i64> %a, i32 3145 %c = insertelement <8 x i64> poison, i64 %b, i32 0146 %d = shufflevector <8 x i64> %c, <8 x i64> poison, <8 x i32> zeroinitializer147 store <8 x i64> %d, ptr %x148 ret void149}150 151define void @splat_concat_low(ptr %x, ptr %y, ptr %z) {152; CHECK-LABEL: splat_concat_low:153; CHECK: # %bb.0:154; CHECK-NEXT: lh a0, 2(a0)155; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma156; CHECK-NEXT: vmv.v.x v8, a0157; CHECK-NEXT: vse16.v v8, (a2)158; CHECK-NEXT: ret159 %a = load <4 x i16>, ptr %x160 %b = load <4 x i16>, ptr %y161 %c = shufflevector <4 x i16> %a, <4 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>162 %d = shufflevector <8 x i16> %c, <8 x i16> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>163 store <8 x i16> %d, ptr %z164 ret void165}166 167define void @splat_concat_high(ptr %x, ptr %y, ptr %z) {168; CHECK-LABEL: splat_concat_high:169; CHECK: # %bb.0:170; CHECK-NEXT: lh a0, 2(a1)171; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma172; CHECK-NEXT: vmv.v.x v8, a0173; CHECK-NEXT: vse16.v v8, (a2)174; CHECK-NEXT: ret175 %a = load <4 x i16>, ptr %x176 %b = load <4 x i16>, ptr %y177 %c = shufflevector <4 x i16> %a, <4 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>178 %d = shufflevector <8 x i16> %c, <8 x i16> poison, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>179 store <8 x i16> %d, ptr %z180 ret void181}182